MC74HC151D - Motorola / Freescale Semiconductor



SEMICONDUCTOR TECHNICAL DATA

1REV 6

 Motorola, Inc. 1995

10/95

 



High–Performance Silicon–Gate CMOS

The MC74HC151 is identical in pinout to the LS151. The device inputs are

compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

This device selects one of the eight binary Data Inputs, as determined by

the Address Inputs. The Strobe pin must be at a low level for the selected

data to appear at the outputs. If Strobe is high, the Y output is forced to a low

level and the Y output is forced to a high level.

The HC151 is similar in function to the HC251 which has 3–state outputs.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 µA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•Chip Complexity: 132 FETs or 33 Equivalent Gates

LOGIC DIAGRAM

STROBE

DATA

OUTPUTS

DATA

INPUTS

ADDRESS

INPUTS

PIN 16 = VCC

PIN 8 = GND



FUNCTION TABLE

PIN ASSIGNMENT

Inputs Outputs

A2 A1 A0 Strobe Y Y

X X X H L H

L L L L D0 D0

L L H L D1 D1

L H L L D2 D2

L H H L D3 D3

H L L L D4 D4

H L H L D5 D5

H H L L D6 D6

H H H L D7 D7

D0, D1, …, D7 = the level of the respective

D input.

125

STROBE

GND

VCC

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC74HCXXXN

MC74HCXXXD Plastic

SOIC

MC74HC151

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 1.5 to VCC + 1.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

± 20

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

± 25

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

± 50

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

ÎÎÎÎÎÎ

750

500

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

ÎÎÎÎÎÎ

260

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

SOIC Package: – 7 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

500

400

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.3

0.9

1.2

ÎÎÎÎ

0.3

0.9

1.2

ÎÎÎÎ

0.3

0.9

1.2

ÎÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH |Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

4.5

6.0

ÎÎÎ

3.98

5.48

ÎÎÎÎ

3.84

5.34

ÎÎÎÎ

3.70

5.20

ÎÎÎ

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

4.5

6.0

ÎÎÎ

0.26

ÎÎÎÎ

0.33

ÎÎÎÎ

0.40

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

6.0

ÎÎÎ

± 0.1

ÎÎÎÎ

± 1.0

ÎÎÎÎ

± 1.0

ÎÎÎ

µA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

Iout = 0 µA

ÎÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

160

ÎÎÎ

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or V out)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74HC151

High–Speed CMOS Logic Data

DL129 — Rev 6 3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Input D to Output Y or Y

(Figures 1, 3 and 6)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

185

ÎÎÎÎ

230

ÎÎÎÎ

280

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Input A to Output Y or Y

(Figures 2 and 6)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

205

ÎÎÎÎ

255

ÎÎÎÎ

310

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Strobe to Output Y or Y

(Figures 4, 5 and 6)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

125

ÎÎÎÎ

155

ÎÎÎÎ

190

ÎÎÎ

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 6)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

110

ÎÎÎ

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Package)*

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)*

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

PIN DESCRIPTIONS

INPUTS

D0, D1, … , D7 (Pins 4, 3, 2, 1, 15, 14, 13, 12)

Data inputs. Data on any one of these eight binary inputs

may be selected to appear on the output.

CONTROL INPUTS

A0, A1, A2 (Pins 11, 10, 9)

Address inputs. The data on these pins are the binary ad-

dress of the selected input (see the Function Table).

Strobe (Pin 7)

Strobe. This input pin must be at a low level for the se-

lected data to appear at the outputs. If the Strobe pin is high,

the Y output is forced to a low level and the Y output is forced

to a high level.

OUTPUTS

Y, Y (Pins 5, 6)

Data outputs. The selected data is presented at these pins

in both true (Y output) and complemented (Y output) forms.

MC74HC151

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

SWITCHING WAVEFORMS

STROBE

Figure 1. Figure 2.

Figure 3.

tPHL

tPLH

tTHL

tTLH

STROBE 10%

50%

VCC

GND

INPUT D

OUTPUT Y

10%

50%

90%

10%

50%

90%

tTLH

tPLH tPHL

tTHL

trtfVCC

GND

INPUT D

OUTPUT Y

tPHL tPLH

tTHL tTLH

10%

50%

90%

10%

50%

90%

tftrVCC

GND

10%

50%

90%

tPHL tPLH

10%

50%

90%

tTHL tTLH

VCC

GND

VCC

GND

50%

INPUT A

tPLH tPHL

50%

OUTPUT

Y OR Y

10%

50%

90%

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 4.

Figure 5. Figure 6. Test Circuit

VALIDVALID

MC74HC151

High–Speed CMOS Logic Data

DL129 — Rev 6 5 MOTOROLA

DATA

INPUTS

EXPANDED LOGIC DIAGRAM

DATA

OUTPUTS

ADDRESS

INPUTS

STROBE

MC74HC151

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

OUTLINE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

1 8

916

HGD 16 PL

–T

–

SEATING

PLANE

KJM

T A0.25 (0.010) M M

0.25 (0.010) T B A

MS S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

9.80

3.80

1.35

0.35

0.40

0.19

0.10

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

916

–A

–

–B

–

D16 PL

–T

–

SEATING

PLANE

R X 45°

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

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MC74HC151/D

*MC74HC151/D*

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