RFD3055LE, RFD3055LESM, RFP3055LE Data Sheet November 1999 11A, 60V, 0.107 Ohm, Logic Level, N-Channel Power MOSFETs * 11A, 60V Formerly developmental type TA49158. * rDS(ON) = 0.107 * Temperature Compensating PSPICE(R) Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol Ordering Information PACKAGE 4044.3 Features These N-Channel enhancement-mode power MOSFETs are manufactured using the latest manufacturing process technology. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits. PART NUMBER File Number D BRAND RFD3055LE TO-251AA F3055L RFD3055LESM TO-252AA F3055L RFP3055LE TO-220AB FP3055LE G S NOTE: When ordering, use the entire part number. Add the suffix, 9A, to obtain the TO-252 variant in tape and reel, e.g. RFD3055LESM9A. Packaging JEDEC TO-220AB JEDEC TO-251AA SOURCE DRAIN GATE SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (FLANGE) JEDEC TO-252AA DRAIN (FLANGE) GATE SOURCE 6-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. 1-888-INTERSIL or 407-727-9207 | Copyright (c) Intersil Corporation 1999 RFD3055LE, RFD3055LESM, RFP3055LE Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD3055LE, RFD3055LESM, RFP3055LE 60 60 16 11 Refer to Peak Current Curve Refer to UIS Curve 38 0.25 -55 to 175 Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg UNITS V V V A W W/oC oC oC oC 300 260 CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS ID = 250A, VGS = 0V 60 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250A 1 - 3 V VDS = 55V, VGS = 0V - - 1 A Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) rDS(ON) Turn-On Time tON Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time TEST CONDITIONS VDS = 50V, VGS = 0V, TC = 150oC - - 250 A VGS = 16V - - 100 nA ID = 8A, VGS = 5V (Figure 11) - - 0.107 VDD 30V, ID = 8A, VGS = 4.5V, RGS = 32 (Figures 10, 18, 19) - - 170 ns - 8 - ns tr - 105 - ns td(OFF) - 22 - ns tf - 39 - ns tOFF Total Gate Charge Gate Charge at 5V Threshold Gate Charge Qg(TOT) VGS = 0V to 10V Qg(5) VGS = 0V to 5V Qg(TH) VGS = 0V to 1V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJA VDD = 30V, ID = 8A, Ig(REF) = 1.0mA (Figures 20, 21) VDS = 25V, VGS = 0V, f = 1MHz (Figure 14) - - 92 ns - 9.4 11.3 nC - 5.2 6.2 nC - 0.36 0.43 nC - 350 - pF - 105 - pF CRSS - 23 - pF RJC - - 3.94 oC/W TO-220AB - - 62 oC/W TO-251AA, TO-252AA - - 100 oC/W TYP MAX UNITS ISD = 8A - 1.25 V ISD = 8A, dISD/dt = 100A/s - 66 ns Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD Diode Reverse Recovery Time trr TEST CONDITIONS MIN NOTES: 2. Pulse Test: Pulse Width 300ms, Duty Cycle 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). 6-2 RFD3055LE, RFD3055LESM, RFP3055LE Typical Performance Curves Unless Otherwise Specified POWER DISSIPATION MULTIPLIER 1.2 15 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 VGS = 10V 10 VGS = 4.5V 5 0.2 0 0 25 0 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 25 175 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 ZJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE 200 10 IDM, PEAK CURRENT (A) ID, DRAIN CURRENT (A) 100 100s OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1ms 10ms SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 6-3 200 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 100 I = I25 175 - TC 150 VGS = 5V 10 1 TC = 25oC TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-5 10-4 10-3 10-2 10-1 100 t, PULSE WIDTH (s) FIGURE 5. PEAK CURRENT CAPABILITY 101 RFD3055LE, RFD3055LESM, RFP3055LE Typical Performance Curves Unless Otherwise Specified (Continued) 15 VGS = 10V If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC 1 VGS = 5V 12 9 VGS = 3.5V 6 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 3 0.01 0.1 1 10 VGS = 3V TC = 25oC 0 0.001 VGS = 4V 0 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms) 4 NOTE: Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 7. SATURATION CHARACTERISTICS FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING 15 150 ID, DRAIN CURRENT (A) 12 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 9 TJ = 25oC 6 3 TJ = 175oC ID = 3A ID = 5A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 120 90 TJ = -55oC 0 60 2 3 4 5 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS 10 FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 150 2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VGS = 4.5V, VDD = 30V, ID = 8A SWITCHING TIME (ns) ID = 11A tr 100 tf 50 td(OFF) td(ON) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 VGS = 10V, ID = 11A 0.5 0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () FIGURE 10. SWITCHING TIME vs GATE RESISTANCE 6-4 50 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 200 RFD3055LE, RFD3055LESM, RFP3055LE Typical Performance Curves Unless Otherwise Specified (Continued) 1.2 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250A 1.0 0.8 1.1 1.0 0.9 0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) -80 200 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 10 VGS , GATE TO SOURCE VOLTAGE (V) 1000 CISS = CGS + CGD C, CAPACITANCE (pF) ID = 250A COSS CDS + CGD 100 VGS = 0V, f = 1MHz CRSS = CGD 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 11A ID = 5A ID = 3A 2 0 60 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 8 0 10 0.1 VDD = 30V 2 4 6 Qg, GATE CHARGE (nC) 8 10 NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS tP + RG VDS IAS VDD VDD - VGS DUT 0V tP IAS 0 0.01 tAV FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT 6-5 FIGURE 17. UNCLAMPED ENERGY WAVEFORMS RFD3055LE, RFD3055LESM, RFP3055LE Test Circuits and Waveforms (Continued) tON tOFF td(ON) VDS td(OFF) tf tr VDS 90% 90% RL VGS + - DUT 10% 10% 0 VDD 90% RGS VGS VGS 0 10% FIGURE 18. SWITCHING TEST CIRCUIT 50% 50% PULSE WIDTH FIGURE 19. RESISTIVE SWITCHING WAVEFORMS VDS VDD RL Qg(TOT) VDS Qg(10) OR Qg(5) VGS + VDD VGS DUT Ig(REF) VGS = 2V 0 VGS = 1V FOR L2 DEVICES Qg(TH) VGS = 20V VGS = 10V FOR L2 DEVICES VGS = 10V VGS = 5V FOR L2 DEVICES Ig(REF) 0 FIGURE 20. GATE CHARGE TEST CIRCUIT 6-6 FIGURE 21. GATE CHARGE WAVEFORMS RFD3055LE, RFD3055LESM, RFP3055LE PSPICE Electrical Model .SUBCKT RFD3055LE 2 1 3 ; rev 1/30/95 CA 12 8 3.9e-9 CB 15 14 4.9e-9 CIN 6 8 3.25e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD LDRAIN DPLCAP DRAIN 2 5 10 5 51 ESLC 11 - RDRAIN 6 8 EVTHRES + 19 8 + LGATE GATE 1 EVTEMP RGATE + 18 22 9 20 21 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD + 17 EBREAK 18 50 ESG LSOURCE CIN 8 SOURCE 3 7 RSOURCE RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.7e-2 RGATE 9 20 3.37 RLDRAIN 2 5 10 RLGATE 1 9 54.2 RLSOURCE 3 7 25.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 2.50e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B DBREAK + RSLC2 IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 5.42e-9 LSOURCE 3 7 2.57e-9 RLDRAIN RSLC1 51 EBREAK 11 7 17 18 67.8 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RLSOURCE S1A 12 S2A 13 8 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 - 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD - IT 14 + + EGS 19 VBAT 5 8 EDS - + 8 22 RVTHRES VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),3))} .MODEL DBODYMOD D (IS = 1.75e-13 RS = 1.75e-2 TRS1 = 1e-4 TRS2 = 5e-6 CJO = 5.9e-10 TT = 5.45e-8 N = 1.03 M = 0.6) .MODEL DBREAKMOD D (RS = 6.50e-1 TRS1 = 1.25e-4 TRS2 = 1.34e-6) .MODEL DPLCAPMOD D (CJO = 3.21e-10 IS = 1e-30 N = 10 M = 0.81) .MODEL MMEDMOD NMOS (VTO = 2.02 KP = .83 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.37) .MODEL MSTROMOD NMOS (VTO = 2.39 KP = 14 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.78 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.7 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.06e-3 TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5) .MODEL RSLCMOD RES (TC1 = 0 TC2 = 0) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6) .MODEL RVTEMPMOD RES (TC1 = -1.6e-3 TC2 = 1e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4 VOFF= -2.5) VON = -2.5 VOFF= -4) VON = -0.5 VOFF= 0) VON = 0 VOFF= -0.5) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 6-7 RFD3055LE, RFD3055LESM, RFP3055LE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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