G = 0.2, Level Translation,
16-Bit ADC Driver
AD8275
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008-2010 Analog Devices, Inc. All rights reserved.
FEATURES
Translates ±10 V to +4 V
Drives 16-bit SAR ADCs
Small MSOP package
Input overvoltage: +40 V to −35 V (VS = 5 V)
Fast settling time: 450 ns to 0.001%
Rail-to-rail output
Wide supply operation: +3.3 V to +15 V
High CMRR: 80 dB
Low gain drift: 1 ppm/°C
Low offset drift: 2.5 μV/°C
APPLICATIONS
Level translator
ADC driver
Instrumentation amplifier building block
Automated test equipment
PIN CONFIGURATION
07546-001
REF1 1
–IN 2
+IN 3
–VS4
REF2
8
+VS
7
OUT
6
SENSE
5
AD8275
TOP VIEW
(Not t o Scale)
Figure 1.
TYPICAL APPLICATION
07546-002
VREF
4.096V
AD8275
7
4
5
6
8
2
50kΩ
0.1µF
50kΩ
20kΩ
20kΩ
33Ω
10kΩ
3
+IN
–IN
VIN REF2
REF1
–V
S
+V
S
+5V
OUT
SENSE
0.1µF
2.7nF
10µF
1
AD7685
VDD
GNDREF
IN+
IN–
+10V
–10V
+4.048V
+0.048V
+2.048V
Figure 2. Translating ±10 V to 4.096 V ADC Full Scale
GENERAL DESCRIPTION
The AD8275 is a G = 0.2 difference amplifier that can be used
to translate ±10 V signals to a +4 V level. It solves the problem
typically encountered in industrial and instrumentation applic-
ations where ±10 V signals must be interfaced to a single-supply
4 V or 5 V ADC. The AD8275 interfaces the two signal levels,
simplifying design.
The AD8275 has fast settling time of 450 ns and low distortion,
making it suitable for driving medium speed successive approx-
imation (SAR) ADCs. Its wide input voltage range and rail-to-
rail outputs make it an easy to use building block. Single-supply
operation reduces the power consumption of the amplifier and
helps to protect the ADC from overdrive conditions.
Internal, matched, precision laser-trimmed resistors ensure
low gain error, low gain drift of 1 ppm/°C (maximum), and
high common-mode rejection of 80 dB. Low offset and low
offset drift, combined with its fast settling time, make the
AD8275 suitable for a variety of data acquisition applications
where accurate and quick capture is required.
The AD8275 can be used as an analog front end, or it can follow
buffers to level translate high voltages to a voltage range accepted
by the ADC. In addition, the AD8275 can be configured for diff-
erential outputs if used with a differential ADC.
The AD8275 is available in a space-saving, 8-lead MSOP
and is specified for performance over the −40°C to +85°C
temperature range.
Table 1. Difference Amplifiers by Category
Low Distortion High Voltage
Single-Supply
Current Sense
AD8270 AD628 AD8202
AD8273 AD629 AD8203
AD8274 AD8205
AD8275 AD8206
AMP03 AD8216
AD8275
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configuration ............................................................................. 1
Typical Application........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Maximum Power Dissipation ..................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 11
Basic Connection ........................................................................ 11
Power Supplies ............................................................................ 12
Reference ..................................................................................... 12
Common-Mode Input Voltage Range ..................................... 12
Input Protection ......................................................................... 12
Configurations ............................................................................ 13
Applications Information .............................................................. 14
Driving a Single-Ended ADC ................................................... 14
Differential Outputs ................................................................... 14
Increasing Input Impedance ..................................................... 15
AC Coupling ............................................................................... 15
Using the AD8275 as a Level Translator in a Data Acquisition
System .......................................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
8/10—Rev. 0 to Rev. A
Changes to Figure 40 ...................................................................... 14
10/08—Revision 0: Initial Version
AD8275
Rev. A | Page 3 of 16
SPECIFICATIONS
VS = 5 V, G = 0.2, REF1 connected to GND and REF2 connected to 5 V, RL = 2 kΩ connected to VS/2, TA = 25°C, unless otherwise noted.
Specifications referred to output unless otherwise noted.
Table 2.
A Grade B Grade
Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
Small Signal Bandwidth −3 dB 10 15 10 15 MHz
Slew Rate 4 V step 20 25 20 25 V/µs
Settling Time to 0.01% 4 V step on output, CL = 100 pF 350 350 450 ns
Settling Time to 0.001% 4 V step on output, CL = 100 pF 450 450 550 ns
Overload Recovery Time 50% overdrive 300 300 ns
NOISE/DISTORTION1
THD + N f = 1 kHz, VOUT = 4 V p-p, 22 kHz band
pass filter
106 106 dB
Voltage Noise f = 0.1 Hz to 10 Hz, referred to output 1 4 1 4 µV p-p
Spectral Noise Density f = 1 kHz, referred to output 40 40 nV/√Hz
GAIN VREF2 = 4.096 V, REF1 and RL connected
to GND, (VIN+) − (VIN−) = −10 V to +10 V
0.2 0.2 V/V
Gain Error 0.024 0.024 %
Gain Drift −40°C to +85°C 1 3 0.3 1 ppm/°C
Gain Nonlinearity VOUT = 4 V p-p, RL = 600 Ω, 2 kΩ, 10 kΩ 2.5 2.5 3 ppm
OFFSET AND CMRR
Offset2Referred to output, VS = ±2.5 V,
reference and input pins grounded
300 700 150 500 µV
vs. Temperature −40°C to +85°C 2.5 2.5 7 µV/°C
vs. Power Supply VS = 3.3 V to 5 V 90 100 dB
Reference Divider Accuracy 0.024 0.024 %
Common-Mode Rejection
Ratio3
VCM = ±10 V, referred to output
80 96 86 dB
INPUT CHARACTERISTICS
Input Voltage Range4 −12.3 +12 −12.3 +12 V
Impedance5
Differential VCM = VS/2 108||2 108||2 kΩ||pF
Common Mode 27.5||2 27.5||2 kΩ||pF
OUTPUT CHARACTERISTICS
Output Swing VREF2 = 4.096 V, REF1 and RL connected
to GND, RL = 2 kΩ
−VS +
0.048
+VS −
0.1
−VS +
0.048
+VS −
0.1
V
Capacitive Load6 100 100 pF
Short-Circuit Current Limit 30 30 mA
POWER SUPPLY
Specified Voltage Range 5 5 V
Operating Voltage Range 3.3 15 3.3 15 V
Supply Current IO = 0 mA, VS = ±2.5 V, reference and
input pins grounded
1.9 2.3 1.9 2.3 mA
Over Temperature IO = 0 mA, VS = ±2.5 V, reference and
input pins grounded, −40°C to +85°C
2.1 2.7 2.1 2.7 mA
TEMPERATURE RANGE
Specified Performance −40 +85 −40 +85 °C
1 Includes amplifier voltage and current noise, as well as noise of internal resistors.
2 Includes input bias and offset current errors.
3 See Figure 7 for CMRR vs. temperature.
4 The input voltage range is a function of the voltage supplies, reference voltage, and ESD diodes. When operating on other supply voltages, see the Absolute Maximum
Ratings section, Figure 11, and Table 5 for more information.
5 Internal resistors are trimmed to be ratio matched but have ±20% absolute accuracy.
6 See Figure 25 to Figure 28 in the Typical Performance Characteristics section for more information.
AD8275
Rev. A | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 18 V
Output Short-Circuit Current See derating curve
(Figure 3)
Voltage at +IN, −IN Pins −VS + 40 V, +VS − 40 V
Voltage at REFx, +VS, − VS, SENSE,
and OUT Pins
−VS − 0.5 V, +VS + 0.5 V
Current into REFx, +IN, −IN, SENSE,
and OUT Pins
3 mA
Storage Temperature Range −65°C to +130°C
Specified Temperature Range −40°C to +85°C
Thermal Resistance (θJA) 135°C/W
Package Glass Transition Temperature
(TG)
140°C
ESD Human Body Model 2 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8275 package is
limited by the associated rise in junction temperature (TJ) on
the die. The plastic encapsulating the die locally reaches the
junction temperature. At approximately 140°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8275. Exceeding
a junction temperature of 140°C for an extended period can
result in changes in silicon devices, potentially causing failure.
The still air thermal properties of the package and PCB (θJA),
the ambient temperature (TA), and the total power dissipated in
the package (PD) determine the junction temperature of the die.
The junction temperature is calculated as follows:
TJ = TA + (PD × θJA)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some of which is dissipated in the
load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power − Load Power)
( )
L
OUT
L
OUTS
SS
D
R
V
R
V
V
IVP
2
–
2
×
+×=
In single-supply operation with RL referenced to –VS, the worst
case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a 4-layer JEDEC
standard board.
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
–40 0–20 20 40 60 80 100 120
07546-003
MAXIMUM POWER DISSIPATIO N (W)
AMBI E NT TE M P E RATURE ( °C)
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
AD8275
Rev. A | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
07546-001
REF1 1
–IN 2
+IN 3
–VS4
REF2
8
+VS
7
OUT
6
SENSE
5
AD8275
TOP VIEW
(Not t o Scale)
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 REF1 Reference Pin. Sets the output voltage level (see the Reference section).
2 −IN Negative Input Pin.
3 +IN Positive Input Pin.
4 −VS Negative Supply Pin.
5 SENSE Sense Output Pin. Tie this pin to the OUT pin.
6 OUT Output Pin (Force Output).
7 +VS Positive Supply Pin.
8 REF2 Reference Pin. Sets the output voltage level (see the Reference section).
AD8275
Rev. A | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, G = 0.2, REF1 connected to GND and REF2 connected to 5 V, RL = 2 kΩ connected to VS/2, TA = 25°C, unless otherwise noted.
07546-004
OFFSET VOLTAGE (µV)
HITS
0
2
4
6
10
8
12
14
–600 –400 –200 0200 400 600
Figure 5. Typical Distribution of System Offset Voltage, Referred to Output
07546-005
CMRR (µV/V)
HITS
0
10
20
30
40
50
60
70
–60 –40 –20 020 40 60
Figure 6. Typical Distribution of CMRR, Referred to Output
Figure 7. CMRR vs. Temperature, Normalized at 25°C
07546-007
TEMPERATURE (°C)
OFFSET VOLTAGE (µV)
–40 –20 020 40 60 80 100 120
–300
–250
–200
–150
–100
–50
50
0
100
150
200
250
300
NORM ALIZED AT 25° C, REP RE S E NTAT IVE S AM P LES
Figure 8. Offset Voltage vs. Temperature, Normalized at 25°C,
Referred to Output
07546-008
TEMPERATURE (°C)
GAIN ERRO R ( µV/V)
–45 –30 –15 015 30 45 60 75 90 105 120
50
40
30
20
10
0
–10
–20
–30
–40
–50 GAIN ERRO R NORMALI ZED AT 25° C
Figure 9. Gain Error vs. Temperature, Normalized at 25°C
07546-009
TEMPERATURE (°C)
–50 –25
5
4
3
2
10
QUIESCE NT CURRENT (mA)
25 50 75
3.3V
100 125
5V
Figure 10. Quiescent Current vs. Temperature
AD8275
Rev. A | Page 7 of 16
07546-010
OUTPUT VOLTAGE (V)
INPUT COMMON-MODE VOLT AGE (V)
–0.5 00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.5
35
30
25
20
15
10
5
0
–5
–10
–15
–20
–25
Figure 11. Input Common-Mode Voltage vs. Output Voltage, No Load
0
–5
–10
–15
–20
–25
–30
–35
–40
GAIN (d B)
1k100 10k 100k 1M 100M10M
07546-011
FRE QUENCY ( Hz )
Figure 12. Gain vs. Frequency
07546-012
40
50
60
80
70
90
100
100 1k 10k 100k 10M1M
FRE QUENCY ( Hz )
COM M ON-MODE RE JE CTI ON (dB)
Figure 13. Common-Mode Rejection vs. Frequency, Referred to Input
07546-013
FRE QUENCY ( Hz )
POWER SUPPLY REJECTION (dB)
–20
0
20
40
60
80
100
120
100 1M100k10k1k
Figure 14. Power Supply Rejection vs. Frequency, Referred to Output
07546-014
6
5
4
3
2
1
0
MAXIMUM OUTPUT VOLT AGE (V p -p )
1k100 10k 100k 1M 10M
FRE QUENCY ( Hz )
Figure 15. Maximum Output Voltage vs. Frequency
07546-015
20
15
10
5
–5
–15
0
–10
–20 0 1 2 3 4
GAIN NONLINEARITY (ppm)
OUTPUT VOLTAGE (V)
Figure 16. Gain Nonlinearity, RL = 600 Ω, 2 kΩ, 10 kΩ
AD8275
Rev. A | Page 8 of 16
07546-016
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
–70 –25–50 025 50 75 100 125
CURRENT ( mA)
TEMPERATURE (°C)
5V SINK
3.3V S INK
5V SOURCE
3.3V S OURCE
Figure 17. Short-Circuit Current vs. Temperature, VS = 3.3 V, 5 V
07546-017
+VS
+VS– 0.2
+VS– 0.4
+VS– 0.6
+VS– 0.8
+VS– 1.0
–VS+ 1.0
–VS+ 0.8
–VS+ 0.6
–VS+ 0.4
–VS+ 0.2
–VS
OUTPUT VOLTAGE SWING (V)
(REFERRED TO SUPPLY RAILS)
1k 10k100 100k
RLOAD (Ω)
–40°C
–40°C
+125°C
+25°C
+85°C
+125°C
+25°C
+85°C
Figure 18. Output Voltage Swing vs. RLOAD, VS = 5 V
+V
S
+V
S
– 0.4
+V
S
– 0.8
+V
S
– 1.2
+V
S
– 1.6
+V
S
– 2.0
–V
S
+ 2.0
–V
S
+ 1.6
–V
S
+ 1.2
–V
S
+ 0.8
–V
S
+ 0.4
–V
S
OUTPUT VOLTAGE SWING (V)
(REFERRED TO SUPPLY RAILS)
246810 12 140OUTPUT CURRE NT (mA)
–40°C
+125°C
+25°C
+125°C
07546-018
+85°C
+25°C
+85°C
–40°C
Figure 19. Output Voltage Swing vs. Output Current, VS = 3.3 V
+V
S
+V
S
– 0.4
+V
S
– 0.8
+V
S
– 1.2
+V
S
– 1.6
+V
S
– 2.0
–V
S
+ 2.0
–V
S
+ 1.6
–V
S
+ 1.2
–V
S
+ 0.8
–V
S
+ 0.4
–V
S
OUTPUT VOLTAGE SWING (V)
(REFERRED TO SUPPLY RAILS)
246810 12 140OUTPUT CURRE NT (mA)
–40°C
07546-119
–40°C
+125°C
+85°C
+25°C
+125°C +85°C +25°C
Figure 20. Output Voltage Swing vs. Output Current, VS = 5 V
07546-019
FRE QUENCY ( Hz )
VOLT AGE NOI SE DENSITY (n V/√Hz)
10
100
1k
110 100 1k 10k 100k
Figure 21. Voltage Noise Density vs. Frequency, Referred to Output
07546-020
TIME (1s/DIV)
VOLTAGE NOISE (1µV/DIV)
Figure 22. 0.1 Hz to 10 Hz Voltage Noise, Referred to Output
AD8275
Rev. A | Page 9 of 16
07546-021
40
35
30
25
20
15
10
5
0
–40 –20 020 40 60 80 100 120
SLEW RATE (V/µs)
TEMPERATURE (°C)
+SR
–SR
Figure 23. Slew Rate vs. Temperature
07546-022
1µs/DIV
20mV/DIV
C
LOAD
= 47pF
600Ω
2kΩ
10kΩ
NO LOAD
Figure 24. Small Signal Step Response for Various Resistive Loads
(Step Responses Staggered for Clarity)
07546-023
1µs/DIV
20mV/DIV
NO RESISTIVE LOAD
20pF
47pF
NO CAP
100pF
Figure 25. Small Signal Pulse Response for Various Capacitive Loads
(Step Responses Staggered for Clarity)
07546-024
0
10
20
30
40
50
60
020 40 60 80 100 120 140 160
CAPACI TANCE (pF )
OVERSHOOT (%)
3.3V
5V
Figure 26. Small Signal Overshoot vs. Capacitive Load,
No Resistive Load
07546-025
0
10
20
30
40
50
60
020 40 60 80 100 120 140 160
CAPACI TANCE (pF )
OVERSHOOT (%)
3.3V
5V
Figure 27. Small Signal Overshoot vs. Capacitive Load,
600 Ω in Parallel with Capacitive Load
07546-026
0
10
20
30
40
50
60
020 40 60 80 100 120 140 160
CAPACI TANCE (pF )
OVERSHOOT (%)
3.3V
5V
Figure 28. Small Signal Overshoot vs. Capacitive Load,
2 kΩ in Parallel with Capacitive Load
AD8275
Rev. A | Page 10 of 16
07546-027
10V/DIV
2µs/DIV
10mV/DIV
Figure 29. Large Signal Pulse Response and Settling Time, RL = 2 kΩ
07546-029
1.0
0.1
0.01
0.001
0.000110 100 10k1k 100k
THD + N ( %)
FRE QUENCY ( Hz )
R
L
= 600Ω
R
L
= 10kΩ
R
L
= 2kΩ
V
OUT
= 4V p-p
Figure 30. THD + N vs. Frequency, VOUT = 4 V p-p
AD8275
Rev. A | Page 11 of 16
THEORY OF OPERATION
The AD8275 level translates ±10 V signals at its inputs to 4 V
at its output. It does this by attenuating the input signal by 5.
A subtractor network performs the attenuation, the level shifting,
and the differential-to-single-ended conversion. One benefit of
the subtractor topology is that it can accept input signals
beyond its supply voltage. The subtractor is composed of tightly
matched resistors. By integrating the resistors and trimming the
resistor ratios, the AD8275 achieves 80 dB CMRR and 0.024%
gain error.
07546-030
INPUT
ESD
REF2
+V
S
+V
S
+V
S
–V
S
–V
S
+V
S
–VS
–VS
+VS
–VS
–VS
OUT
SENSE
50kΩ
7kΩ
7kΩ
50kΩ
20kΩ
20kΩ
10kΩ
2.5V
–IN
+IN INPUT
ESD
+VS
–VS
REF1
+VS
–VS
Figure 31. AD8275 Simplified Schematic
To achieve a wider input voltage range, the AD8275 uses an
internal 2.5 V voltage bias tied to –VS and two 7 kΩ resistors, as
shown in Figure 31. The resistors help to set the common mode
of the internal amplifier. The benefit of this circuit is that it
extends the input range without causing crossover distortion
typical of amplifiers that have rail-to-rail complementary
transistor inputs. The input range of the internal op amp is
+VS − 0.9 V to −VS + 1.35 V.
–10 –8 –6
600
400
200
0
–200
–400
–600 –4 –2 0246810
COMMON-MODE VOLT AGE (V)
OFF SET (µV)
07546-132
Figure 32. AD8275 Does Not Have Crossover Distortion Typical of Rail-to-Rail
Input Amplifiers
The AD8275 employs a balanced, high gain, linear output stage
that adaptively generates current as required, eliminating the
dynamic errors found in other amplifiers. This is useful when
driving SAR ADCs, which can deliver kickback current into the
output of the amplifier. The result is a design that achieves low
distortion, consistent bandwidth, and high slew rate.
BASIC CONNECTION
The basic configurations for the AD8275 are shown in
Figure 33 and Figure 34. In Figure 33, REF1 and REF2 are
tied together. A voltage, VREF, applied to the tied REF1 and
REF2 pins, sets the output voltage level to VREF. For example,
in Figure 33, if VREF = 2 V and the inputs are tied to ground,
the output remains at 2 V.
07546-031
AD8275
7
4
5
6
8
1
250kΩ
0.1µF
50kΩ
20kΩ
20kΩ
10kΩ
3
VINN
+IN
–IN
VINP REF2
VREF
VOUT
REF1
–VS
+VS
+5V
OUT
SENSE
VOUT = + VREF
(VINP) – (VINN)
5
Figure 33. Basic Configuration 1: Shared Reference
In contrast, Figure 34 shows REF1 tied to ground and REF2
tied to VREF. In this example, the two 20 kΩ resistors serve as a
resistor divider, and VREF is divided by 2. For example, if both
inputs of the AD8275 are grounded and VREF = 5 V, the output
is 2.5 V.
07546-032
AD8275
7
4
5
6
8
1
2
50kΩ
0.1µF
50kΩ
20kΩ
20kΩ
10kΩ
3
V
INN
+IN
–IN
V
INP
REF2
V
REF
V
OUT
REF1
–V
S
+V
S
+5V
OUT
SENSE
V
OUT
= +
(V
INP
) – (V
INN
)
5V
REF
+ 0V
2
Figure 34. Basic Configuration 2: Split Reference
AD8275
Rev. A | Page 12 of 16
POWER SUPPLIES
Use a stable dc voltage to power the AD8275. Noise on the
supply pins can adversely affect performance. Place a bypass
capacitor of 0.1 µF between each supply pin and ground, as
close to each pin as possible. A tantalum capacitor of 10 µF
should also be used between each supply and ground. It can
be farther away from the AD8275 and typically can be shared
by other precision integrated circuits.
REFERENCE
The reference terminals are used to provide a bias level for the
output. For example, in a single-supply 5 V operation, the
reference terminals can be set so that the output is biased at
2.5 V. This ensures that the output can swing positive or
negative around a 2.5 V level.
Figure 33 and Figure 34 illustrate two different ways to set the
reference voltage. See the Basic Connection section for the
differences between the two settings.
The allowable reference voltage range is a function of the
common-mode input and supply voltages. The REF1 and REF2
pins should not exceed either +VS or −VS by more than 0.5 V.
The REFx terminals should be driven by low source impedance
because parasitic resistance in series with REF1 and REF2 can
adversely affect CMRR and gain accuracy.
20kΩ
20kΩREF2
REF1
50kΩ
–IN
INCORRECTCORRECT
07546-033
7
4
5
6
8
1
2
50kΩ
50kΩ
20kΩ
20kΩ
10kΩ
3
–IN
+IN
REF2 V
REF
REF1
–V
S
+V
S
OUT
SENSE
3
AD8275
7
4
5
6
8
2
50kΩ10kΩ
3
+IN
V
REF
–V
S
+V
S
OUT
SENSE
AD8275
1
20kΩ
20kΩREF2
REF1
50kΩ
–IN
7
4
5
6
8
1
2
50kΩ
50kΩ
20kΩ
20kΩ
10kΩ
3
–IN
+IN
REF2 V
REF
REF1
–V
S
+V
S
OUT
SENSE
AD8275 4
5
6
8
2
50kΩ10kΩ
3
+IN
V
REF
–V
S
+V
S
OUT
SENSE
AD8275
1
IN
2
50
0kΩ
R
REF1
1
0kΩ
5
+IN
NSE
IN
2
50
0kΩ
R
REF1
1
0kΩ
5
+IN
O
NSE
7
Figure 35. REF1 and REF2 Pin Guidelines
COMMON-MODE INPUT VOLTAGE RANGE
The common-mode voltage range is a function of the input
voltage range of the internal op amp, the supply voltage, and
the reference voltage.
Equation 1 expresses the maximum positive common-mode
voltage range.
VCM_POS ≤ 13.14(+VS) – 7.14(–VS) – 5((REF1 + REF2)/2) – 29.69 (1)
Equation 2 expresses the minimum common-mode voltage
range.
VCM_NEG ≥ 6(–VS) – 5((REF1 + REF2)/2) – 0.11 (2)
The voltage range of the internal op amp varies depending on
temperature. The equations reflect a typical input voltage range
of +VS − 0.9 V and −VS + 1.35 V over temperature. Table 5 lists
expected common-mode ranges for typical configurations.
Table 5. Expected Common-Mode Voltage Range for Typical
Configurations
+VS (V)1 VREF1 (V) VREF2 (V) VCM+ (V) VCM− (V)
5 5 0 23.5 −12.6
5 2.5 0 29.8 −6.4
5 4.096 0 25.8 −10.4
3.3 3.3 0 5.4 −8.4
3.3 2.5 0 7.4 −6.4
5 5 5 11.0 −25.1
5 4.096 4.096 15.5 −20.6
5 3 3 21.0 −15.1
5 2.5 2.5 23.5 −12.6
5 2.048 2.048 25.8 −10.4
5 1.25 1.25 29.8 −6.4
5 0 0 36.0 −0.1
1 –VS = 0 V.
INPUT PROTECTION
The inputs of the AD8275, +IN and −IN, are protected by ESD
diodes that clamp 40 V above −VS and 40 V below +VS. When
operating on a single +5 V supply, the ESD diode conducts at
input voltages less than −35 V and greater than +40 V.
If the input voltage is expected to exceed the maximum ratings
of the AD8275, use external transorbs. Adding series resistors to
the inputs of the AD8275 is not recommended because the
internal resistor ratios are matched to provide optimal CMRR
and gain accuracy. Adding external series resistors to the input
degrades the performance of the AD8275.
All other pins are protected by ESD diodes that clamp 0.5 V
beyond either supply rail. For example, the voltage range of the
REF1 and REF2 pins on a 5 V supply is −0.5 V to +5.5 V.
AD8275
Rev. A | Page 13 of 16
CONFIGURATIONS
Figure 36 and Figure 37, along with Table 6 and Table 7, provide
examples of the possible input and output ranges for various
supplies and reference voltages.
Note that Table 6 and Table 7 list the typical voltage range of the
AD8275; these values do not reflect variation over process or
temperature.
HI +SWING
–SWING
USEFUL VOUT
LINEAR VIN
RANGE
LO
HI
LO
MID
07546-136
VREF
AD8275
7
4
5
6
8
250kΩ
0.1µF
50kΩ
20kΩ
20kΩ
10kΩ
3+IN
–IN
VINP
VINN
REF2
REF1
–VS
+VS
+5V
OUT
SENSE
1
VOUT
HI +SWING
–SWING
USEFUL VOUT
LINEAR VIN
RANGE
LO
HI
LO
MID
07546-137
VREF
AD8275
7
4
5
6
8
250kΩ
0.1µF
50kΩ
20kΩ
20kΩ
10kΩ
3+IN
–IN
REF2
REF1
–VS
+VS
+5V
OUT
SENSE
1
V
OUT
V
INP
V
INN
Figure 36. Split Reference Figure 37. Shared Reference
Table 6. Input and Output Relationships for Split Reference
Configuration in Figure 36
+VS1 VREF
VOUT for
VIN = 0 V
Linear
Differential
VIN Range
Useful VOUT
Ranges
5 V 5 V 2.5 V High: +12 V
Mid: 0 V
Low: −12.3 V
High: +4.95 V
Swing: +2.45 V,
−2.455 V
Low: +0.045 V
5 V 2.5 V 1.25 V High: +18.3 V
Mid: 0 V
Low: −6 V
High: +4.95 V
Swing: +3.7 V,
−1.205 V
Low: +0.045 V
5 V 4.096 V 2.048 V High: +14.3 V
Mid: 0 V
Low: −10 V
High: +4.95 V
Swing: +2.902 V,
−2.003 V
Low: +0.045 V
3.3 V 3.3 V 1.65 V High: +8 V
Mid: 0 V
Low: −8 V
High: +3.24 V
Swing: +1.59 V,
−1.605 V
Low: +0.045 V
3.3 V 2.5 V 1.25 V High: +10 V
Mid: 0 V
Low: −6 V
High: +3.24 V
Swing: +1.99 V,
−1.205 V
Low: +0.045 V
1 −VS = 0 V.
Table 7. Input and Output Relationships for Shared
Reference Configuration in Figure 37
+VS1 VREF
VOUT for
VIN = 0 V
Linear
Differential
VIN Range
Useful VOUT
Ranges
5 V 5 V 5 V High: −0.1 V
Mid: 0 V
Low: −24.7 V
High: +4.98 V
Swing: −4.94 V
Low: +0.06 V
5 V 4.096 V 4.096 V High: +4.4 V
Mid: 0 V
Low: −20.2 V
High: +4.98 V
Swing: +0.884 V
to −4.03 V
Low: +0.06 V
5 V 3 V 3 V High: +9.5 V
Mid: 0 V
Low: −14.8 V
High: +4.95 V
Swing: +1.9 V,
−2.955 V
Low: +0.045 V
5 V 2.5 V 2.5 V High: +12 V
Mid: 0 V
Low: −12.3 V
High: +4.95 V
Swing: +2.45 V,
−2.455 V
Low: +0.045 V
5 V 2.048 V 2.048 V High: +14.3 V
Mid: 0 V
Low: −10 V
High: +4.95 V
Swing: +2.902 V,
−2.003 V
Low: +0.045 V
5 V 1.25 V 1.25 V +18.3 V to
−6 V
High: +4.95 V
Swing: +3.7 V,
−1.205 V
Low: +0.045 V
0 V 0 V 0 V 24.5 V to 0.2 V High: 4.95 V
Swing: 4.95 V
Low: 0.045 V
1 −VS = 0 V.
AD8275
Rev. A | Page 14 of 16
APPLICATIONS INFORMATION
DRIVING A SINGLE-ENDED ADC
The AD8275 provides the common-mode rejection that SAR
ADCs often lack. In addition, it enables designers to use cost-
effective, precision, 16-bit ADCs such as the AD7685, yet still
condition ±10 V signals.
One important factor in selecting an ADC driver is its ability to
settle within the acquisition window of the ADC. The AD8275
is able to drive medium speed SAR ADCs.
In Figure 38, the 2.7 nF capacitor serves to store and deliver
necessary charge to the switched capacitor input of the ADC.
The 33 Ω series resistor reduces the burden of the 2.7 nF load
from the amplifier and isolates it from the kickback current
injected from the switched capacitor input of the AD7685. The
output impedance of the amplifier can affect the THD of the
ADC. In this case, the combined impedance of the 33 Ω resistor
and the output impedance of the AD8275 provides extremely
low THD of −112 dB. Figure 39 shows the ac response of the
AD8275 driving the AD7685.
07546-034
VREF
(ADR444,
ADR445)
AD8275
7
4
5
6
8
2
50kΩ
0.1µF
50kΩ
20kΩ
20kΩ
33Ω
10kΩ
3
+IN
–IN
VIN REF2
REF1
–V
S
+V
S
+5V
OUT
SENSE
0.1µF
2.7nF
10µF
1
AD7685
VDD
GNDREF
IN+
IN–
Figure 38. Driving a Single-Ended ADC
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170 0 1 4 7 10
07546-139
ADC FULL S CALE ( dB)
FRE QUENCY ( kHz )
258
369
Figure 39. FFT of AD8275 Directly Driving the AD7685 Using the 5 V
Reference of the Evaluation Board (Input = 20 V p-p, 1 kHz, THD = −112 dB)
The AD8275 can condition signals for higher resolution ADCs
such as 18-bit SAR converters, provided that a narrower
bandwidth is sampled to limit noise.
DIFFERENTIAL OUTPUTS
In certain applications, it is necessary to create a differential signal.
For example, high resolution ADCs often require a differential
input. In other cases, transmission over a long distance can require
differential signals for better immunity to interference.
Figure 40 shows how to configure the AD8275 to output a
differential signal. The AD8655 op amp is used in an inverting
topology to create a differential voltage. VREF sets the output
midpoint. Errors from the op amp are common to both outputs
and are thus common mode. Likewise, errors from using
mismatched resistors cause a common-mode dc offset error.
Such errors are rejected in differential signal processing by
differential input ADCs or by instrumentation amplifiers.
When using this circuit to drive a differential ADC, VREF can be
set using a resistor divider from the ADC reference to make the
output ratiometric with the ADC.
07546-035
AD8275
7
4
5
6
8
2
50kΩ
0.1µF
0.1µF
8.2µF
50kΩ
20kΩ
20kΩ
2kΩ
2kΩ
10kΩ
3
+IN
–IN
REF2
REF1
–V
S
+V
S
+5V
+10V
–10V +5V
OUT
SENSE
1
AD8655
V
REF
= 2.5V
+V
OUT
–V
OUT
+3.5V
+1.5V
+2.5V
+3.5V
+1.5V
+2.5V
Figure 40. AD8275 Configured for Differential Output (for Driving a Differential ADC)
AD8275
Rev. A | Page 15 of 16
INCREASING INPUT IMPEDANCE
In applications where a high input impedance is needed, low
input bias current op amps can be used to buffer the AD8275.
In Figure 41, an AD8620 is used to provide high input imped-
ance. Input bias current is limited to 10 pA.
07546-036
AD8275
7
4
5
6
8
1
2
1
3
2
7
6
5
4
8
50kΩ
0.1µF
50kΩ
20kΩ
20kΩ
10kΩ
3
–IN
1/2
2/2 +IN REF2 VREF
REF1
–VS
–13V
0.1µF
0.1µF +VS
+5V
+13V
OUT VOUT
SENSE
INVERTING
INPUT
NON-
INVERTING
INPUT
AD8620
AD8620
Figure 41. Adding Op Amp Buffers for High Input Impedance
AC COUPLING
An integrator can be tied to the AD8275 in feedback to create a
high-pass filter as shown in Figure 42. This circuit can be used
to reject dc voltages and offsets. At low frequencies, the impedance
of the capacitor, C, is high. Thus, the gain of the integrator is
high. DC voltage at the output of the AD8275 is inverted and
gained by the integrator. The inverted signal is injected back
into the REFx pins, nulling the output. In contrast, at high fre-
quencies, the integrator has low gain because the impedance of
C is low. Voltage changes at high frequencies are inverted but at
a low gain. The signal is injected into the REFx pins but it is not
enough to null the output. High frequency signals are, therefore,
allowed to pass.
When a signal exceeds fHIGH-PAS S, the AD8275 outputs the
conditioned input signal.
07546-037
AD8275
7
4
5
6
8
250kΩ
0.1µF
0.1µF
50kΩ
20kΩ
20kΩR
C
10kΩ
3+IN
–IN
REF2
REF1
VREF
–VS
+VS
+5V
+5V
OUT VOUT
SENSE
VOUT
1
fHIGH-PASS =1
2πRC
OP
AMP
Figure 42. AC-Coupled Level Translator
USING THE AD8275 AS A LEVEL TRANSLATOR IN
A DATA ACQUISITION SYSTEM
Signal size varies dramatically in some data acquisition applica-
tions. Instrumentation amplifiers, such as the AD8253, AD8228,
or AD8221, are often used at the inputs to provide CMRR and
high input impedance. However, the instrumentation amplifiers
output ±10 V signals and the ADC full scale is 5 V or 4.096 V.
In Figure 43, the AD8275 serves as a level translator between
the in-amp and the ADC. The AD8275, along with the AD8228
and the AD8253, have very low gain drift because all gain setting
resistors are internal and laser-trimmed.
07546-143
VREF
AD8275
7
4
5
6
8
2
50kΩ
0.1µF
50kΩ
20kΩ
20kΩ
33Ω
10kΩ
3
+IN
–IN
REF2
REF1
–V
S
+V
S
+5V
OUT
SENSE
0.1µF
2.7nF
10µF
1
ADC
VCC
GNDREF
+IN
–IN
0.1µF
+15V
–15V0.1µF
IN-AMP
Figure 43. Level Translation in a Data Acquisition System
AD8275
Rev. A | Page 16 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 44. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1Temperature Range Package Description Package Option Branding
AD8275ARMZ −40°C to +85°C 8-Lead MSOP RM-8 Y13
AD8275ARMZ-R7 −40°C to +85°C 8-Lead MSOP, 7” Tape and Reel RM-8 Y13
AD8275ARMZ-RL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y13
AD8275BRMZ −40°C to +85°C 8-Lead MSOP RM-8 Y1V
AD8275BRMZ-R7 −40°C to +85°C 8-Lead MSOP, 7” Tape and Reel RM-8 Y1V
AD8275BRMZ-RL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y1V
1 Z = RoHS Compliant Part.
©2008-2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07546-0-8/10(A)