TLC556, TLC556Y DUAL LinCMOS TIMERS SLFS047B - FEBRUARY 1984 - REVISED SEPTEMBER 1997 D D D D D D D Very Low Power Consumption . . . 2 mW Typ at VDD = 5 V Capable of Operation in Astable Mode CMOS Output Capable of Swinging Rail to Rail High Output-Current Capability Sink 100 mA Typ Source 10 mA Typ Output Fully Compatible With CMOS, TTL, and MOS Low Supply Current Reduces Spikes During Output Transitions Single-Supply Operation From 2 V to 15 V Functionally interchangeable With the NE556; Has Same Pinout D, J, OR N PACKAGE (TOP VIEW) 1 DISCH 1 THRES 1 CONT 1 RESET 1 OUT 1 TRIG GND 14 2 13 3 12 4 11 5 10 6 9 7 8 VDD 2 DISCH 2 THRES 2 CONT 2 RESET 2 OUT 2 TRIG FK PACKAGE (TOP VIEW) description 1 CONT NC 1 RESET NC 1 OUT 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2 THRES NC 2 CONT NC 2 RESET 1 TRIG GND NC 2 TRIG 2 OUT The TLC556 series are monolithic timing circuits fabricated using the TI LinCMOS process, which provides full compatibility with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Accurate time delays and oscillations are possible with smaller, less-expensive timing capacitors than the NE556 because of the high input impedance. Power consumption is low across the full range of power supply voltages. 1 1 THRES 1 DISCH NC V DD 2 DISCH D NC-No internal connection Like the NE556, the TLC556 has a trigger level approximately one-third of the supply voltage and a threshold level approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal and ground. While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC556 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE556. These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015. However, care should be exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric performance. All unused inputs should be tied to an appropriate logic level to prevent false triggering. The TLC556C is characterized for operation from 0C to 70C. The TLC556I is characterized for operation from - 40C to 85C. The TLC556M is characterized for operation over the full military temperature range of - 55C to 125C. LinCMOS is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TLC556, TLC556Y DUAL LinCMOS TIMERS SLFS047B - FEBRUARY 1984 - REVISED SEPTEMBER 1997 AVAILABLE OPTIONS PACKAGE TA RANGE VDD RANGE OC to 70C 2V to 18 V TLC556CD TLC556CN - 4OC to 85C 3V to 18 V TLC556lD TLC556IN - 55C to 125C 5V to 18 V TLC556MD SMALL OUTLINE (D) CHIP CARRIER (FK) CERAMIC DIP (J) TLC556MFK PLASTIC DIP (N) TLC556MJ CHIP FORM (Y) TLC556Y TLC556MN The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC556CDR). FUNCTION TABLE RESET VOLTAGE TRIGGER VOLTAGE THRESHOLD VOLTAGE OUTPUT DISCHARGE SWITCH On < MIN Irrelevant Irrelevant L > MAX < MIN Irrelevant H Off >MAX >MAX >MAX L On > MAX > MAX < MIN As previously established For conditions shown as MIN or MAX, use the appropriate value specified under electrical characteristics. functional block diagram (each timer) VDD 14 CONT 3 RESET 4 R THRES R1 2 R 1 5 OUT S R 6 TRIG R 1 DISCH 7 GND RESET can override TRIG and THRES. TRIG can override THRES. Pin numbers shown are for the D, J, or N packages. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC556, TLC556Y DUAL LinCMOS TIMERS SLFS047B - FEBRUARY 1984 - REVISED SEPTEMBER 1997 TLC556Y chip information These chips, properly assembled, display characteristics similar to the TLC556 (see electrical table). Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 x 4 MINIMUM TJ max = 150C TOLERANCES ARE 10% 61 ALL DIMENSIONS ARE IN MILS NO BACKSIDE METALLIZATION PIN (7) INTERNALLY CONNECTED TO BACKSIDE OF CHIP 97 FUNCTIONAL BLOCK DIAGRAM (EACH TIMER) VDD (14) CONT (3) RESET (4) R THRESH R1 (2) R 1 (5) OUT S R (6) TRIG R (1) DISCH (7) GND POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TLC556, TLC556Y DUAL LinCMOS TIMERS SLFS047B - FEBRUARY 1984 - REVISED SEPTEMBER 1997 absolute maximum ratings over operating free-air temperature (unless otherwise noted) TLC556C TLC556I TLC556M UNIT 18 18 18 V - 0.3 to VDD - 0.3 to VDD - 0.3 to VDD V Sink current, discharge or output 150 150 150 mA Source current, output 15 15 15 mA Supply voltage, VDD (see Note 1) Input voltage range, VI Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range Storage temperature range Case temperature for 60 seconds Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds FK package J package Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds D or N package 0 to 70 - 40 to 85 - 55 to 125 C - 65 to 150 - 65 to 150 - 65 to 150 C 260 300 C 260 260 NOTE 1: All voltage values are with respect to network ground terminal. DISSIPATION RATING TABLE PACKAGE D FK J N TA 25C POWER RATING 950 mW 1375 mW 1375 mW 1150 mW DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING TA = 125C POWER RATING 7.6 mW/C 11.0 mW/C 11.0 mW/C 9.2 mW/C 608 mW 880 mW 880 mW 736 mW 494 mW 715 mW 715 mW 598 mW N/A 275 mW 275 mW N/A recommended operating conditions Supply voltage, VDD TLC556C Operating free-air temperature range, TA 4 MIN MAX 2 15 0 70 TLC556I - 40 85 TLC556M - 55 125 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 UNIT V C TLC556, TLC556Y DUAL LinCMOS TIMERS SLFS047B - FEBRUARY 1984 - REVISED SEPTEMBER 1997 electrical characteristics at specified free-air temperature, VDD = 2 V for TLC556C, VDD = 3 V for TLC556I PARAMETER VIT TEST CONDITIONS Input threshold voltage Trigger voltage I(trigger) (t i ) Trigger current V((reset) t) Reset voltage I(reset) ( t) Reset current TYP MAX MIN TYP MAX 25C 0.95 1.33 1.65 1.6 2 2.4 Full range 0.85 1.75 1.5 IOL = 1 mA VOH High level output voltage High-level IOH = -300 300 A VOL Low level output voltage Low-level IOL = 1 mA IDD Supply current See Note 2 10 10 MAX 75 150 0.4 Full range 0.3 0.67 0.95 0.71 1.05 0.61 1 10 10 MAX 75 150 25C 0.4 0.3 1.1 1.5 0.4 1.8 0.3 1.1 10 10 MAX 75 150 MAX 66.7% 66.7% 25C 0.04 Full range 0.2 0.03 0.25 0.1 0.1 MAX 0.5 120 25C 1.5 1.5 25C 1.9 Full range 1.5 0.07 0.2 0.3 0.07 130 500 800 V V 0.3 0.4 130 V nA 1.9 0.35 V pA 2.5 Full range 25C 1.5 V pA 0.375 25C Full range 1.29 1.8 25C UNIT pA 1.39 25C Full range Discharge g switch off-state current 2.5 25C 25C Control voltage (open circuit) as a percentage of supply voltage Discharge g switch on-state voltage TLC556I MIN Threshold current V(t i ) (trigger) TLC556C TA 500 1000 V A Full range is 0C to 70C for TLC556C and - 40C to 85C for TLC556I. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TLC556, TLC556Y DUAL LinCMOS TIMERS SLFS047B - FEBRUARY 1984 - REVISED SEPTEMBER 1997 electrical characteristics at specified free-air temperature, VDD = 5 V PARAMETER VIT TEST CONDITIONS Input threshold voltage Threshold current V((trigger)) Trigger voltage I((trigger) i ) Trigger current V((reset)) Reset voltage I((reset)) Reset current Control voltage (open circuit) as a percentage of supply voltage Discharge g switch on-state voltage IOL O = 10 mA Discharge g switch off-state current VO OH High-level g output voltage IOH 1 mA O = -1 IOL O = 8 mA VO OL Low-level output voltage IOL O = 5 mA IOL 3 2 mA O = 3.2 IDD Supply current See Note 2 TLC556C TLC556I TLC556M TA MIN TYP MAX MIN TYP MAX MIN TYP MAX 25C 2.8 3.3 3.8 2.8 3.3 3.8 2.8 3.3 3.8 Full range 2.7 3.9 2.7 3.9 2.7 25C 10 10 10 MAX 75 150 5000 25C 1.36 Full range 1.26 1.66 1.96 1.36 2.06 1.26 1.66 1.96 1.36 2.06 1.26 1.66 10 10 10 MAX 75 150 5000 25C 0.4 Full range 0.3 1.1 1.5 0.4 1.8 0.3 1.1 1.5 0.4 1.8 0.3 1.1 10 10 10 MAX 75 150 5000 MAX 66.7% 66.7% 66.7% 25C 0.15 Full range 0.5 0.15 0.6 0.5 0.15 0.6 0.6 25C 0.1 0.1 0.1 MAX 0.5 2 120 25C 4.1 Full range 4.1 25C 4.8 0.21 0.13 Full range 0.4 0.21 0.3 0.08 0.3 0.13 700 1000 0.4 0.3 0.08 0.3 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 0.21 pA 0.5 V nA 700 1200 0.4 0.6 0.13 0.3 0.45 0.08 0.3 340 700 0.35 340 V V 0.4 0.35 340 1.5 4.8 0.5 0.4 Full range 25C 4.1 V pA 4.1 0.5 Full range 25C 4.8 4.1 Full range 25C 4.1 1.96 1.8 25C V pA 2.06 25C Full range is 0C to 70C for TLC556C, - 40C to 85C for TLC556I, and - 55C to 125C for TLC556M. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG. 6 3.9 UNIT V 0.4 1400 A TLC556, TLC556Y DUAL LinCMOS TIMERS SLFS047B - FEBRUARY 1984 - REVISED SEPTEMBER 1997 electrical characteristics at specified free-air temperature, VDD = 15 V PARAMETER VIT TEST CONDITIONS Input threshold voltage Threshold current V(t (trigger) i ) Trigger voltage I(trigger) (t i ) Trigger current V((reset) t) Reset voltage I(reset) ( t) Reset current Control voltage (open circuit) as a percentage of supply voltage Discharge g switch onstate voltage IOL = 100 mA Discharge g switch offstate current IOH = -10 10 mA VOH High-level g output voltage IOH = -5 5 mA IOH = -1 1 mA IOL = 100 mA VOL Low-level output voltage IOL = 50 mA IOL = 10 mA IDD Supply current See Note 2 TA TLC556C TLC556I TLC556M MIN TYP MAX MIN TYP MAX MIN TYP MAX 25C 9.45 10 10.55 9.45 10 10.55 9.45 10 10.55 Full range 9.35 10.65 9.35 10.65 9.35 10 10 10 MAX 75 150 5000 25C 4.65 4.55 5 5.35 4.65 5.45 4.55 5 5.35 4.65 5.45 4.55 5 10 10 10 MAX 75 150 5000 25C 0.4 0.3 1.1 1.5 0.4 1.8 0.3 1.1 1.5 0.4 1.8 0.3 1.1 10 10 10 MAX 75 150 5000 MAX 66.7% 66.7% 66.7% 25C 0.8 1.7 0.8 1.8 1.7 0.8 1.8 0.1 0.1 0.1 MAX 0.5 2 120 25C 12.5 12.5 25C 13.5 Full range 13.5 25C 14.2 Full range 14.2 25C 14.2 14.6 25C 13.5 14.9 14.2 1.28 3.2 14.6 1 13.5 14.9 0.3 1.28 1.2 1.6 pA 1.7 V nA 14.2 14.6 14.2 V 14.9 3.2 1.28 3.7 0.63 1 0.12 0.3 0.63 1.2 1.8 1 V 1.5 0.12 0.4 0.72 3.2 3.8 1.4 0.4 0.72 V 14.2 1.3 0.12 1.5 13.5 3.6 0.63 pA 12.5 14.2 Full range Full range 12.5 13.5 Full range 25C 14.2 12.5 Full range 25C 12.5 V 1.8 25C Full range 5.35 1.8 25C Full range pA 5.45 25C Full range V 10.65 25C Full range UNIT 0.3 0.45 0.72 1.2 mA 2 Full range is 0C to 70C for TLC556C, - 40C to 85C for TLC556I, and - 55C to 125C for TLC556M. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TLC556, TLC556Y DUAL LinCMOS TIMERS SLFS047B - FEBRUARY 1984 - REVISED SEPTEMBER 1997 electrical characteristics, VDD = 5 V, TA = 25C PARAMETER VIT TEST CONDITIONS Input threshold voltage MIN TYP MAX 2.8 3.3 3.8 1.36 1.66 0.4 1.1 Threshold current V(trigger) Trigger voltage I(trigger) Trigger current V(reset) I(reset) Reset voltage 10 IOL = 10 mA 0.15 Discharge switch off-state current VOH VOL IOH = - 1 mA IOL = 8 mA Low-level output voltage 4.1 IOL = 5 mA IOL = 2.1 mA V pA 0.5 0.1 High-level output voltage V pA 1.5 10 Discharge switch on-state voltage V pA 1.96 10 Reset current UNIT V nA 4.8 V 0.21 0.4 0.13 0.3 0.08 0.3 IDD Supply current See Note 2 3.40 700 NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG. V A operating characteristics, VDD = 5 V, TA = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS Initial error of timing interval VDD = 5 V to 15 V, Supply voltage sensitivity of timing interval CT = 0.1 F, tr tf Output pulse rise time fmax Maximum frequency in astable mode Output pulse fall time TYP MAX RA = RB = 1 k to 100 k 1% 3% See Note 3 0.1 0.5 20 75 15 60 RL = 10 M, M CL = 10 pF RA = 470 , CT = 200 pF, RB = 200 , See Note 3 MIN 1.2 2.1 UNIT %/V ns MHz Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. NOTE 3: RA, RB, and CT are as defined in Figure 3. 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC556, TLC556Y DUAL LinCMOS TIMERS SLFS047B - FEBRUARY 1984 - REVISED SEPTEMBER 1997 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIMES (TO DISCHARGE OUTPUT FROM TRIGGER AND THRESHOLD SHORTED TOGETHER) vs SUPPLY VOLTAGE DISCHARGE SWITCH ON-STATE RESISTANCE vs FREE-AIR TEMPERATURE 600 Discharge Switch On-State Resistance - 70 VDD = 2 V, IO = 1 mA 40 VDD = 5 V, IO = 10 mA 20 VDD = 15 V, IO = 100 mA 10 7 4 2 1 -75 t PHL , t PLH - Propagation Delay Times - ns 100 IO(on) 1 mA CL 0 TA = 25C 500 400 300 tPHL 200 tPLH 100 0 -50 -25 0 25 50 75 100 125 0 2 TA - Free-Air Temperature - C 4 6 8 10 12 14 16 18 20 VDD - Supply Voltage - V The effects of the load resistance on these values must be taken into account separately. Figure 1 Figure 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TLC556, TLC556Y DUAL LinCMOS TIMERS SLFS047B - FEBRUARY 1984 - REVISED SEPTEMBER 1997 APPLICATION INFORMATION 0.1 F RA tL tH VDD 0.1 F tPHL CONT VDD RESET TLC556 DISCH RL 2/3 VDD Output OUT RB THRES CL 1/3 VDD TRIG GND GND CT tPLH CIRCUIT TRIGGER AND THRESHOLD VOLTAGE WAVEFORM Figure 3. Astable Operation Connecting the trigger input to the threshold input, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor CT charges through RA and RB to the threshold voltage level (approximately 0.67 VDD) and then discharges through RB only to the value of the trigger voltage level (approximately 0.33 VDD). The output is high during the charging cycle (tH) and low during the discharge cycle (tL). The duty cycle is controlled by the values of RA, and RB, and CT, as shown in the equations below. [ CT (RA ) RB) In 2 (In 2 + 0.693) t L [ C T R B In 2 Period + t H ) t L [ C T (R A ) 2R B) In 2 tL RB Output driver duty cycle + [ 1 * tH ) tL R A ) 2R B tH Output waveform duty cycle + tH t)H tL [ R )RB2R B A The 0.1-F capacitor at CONT in Figure 3 decreases the period by about 10%. The formulas shown above do not allow for any propagation delay from the trigger and threshold inputs to the discharge output. These delay times add directly to the period and create differences between calculated and actual values that increase with frequency. In addition, the discharge output resistance ron adds to RB to provide another source of error in the calculation when RB is very low or ron is very high. The equations below provide better agreement with measured values. 10 tH + CT (RA ) RB) In tL + CT (RB ) ron) In 3 * exp * tPLH C T (R B ) r on) 3 * exp * tPHL C T (R A ) R B) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 ) tPHL ) tPLH TLC556, TLC556Y DUAL LinCMOS TIMERS SLFS047B - FEBRUARY 1984 - REVISED SEPTEMBER 1997 APPLICATION INFORMATION The preceding equations and those given earlier are similar in that a time constant is multiplied by the logarithm of a number or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and In 3 at extremely high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic t t H terms can be substituted with good results. Duty cycles less than 50% will require that H < 1 and t t t H L L possibly RA ron. These conditions can be difficult to obtain. ) In monostable applications, the trip point of the trigger input can be set by a voltage applied to CONT. An input voltage between 10% and 80% of the supply voltage from a resistor divider with at least 500-A bias provides good results. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp Samples (Requires Login) 5962-89503022A ACTIVE LCCC FK 20 1 TBD Call TI Call TI 5962-8950302CA ACTIVE CDIP J 14 1 TBD Call TI Call TI TLC556CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC556CDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC556CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC556CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC556CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC556CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC556ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC556IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC556IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC556IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC556IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC556INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC556MD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC556MDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC556MDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC556MDRG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC556MFKB ACTIVE LCCC FK 20 1 TBD TLC556MJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type TLC556MJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type Addendum-Page 1 (3) POST-PLATE N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2012 Orderable Device TLC556MN Status (1) Package Type Package Drawing OBSOLETE PDIP N Pins Package Qty Eco Plan 14 TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLC556, TLC556M : * Catalog: TLC556 * Military: TLC556M NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2012 * Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC556CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLC556IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC556CDR SOIC D 14 2500 333.2 345.9 28.6 TLC556IDR SOIC D 14 2500 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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