S6J3310 Series S6J3320 Series S6J3330 Series S6J3340 Series 32-bit Microcontroller TraveoTM Family The Traveo family expands the company's automotive applications, scalability and high performance into one line-up and at the same time adds new features to fulfill the latest requirements of the automotive industry. Based on the powerful Arm(R) Cortex(R)- R5F core in single operations, it offers state-of-the-art real time performance, safety and security features. The family supports the latest in-car networks and offers high performance graphics engines optimized for a minimum memory footprint and embeds dedicated features to increase data security in the car. S6J3310/20/30/40 is a microcontroller series for instrument clusters with small thin-film transistor (TFT) displays. Features System 32-bit Arm Cortex-R5F CPU core at up to 240 MHz General purpose I/O port: up to 148 12-bit A/D converter: up to 48 channels External interrupt: up to 24 channels Base timer: up to 32 channels 32-bit reload timer: up to 6 channels 32-bit free-run timer: 8 channels Input capture unit: 12 channels Output compare unit: 12 channels Stepper motor controller (SMC): 6 Units Built-in CR oscillator Real-time clock DMA controller: 16 channels JTAG debug interface Security and Safety Secure Hardware Extension - SHE features, such as MPU, TPU, ECC and others CRC generator: 1 channel Watchdog timer with window function Low voltage detector Clock supervisor for all source clocks Safety Applications Instrument cluster Graphics and Display (optional) 2D graphic engine RGB888 LCDup to 4 COM x 32 SEG Communication CAN-FD: up to 6 channels serial interface: up to 12 channels, selectable protocol: UART, CSIO, LIN and I2C Ethernet AVB MAC (optional) MediaLB (optional) Automotive Remote Handler for APIX(R) (optional) Multi-function Memory HyperBusTM Memory interface High Speed SPI External BUS interface DDR Multimedia (optional) I2S input/output: 2 channels to PWM output unit Sound mixer: 1 unit x 10 inputs Stereo audio DAC PCM Cypress Semiconductor Corporation Document Number: 002-10635 Rev. *H * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised April 17, 2018 S6J3310/20/30/40 Series Table of Contents Features................................................................................................................................................................................... 1 Applications ............................................................................................................................................................................ 1 1. Overview ............................................................................................................................................................................ 4 1.1 Overview ....................................................................................................................................................................... 4 1.2 Document Definition ...................................................................................................................................................... 4 2. Function List ..................................................................................................................................................................... 5 2.1 Function List .................................................................................................................................................................. 5 2.2 Optional Function .......................................................................................................................................................... 7 2.2.1 Basic Option ................................................................................................................................................................... 7 2.2.2 ID ................................................................................................................................................................................... 8 2.2.3 Restriction ...................................................................................................................................................................... 8 3. Product Description ........................................................................................................................................................ 10 3.1 Overview ..................................................................................................................................................................... 10 3.2 Product Description ..................................................................................................................................................... 10 3.2.1 Ethernet ....................................................................................................................................................................... 15 4. Package and Pin Assignment ........................................................................................................................................ 16 4.1 Pin Assignment ........................................................................................................................................................... 16 4.1.1 TEQFP-208 Pin Assignment ........................................................................................................................................ 16 4.1.2 TEQFP-176 Pin Assignment ........................................................................................................................................ 20 4.1.3 TEQFP-144 Pin Assignment ........................................................................................................................................ 24 4.2 Package Dimensions ................................................................................................................................................... 28 4.2.1 TEQFP208 ................................................................................................................................................................... 28 4.2.2 TEQFP176 ................................................................................................................................................................... 29 4.2.3 TEQFP144 ................................................................................................................................................................... 30 5. IO Circuit Type................................................................................................................................................................. 32 5.1 I/O Circuit Type ........................................................................................................................................................... 32 5.2 Note ............................................................................................................................................................................. 37 6. Port Description .............................................................................................................................................................. 38 6.1 Port Description List .................................................................................................................................................... 38 6.2 Remark ........................................................................................................................................................................ 59 7. Port Configuration .......................................................................................................................................................... 60 7.1 Resource Input Configuration Module ......................................................................................................................... 60 7.1.1 RIC (S6J3310) ............................................................................................................................................................. 60 7.2 Port Output Function Configuration ........................................................................................................................... 149 7.2.1 Standard Configuration (S6J3310) ............................................................................................................................. 149 8. Precautions and Handling Devices ............................................................................................................................. 160 8.1 Handling Precautions ................................................................................................................................................ 160 8.1.1 Precautions for Product Design.................................................................................................................................. 160 8.1.2 Precautions for Package Mounting ............................................................................................................................ 161 8.1.3 Precautions for Use Environment............................................................................................................................... 162 8.2 Handling Devices ...................................................................................................................................................... 163 9. Electric Characteristics ................................................................................................................................................ 165 9.1 Electrical Characteristics ........................................................................................................................................... 165 9.1.1 Absolute Maximum Rating ......................................................................................................................................... 165 9.1.2 Recommended Operating Condition .......................................................................................................................... 170 9.1.3 DC Characteristics ..................................................................................................................................................... 173 Document Number: 002-10635 Rev. *H Page 2 of 322 S6J3310/20/30/40 Series 9.1.4 AC Characteristics ..................................................................................................................................................... 185 9.1.5 A/D Converter ............................................................................................................................................................ 255 9.1.6 Audio DAC ................................................................................................................................................................. 259 9.1.7 FLASH Memory.......................................................................................................................................................... 262 10. Acronyms ...................................................................................................................................................................... 263 11. Ordering Information .................................................................................................................................................... 265 12. Appendix ........................................................................................................................................................................ 266 12.1 Application 1: JTAG Tool Connection ........................................................................................................................ 266 13. Major Changes .............................................................................................................................................................. 267 Document History ............................................................................................................................................................... 320 Sales, Solutions, and Legal Information........................................................................................................................... 322 Document Number: 002-10635 Rev. *H Page 3 of 322 S6J3310/20/30/40 Series 1. Overview 1.1 Overview S6J3310/20/30/40 is a microcontroller series which is to be applied to automotive systems representative of a graphical cluster control unit on a dashboard. 1.2 Document Definition The related documents of S6J3310/20/30/40 are the followings. Table 1-1: Document Definition Document Type Definition This document. S6J3310/20/30/40 Datasheet The function and its characteristics are specified quantitatively. S6J3300 Series 32-bit Microcontroller TraveoTM Family Hardware Manual S6J3300 Hardware Manual The function and its operation of S6J3300 series are described. 32-Bit Microcontroller TraveoTM Family S6J33xx, S6J34xx, S6J35xx Series Hardware Manual Platform TM Traveo Platform Part Hardware Manual Primary User Document Code Investigator and hardware engineer 002-10635 Software engineer 002-10185 Software engineer 002-07884 Software and hardware engineer 002-03898 002-04455 002-04446 002-09716 002-04452 002-04096 002-12061 002-02495 The function and its operation of CPU core platform are described. Application Note The reference software, sample application, the reference board design and so on are explained. Notes: - Refer all documents for the system development. - - "Primary user" is a most likely engineer for whom the document is the most useful. - TraveoTM Platform Hardware Manual is expected to be used as dictionary of platform specification. The description of the datasheet and the S6J3300 Hardware Manual should precede the duplicated description of Traveo TM Platform Hardware Manual. Document Number: 002-10635 Rev. *H Page 4 of 322 S6J3310/20/30/40 Series 2. Function List 2.1 Function List The table shows the functions which are implemented in S6J3310/20/30/40 series. Table 2-1: Function List Function CPU core FPU PPU MPU TPU Endian Core clock frequency HPM bus frequency LLPM bus frequency Resource clock frequency Embedded CR oscillation PLL SSCG PLL Clock supervisor DMA Boot-ROM JTAG Data cache Instruction cache Program FLASH Work FLASH TCRAM System SRAM Backup RAM Security (SHE) Low latency interrupt Power domain External power supply Embedded LDO power supply for 5.0 V Low voltage detection of external power supply Low voltage detection of internal LDO output Hardware watchdog timer Software watchdog timer Package AUTOSAR General Purpose I/O Up/down counter I/O timer 32bit Reload timer Real time clock Sound generator S6J3310 S6J3320 S6J3330 Arm Cortex R5F Available Available Available Available Little endian 240 MHz 200 MHz 240 MHz 80 MHz (Max) Slow clock:100 kHz, Fast clock: 4 MHz (Center frequency) PLL0, 1, 2, 3 SSCG0, 1, 2, 3 Available 16 ch 16 Kbyte Available 16 Kbyte 16 Kbyte Option 112 Kbyte 128 Kbyte 384 Kbyte 32 Kbyte Option Available 5 domains 5 V (VCC5, VCC53), 3 V (VCC3, VCC53), 1.2 V (VCC12) S6J3340 Remarks See 9.1.4.1 See 2.2.1 Available Available Available Available Available Option AUTOSAR 4.0.3 Option 2 ch (FRT 5 ch x ICU 6 ch x OCU 6 ch) + (FRT 3 ch x ICU 6 ch x OCU 6 ch) 6 ch Available 5 ch See 2.2.1 See 2.2.3 Automatic calibration Sound waveform generator 1 unit x 5 outputs No See 2.2.1 Sound mixer 1 unit x 10 inputs No See 2.2.1 Document Number: 002-10635 Rev. *H Page 5 of 322 S6J3310/20/30/40 Series Function Stereo audio DAC PCM-PWM Base timer Stepping motor controller (SMC) 12bit-A/D converter CRC Programmable CRC Source clock timer NMI External interrupt Internal interrupt I2S S6J3310 S6J3320 S6J3330 1 unit (L and R) 1 unit (L and R) 16 units (32 ch) S6J3340 No No For 6 gauges 2 unit - 48 input ports (Max) 4 units 1 unit 4 ch Available 24 ch 512 vectors 2 ch See 2.2.3 1 ch DDR HSSPI 1 ch Hyper BUS 1 ch Multi-function serial interface 12 ch CAN-FD 6 ch CAN-FD RAM (ECC 16 KB/ch supported) It equivalents to 128 message buffer per channel of MCAN module Ethernet AVB 1 unit No Media-LB (MOST50) 1 unit No LCD controller 4 COM x 32 SEG (Max) Indicator PWM 1 ch MPU for AHB 1 unit MPU for AXI 1 unit Graphic engine clock 80 MHz (Max) Graphic AXI clock 80 MHz (Max) Display clock 25 MHz Display clock source Graphic display controller clock or external clock Target resolution WQVGA 480 x 272 Target frame rate 60 fps Number of display outputs 1 output TTL output (RGB888) Option 2D Graphic engine 1 unit 2D Driver API CYPRESS proprietary External BUS 1 ch APIX(R) for ARH 1 unit (2 ch) No (Automotive Remote Handler) Notes: - The options are described in 2.2. Document Number: 002-10635 Rev. *H Remarks See 2.2.1 See 2.2.1 One only supports an output as a function of the sound system. A type of Quad SPI See the AC specification on 9.1.4.17. See 2.2.1 See 2.2.1 See 2.2.3 See 2.2.1 See 2.2.1 Page 6 of 322 S6J3310/20/30/40 Series 2.2 Optional Function 2.2.1 Basic Option The figure shows the optional function and the part number relations of the series. Figure 2-1: Option and Part Number for S6J3310/20/30/40 Series S 6 J 3 3 x x x x x x x x x x x x Ordering options 7 digit Revision: Digit C D E Description Fixed Operation frequency of embedded Program Flash and CPU, Fixed Stabilization time for sub oscillator Fixed TCFLASH Sector Write Permission and Data Retention after Reset Leakage current improvement Option: Digit S A B U C D T E F V G H SHE MK_CEER* ON Fixed to Enable OFF VCC 5V DVCC 5V 3V 3V 5V 5V 3V 3V 5V ON 5V 3V Selectable OFF 3V 5V 5V 3V 3V * Chip Erase Enable Register Pin count: Digit H J K Pin Count 144pin 176pin 208pin Memory size: Digit E D C B Flash Program Work 4,160KB 112KB 3,136KB 112KB 2,112KB 112KB 1,600KB 112KB RAM Main 512KB 512KB 512KB 512KB Backup 16+16KB 16+16KB 16+16KB 16+16KB Function: Digit Graphic Ethernet MediaLB 1 2 3 4 Yes Yes Yes Yes Yes Yes Yes - Yes Yes Yes - Sound System Yes Yes - ARH for APIX Yes - Product series Identifer: Automotive MCU Notes: - This table only shows the relations between the optional function and the part numbers. That is, all products are not necessarily available for orders. See 11, and confirm actual availabilities of products. - The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0. Document Number: 002-10635 Rev. *H Page 7 of 322 S6J3310/20/30/40 Series 2.2.2 ID ID is specified for each function digit and revision which is defined at Figure 2-1. Function Digit S,U,T,V A,C,E,G B,D,F,H Revision Chip ID C 0x10122100 D, E 0x10122200 C 0x10128100 D, E 0x10128200 C 0x10120100 D, E 0x10120200 JTAG ID 0x1000B5CF 2.2.3 Restriction Some functions have restrictions which depend on package pin counts. Table 2-2: Pin Restriction Function TEQFP176 Analog input port (12bitADC) - SEG port of LCD controller - General Purpose I/O P4_00 ~ P4_31 CAN RX0_2, TX0_2 RX1_0, TX1_0 RX1_1, TX1_1 RX2_0, TX2_0 RX2_1, TX2_1 RX3_2, TX3_2 BaseTimer - ExtBus - Document Number: 002-10635 Rev. *H TEQFP144 AN4~7, AN10~11, AN14~15, AN25~26, AN28~30, SEG0~3 SEG5~8 P4_00 ~ P4_31 P3_00 ~ P3_31 RX0_1, TX0_1 RX0_2, TX0_2 RX1_0, TX1_0 RX1_1, TX1_1 RX2_0, TX2_0 RX2_1, TX2_1 RX3_1, TX3_1 RX3_2, TX3_2 RX5_1, TX5_1 RX6_1, TX6_1 PPG4/5/6/7/8/9_TOUT0_1 PPG4/5/6/7/8/9_TOUT2_1 PPG10/11/12/13/15_TOUT0_1 PPG10/11/12/13/14/15_TOUT2_1 PPG0/1/2/3/4/5_TIN1_1 PPG6/7/8/9/10/11_TIN1_1 PPG12/13/14/15_TIN1_1 MDQM1 MAD15~21 MDATA8~15 Page 8 of 322 S6J3310/20/30/40 Series Function TEQFP176 External Interrupt EINT1_4, EINT1_5 EINT2_1, EINT2_2 EINT3_2, EINT4_2 EINT5_4, EINT5_5 EINT6_4, EINT7_1 EINT7_4, EINT8_4 EINT8_5, EINT9_1 EINT10_1, EINT10_4 EINT10_5, EINT13_2 EINT13_3, EINT14_2 EINT14_3, EINT15_3 EINT16_1, EINT16_3 EINT16_4, EINT19_4 EINT20_3, EINT21_3 EINT22_1, EINT22_3 EINT23_3, EINT23_4 TEQFP144 EINT0_4, EINT1_1 EINT1_4, EINT1_5 EINT2_1, EINT2_2 EINT2_4, EINT3_1 EINT3_2, EINT3_4 EINT4_2, EINT4_4 EINT5_4, EINT5_5 EINT6_1, EINT6_4 EINT7_1, EINT7_4 EINT8_1, EINT8_4 EINT8_5, EINT9_1 EINT9_2, EINT10_1 EINT10_2, EINT10_4 EINT10_5, EINT11_2 EINT11_5, EINT12_1 EINT12_2, EINT12_5 EINT13_2, EINT13_3 EINT13_5, EINT14_1 EINT14_2, EINT14_3 EINT14_5, EINT15_2 EINT15_3, EINT16_1 EINT16_2, EINT16_3 EINT16_4, EINT16_5 EINT17_1, EINT17_3 EINT17_5, EINT18_1 EINT18_3, EINT18_5 EINT19_1, EINT19_3 EINT19_4, EINT20_1 EINT20_2, EINT20_3 EINT21_1, EINT21_3 EINT22_1, EINT22_3 EINT23_3, EINT23_4 Notes: - See multiplexed functions on pin assignment sheet. - The optional restriction will be added without notification. Document Number: 002-10635 Rev. *H Page 9 of 322 S6J3310/20/30/40 Series 3. Product Description 3.1 Overview This chapter explains the product features of S6J3310/20/30/40 series. The description of this chapter should precede the duplicated description on TraveoTM Platform Hardware Manual. 3.2 Product Description The table shows features. Table 3-1: Product Features Feature Technology Functional Safety Peripherals Power Domain (PD) Debug and Trace System Control Clock Embedded CR oscillation Clock Supervisor Reset Description 40-nm CMOS technology with embedded FLASH Fully automotive qualified according to ISO/TS 16949 and AEC-Q100 Developed according to ISO26262, safety target ASIL-B The product series has some functional safety features suited for ASIL-B application. See function list. See the TraveoTM Platform Hardware Manual and chapter STATE TRANSITION in detail. The product series supports the power off control of PD1, PD2 (including PD3 and 5), PD4_0, PD4_1 and PD6. The power domain resets of PD3 and PD5 included in PD2 are not supported in the product series, and "0" is always read from the reset factor flags of them. This series doesn't support partial wakeup for PD6. See the TraveoTM Platform Hardware Manual in detail. - Standard 5-pin JTAG interface - 4 kB Embedded Trace Buffer 4-bit trace support for TEQFP package. See the TraveoTM Platform Hardware Manual in detail. Main and sub oscillator is available. - A wide range of 3.6 - 16MHz is available for main oscillator - 32KHz is available for sub oscillator Sub clock is enable/disable by register settings See the TraveoTM Platform Hardware Manual in detail. CLK_CLKO (Clock Output Function) is supported. Main Oscillation Stabilization Wait Time (at 4 MHz):8.19ms (Initial value) See the TraveoTM Platform Hardware Manual in detail. Stabilization time is as followings. - 0.35 ms to 0.8 ms for 4 MHz (Fast clock) - 0.43 ms to 1.28 ms for 100 kHz (Slow clock) See the TraveoTM Platform Hardware Manual in detail. This product series doesn't support clock supervisor output port. (Related register and internal circuit is implemented.) RSTX pin + MD pin simultaneous assert INITX (Same as INITX pin input) - Occurrence factor: Simultaneously inputting "L" level to RSTX pin and inputting "L" level to MD pin - Release factor: Inputting "H" level to RSTX pin See the TraveoTM Platform Hardware Manual in detail. Following resets are not mounted on this device. - SRSTX (and nSRST pin) The product series does not support EX5VRST and writing EX5VRSTCNT bits in SYSC0_SPECFGR has no effect. Document Number: 002-10635 Rev. *H Page 10 of 322 S6J3310/20/30/40 Series Feature Hardware watchdog Standby mode PLL / SSCG PLL External Interrupts NMI Memory Protection Peripheral Protection Internal Memories System SRAM Internal Memories TCRAM Internal Memories Backup RAM Description See the TraveoTM Platform Hardware Manual in detail. Hardware watchdog function stops during PSS mode. In the related register of HWDG_CFG, the bit ALLOWSTOPCLK is always read as 1 (HWDG_CFG.ALLOWSTOPCLK = 1). The product series doesn't support Watchdog Counter Monitor Output port. (Related register and internal circuit is implemented.) See the TraveoTM Platform Hardware Manual in detail. Standby mode with 5 V (or 3 V) single external power supply is available. Turning off the 1.2 V external power supply in standby mode is available. The long term pulse of the indicator PWM can be outputted during RTC Standby mode. See the TraveoTM Platform Hardware Manual in detail. Use case assumption is following. PLL - Sound system clock - Sound frequency master clock - Peripherals - Display clock - Trace clock SSCG - CPU core - GDC core - Hyper BUS - DDR-HSSPI Product supports down spread and center spread modes with the conditions defined in 9.1.4.3 Internal Clock Timing (S6J3310). See the TraveoTM Platform Hardware Manual in detail. See the TraveoTM Platform Hardware Manual in detail. 1 NMI pin. MPU16 AHB: See the TraveoTM Platform Hardware Manual in detail. MPU for AXI: ch.0 MPU for AHB: ch.1 Additional MPU for Graphic sub system, MediaLB and Ethernet AVB. They are described on the chapter of MPU for AHB and MPU for AXI To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK, - Lock: 0x112ABB56 - Unlock: 0xACCABB56 See the TraveoTM Platform Hardware Manual in detail. Protected peripherals are described in the base address map. 384 KByte 1 wait cycle is necessary for RAM read at over 120MHz. 128 KByte 32 KByte Backup RAM can only be operated in RUN mode (normal operation mode). In other mode the memory content should be retained, but it cannot be operated. SLEEP control for Backup RAM is not supported and cannot be used. Document Number: 002-10635 Rev. *H Page 11 of 322 S6J3310/20/30/40 Series Feature Description Embedded Program Flash can be accessed with 0-wait-cycle if CPU frequency is 80MHz or less. 0-wait-cycle: 80MHz or less. 1-wait-cycle: 160MHz or less. 2-wait-cycle: more than 160MHz. Embedded Program/Work Flash Memory Internal Power Domain Power Supply Low Voltage Detection Low voltage detection for RAM retention (RVD) Resource inter-connect I/O Ports A/D Converter CRC Programmable CRC Work Flash can be accessed with 0-wait-cycle if CPU frequency is 12.5MHz or less. 6-wait-cycle: 80MHz or less. 12-wait-cycle: 160MHz or less. The wait-cycle setting see the TraveoTM Platform Hardware Manual in details. The CLK_FCLK maximum frequency should be referred in 9.1.4.3. Erase suspend is supported. Reading and writing to the other sector are possible when Flash Erase is suspended. Serial Flash programing and Parallel Flash programing are supported. Margin mode is not supported. PD1: Always ON PD2: Cortex R5F platform/ GDC/ additional peripherals PD4: Backup RAM in Always On domain PD6: Peripherals in Always On domain * The chapter of the block diagram explains in detail. 5 V, and 3 V, 1.2 V external power supply is required. Built in LDO provides internal power supply for Always On region (PD1). 1.2 V external power supply control pin is supported. 3 V external power supply could be controlled by GPIO. There are constraints of power on/off sequence. LVD for external voltage is supported. LVD for internal voltage is supported. See 9.1.4.11 and 9.1.4.12. RVD for RAM retention is effective during the standby mode only. That is, it is only for the Backup RAM of 32KB that the function is available. The output signal of some resources can be inputted to the other resource. 5 V general purpose I/O 3 V general purpose I/O Multi input level and multi output drivability Pull-up, pull-down function is available. Resource input and output is multiplexed. +B input is allowed many pins of 3.3 V, 5 V and 3.3 V/5 V I/O domain. 12 bit resolution, 2 unit (Unit0 is possible to select channels 4-31. Unit1 is possible to select channels 32-63.) 48 channels of analog input for TEQFP208 48 channels of analog input for TEQFP176 35 channel of analog input for TEQFP144 24 channels of them are shared with the SMC for TEQFP208/176/144 External trigger and timer trigger are available. The description of the A/D converter function should be referred in the S6J3300 Hardware Manual. Though the chapter of I/O port in TraveoTM Platform Hardware Manual describes another A/D converter function, do not refer it. A/D Channel Control Register (ADC12Bn_CHCTRL0) [bit5:0] ANIN[5:0]: Analog Input Selection bits. This register setting is possible of channel 0-31 (the register value is 00_0000 to 01_1111). See the TraveoTM Platform Hardware Manual in detail. DMA support Document Number: 002-10635 Rev. *H Page 12 of 322 S6J3310/20/30/40 Series Feature Sound Generator Sound Waveform generator Sound Mixer PCM-PWM Audio DAC I2S Base Timer Reload Timer I/O Timer Up/Down Counter Multi-Functional Serial (MFS) CAN-FD Real Time Clock (RTC) with auto-calibration DDR High Speed SPI Hyper BUS I/F Stepper Motor Control (SMC) Description Produces sound/melody with varying frequency and amplitude for convenient duration Square wave sound output Automatic linear amplitude increment or decrement Interrupt request generated when specified sound length has ended Sine waveform, saw-tooth waveform and Square waveform are generated with easy configuration of the parameters which specified sound sources. Fade-in and Fade-out control for reverberation. The input channels of 0 - 4 are reserved for waveform generator. Mixing different sampling frequency sounds. Mixing Internal sounds and External I2S input sounds. Saturating addition function for keeping sound quality. Cut a specific frequency data by digital filter. LPF is support by FIR filter. Fade-in and Fade-out control. Conversion of PCM audio streaming to Pulse Width Modulated signals. Supports 2 output channels for stereo and mono data Up to 16-bit output sample resolution Support for half and full H-bridges The sound source of the fixed 48 kHz sampling frequency can be outputted. 1 unit, L/R channels support. BTL connection is available. 2 ch. - I2S0 only supports the output of sound sources. - I2S1 supports both the input and the output. See the TraveoTM Platform Hardware Manual in detail. A unit consists of a pair of 16-bit base timers. 16 units, that is, 32 channels of base timers are available. See the TraveoTM Platform Hardware Manual in detail. See the TraveoTM Platform Hardware Manual in detail. See the TraveoTM Platform Hardware Manual in detail. See the TraveoTM Platform Hardware Manual in detail. Only 2 ports of MFS have the dedicated I/O for I 2C. See I2C timing in 9.1.4.6 Multi-Function Serial in detail. The I2C is not designed to be hot swappable. CTS/RTS is not mounted (hardware flow control is not supported for this series.) Flexible data rate is supported. 16 KB/ch of message RAM is available. The clock output from CAN pre-scaler is supplied to every CAN. ECC error generation function of the message RAM is not supported for this device. Therefore CAN FD ECC Error Insertion Control Register (FDFECR) is not writeable. See the TraveoTM Platform Hardware Manual in detail. ch.0: HSSPI as a MCU peripheral ch.0: Hyper Bus as a MCU peripheral The following register is not supported and cannot be used. - Controller Status Register (HYPERBUSIn_CSR) - Interrupt Enable Register (HYPERBUSIn_IEN) - Interrupt Status Register (HYPERBUSIn_ISR) - Write Protection Register (HYPERBUSIn_WPR) - Test Register (HYPERBUSIn_TEST) GPO signal can only be used for "Internal Control example by GPO" in this product, that is, it can select using HyperBus of PF or using HyperBus of Graphic Sub System. Each channel has 6 motor drivers with high output capability Document Number: 002-10635 Rev. *H Page 13 of 322 S6J3310/20/30/40 Series Feature External Interrupt Capture Unit (EICU) Ethernet AVB MediaLB LCD Controller SHE Source Clock Timer Graphics Subsystem External BUS ARH Power Supply Control (PSC) Description See the TraveoTM Platform Hardware Manual in detail. 10/100 Mbps MII-Interface Supports Audio-Video Bridging (AVB) MOST50 (1024FS) 3 wires Maximum 15 ch is available. TEQFP208: 4 com x 32 seg TEQFP176: 4 com x 32 seg TEQFP144: 4 com x 24 seg LCDC pins are initialized with Reset. (Stop LCDC alternating current output) Duty and Static of segment output is supported. (SEG23/ST0, SEG24/ST1, SEG25/ST2, SEG26/ST3, SEG27/ST4, SEG28/ST5, SEG29/ST6, SEG30/ST7, SEG31/ST8) See the TraveoTM Platform Hardware Manual in detail. See the TraveoTM Platform Hardware Manual in detail. 80 MHz maximum clock frequency Variable setting about GDC clock. (Asynchronous with CPU clock) 480 x 272 pixels maximum frame resolution Video modes up to 25 MHz pixel clock RGB888, Order replacement of RGB pins. TEQFP208: 22 bit address and 16 bit data TEQFP176: 22 bit address and 16 bit data TEQFP144: 15 bit address and 8 bit data 2 ch This device does not have PHY macro and its function. PSC (PSC_1) output is used for external 1.2 V power supply module control and automatically switched with the following condition. "High": Request to supply VCC12 - "Power ON Reset" is released - CPU wakes up from PSS shutdown mode "Low": Request to stop supplying VCC12 - CPU transfers from RUN mode to PSS shutdown mode. For timing chart of output signals include PSC in detail, see the "S6J3300 Hardware Manual" and chapter "State Transition" Document Number: 002-10635 Rev. *H Page 14 of 322 S6J3310/20/30/40 Series 3.2.1 Ethernet The following functions are not supported. Functions Remarks Direct Memory Access Interface. - partial store and forward - force max amba burst tx/rc - Priority Queueing (Screening) External FIFO Interface Additional Low Latency TX FIFO Interface for DMA configurations MAC Transmit Block - half-duplex - collision - back_pressure MAC Filtering Block - external address match - VLAN tag - Wakeup On Lan IEEE 1588 and IEEE 802.1AS Support MAC PFC Priority Based Pause Frame Support Energy Efficient Ethernet support LPI Operation in Cadence IP 802.1Qav Support - Credit Based Shaping PHY Interface - GMII - SGMII - TBI 10/100/1000 Operation - 10 M - 1000 M SGMII Operation Jumbo Frames Physical Control Sub-Layer Document Number: 002-10635 Rev. *H Page 15 of 322 S6J3310/20/30/40 Series 4. Package and Pin Assignment 4.1 Pin Assignment Alphabets with pin numbers are signs specify I/O circuit type. 4.1.1 TEQFP-208 Pin Assignment 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 S S S S S S S S2 S S S S S S S S S S S Q Q P Q P P P Q P P P Q P P Q P P P Q P P P P P - VSS P2_19 P2_18 P2_17 P2_16 P2_15 P2_14 P2_13 P2_12 P2_11 P2_10 P3_31 P3_30 P3_29 P3_28 VCC53 VSS VCC12 P2_09 P3_27 P3_26 P3_25 P3_24 P4_31 P4_30 DVCC DVSS P2_08 P4_29 P2_07 P2_06 P2_05 P4_28 P2_04 P2_03 P2_02 P4_27 P2_01 DVCC DVSS P2_00 P4_26 P1_31 P1_30 P1_29 P4_25 P1_28 P1_27 P1_26 P4_24 P1_25 DVCC DSP0_R6_0 DSP0_R5_0 DSP0_R4_0 DSP0_R3_0 DSP0_R2_0 DSP0_R1_0 DSP0_R0_0 DSP0_CLK_0 DSP0_VSYNC_0 DSP0_HSYNC_0 MDATA15 MDATA14 MDATA13 MDATA12 DSP0_EN_0 I2S0_SCK_1 I2S0_WS_1 I2S0_SD_1 I2S0_ECLK_1 EINT10_5 EINT2_1 AN63 EINT8_5 AN62 AN61 AN60 EINT5_5 AN59 AN58 AN57 EINT1_5 AN56 AN55 EINT23_4 AN54 AN53 AN52 EINT19_4 AN51 AN50 AN49 AN47 - MAD0 MDATA7 MDATA6 MDATA5 MDATA4 MDATA3 MDATA2 MDATA1 MDATA0 MCSX1 SEG8 SEG7 SEG6 SEG5 MCSX0 MDATA11 MDATA10 MDATA9 MDATA8 PWM2M5 PWM2P5 PWM1M5 PWM1P5 PWM2M4 PWM2P4 PWM1M4 PWM1P4 PWM2M3 PWM2P3 PWM1M3 PWM1P3 PWM2M2 PWM2P2 PWM1M2 EINT16_4 PWM1P2 - SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 EINT18_5 EINT17_5 EINT16_5 EINT3_1 SEG4 SEG3 SEG2 SEG1 SEG0 SCK2_1 SIN2_1 EINT9_5 EINT7_5 EINT6_5 EINT23_0 EINT4_5 EINT3_5 EINT2_5 EINT0_5 EINT22_0 EINT22_4 EINT21_4 EINT20_4 EINT21_0 EINT18_4 EINT17_4 EINT15_4 - EINT3_6 EINT2_6 EINT1_6 EINT0_6 EINT23_5 EINT22_5 EINT0_0 EINT21_5 ADTRG1_2 ADTRG0_1 PPG12/13/14/15_TIN1_1 PPG15_TOUT2_1 PPG15_TOUT0_1 PPG14_TOUT2_1 EINT15_5 EINT14_5 EINT13_5 EINT12_5 EINT11_5 SCS120_0 SOT12_0 PPG12/13/14/15_TIN1_0 PPG15_TOUT2_0 PPG15_TOUT0_0 PPG14_TOUT2_0 PPG14_TOUT0_0 PPG13_TOUT2_0 PPG13_TOUT0_0 PPG12_TOUT2_0 PPG12_TOUT0_0 PPG6/7/8/9/10/11_TIN1_0 PPG11_TOUT2_0 PPG11_TOUT0_0 PPG10_TOUT2_0 PPG10_TOUT0_0 - SCS41_0 SCS40_0 SOT4_0 SCK4_0 SIN4_0 SCS33_1 EINT20_5 EINT19_5 SCS30_1 SOT3_1 SCK3_1 SIN3_1 PPG14_TOUT0_1 PPG13_TOUT2_1 PPG13_TOUT0_1 PPG12_TOUT2_1 PPG12_TOUT0_1 SDA12 SCK12_0 SIN12_0 SCS111_0 SCS110_0 SOT11_0 SCK11_0 SIN11_0 SCS100_0 SOT10_0 SCK10_0 SIN10_0 SCS91_0 SCS90_0 SOT9_0 - SCS43_0 SCS42_0 LCDD2 LCDD1 SDA4 SCL4 SCS32_1 SCS31_1 SCS23_1 SCS22_1 SCS21_1 SCS20_1 SOT2_1 SCL12 SDA11 SCL11 SDA10 SCL10 SDA9 - LCDD4 LCDD3 LCDD0 - - - - - - - Figure 4-1: TEQFP-208 (S6J331xKyz *1) - - LCDD11 LCDD12 - ARH0_AIC1_UPCLK ARH0_AIC1_UPDATA1 LCDD14 LCDD15 - LCDD7 LCDD10 ARH0_AIC1_RCK ARH0_AIC1_RDA1 LCDD13 ARH0_AIC0_TCKI ARH0_AIC0_DNDATA1 - LCDD6 ARH0_AIC1_DNDATA1 LCDD8 LCDD9 ARH0_AIC1_DNDATA0 SCK0_1 SCS00_1 ARH0_AIC1_UPDATA0 ARH0_AIC0_DNCLK ARH0_AIC0_TDA1 LCDD16 LCDD17 CS# RS RES# TE - ARH0_AIC1_TCKI ARH0_AIC1_TDA1 ARH0_AIC1_dbg_out_1 ARH0_AIC1_dbg_out_0 ARH0_AIC1_TDA0 SCS12_0 SCS13_0 ARH0_AIC1_RDA0 SIN17_1 SCS171_1 ARH0_AIC0_dbg_out_1 ARH0_AIC0_dbg_out_0 ARH0_AIC0_dbg_select WR# ARH0_AIC0_DNDATA0 ARH0_AIC0_UPCLK ARH0_AIC0_UPDATA1 ARH0_AIC0_UPDATA0 - ARH0_AIC1_DNCLK SCL1 SDA1 SIN0_1 SOT0_1 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 PPG3_TOUT2_1 ARH0_AIC1_dbg_select RD# ARH0_AIC0_TDA0 SCS43_1 ARH0_AIC0_RCK ARH0_AIC0_RDA1 ARH0_AIC0_RDA0 - LCDD5 SIN1_0 SCK1_0 SOT1_0 SCS10_0 SCS11_0 EINT15_1 EINT23_1 EINT0_2 EINT1_2 SCS170_1 SCK17_1 EINT5_2 EINT6_2 EINT7_2 EINT8_2 SIN1_1 SCK1_1 SOT1_1 SCS10_1 SCS11_1 SCS12_1 SCS13_1 SCK4_1 SCS40_1 SCS41_1 EINT21_2 EINT22_2 EINT23_2 EINT0_3 - EINT0_1 EINT1_0 EINT4_1 EINT5_1 RX0_2 TX0_2 EINT11_1 EINT13_1 SEG25 SEG26 SEG27 SEG28 RX3_2 TX3_2 SOT17_1 SEG29 SEG30 SEG31 COM0 PPG4_TOUT0_1 PPG4_TOUT2_1 PPG5_TOUT0_1 PPG5_TOUT2_1 PPG0/1/2/3/4/5_TIN1_1 SIN4_1 SOT4_1 EINT17_2 EINT18_2 EINT19_2 V0 V1 V2 V3 - SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 EINT1_1 EINT9_2 EINT10_2 EINT11_2 EINT12_2 EINT15_2 EINT16_2 COM1 COM2 COM3 SCS42_1 MDQM0 MCSX2 MCSX3 MRDY - MAD1 MAD2 MAD3 MAD4 EINT7_1 EINT9_1 EINT10_1 MAD5 MAD6 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 EINT2_2 EINT3_2 EINT4_2 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 MAD15 MAD16 MAD17 MAD18 MAD19 EINT13_2 EINT14_2 MAD20 MAD21 MOEX MWEX MCLK EINT20_2 DSP0_B7_0 MDC_1 COL_1 CRS_1 - DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 RXCLK_1 RXER_1 RXDV_1 DSP0_G3_0 DSP0_G4_0 I2S1_ECLK_0 I2S1_SD_0 I2S1_WS_0 I2S1_SCK_0 TXCLK_1 TXEN_1 TXD0_1 I2S0_ECLK_0 I2S0_SD_0 I2S0_WS_0 I2S0_SCK_0 TXD1_1 TXD2_1 TXD3_1 TXER_1 RXD0_1 RXD1_1 RXD2_1 RXD3_1 MDIO_1 DSP0_B5_0 DSP0_B6_0 DSP0_B7_1 MDQM1 RXCLK_0 RXER_0 RXDV_0 TXCLK_0 - VCC53 P0_00 P0_01 P0_02 P0_03 P4_00 P4_01 P4_02 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P4_03 P4_04 P4_05 P0_10 P0_11 P0_12 P0_13 VCC53 VSS VCC12 P3_00 P3_01 P3_02 P3_03 P3_04 P4_06 P4_07 P3_05 P3_06 P0_14 P0_15 P0_16 P3_07 P0_17 P0_18 P0_19 P0_20 VCC53 VSS AVSS DAC_R C_R AVSS AVCC3_DAC DAC_L C_L AVSS VSS S S S S T T T S S S S S S T T T S S S S T T T T T T T T T S S S T V V V U A A A A - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 TOP VIEW TEQFP-208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 P P P P P P P P G E H G G G G G H G G G G E E E O D N G G G G L2 L2 L2 M L K K - DVSS P1_24 P1_23 P1_22 P1_21 P1_20 P1_19 P1_18 P1_17 DVCC DVSS AVSS AVRL5 AVRH5 AVCC5 P4_23 P4_22 P1_16 P4_21 P4_20 P4_19 VCC5 VSS VCC12 VCC12 P4_18 P4_17 P1_15 P1_14 P3_23 P3_22 P3_21 P3_20 P3_19 P3_18 VSS C MODE PSC_1 RSTX P4_16 P3_17 P3_16 P1_13 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_NTRST X0 X1 VSS AN46 AN45 AN44 AN43 AN42 AN41 AN40 AN39 ADTRG1_0 ADTRG0_0 AN32 AN31 AN30 AN29 AN28 EINT2_4 EINT17_1 EINT20_1 AN26 AN25 AN24 - PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 EINT10_4 EINT22_1 EINT8_4 EINT7_4 EINT16_1 EINT6_4 EINT5_4 EINT16_0 EINT15_0 EINT4_4 EINT19_1 EINT3_4 PPG6/7/8/9/10/11_TIN1_1 PPG11_TOUT2_1 PPG11_TOUT0_1 EINT1_4 EINT0_4 EINT14_1 EINT14_0 - EINT14_4 EINT20_0 EINT13_4 EINT19_0 EINT12_4 EINT18_0 EINT11_4 EINT17_0 EINT9_4 SGA4_0 SGO3_0 TX6_1 RX6_1 TOT49_1 TIN49_1 OCU10_OTD1_1 OCU10_OTD0_1 SGO4_1 SGA4_1 SGA3_0 - PPG9_TOUT2_0 PPG9_TOUT0_0 PPG8_TOUT2_0 PPG8_TOUT0_0 PPG7_TOUT2_0 PPG7_TOUT0_0 PPG6_TOUT2_0 PPG6_TOUT0_0 SGO4_0 SCK16_1 SIN12_1 SOT12_1 PPG5_TOUT2_0 PPG5_TOUT0_0 SCS120_1 SCS91_1 SCS90_1 TX5_1 ICU10_IN1_1 ICU10_IN0_1 PPG10_TOUT2_1 PPG10_TOUT0_1 OCU9_OTD0_0 - SCK9_0 SIN9_0 TX6_0 RX6_0 SCK8_0 SIN8_0 TX5_0 RX5_0 SCS160_1 SCS161_1 PPG0/1/2/3/4/5_TIN1_0 SOT16_1 SIN16_1 OCU10_OTD0_0 OCU9_OTD1_0 SOT9_1 RX5_1 SIN9_1 OCU9_OTD1_1 OCU9_OTD0_1 TIN48_0 - SCL9 SCS80_0 SOT8_0 SCL8 SCS171_0 SCS170_0 OCU10_OTD1_0 ICU10_IN1_0 ICU10_IN0_0 SCK9_1 ICU9_IN1_1 ICU9_IN0_1 RX3_0 - SDA8 TOT49_0 TIN49_0 TOT48_0 TOT48_1 TIN48_1 - SOT17_0 SCK17_0 TX3_0 TX3_1 RX3_1 - SDA17 SCK12_1 SIN17_0 - WOT SCL17 SYSC0_CLK_1 - SYSC0_CLK_0 INDICATOR0_1 - - - 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 R R I G G H G G H G G G G G G G G G G G G G G G G G G C C C B B B B B B B B B B B VCC5 X1A X0A NMIX P4_15 P4_14 P1_10 P4_13 P4_12 P1_09 P1_08 P1_07 P3_15 P3_14 P1_06 P1_05 P3_13 P3_12 P1_04 P1_03 P3_11 P3_10 P3_09 P3_08 P4_11 P4_10 P4_09 P4_08 VCC5 VSS VCC12 VCC12 P1_02 P1_01 P1_00 VCC3 VSS P0_31 P0_30 P0_29 P0_28 P0_27 VCC3 VSS P0_26 VSS P0_25 P0_24 P0_23 P0_22 P0_21 VCC3 P1_12 P1_11 AN21 AN18 AN17 AN16 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 MLBDAT MLBSIG MLBCLK M_SDATA1_3 M_SSEL1 M_SDATA1_1 M_SDATA1_2 M_SDATA1_0 M_SCLK0 M_SDATA0_3 M_SSEL0 M_SDATA0_1 M_SDATA0_2 M_SDATA0_0 EINT13_0 EINT12_0 EINT23_3 EINT22_3 EINT11_0 EINT21_3 EINT20_3 EINT10_0 ADTRG1_1 EINT8_0 EINT19_3 EINT12_1 EINT7_0 EINT6_0 EINT18_3 EINT21_1 EINT5_0 EINT4_0 EINT8_1 EINT17_3 EINT6_1 EINT18_1 EINT16_3 EINT15_3 EINT14_3 EINT13_3 CRS_0 COL_0 M_CS#_2 M_DQ7 M_DQ6 M_DQ5 M_DQ4 M_RWDS M_CK M_CS#_1 M_DQ0 M_DQ1 M_DQ2 M_DQ3 PPG4_TOUT2_0 PPG4_TOUT0_0 AP1(AH1) AN1(AL1) EINT9_0 BN1(BL1) SGO3_1 SGA3_1 AP0(AH0) AN0(AL0) SGO2_1 SGA2_1 BP0(BH0) BN0(BL0) SGO1_1 SGA1_1 SGO0_1 SGA0_1 EINT12_3 EINT11_3 MDC_0 MDIO_0 RXD3_0 RXD2_0 RXD1_0 RXD0_0 TXER_0 TXD3_0 TXD2_0 TXD1_0 TXD0_0 TXEN_0 OCU8_OTD1_0 OCU8_OTD0_0 SGO2_0 SGA2_0 BP1(BH1) SGA1_0 PPG9_TOUT2_1 PPG9_TOUT0_1 SGO0_0 SGA0_0 PPG8_TOUT2_1 PPG8_TOUT0_1 PPG0_TOUT2_0 PPG0_TOUT0_0 PPG7_TOUT2_1 SCS33_0 SCS32_0 EINT10_3 EINT9_3 EINT8_3 EINT7_3 EINT3_0 EINT6_3 EINT5_3 EINT4_3 EINT3_3 EINT2_3 EINT1_3 EINT2_0 ICU9_IN1_0 ICU9_IN0_0 PPG3_TOUT2_0 PPG3_TOUT0_0 SGO1_0 PPG2_TOUT0_0 OCU8_OTD1_1 OCU8_OTD0_1 PPG1_TOUT2_0 PPG1_TOUT0_0 OCU2_OTD1_1 OCU2_OTD0_1 OCU0_OTD1_0 OCU0_OTD0_0 OCU1_OTD1_1 PPG7_TOUT0_1 PPG6_TOUT2_1 PPG6_TOUT0_1 SCS31_0 SCS30_0 SOT3_0 SCK3_0 SIN3_0 SCS23_0 SCS22_0 SCS21_0 SCS20_0 SOT2_0 SCK2_0 SIN2_0 TOT17_0 TIN17_0 OCU2_OTD1_0 OCU2_OTD0_0 PPG2_TOUT2_0 OCU1_OTD0_0 ICU8_IN1_1 ICU8_IN0_1 ICU1_IN1_0 ICU1_IN0_0 ICU2_IN1_1 ICU2_IN0_1 ICU0_IN1_0 ICU0_IN0_0 ICU1_IN1_1 OCU1_OTD0_1 OCU0_OTD1_1 OCU0_OTD0_1 SCS80_2 SOT8_2 SCK8_2 SIN8_2 SCS91_2 SCS90_2 SCK9_2 SOT9_2 SIN9_2 TX2_0 RX2_0 ICU8_IN1_0 ICU8_IN0_0 OCU1_OTD1_0 ICU2_IN0_0 TOT17_1 TIN17_1 AIN9 ZIN8 TOT16_1 TIN16_1 BIN8 AIN8 TOT1_1 ICU1_IN0_1 ICU0_IN1_1 ICU0_IN0_1 SCS161_0 SCS160_0 SOT16_0 SCK16_0 ICU2_IN1_0 BIN9 TX2_1 RX2_1 TOT1_0 TIN1_0 SCK10_1 TX1_1 TOT0_0 TIN0_0 RX1_1 TIN1_1 TOT0_1 TIN0_1 INDICATOR0_0 SDA16 SCL16 ZIN9 TIN16_0 SCS100_1 SOT10_1 TX0_0 RX0_0 TRACE3_1 SIN10_1 FRT4/8/9/10_TEXT FRT0/1/2/3_TEXT SCS80_1 TX0_1 RX0_1 SIN8_1 TRACE_CLK_0 TRACE_CTL_0 TOT16_0 RX1_0 TRACE_CLK_1 TRACE_CTL_1 SCS00_0 SOT0_0 TRACE2_1 SCK0_0 SIN0_0 TRACE1_1 SOT8_1 SCK8_1 TX1_0 TRACE2_0 TRACE1_0 SDA0 SCL0 TRACE0_1 SIN16_0 TRACE0_0 TRACE3_0 - *1: x, y, z are selected from the following parameters: x: E, D, C, B (Memory Size) y: S, A, B, U, C, D, T, E, F, V, G, H (Option) z: C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 16 of 322 S6J3310/20/30/40 Series 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 S S S S S S S S2 S S S S S S S S S S S Q Q P Q P P P Q P P P Q P P Q P P P Q P P P P P - VSS P2_19 P2_18 P2_17 P2_16 P2_15 P2_14 P2_13 P2_12 P2_11 P2_10 P3_31 P3_30 P3_29 P3_28 VCC53 VSS VCC12 P2_09 P3_27 P3_26 P3_25 P3_24 P4_31 P4_30 DVCC DVSS P2_08 P4_29 P2_07 P2_06 P2_05 P4_28 P2_04 P2_03 P2_02 P4_27 P2_01 DVCC DVSS P2_00 P4_26 P1_31 P1_30 P1_29 P4_25 P1_28 P1_27 P1_26 P4_24 P1_25 DVCC DSP0_R6_0 DSP0_R5_0 DSP0_R4_0 DSP0_R3_0 DSP0_R2_0 DSP0_R1_0 DSP0_R0_0 DSP0_CLK_0 DSP0_VSYNC_0 DSP0_HSYNC_0 MDATA15 MDATA14 MDATA13 MDATA12 DSP0_EN_0 I2S0_SCK_1 I2S0_WS_1 I2S0_SD_1 I2S0_ECLK_1 EINT10_5 EINT2_1 AN63 EINT8_5 AN62 AN61 AN60 EINT5_5 AN59 AN58 AN57 EINT1_5 AN56 AN55 EINT23_4 AN54 AN53 AN52 EINT19_4 AN51 AN50 AN49 AN47 - MAD0 MDATA7 MDATA6 MDATA5 MDATA4 MDATA3 MDATA2 MDATA1 MDATA0 MCSX1 SEG8 SEG7 SEG6 SEG5 MCSX0 MDATA11 MDATA10 MDATA9 MDATA8 PWM2M5 PWM2P5 PWM1M5 PWM1P5 PWM2M4 PWM2P4 PWM1M4 PWM1P4 PWM2M3 PWM2P3 PWM1M3 PWM1P3 PWM2M2 PWM2P2 PWM1M2 EINT16_4 PWM1P2 - SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 EINT18_5 EINT17_5 EINT16_5 EINT3_1 SEG4 SEG3 SEG2 SEG1 SEG0 SCK2_1 SIN2_1 EINT9_5 EINT7_5 EINT6_5 EINT23_0 EINT4_5 EINT3_5 EINT2_5 EINT0_5 EINT22_0 EINT22_4 EINT21_4 EINT20_4 EINT21_0 EINT18_4 EINT17_4 EINT15_4 - EINT3_6 EINT2_6 EINT1_6 EINT0_6 EINT23_5 EINT22_5 EINT0_0 EINT21_5 ADTRG1_2 ADTRG0_1 PPG12/13/14/15_TIN1_1 PPG15_TOUT2_1 PPG15_TOUT0_1 PPG14_TOUT2_1 EINT15_5 EINT14_5 EINT13_5 EINT12_5 EINT11_5 SCS120_0 SOT12_0 PPG12/13/14/15_TIN1_0 PPG15_TOUT2_0 PPG15_TOUT0_0 PPG14_TOUT2_0 PPG14_TOUT0_0 PPG13_TOUT2_0 PPG13_TOUT0_0 PPG12_TOUT2_0 PPG12_TOUT0_0 PPG6/7/8/9/10/11_TIN1_0 PPG11_TOUT2_0 PPG11_TOUT0_0 PPG10_TOUT2_0 PPG10_TOUT0_0 - SCS41_0 SCS40_0 SOT4_0 SCK4_0 SIN4_0 SCS33_1 EINT20_5 EINT19_5 SCS30_1 SOT3_1 SCK3_1 SIN3_1 PPG14_TOUT0_1 PPG13_TOUT2_1 PPG13_TOUT0_1 PPG12_TOUT2_1 PPG12_TOUT0_1 SDA12 SCK12_0 SIN12_0 SCS111_0 SCS110_0 SOT11_0 SCK11_0 SIN11_0 SCS100_0 SOT10_0 SCK10_0 SIN10_0 SCS91_0 SCS90_0 SOT9_0 - SCS43_0 SCS42_0 LCDD2 LCDD1 SDA4 SCL4 SCS32_1 SCS31_1 SCS23_1 SCS22_1 SCS21_1 SCS20_1 SOT2_1 SCL12 SDA11 SCL11 SDA10 SCL10 SDA9 - LCDD4 LCDD3 LCDD0 - - - - - - - Figure 4-2: TEQFP-208 (S6J332xKyz *1) - - LCDD11 LCDD12 - LCDD14 LCDD15 - LCDD7 LCDD10 LCDD13 - LCDD6 LCDD8 LCDD9 SCK0_1 SCS00_1 LCDD16 LCDD17 CS# RS RES# TE - SCS12_0 SCS13_0 SIN17_1 SCS171_1 WR# - SCL1 SDA1 SIN0_1 SOT0_1 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 PPG3_TOUT2_1 RD# SCS43_1 - LCDD5 SIN1_0 SCK1_0 SOT1_0 SCS10_0 SCS11_0 EINT15_1 EINT23_1 EINT0_2 EINT1_2 SCS170_1 SCK17_1 EINT5_2 EINT6_2 EINT7_2 EINT8_2 SIN1_1 SCK1_1 SOT1_1 SCS10_1 SCS11_1 SCS12_1 SCS13_1 SCK4_1 SCS40_1 SCS41_1 EINT21_2 EINT22_2 EINT23_2 EINT0_3 - EINT0_1 EINT1_0 EINT4_1 EINT5_1 RX0_2 TX0_2 EINT11_1 EINT13_1 SEG25 SEG26 SEG27 SEG28 RX3_2 TX3_2 SOT17_1 SEG29 SEG30 SEG31 COM0 PPG4_TOUT0_1 PPG4_TOUT2_1 PPG5_TOUT0_1 PPG5_TOUT2_1 PPG0/1/2/3/4/5_TIN1_1 SIN4_1 SOT4_1 EINT17_2 EINT18_2 EINT19_2 V0 V1 V2 V3 - SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 EINT1_1 EINT9_2 EINT10_2 EINT11_2 EINT12_2 EINT15_2 EINT16_2 COM1 COM2 COM3 SCS42_1 MDQM0 MCSX2 MCSX3 MRDY - MAD1 MAD2 MAD3 MAD4 EINT7_1 EINT9_1 EINT10_1 MAD5 MAD6 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 EINT2_2 EINT3_2 EINT4_2 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 MAD15 MAD16 MAD17 MAD18 MAD19 EINT13_2 EINT14_2 MAD20 MAD21 MOEX MWEX MCLK EINT20_2 DSP0_B7_0 MDC_1 COL_1 CRS_1 - DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 RXCLK_1 RXER_1 RXDV_1 DSP0_G3_0 DSP0_G4_0 I2S1_ECLK_0 I2S1_SD_0 I2S1_WS_0 I2S1_SCK_0 TXCLK_1 TXEN_1 TXD0_1 I2S0_ECLK_0 I2S0_SD_0 I2S0_WS_0 I2S0_SCK_0 TXD1_1 TXD2_1 TXD3_1 TXER_1 RXD0_1 RXD1_1 RXD2_1 RXD3_1 MDIO_1 DSP0_B5_0 DSP0_B6_0 DSP0_B7_1 MDQM1 RXCLK_0 RXER_0 RXDV_0 TXCLK_0 - VCC53 P0_00 P0_01 P0_02 P0_03 P4_00 P4_01 P4_02 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P4_03 P4_04 P4_05 P0_10 P0_11 P0_12 P0_13 VCC53 VSS VCC12 P3_00 P3_01 P3_02 P3_03 P3_04 P4_06 P4_07 P3_05 P3_06 P0_14 P0_15 P0_16 P3_07 P0_17 P0_18 P0_19 P0_20 VCC53 VSS AVSS DAC_R C_R AVSS AVCC3_DAC DAC_L C_L AVSS VSS S S S S T T T S S S S S S T T T S S S S T T T T T T T T T S S S T V V V U A A A A - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 TOP VIEW TEQFP-208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 P P P P P P P P G E H G G G G G H G G G G E E E O D N G G G G L2 L2 L2 M L K K - DVSS P1_24 P1_23 P1_22 P1_21 P1_20 P1_19 P1_18 P1_17 DVCC DVSS AVSS AVRL5 AVRH5 AVCC5 P4_23 P4_22 P1_16 P4_21 P4_20 P4_19 VCC5 VSS VCC12 VCC12 P4_18 P4_17 P1_15 P1_14 P3_23 P3_22 P3_21 P3_20 P3_19 P3_18 VSS C MODE PSC_1 RSTX P4_16 P3_17 P3_16 P1_13 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_NTRST X0 X1 VSS AN46 AN45 AN44 AN43 AN42 AN41 AN40 AN39 ADTRG1_0 ADTRG0_0 AN32 AN31 AN30 AN29 AN28 EINT2_4 EINT17_1 EINT20_1 AN26 AN25 AN24 - PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 EINT10_4 EINT22_1 EINT8_4 EINT7_4 EINT16_1 EINT6_4 EINT5_4 EINT16_0 EINT15_0 EINT4_4 EINT19_1 EINT3_4 PPG6/7/8/9/10/11_TIN1_1 PPG11_TOUT2_1 PPG11_TOUT0_1 EINT1_4 EINT0_4 EINT14_1 EINT14_0 - EINT14_4 EINT20_0 EINT13_4 EINT19_0 EINT12_4 EINT18_0 EINT11_4 EINT17_0 EINT9_4 SGA4_0 SGO3_0 TX6_1 RX6_1 TOT49_1 TIN49_1 OCU10_OTD1_1 OCU10_OTD0_1 SGO4_1 SGA4_1 SGA3_0 - PPG9_TOUT2_0 PPG9_TOUT0_0 PPG8_TOUT2_0 PPG8_TOUT0_0 PPG7_TOUT2_0 PPG7_TOUT0_0 PPG6_TOUT2_0 PPG6_TOUT0_0 SGO4_0 SCK16_1 SIN12_1 SOT12_1 PPG5_TOUT2_0 PPG5_TOUT0_0 SCS120_1 SCS91_1 SCS90_1 TX5_1 ICU10_IN1_1 ICU10_IN0_1 PPG10_TOUT2_1 PPG10_TOUT0_1 OCU9_OTD0_0 - SCK9_0 SIN9_0 TX6_0 RX6_0 SCK8_0 SIN8_0 TX5_0 RX5_0 SCS160_1 SCS161_1 PPG0/1/2/3/4/5_TIN1_0 SOT16_1 SIN16_1 OCU10_OTD0_0 OCU9_OTD1_0 SOT9_1 RX5_1 SIN9_1 OCU9_OTD1_1 OCU9_OTD0_1 TIN48_0 - SCL9 SCS80_0 SOT8_0 SCL8 SCS171_0 SCS170_0 OCU10_OTD1_0 ICU10_IN1_0 ICU10_IN0_0 SCK9_1 ICU9_IN1_1 ICU9_IN0_1 RX3_0 - SDA8 TOT49_0 TIN49_0 TOT48_0 TOT48_1 TIN48_1 - SOT17_0 SCK17_0 TX3_0 TX3_1 RX3_1 - SDA17 SCK12_1 SIN17_0 - WOT SCL17 SYSC0_CLK_1 - SYSC0_CLK_0 INDICATOR0_1 - 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 R R I G G H G G H G G G G G G G G G G G G G G G G G G C C C B B B B B B B B B B B VCC5 X1A X0A NMIX P4_15 P4_14 P1_10 P4_13 P4_12 P1_09 P1_08 P1_07 P3_15 P3_14 P1_06 P1_05 P3_13 P3_12 P1_04 P1_03 P3_11 P3_10 P3_09 P3_08 P4_11 P4_10 P4_09 P4_08 VCC5 VSS VCC12 VCC12 P1_02 P1_01 P1_00 VCC3 VSS P0_31 P0_30 P0_29 P0_28 P0_27 VCC3 VSS P0_26 VSS P0_25 P0_24 P0_23 P0_22 P0_21 VCC3 P1_12 P1_11 AN21 AN18 AN17 AN16 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 MLBDAT MLBSIG MLBCLK M_SDATA1_3 M_SSEL1 M_SDATA1_1 M_SDATA1_2 M_SDATA1_0 M_SCLK0 M_SDATA0_3 M_SSEL0 M_SDATA0_1 M_SDATA0_2 M_SDATA0_0 EINT13_0 EINT12_0 EINT23_3 EINT22_3 EINT11_0 EINT21_3 EINT20_3 EINT10_0 ADTRG1_1 EINT8_0 EINT19_3 EINT12_1 EINT7_0 EINT6_0 EINT18_3 EINT21_1 EINT5_0 EINT4_0 EINT8_1 EINT17_3 EINT6_1 EINT18_1 EINT16_3 EINT15_3 EINT14_3 EINT13_3 CRS_0 COL_0 M_CS#_2 M_DQ7 M_DQ6 M_DQ5 M_DQ4 M_RWDS M_CK M_CS#_1 M_DQ0 M_DQ1 M_DQ2 M_DQ3 PPG4_TOUT2_0 PPG4_TOUT0_0 AP1(AH1) AN1(AL1) EINT9_0 BN1(BL1) SGO3_1 SGA3_1 AP0(AH0) AN0(AL0) SGO2_1 SGA2_1 BP0(BH0) BN0(BL0) SGO1_1 SGA1_1 SGO0_1 SGA0_1 EINT12_3 EINT11_3 MDC_0 MDIO_0 RXD3_0 RXD2_0 RXD1_0 RXD0_0 TXER_0 TXD3_0 TXD2_0 TXD1_0 TXD0_0 TXEN_0 OCU8_OTD1_0 OCU8_OTD0_0 SGO2_0 SGA2_0 BP1(BH1) SGA1_0 PPG9_TOUT2_1 PPG9_TOUT0_1 SGO0_0 SGA0_0 PPG8_TOUT2_1 PPG8_TOUT0_1 PPG0_TOUT2_0 PPG0_TOUT0_0 PPG7_TOUT2_1 SCS33_0 SCS32_0 EINT10_3 EINT9_3 EINT8_3 EINT7_3 EINT3_0 EINT6_3 EINT5_3 EINT4_3 EINT3_3 EINT2_3 EINT1_3 EINT2_0 ICU9_IN1_0 ICU9_IN0_0 PPG3_TOUT2_0 PPG3_TOUT0_0 SGO1_0 PPG2_TOUT0_0 OCU8_OTD1_1 OCU8_OTD0_1 PPG1_TOUT2_0 PPG1_TOUT0_0 OCU2_OTD1_1 OCU2_OTD0_1 OCU0_OTD1_0 OCU0_OTD0_0 OCU1_OTD1_1 PPG7_TOUT0_1 PPG6_TOUT2_1 PPG6_TOUT0_1 SCS31_0 SCS30_0 SOT3_0 SCK3_0 SIN3_0 SCS23_0 SCS22_0 SCS21_0 SCS20_0 SOT2_0 SCK2_0 SIN2_0 TOT17_0 TIN17_0 OCU2_OTD1_0 OCU2_OTD0_0 PPG2_TOUT2_0 OCU1_OTD0_0 ICU8_IN1_1 ICU8_IN0_1 ICU1_IN1_0 ICU1_IN0_0 ICU2_IN1_1 ICU2_IN0_1 ICU0_IN1_0 ICU0_IN0_0 ICU1_IN1_1 OCU1_OTD0_1 OCU0_OTD1_1 OCU0_OTD0_1 SCS80_2 SOT8_2 SCK8_2 SIN8_2 SCS91_2 SCS90_2 SCK9_2 SOT9_2 SIN9_2 TX2_0 RX2_0 ICU8_IN1_0 ICU8_IN0_0 OCU1_OTD1_0 ICU2_IN0_0 TOT17_1 TIN17_1 AIN9 ZIN8 TOT16_1 TIN16_1 BIN8 AIN8 TOT1_1 ICU1_IN0_1 ICU0_IN1_1 ICU0_IN0_1 SCS161_0 SCS160_0 SOT16_0 SCK16_0 ICU2_IN1_0 BIN9 TX2_1 RX2_1 TOT1_0 TIN1_0 SCK10_1 TX1_1 TOT0_0 TIN0_0 RX1_1 TIN1_1 TOT0_1 TIN0_1 INDICATOR0_0 SDA16 SCL16 ZIN9 TIN16_0 SCS100_1 SOT10_1 TX0_0 RX0_0 TRACE3_1 SIN10_1 FRT4/8/9/10_TEXT FRT0/1/2/3_TEXT SCS80_1 TX0_1 RX0_1 SIN8_1 TRACE_CLK_0 TRACE_CTL_0 TOT16_0 RX1_0 TRACE_CLK_1 TRACE_CTL_1 SCS00_0 SOT0_0 TRACE2_1 SCK0_0 SIN0_0 TRACE1_1 SOT8_1 SCK8_1 TX1_0 TRACE2_0 TRACE1_0 SDA0 SCL0 TRACE0_1 SIN16_0 TRACE0_0 TRACE3_0 - *1: x, y, z are selected from the following parameters: x: E, D, C, B (Memory Size) y: S, A, B, U, C, D, T, E, F, V, G, H (Option) z: C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 17 of 322 - - S6J3310/20/30/40 Series 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 S S S S S S S S2 S S S S S S S S S S S Q Q P Q P P P Q P P P Q P P Q P P P Q P P P P P - VSS P2_19 P2_18 P2_17 P2_16 P2_15 P2_14 P2_13 P2_12 P2_11 P2_10 P3_31 P3_30 P3_29 P3_28 VCC53 VSS VCC12 P2_09 P3_27 P3_26 P3_25 P3_24 P4_31 P4_30 DVCC DVSS P2_08 P4_29 P2_07 P2_06 P2_05 P4_28 P2_04 P2_03 P2_02 P4_27 P2_01 DVCC DVSS P2_00 P4_26 P1_31 P1_30 P1_29 P4_25 P1_28 P1_27 P1_26 P4_24 P1_25 DVCC DSP0_R6_0 DSP0_R5_0 DSP0_R4_0 DSP0_R3_0 DSP0_R2_0 DSP0_R1_0 DSP0_R0_0 DSP0_CLK_0 DSP0_VSYNC_0 DSP0_HSYNC_0 MDATA15 MDATA14 MDATA13 MDATA12 DSP0_EN_0 EINT10_5 EINT2_1 AN63 EINT8_5 AN62 AN61 AN60 EINT5_5 AN59 AN58 AN57 EINT1_5 AN56 AN55 EINT23_4 AN54 AN53 AN52 EINT19_4 AN51 AN50 AN49 AN47 - MAD0 MDATA7 MDATA6 MDATA5 MDATA4 MDATA3 MDATA2 MDATA1 MDATA0 MCSX1 SEG8 SEG7 SEG6 SEG5 MCSX0 MDATA11 MDATA10 MDATA9 MDATA8 PWM2M5 PWM2P5 PWM1M5 PWM1P5 PWM2M4 PWM2P4 PWM1M4 PWM1P4 PWM2M3 PWM2P3 PWM1M3 PWM1P3 PWM2M2 PWM2P2 PWM1M2 EINT16_4 PWM1P2 - SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 EINT18_5 EINT17_5 EINT16_5 EINT3_1 SEG4 SEG3 SEG2 SEG1 SEG0 SCK2_1 SIN2_1 EINT9_5 EINT7_5 EINT6_5 EINT23_0 EINT4_5 EINT3_5 EINT2_5 EINT0_5 EINT22_0 EINT22_4 EINT21_4 EINT20_4 EINT21_0 EINT18_4 EINT17_4 EINT15_4 - EINT3_6 EINT2_6 EINT1_6 EINT0_6 EINT23_5 EINT22_5 EINT0_0 EINT21_5 ADTRG1_2 ADTRG0_1 PPG12/13/14/15_TIN1_1 PPG15_TOUT2_1 PPG15_TOUT0_1 PPG14_TOUT2_1 EINT15_5 EINT14_5 EINT13_5 EINT12_5 EINT11_5 SCS120_0 SOT12_0 PPG12/13/14/15_TIN1_0 PPG15_TOUT2_0 PPG15_TOUT0_0 PPG14_TOUT2_0 PPG14_TOUT0_0 PPG13_TOUT2_0 PPG13_TOUT0_0 PPG12_TOUT2_0 PPG12_TOUT0_0 PPG6/7/8/9/10/11_TIN1_0 PPG11_TOUT2_0 PPG11_TOUT0_0 PPG10_TOUT2_0 PPG10_TOUT0_0 - SCS41_0 SCS40_0 SOT4_0 SCK4_0 SIN4_0 SCS33_1 EINT20_5 EINT19_5 SCS30_1 SOT3_1 SCK3_1 SIN3_1 PPG14_TOUT0_1 PPG13_TOUT2_1 PPG13_TOUT0_1 PPG12_TOUT2_1 PPG12_TOUT0_1 SDA12 SCK12_0 SIN12_0 SCS111_0 SCS110_0 SOT11_0 SCK11_0 SIN11_0 SCS100_0 SOT10_0 SCK10_0 SIN10_0 SCS91_0 SCS90_0 SOT9_0 - SCS43_0 SCS42_0 LCDD2 LCDD1 SDA4 SCL4 SCS32_1 SCS31_1 SCS23_1 SCS22_1 SCS21_1 SCS20_1 SOT2_1 SCL12 SDA11 SCL11 SDA10 SCL10 SDA9 - LCDD4 LCDD3 LCDD0 - - - - - - - Figure 4-3: TEQFP-208 (S6J333xKyz *1) - - LCDD11 LCDD12 - LCDD14 LCDD15 - LCDD7 LCDD10 LCDD13 - LCDD6 LCDD8 LCDD9 SCK0_1 SCS00_1 LCDD16 LCDD17 CS# RS RES# TE - SCS12_0 SCS13_0 SIN17_1 SCS171_1 WR# - SCL1 SDA1 SIN0_1 SOT0_1 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 PPG3_TOUT2_1 RD# SCS43_1 - LCDD5 SIN1_0 SCK1_0 SOT1_0 SCS10_0 SCS11_0 EINT15_1 EINT23_1 EINT0_2 EINT1_2 SCS170_1 SCK17_1 EINT5_2 EINT6_2 EINT7_2 EINT8_2 SIN1_1 SCK1_1 SOT1_1 SCS10_1 SCS11_1 SCS12_1 SCS13_1 SCK4_1 SCS40_1 SCS41_1 EINT21_2 EINT22_2 EINT23_2 EINT0_3 - EINT0_1 EINT1_0 EINT4_1 EINT5_1 RX0_2 TX0_2 EINT11_1 EINT13_1 SEG25 SEG26 SEG27 SEG28 RX3_2 TX3_2 SOT17_1 SEG29 SEG30 SEG31 COM0 PPG4_TOUT0_1 PPG4_TOUT2_1 PPG5_TOUT0_1 PPG5_TOUT2_1 PPG0/1/2/3/4/5_TIN1_1 SIN4_1 SOT4_1 EINT17_2 EINT18_2 EINT19_2 V0 V1 V2 V3 - SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 EINT1_1 EINT9_2 EINT10_2 EINT11_2 EINT12_2 EINT15_2 EINT16_2 COM1 COM2 COM3 SCS42_1 MDQM0 MCSX2 MCSX3 MRDY - MAD1 MAD2 MAD3 MAD4 EINT7_1 EINT9_1 EINT10_1 MAD5 MAD6 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 EINT2_2 EINT3_2 EINT4_2 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 MAD15 MAD16 MAD17 MAD18 MAD19 EINT13_2 EINT14_2 MAD20 MAD21 MOEX MWEX MCLK EINT20_2 DSP0_B7_0 MDC_1 COL_1 CRS_1 - DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 RXCLK_1 RXER_1 RXDV_1 DSP0_G3_0 DSP0_G4_0 I2S1_ECLK_0 I2S1_SD_0 I2S1_WS_0 I2S1_SCK_0 TXCLK_1 TXEN_1 TXD0_1 TXD1_1 TXD2_1 TXD3_1 TXER_1 RXD0_1 RXD1_1 RXD2_1 RXD3_1 MDIO_1 DSP0_B5_0 DSP0_B6_0 DSP0_B7_1 MDQM1 RXCLK_0 RXER_0 RXDV_0 TXCLK_0 - VCC53 P0_00 P0_01 P0_02 P0_03 P4_00 P4_01 P4_02 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P4_03 P4_04 P4_05 P0_10 P0_11 P0_12 P0_13 VCC53 VSS VCC12 P3_00 P3_01 P3_02 P3_03 P3_04 P4_06 P4_07 P3_05 P3_06 P0_14 P0_15 P0_16 P3_07 P0_17 P0_18 P0_19 P0_20 VCC53 VSS AVSS AVSS AVCC3_DAC AVSS VSS S S S S T T T S S S S S S T T T S S S S T T T T T T T T T S S S T V V V U - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 TOP VIEW TEQFP-208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 P P P P P P P P G E H G G G G G H G G G G E E E O D N G G G G L2 L2 L2 M L K K - DVSS P1_24 P1_23 P1_22 P1_21 P1_20 P1_19 P1_18 P1_17 DVCC DVSS AVSS AVRL5 AVRH5 AVCC5 P4_23 P4_22 P1_16 P4_21 P4_20 P4_19 VCC5 VSS VCC12 VCC12 P4_18 P4_17 P1_15 P1_14 P3_23 P3_22 P3_21 P3_20 P3_19 P3_18 VSS C MODE PSC_1 RSTX P4_16 P3_17 P3_16 P1_13 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_NTRST X0 X1 VSS AN46 AN45 AN44 AN43 AN42 AN41 AN40 AN39 ADTRG1_0 ADTRG0_0 AN32 AN31 AN30 AN29 AN28 EINT2_4 EINT17_1 EINT20_1 AN26 AN25 AN24 - PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 EINT10_4 EINT22_1 EINT8_4 EINT7_4 EINT16_1 EINT6_4 EINT5_4 EINT16_0 EINT15_0 EINT4_4 EINT19_1 EINT3_4 PPG6/7/8/9/10/11_TIN1_1 PPG11_TOUT2_1 PPG11_TOUT0_1 EINT1_4 EINT0_4 EINT14_1 EINT14_0 - EINT14_4 EINT20_0 EINT13_4 EINT19_0 EINT12_4 EINT18_0 EINT11_4 EINT17_0 EINT9_4 SGA4_0 SGO3_0 TX6_1 RX6_1 TOT49_1 TIN49_1 OCU10_OTD1_1 OCU10_OTD0_1 SGO4_1 SGA4_1 SGA3_0 - PPG9_TOUT2_0 PPG9_TOUT0_0 PPG8_TOUT2_0 PPG8_TOUT0_0 PPG7_TOUT2_0 PPG7_TOUT0_0 PPG6_TOUT2_0 PPG6_TOUT0_0 SGO4_0 SCK16_1 SIN12_1 SOT12_1 PPG5_TOUT2_0 PPG5_TOUT0_0 SCS120_1 SCS91_1 SCS90_1 TX5_1 ICU10_IN1_1 ICU10_IN0_1 PPG10_TOUT2_1 PPG10_TOUT0_1 OCU9_OTD0_0 - SCK9_0 SIN9_0 TX6_0 RX6_0 SCK8_0 SIN8_0 TX5_0 RX5_0 SCS160_1 SCS161_1 PPG0/1/2/3/4/5_TIN1_0 SOT16_1 SIN16_1 OCU10_OTD0_0 OCU9_OTD1_0 SOT9_1 RX5_1 SIN9_1 OCU9_OTD1_1 OCU9_OTD0_1 TIN48_0 - SCL9 SCS80_0 SOT8_0 SCL8 SCS171_0 SCS170_0 OCU10_OTD1_0 ICU10_IN1_0 ICU10_IN0_0 SCK9_1 ICU9_IN1_1 ICU9_IN0_1 RX3_0 - SDA8 TOT49_0 TIN49_0 TOT48_0 TOT48_1 TIN48_1 - SOT17_0 SCK17_0 TX3_0 TX3_1 RX3_1 - SDA17 SCK12_1 SIN17_0 - WOT SCL17 SYSC0_CLK_1 - SYSC0_CLK_0 INDICATOR0_1 - 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 R R I G G H G G H G G G G G G G G G G G G G G G G G G C C C B B B B B B B B B B B VCC5 X1A X0A NMIX P4_15 P4_14 P1_10 P4_13 P4_12 P1_09 P1_08 P1_07 P3_15 P3_14 P1_06 P1_05 P3_13 P3_12 P1_04 P1_03 P3_11 P3_10 P3_09 P3_08 P4_11 P4_10 P4_09 P4_08 VCC5 VSS VCC12 VCC12 P1_02 P1_01 P1_00 VCC3 VSS P0_31 P0_30 P0_29 P0_28 P0_27 VCC3 VSS P0_26 VSS P0_25 P0_24 P0_23 P0_22 P0_21 VCC3 P1_12 P1_11 AN21 AN18 AN17 AN16 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 MLBDAT MLBSIG MLBCLK M_SDATA1_3 M_SSEL1 M_SDATA1_1 M_SDATA1_2 M_SDATA1_0 M_SCLK0 M_SDATA0_3 M_SSEL0 M_SDATA0_1 M_SDATA0_2 M_SDATA0_0 EINT13_0 EINT12_0 EINT23_3 EINT22_3 EINT11_0 EINT21_3 EINT20_3 EINT10_0 ADTRG1_1 EINT8_0 EINT19_3 EINT12_1 EINT7_0 EINT6_0 EINT18_3 EINT21_1 EINT5_0 EINT4_0 EINT8_1 EINT17_3 EINT6_1 EINT18_1 EINT16_3 EINT15_3 EINT14_3 EINT13_3 CRS_0 COL_0 M_CS#_2 M_DQ7 M_DQ6 M_DQ5 M_DQ4 M_RWDS M_CK M_CS#_1 M_DQ0 M_DQ1 M_DQ2 M_DQ3 PPG4_TOUT2_0 PPG4_TOUT0_0 EINT9_0 SGO3_1 SGA3_1 SGO2_1 SGA2_1 SGO1_1 SGA1_1 SGO0_1 SGA0_1 EINT12_3 EINT11_3 MDC_0 MDIO_0 RXD3_0 RXD2_0 RXD1_0 RXD0_0 TXER_0 TXD3_0 TXD2_0 TXD1_0 TXD0_0 TXEN_0 OCU8_OTD1_0 OCU8_OTD0_0 SGO2_0 SGA2_0 SGA1_0 PPG9_TOUT2_1 PPG9_TOUT0_1 SGO0_0 SGA0_0 PPG8_TOUT2_1 PPG8_TOUT0_1 PPG0_TOUT2_0 PPG0_TOUT0_0 PPG7_TOUT2_1 SCS33_0 SCS32_0 EINT10_3 EINT9_3 EINT8_3 EINT7_3 EINT3_0 EINT6_3 EINT5_3 EINT4_3 EINT3_3 EINT2_3 EINT1_3 EINT2_0 ICU9_IN1_0 ICU9_IN0_0 PPG3_TOUT2_0 PPG3_TOUT0_0 SGO1_0 PPG2_TOUT0_0 OCU8_OTD1_1 OCU8_OTD0_1 PPG1_TOUT2_0 PPG1_TOUT0_0 OCU2_OTD1_1 OCU2_OTD0_1 OCU0_OTD1_0 OCU0_OTD0_0 OCU1_OTD1_1 PPG7_TOUT0_1 PPG6_TOUT2_1 PPG6_TOUT0_1 SCS31_0 SCS30_0 SOT3_0 SCK3_0 SIN3_0 SCS23_0 SCS22_0 SCS21_0 SCS20_0 SOT2_0 SCK2_0 SIN2_0 TOT17_0 TIN17_0 OCU2_OTD1_0 OCU2_OTD0_0 PPG2_TOUT2_0 OCU1_OTD0_0 ICU8_IN1_1 ICU8_IN0_1 ICU1_IN1_0 ICU1_IN0_0 ICU2_IN1_1 ICU2_IN0_1 ICU0_IN1_0 ICU0_IN0_0 ICU1_IN1_1 OCU1_OTD0_1 OCU0_OTD1_1 OCU0_OTD0_1 SCS80_2 SOT8_2 SCK8_2 SIN8_2 SCS91_2 SCS90_2 SCK9_2 SOT9_2 SIN9_2 TX2_0 RX2_0 ICU8_IN1_0 ICU8_IN0_0 OCU1_OTD1_0 ICU2_IN0_0 TOT17_1 TIN17_1 AIN9 ZIN8 TOT16_1 TIN16_1 BIN8 AIN8 TOT1_1 ICU1_IN0_1 ICU0_IN1_1 ICU0_IN0_1 SCS161_0 SCS160_0 SOT16_0 SCK16_0 ICU2_IN1_0 BIN9 TX2_1 RX2_1 TOT1_0 TIN1_0 SCK10_1 TX1_1 TOT0_0 TIN0_0 RX1_1 TIN1_1 TOT0_1 TIN0_1 INDICATOR0_0 SDA16 SCL16 ZIN9 TIN16_0 SCS100_1 SOT10_1 TX0_0 RX0_0 TRACE3_1 SIN10_1 FRT4/8/9/10_TEXT FRT0/1/2/3_TEXT SCS80_1 TX0_1 RX0_1 SIN8_1 TRACE_CLK_0 TRACE_CTL_0 TOT16_0 RX1_0 TRACE_CLK_1 TRACE_CTL_1 SCS00_0 SOT0_0 TRACE2_1 SCK0_0 SIN0_0 TRACE1_1 SOT8_1 SCK8_1 TX1_0 TRACE2_0 TRACE1_0 SDA0 SCL0 TRACE0_1 SIN16_0 TRACE0_0 TRACE3_0 - *1: x, y, z are selected from the following parameters: x: E, D, C, B (Memory Size) y: S, A, B, U, C, D, T, E, F, V, G, H (Option) z: C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 18 of 322 - - S6J3310/20/30/40 Series 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 S S S S S S S S2 S S S S S S S S S S S Q Q P Q P P P Q P P P Q P P Q P P P Q P P P P P - VSS P2_19 P2_18 P2_17 P2_16 P2_15 P2_14 P2_13 P2_12 P2_11 P2_10 P3_31 P3_30 P3_29 P3_28 VCC53 VSS VCC12 P2_09 P3_27 P3_26 P3_25 P3_24 P4_31 P4_30 DVCC DVSS P2_08 P4_29 P2_07 P2_06 P2_05 P4_28 P2_04 P2_03 P2_02 P4_27 P2_01 DVCC DVSS P2_00 P4_26 P1_31 P1_30 P1_29 P4_25 P1_28 P1_27 P1_26 P4_24 P1_25 DVCC DSP0_R6_0 DSP0_R5_0 DSP0_R4_0 DSP0_R3_0 DSP0_R2_0 DSP0_R1_0 DSP0_R0_0 DSP0_CLK_0 DSP0_VSYNC_0 DSP0_HSYNC_0 MDATA15 MDATA14 MDATA13 MDATA12 DSP0_EN_0 EINT10_5 EINT2_1 AN63 EINT8_5 AN62 AN61 AN60 EINT5_5 AN59 AN58 AN57 EINT1_5 AN56 AN55 EINT23_4 AN54 AN53 AN52 EINT19_4 AN51 AN50 AN49 AN47 - MAD0 MDATA7 MDATA6 MDATA5 MDATA4 MDATA3 MDATA2 MDATA1 MDATA0 MCSX1 SEG8 SEG7 SEG6 SEG5 MCSX0 MDATA11 MDATA10 MDATA9 MDATA8 PWM2M5 PWM2P5 PWM1M5 PWM1P5 PWM2M4 PWM2P4 PWM1M4 PWM1P4 PWM2M3 PWM2P3 PWM1M3 PWM1P3 PWM2M2 PWM2P2 PWM1M2 EINT16_4 PWM1P2 - SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 EINT18_5 EINT17_5 EINT16_5 EINT3_1 SEG4 SEG3 SEG2 SEG1 SEG0 SCK2_1 SIN2_1 EINT9_5 EINT7_5 EINT6_5 EINT23_0 EINT4_5 EINT3_5 EINT2_5 EINT0_5 EINT22_0 EINT22_4 EINT21_4 EINT20_4 EINT21_0 EINT18_4 EINT17_4 EINT15_4 - EINT3_6 EINT2_6 EINT1_6 EINT0_6 EINT23_5 EINT22_5 EINT0_0 EINT21_5 ADTRG1_2 ADTRG0_1 PPG12/13/14/15_TIN1_1 PPG15_TOUT2_1 PPG15_TOUT0_1 PPG14_TOUT2_1 EINT15_5 EINT14_5 EINT13_5 EINT12_5 EINT11_5 SCS120_0 SOT12_0 PPG12/13/14/15_TIN1_0 PPG15_TOUT2_0 PPG15_TOUT0_0 PPG14_TOUT2_0 PPG14_TOUT0_0 PPG13_TOUT2_0 PPG13_TOUT0_0 PPG12_TOUT2_0 PPG12_TOUT0_0 PPG6/7/8/9/10/11_TIN1_0 PPG11_TOUT2_0 PPG11_TOUT0_0 PPG10_TOUT2_0 PPG10_TOUT0_0 - SCS41_0 SCS40_0 SOT4_0 SCK4_0 SIN4_0 SCS33_1 EINT20_5 EINT19_5 SCS30_1 SOT3_1 SCK3_1 SIN3_1 PPG14_TOUT0_1 PPG13_TOUT2_1 PPG13_TOUT0_1 PPG12_TOUT2_1 PPG12_TOUT0_1 SDA12 SCK12_0 SIN12_0 SCS111_0 SCS110_0 SOT11_0 SCK11_0 SIN11_0 SCS100_0 SOT10_0 SCK10_0 SIN10_0 SCS91_0 SCS90_0 SOT9_0 - SCS43_0 SCS42_0 LCDD2 LCDD1 SDA4 SCL4 SCS32_1 SCS31_1 SCS23_1 SCS22_1 SCS21_1 SCS20_1 SOT2_1 SCL12 SDA11 SCL11 SDA10 SCL10 SDA9 - LCDD4 LCDD3 LCDD0 - - - - - - - Figure 4-4: TEQFP-208 (S6J334xKyz *1) - - LCDD11 LCDD12 - LCDD14 LCDD15 - LCDD7 LCDD10 LCDD13 - LCDD6 LCDD8 LCDD9 SCK0_1 SCS00_1 LCDD16 LCDD17 CS# RS RES# TE - SCS12_0 SCS13_0 SIN17_1 SCS171_1 WR# - SCL1 SDA1 SIN0_1 SOT0_1 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 PPG3_TOUT2_1 RD# SCS43_1 - LCDD5 SIN1_0 SCK1_0 SOT1_0 SCS10_0 SCS11_0 EINT15_1 EINT23_1 EINT0_2 EINT1_2 SCS170_1 SCK17_1 EINT5_2 EINT6_2 EINT7_2 EINT8_2 SIN1_1 SCK1_1 SOT1_1 SCS10_1 SCS11_1 SCS12_1 SCS13_1 SCK4_1 SCS40_1 SCS41_1 EINT21_2 EINT22_2 EINT23_2 EINT0_3 - EINT0_1 EINT1_0 EINT4_1 EINT5_1 RX0_2 TX0_2 EINT11_1 EINT13_1 SEG25 SEG26 SEG27 SEG28 RX3_2 TX3_2 SOT17_1 SEG29 SEG30 SEG31 COM0 PPG4_TOUT0_1 PPG4_TOUT2_1 PPG5_TOUT0_1 PPG5_TOUT2_1 PPG0/1/2/3/4/5_TIN1_1 SIN4_1 SOT4_1 EINT17_2 EINT18_2 EINT19_2 V0 V1 V2 V3 - SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 EINT1_1 EINT9_2 EINT10_2 EINT11_2 EINT12_2 EINT15_2 EINT16_2 COM1 COM2 COM3 SCS42_1 MDQM0 MCSX2 MCSX3 MRDY - MAD1 MAD2 MAD3 MAD4 EINT7_1 EINT9_1 EINT10_1 MAD5 MAD6 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 EINT2_2 EINT3_2 EINT4_2 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 MAD15 MAD16 MAD17 MAD18 MAD19 EINT13_2 EINT14_2 MAD20 MAD21 MOEX MWEX MCLK EINT20_2 DSP0_B7_0 - DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 DSP0_G3_0 DSP0_G4_0 I2S1_ECLK_0 I2S1_SD_0 I2S1_WS_0 I2S1_SCK_0 DSP0_B5_0 DSP0_B6_0 DSP0_B7_1 MDQM1 - VCC53 P0_00 P0_01 P0_02 P0_03 P4_00 P4_01 P4_02 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P4_03 P4_04 P4_05 P0_10 P0_11 P0_12 P0_13 VCC53 VSS VCC12 P3_00 P3_01 P3_02 P3_03 P3_04 P4_06 P4_07 P3_05 P3_06 P0_14 P0_15 P0_16 P3_07 P0_17 P0_18 P0_19 P0_20 VCC53 VSS AVSS AVSS AVCC3_DAC AVSS VSS S S S S T T T S S S S S S T T T S S S S T T T T T T T T T S S S T V V V U - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 TOP VIEW TEQFP-208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 P P P P P P P P G E H G G G G G H G G G G E E E O D N G G G G L2 L2 L2 M L K K - DVSS P1_24 P1_23 P1_22 P1_21 P1_20 P1_19 P1_18 P1_17 DVCC DVSS AVSS AVRL5 AVRH5 AVCC5 P4_23 P4_22 P1_16 P4_21 P4_20 P4_19 VCC5 VSS VCC12 VCC12 P4_18 P4_17 P1_15 P1_14 P3_23 P3_22 P3_21 P3_20 P3_19 P3_18 VSS C MODE PSC_1 RSTX P4_16 P3_17 P3_16 P1_13 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_NTRST X0 X1 VSS AN46 AN45 AN44 AN43 AN42 AN41 AN40 AN39 ADTRG1_0 ADTRG0_0 AN32 AN31 AN30 AN29 AN28 EINT2_4 EINT17_1 EINT20_1 AN26 AN25 AN24 - PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 EINT10_4 EINT22_1 EINT8_4 EINT7_4 EINT16_1 EINT6_4 EINT5_4 EINT16_0 EINT15_0 EINT4_4 EINT19_1 EINT3_4 PPG6/7/8/9/10/11_TIN1_1 PPG11_TOUT2_1 PPG11_TOUT0_1 EINT1_4 EINT0_4 EINT14_1 EINT14_0 - EINT14_4 EINT20_0 EINT13_4 EINT19_0 EINT12_4 EINT18_0 EINT11_4 EINT17_0 EINT9_4 SGA4_0 SGO3_0 TX6_1 RX6_1 TOT49_1 TIN49_1 OCU10_OTD1_1 OCU10_OTD0_1 SGO4_1 SGA4_1 SGA3_0 - PPG9_TOUT2_0 PPG9_TOUT0_0 PPG8_TOUT2_0 PPG8_TOUT0_0 PPG7_TOUT2_0 PPG7_TOUT0_0 PPG6_TOUT2_0 PPG6_TOUT0_0 SGO4_0 SCK16_1 SIN12_1 SOT12_1 PPG5_TOUT2_0 PPG5_TOUT0_0 SCS120_1 SCS91_1 SCS90_1 TX5_1 ICU10_IN1_1 ICU10_IN0_1 PPG10_TOUT2_1 PPG10_TOUT0_1 OCU9_OTD0_0 - SCK9_0 SIN9_0 TX6_0 RX6_0 SCK8_0 SIN8_0 TX5_0 RX5_0 SCS160_1 SCS161_1 PPG0/1/2/3/4/5_TIN1_0 SOT16_1 SIN16_1 OCU10_OTD0_0 OCU9_OTD1_0 SOT9_1 RX5_1 SIN9_1 OCU9_OTD1_1 OCU9_OTD0_1 TIN48_0 - SCL9 SCS80_0 SOT8_0 SCL8 SCS171_0 SCS170_0 OCU10_OTD1_0 ICU10_IN1_0 ICU10_IN0_0 SCK9_1 ICU9_IN1_1 ICU9_IN0_1 RX3_0 - SDA8 TOT49_0 TIN49_0 TOT48_0 TOT48_1 TIN48_1 - SOT17_0 SCK17_0 TX3_0 TX3_1 RX3_1 - SDA17 SCK12_1 SIN17_0 - WOT SCL17 SYSC0_CLK_1 - SYSC0_CLK_0 INDICATOR0_1 - 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 R R I G G H G G H G G G G G G G G G G G G G G G G G G C C C B B B B B B B B B B B VCC5 X1A X0A NMIX P4_15 P4_14 P1_10 P4_13 P4_12 P1_09 P1_08 P1_07 P3_15 P3_14 P1_06 P1_05 P3_13 P3_12 P1_04 P1_03 P3_11 P3_10 P3_09 P3_08 P4_11 P4_10 P4_09 P4_08 VCC5 VSS VCC12 VCC12 P1_02 P1_01 P1_00 VCC3 VSS P0_31 P0_30 P0_29 P0_28 P0_27 VCC3 VSS P0_26 VSS P0_25 P0_24 P0_23 P0_22 P0_21 VCC3 P1_12 P1_11 AN21 AN18 AN17 AN16 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 M_SDATA1_3 M_SSEL1 M_SDATA1_1 M_SDATA1_2 M_SDATA1_0 M_SCLK0 M_SDATA0_3 M_SSEL0 M_SDATA0_1 M_SDATA0_2 M_SDATA0_0 EINT13_0 EINT12_0 EINT23_3 EINT22_3 EINT11_0 EINT21_3 EINT20_3 EINT10_0 ADTRG1_1 EINT8_0 EINT19_3 EINT12_1 EINT7_0 EINT6_0 EINT18_3 EINT21_1 EINT5_0 EINT4_0 EINT8_1 EINT17_3 EINT6_1 EINT18_1 EINT16_3 EINT15_3 EINT14_3 EINT13_3 M_CS#_2 M_DQ7 M_DQ6 M_DQ5 M_DQ4 M_RWDS M_CK M_CS#_1 M_DQ0 M_DQ1 M_DQ2 M_DQ3 PPG4_TOUT2_0 PPG4_TOUT0_0 EINT9_0 SGO3_1 SGA3_1 SGO2_1 SGA2_1 SGO1_1 SGA1_1 SGO0_1 SGA0_1 EINT12_3 EINT11_3 OCU8_OTD1_0 OCU8_OTD0_0 SGO2_0 SGA2_0 SGA1_0 PPG9_TOUT2_1 PPG9_TOUT0_1 SGO0_0 SGA0_0 PPG8_TOUT2_1 PPG8_TOUT0_1 PPG0_TOUT2_0 PPG0_TOUT0_0 PPG7_TOUT2_1 SCS33_0 SCS32_0 EINT10_3 EINT9_3 EINT8_3 EINT7_3 EINT3_0 EINT6_3 EINT5_3 EINT4_3 EINT3_3 EINT2_3 EINT1_3 EINT2_0 ICU9_IN1_0 ICU9_IN0_0 PPG3_TOUT2_0 PPG3_TOUT0_0 SGO1_0 PPG2_TOUT0_0 OCU8_OTD1_1 OCU8_OTD0_1 PPG1_TOUT2_0 PPG1_TOUT0_0 OCU2_OTD1_1 OCU2_OTD0_1 OCU0_OTD1_0 OCU0_OTD0_0 OCU1_OTD1_1 PPG7_TOUT0_1 PPG6_TOUT2_1 PPG6_TOUT0_1 SCS31_0 SCS30_0 SOT3_0 SCK3_0 SIN3_0 SCS23_0 SCS22_0 SCS21_0 SCS20_0 SOT2_0 SCK2_0 SIN2_0 TOT17_0 TIN17_0 OCU2_OTD1_0 OCU2_OTD0_0 PPG2_TOUT2_0 OCU1_OTD0_0 ICU8_IN1_1 ICU8_IN0_1 ICU1_IN1_0 ICU1_IN0_0 ICU2_IN1_1 ICU2_IN0_1 ICU0_IN1_0 ICU0_IN0_0 ICU1_IN1_1 OCU1_OTD0_1 OCU0_OTD1_1 OCU0_OTD0_1 SCS80_2 SOT8_2 SCK8_2 SIN8_2 SCS91_2 SCS90_2 SCK9_2 SOT9_2 SIN9_2 TX2_0 RX2_0 ICU8_IN1_0 ICU8_IN0_0 OCU1_OTD1_0 ICU2_IN0_0 TOT17_1 TIN17_1 AIN9 ZIN8 TOT16_1 TIN16_1 BIN8 AIN8 TOT1_1 ICU1_IN0_1 ICU0_IN1_1 ICU0_IN0_1 SCS161_0 SCS160_0 SOT16_0 SCK16_0 ICU2_IN1_0 BIN9 TX2_1 RX2_1 TOT1_0 TIN1_0 SCK10_1 TX1_1 TOT0_0 TIN0_0 RX1_1 TIN1_1 TOT0_1 TIN0_1 INDICATOR0_0 SDA16 SCL16 ZIN9 TIN16_0 SCS100_1 SOT10_1 TX0_0 RX0_0 TRACE3_1 SIN10_1 FRT4/8/9/10_TEXT FRT0/1/2/3_TEXT SCS80_1 TX0_1 RX0_1 SIN8_1 TRACE_CLK_0 TRACE_CTL_0 TOT16_0 RX1_0 TRACE_CLK_1 TRACE_CTL_1 SCS00_0 SOT0_0 TRACE2_1 SCK0_0 SIN0_0 TRACE1_1 SOT8_1 SCK8_1 TX1_0 TRACE2_0 TRACE1_0 SDA0 SCL0 TRACE0_1 SIN16_0 TRACE0_0 TRACE3_0 - *1: x, y, z are selected from the following parameters: x: E, D, C, B (Memory Size) y: S, A, B, U, C, D, T, E, F, V, G, H (Option) z: C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 19 of 322 - - S6J3310/20/30/40 Series 4.1.2 TEQFP-176 Pin Assignment - - LCDD11 LCDD12 - ARH0_AIC1_UPCLK ARH0_AIC1_UPDATA1 LCDD14 LCDD15 - LCDD7 LCDD10 ARH0_AIC1_RCK ARH0_AIC1_RDA1 LCDD13 ARH0_AIC0_TCKI ARH0_AIC0_DNDATA1 - LCDD6 ARH0_AIC1_DNDATA1 LCDD8 LCDD9 ARH0_AIC1_DNDATA0 SCK0_1 SCS00_1 ARH0_AIC1_UPDATA0 ARH0_AIC0_DNCLK ARH0_AIC0_TDA1 LCDD16 LCDD17 CS# RS RES# TE - ARH0_AIC1_TCKI ARH0_AIC1_TDA1 ARH0_AIC1_dbg_out_1 ARH0_AIC1_dbg_out_0 ARH0_AIC1_TDA0 SCS12_0 SCS13_0 ARH0_AIC1_RDA0 SIN17_1 SCS171_1 ARH0_AIC0_dbg_out_1 ARH0_AIC0_dbg_out_0 ARH0_AIC0_dbg_select WR# ARH0_AIC0_DNDATA0 ARH0_AIC0_UPCLK ARH0_AIC0_UPDATA1 ARH0_AIC0_UPDATA0 - ARH0_AIC1_DNCLK SCL1 SDA1 SIN0_1 SOT0_1 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 PPG3_TOUT2_1 ARH0_AIC1_dbg_select RD# ARH0_AIC0_TDA0 SCS43_1 ARH0_AIC0_RCK ARH0_AIC0_RDA1 ARH0_AIC0_RDA0 - LCDD5 SIN1_0 SCK1_0 SOT1_0 SCS10_0 SCS11_0 EINT15_1 EINT23_1 EINT0_2 EINT1_2 EINT5_2 EINT6_2 EINT7_2 EINT8_2 SIN1_1 SCK1_1 SOT1_1 SCS10_1 SCS11_1 SCS12_1 SCS13_1 SCK4_1 SCS40_1 SCS41_1 EINT21_2 EINT22_2 EINT23_2 EINT0_3 - EINT0_1 EINT1_0 EINT4_1 EINT5_1 EINT11_1 EINT13_1 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM0 PPG4_TOUT0_1 PPG4_TOUT2_1 PPG5_TOUT0_1 PPG5_TOUT2_1 PPG0/1/2/3/4/5_TIN1_1 SIN4_1 SOT4_1 EINT17_2 EINT18_2 EINT19_2 V0 V1 V2 V3 - SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 EINT1_1 EINT9_2 EINT10_2 EINT11_2 EINT12_2 EINT15_2 EINT16_2 COM1 COM2 COM3 SCS42_1 MDQM0 MCSX2 MCSX3 MRDY - MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 MAD15 MAD16 MAD17 MAD18 MAD19 MAD20 MAD21 MOEX MWEX MCLK EINT20_2 DSP0_B7_0 MDC_1 COL_1 CRS_1 - DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 DSP0_G3_0 DSP0_G4_0 I2S1_ECLK_0 I2S1_SD_0 I2S1_WS_0 I2S1_SCK_0 I2S0_ECLK_0 I2S0_SD_0 I2S0_WS_0 I2S0_SCK_0 TXD1_1 TXD2_1 TXD3_1 TXER_1 RXD0_1 RXD3_1 MDIO_1 DSP0_B5_0 DSP0_B6_0 DSP0_B7_1 MDQM1 RXCLK_0 RXER_0 RXDV_0 TXCLK_0 - VCC53 P0_00 P0_01 P0_02 P0_03 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 VCC53 VSS VCC12 P3_00 P3_01 P3_02 P3_03 P3_04 P3_05 P3_06 P0_14 P0_15 P0_16 P3_07 P0_17 P0_18 P0_19 P0_20 VCC53 VSS AVSS DAC_R C_R AVSS AVCC3_DAC DAC_L C_L AVSS VSS S S S S S S S S S S S S S S T T T T T T T S S S T V V V U A A A A - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SDA9 - SCS91_0 SCS90_0 SOT9_0 - - - EINT18_4 PPG11_TOUT0_0 EINT15_4 PPG10_TOUT0_0 PWM2P2 PWM1M2 EINT17_4 PPG10_TOUT2_0 PWM1P2 - AN50 AN49 AN47 - P1_27 P1_26 P1_25 DVCC P P P 136 135 134 133 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL11 - - - - SDA10 SCL10 - SCK11_0 - - SIN11_0 SCS100_0 - - SOT10_0 SIN10_0 PPG13_TOUT2_0 - - EINT0_5 - - EINT22_4 PPG12_TOUT2_0 PWM1P4 - - PWM2M3 EINT22_0 PPG13_TOUT0_0 PWM2P3 PWM1M3 EINT21_4 PPG12_TOUT0_0 PWM1P3 PWM2M2 EINT21_0 PPG11_TOUT2_0 AN56 - - AN55 AN54 AN53 AN52 AN51 P2_01 DVCC DVSS P2_00 P1_31 P1_30 P1_29 P1_28 P P P P P P 143 142 141 140 139 138 137 EINT20_4 PPG6/7/8/9/10/11_TIN1_0 SCK10_0 144 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL12 - - - SDA11 - - SDA12 SCK12_0 SIN12_0 SCS111_0 SCS110_0 SOT11_0 - SCS120_0 PPG15_TOUT0_0 PPG14_TOUT2_0 PPG14_TOUT0_0 EINT7_5 EINT23_0 PPG15_TOUT2_0 EINT3_5 - PWM2M5 EINT9_5 PWM2P5 PWM1M5 EINT6_5 PWM1P5 PWM2M4 EINT4_5 PWM2P4 PWM1M4 EINT2_5 - AN63 AN62 AN61 AN60 AN59 AN58 AN57 DVSS P2_08 P2_07 P2_06 P2_05 P2_04 P2_03 P2_02 - P P P P P P P 152 151 150 149 148 147 146 145 SOT12_0 - - PPG12/13/14/15_TIN1_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PPG14_TOUT0_1 SCS23_1 PPG13_TOUT2_1 SCS22_1 PPG13_TOUT0_1 SCS21_1 PPG12_TOUT2_1 SCS20_1 PPG12_TOUT0_1 SOT2_1 - - - EINT15_5 EINT14_5 EINT13_5 EINT12_5 EINT11_5 - - - SEG4 SEG1 SEG0 - - - MCSX0 MDATA11 SEG3 MDATA10 SEG2 MDATA9 MDATA8 - - DSP0_EN_0 I2S0_SCK_1 I2S0_WS_1 I2S0_SD_1 I2S0_ECLK_1 - VSS VCC12 - P2_09 P3_27 P3_26 P3_25 P3_24 DVCC - - S S S S S 160 159 158 157 156 155 - 154 P2_10 P3_31 P3_30 P3_29 P3_28 VCC53 - S S S S S 153 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCS32_1 SCS31_1 - - - - - SCS33_1 EINT20_5 EINT19_5 SCS30_1 SOT3_1 SCK3_1 SIN3_1 - EINT21_5 ADTRG1_2 ADTRG0_1 PPG14_TOUT2_1 - SEG11 SEG10 SEG9 EINT18_5 PPG12/13/14/15_TIN1_1 EINT17_5 PPG15_TOUT2_1 EINT16_5 PPG15_TOUT0_1 EINT3_1 - MDATA1 MDATA0 MCSX1 SEG8 SEG7 SEG6 SEG5 - DSP0_CLK_0 DSP0_VSYNC_0 DSP0_HSYNC_0 MDATA15 MDATA14 MDATA13 MDATA12 S2 P2_12 S P2_11 168 167 166 165 164 163 162 161 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LCDD4 LCDD3 - - LCDD0 - - - SCS43_0 SCS42_0 LCDD2 LCDD1 SDA4 SCL4 - - - - SCS41_0 SCS40_0 SOT4_0 SCK4_0 SIN4_0 - EINT3_6 EINT2_6 EINT1_6 EINT0_6 EINT23_5 EINT22_5 EINT0_0 - SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 - MAD0 MDATA7 MDATA6 MDATA5 MDATA4 MDATA3 MDATA2 - DSP0_R6_0 DSP0_R5_0 DSP0_R4_0 DSP0_R3_0 DSP0_R2_0 DSP0_R1_0 DSP0_R0_0 VSS P2_19 P2_18 P2_17 P2_16 P2_15 P2_14 P2_13 - S S S S S S S 176 175 174 173 172 171 170 169 Figure 4-5: TEQFP-176 (S6J331xJyz *1) 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 TOP VIEW TEQFP-176 P P P P P P P P H H G G G G E E E O D N G G G L2 L2 L2 M L K K - DVSS P1_24 P1_23 P1_22 P1_21 P1_20 P1_19 P1_18 P1_17 DVCC DVSS AVSS AVRL5 AVRH5 AVCC5 P1_16 VCC5 VSS VCC12 VCC12 P1_15 P1_14 P3_23 P3_22 P3_21 P3_20 P3_19 P3_18 VSS C MODE PSC_1 RSTX P3_17 P3_16 P1_13 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_NTRST X0 X1 VSS AN46 AN45 AN44 AN43 AN42 AN41 AN40 AN39 ADTRG0_0 AN32 AN31 AN30 AN29 AN28 EINT2_4 EINT17_1 EINT20_1 AN26 AN25 AN24 - PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 EINT16_0 EINT15_0 EINT4_4 EINT19_1 EINT3_4 PPG6/7/8/9/10/11_TIN1_1 PPG11_TOUT2_1 PPG11_TOUT0_1 EINT0_4 EINT14_1 EINT14_0 - EINT14_4 EINT20_0 EINT13_4 EINT19_0 EINT12_4 EINT18_0 EINT11_4 EINT17_0 EINT9_4 SGA4_0 SGO3_0 TX6_1 RX6_1 TOT49_1 TIN49_1 OCU10_OTD1_1 OCU10_OTD0_1 SGO4_1 SGA4_1 SGA3_0 - PPG9_TOUT2_0 PPG9_TOUT0_0 PPG8_TOUT2_0 PPG8_TOUT0_0 PPG7_TOUT2_0 PPG7_TOUT0_0 PPG6_TOUT2_0 PPG6_TOUT0_0 SGO4_0 PPG5_TOUT2_0 PPG5_TOUT0_0 SCS120_1 SCS91_1 SCS90_1 TX5_1 ICU10_IN1_1 ICU10_IN0_1 PPG10_TOUT2_1 PPG10_TOUT0_1 OCU9_OTD0_0 - SCK9_0 SIN9_0 TX6_0 RX6_0 SCK8_0 SIN8_0 TX5_0 RX5_0 PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD0_0 OCU9_OTD1_0 SOT9_1 RX5_1 SIN9_1 OCU9_OTD1_1 OCU9_OTD0_1 TIN48_0 - SCL9 SCS80_0 SOT8_0 SCL8 SCS171_0 SCS170_0 OCU10_OTD1_0 ICU10_IN1_0 ICU10_IN0_0 SCK9_1 ICU9_IN1_1 ICU9_IN0_1 RX3_0 - SDA8 TOT49_0 TIN49_0 TOT48_0 TOT48_1 TIN48_1 - SOT17_0 SCK17_0 TX3_0 TX3_1 RX3_1 - SDA17 SCK12_1 SIN17_0 - WOT SCL17 SYSC0_CLK_1 - SYSC0_CLK_0 INDICATOR0_1 - - - 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 B B B - - C C C - - - - G G G G G G G G G G G G G G H H I R R - P0_28 M_SDATA1_2 M_DQ4 P0_29 M_SDATA1_1 M_DQ5 VCC3 - P1_00 MLBCLK P1_01 MLBSIG P1_02 MLBDAT VCC12 - VCC12 - VSS P3_08 AN4 P3_09 AN5 P3_10 AN6 P3_11 AN7 P1_03 AN8 P1_04 AN9 P3_12 AN10 P3_13 AN11 P1_05 AN12 P1_06 AN13 P3_14 AN14 P3_15 AN15 P1_07 AN16 P1_08 AN17 P1_09 AN18 P1_10 AN21 NMIX - X1A - VCC5 - X0A - P1_11 P1_12 VCC5 - M_DQ6 P0_31 M_SDATA1_3 M_DQ7 VSS - - - CRS_0 - - - - EINT4_0 EINT5_0 EINT11_3 EINT12_3 - - - - SGO0_1 SGO1_1 BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) ADTRG1_1 EINT9_0 EINT10_0 AN1(AL1) EINT11_0 AP1(AH1) - - EINT6_3 EINT3_0 EINT7_3 EINT8_3 EINT9_3 - - EINT10_3 SCS32_0 SCS33_0 - - - - - - - - - SCS31_0 - - - - - - - - - - - - - - PPG1_TOUT0_0 ICU1_IN0_0 PPG1_TOUT2_0 ICU1_IN1_0 - - - - - - - - - - - - - - - - - - - - TOT1_1 AIN8 BIN8 TIN16_1 TOT16_1 ZIN8 AIN9 TIN17_1 TOT17_1 PPG3_TOUT2_0 OCU2_OTD1_0 ICU8_IN1_0 TOT17_0 - PPG3_TOUT0_0 OCU2_OTD0_0 ICU8_IN0_0 TIN17_0 - PPG2_TOUT0_0 OCU1_OTD0_0 ICU2_IN0_0 - - PPG7_TOUT0_1 OCU1_OTD0_1 ICU1_IN0_1 EINT13_0 PPG4_TOUT2_0 OCU8_OTD1_0 ICU9_IN1_0 - - PPG6_TOUT2_1 OCU0_OTD1_1 ICU0_IN1_1 - - - PPG6_TOUT0_1 OCU0_OTD0_1 ICU0_IN0_1 SGO1_0 SCS80_2 PPG9_TOUT2_1 OCU8_OTD1_1 ICU8_IN1_1 - SCS30_0 SOT8_2 PPG9_TOUT0_1 OCU8_OTD0_1 ICU8_IN0_1 SGO2_0 SOT3_0 SCK8_2 PPG8_TOUT2_1 OCU2_OTD1_1 ICU2_IN1_1 SGA2_0 SCK3_0 SIN8_2 PPG8_TOUT0_1 OCU2_OTD0_1 ICU2_IN0_1 BP1(BH1) SIN3_0 - PPG0_TOUT2_0 OCU0_OTD1_0 ICU0_IN1_0 SGA1_0 SCS23_0 - PPG0_TOUT0_0 OCU0_OTD0_0 ICU0_IN0_0 SGO0_0 - PPG7_TOUT2_1 OCU1_OTD1_1 ICU1_IN1_1 SGA0_0 - EINT12_0 PPG4_TOUT0_0 OCU8_OTD0_0 ICU9_IN0_0 - - EINT19_3 SGO3_1 - - EINT12_1 SGA3_1 EINT8_0 MDIO_0 EINT18_3 SGO2_1 EINT7_0 RXD3_0 EINT21_1 SGA2_1 EINT6_0 RXD2_0 EINT17_3 SGA1_1 EINT8_1 RXD1_0 EINT18_1 SGA0_1 EINT6_1 - M_CS#_2 MDC_0 COL_0 - P0_27 M_SDATA1_0 M_RWDS RXD0_0 P0_30 M_SSEL1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TIN1_0 RX0_0 TOT1_0 TX0_0 SOT10_1 SCS100_1 TIN16_0 SCK16_0SCL16 SOT16_0SDA16 SCS161_0 - - - - - - - - - - - - - - - - - - - - - - - - - SCK8_1 SOT8_1 TRACE1_1 TRACE2_1 - SOT0_0 SCS00_0 TOT16_0 - - - - - - - - - - - - - - - - - - - - - - - - TRACE0_1 - - SCL0 - - SDA0 TRACE1_0 TRACE2_0 - TRACE_CLK_0 - - TRACE_CTL_0 - - TRACE_CLK_1 - - TRACE_CTL_1 INDICATOR0_0SCS160_0 - - SCK10_1TRACE3_1 - - SCK0_0 TOT0_0 FRT4/8/9/10_TEXT BIN9 - SIN0_0 TIN0_0 FRT0/1/2/3_TEXT - - TIN1_1 TX0_1 - - TOT0_1 RX0_1 - - TIN0_1 SIN8_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRACE0_0 - - - - SIN16_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRACE3_0 - - - - - - - 58 B - VCC3 - - - 57 B VSS SCS91_2 - - ZIN9 PPG2_TOUT2_0 OCU1_OTD1_0 ICU2_IN1_0 56 - SCS90_2 BN1(BL1) 55 - SCK9_2 SIN10_1 54 SOT9_2 SCS80_1 53 SIN9_2 - SCS22_0 SIN2_0 - - SCS21_0 EINT1_3 SCS20_0 EINT2_0 SOT2_0 - SCK2_0 TXD1_0 EINT5_3 TXD0_0 - TXEN_0 M_DQ0 - EINT4_3 - - EINT3_3 P0_24 M_SSEL0 EINT2_3 P0_23 M_SDATA0_1 M_DQ1 TXER_0 P0_22 M_SDATA0_2 M_DQ2 - P0_21 M_SDATA0_0 M_DQ3 TXD2_0 VCC3 - M_CK B - B P0_26 M_SCLK0 B VSS - B P0_25 M_SDATA0_3 M_CS#_1 TXD3_0 50 - 49 B 48 B 47 52 46 51 45 *1: x, y, z are selected from the following parameters: x: E, D, C, B (Memory Size) y: S, A, B, U, C, D, T, E, F, V, G, H (Option) z: C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 20 of 322 S6J3310/20/30/40 Series - - LCDD11 LCDD12 - LCDD14 LCDD15 - LCDD7 LCDD10 LCDD13 - LCDD6 LCDD8 LCDD9 SCK0_1 SCS00_1 LCDD16 LCDD17 CS# RS RES# TE - SCS12_0 SCS13_0 SIN17_1 SCS171_1 WR# - SCL1 SDA1 SIN0_1 SOT0_1 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 PPG3_TOUT2_1 RD# SCS43_1 - LCDD5 SIN1_0 SCK1_0 SOT1_0 SCS10_0 SCS11_0 EINT15_1 EINT23_1 EINT0_2 EINT1_2 EINT5_2 EINT6_2 EINT7_2 EINT8_2 SIN1_1 SCK1_1 SOT1_1 SCS10_1 SCS11_1 SCS12_1 SCS13_1 SCK4_1 SCS40_1 SCS41_1 EINT21_2 EINT22_2 EINT23_2 EINT0_3 - EINT0_1 EINT1_0 EINT4_1 EINT5_1 EINT11_1 EINT13_1 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM0 PPG4_TOUT0_1 PPG4_TOUT2_1 PPG5_TOUT0_1 PPG5_TOUT2_1 PPG0/1/2/3/4/5_TIN1_1 SIN4_1 SOT4_1 EINT17_2 EINT18_2 EINT19_2 V0 V1 V2 V3 - SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 EINT1_1 EINT9_2 EINT10_2 EINT11_2 EINT12_2 EINT15_2 EINT16_2 COM1 COM2 COM3 SCS42_1 MDQM0 MCSX2 MCSX3 MRDY - MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 MAD15 MAD16 MAD17 MAD18 MAD19 MAD20 MAD21 MOEX MWEX MCLK EINT20_2 DSP0_B7_0 MDC_1 COL_1 CRS_1 - DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 DSP0_G3_0 DSP0_G4_0 I2S1_ECLK_0 I2S1_SD_0 I2S1_WS_0 I2S1_SCK_0 I2S0_ECLK_0 I2S0_SD_0 I2S0_WS_0 I2S0_SCK_0 TXD1_1 TXD2_1 TXD3_1 TXER_1 RXD0_1 RXD3_1 MDIO_1 DSP0_B5_0 DSP0_B6_0 DSP0_B7_1 MDQM1 RXCLK_0 RXER_0 RXDV_0 TXCLK_0 - VCC53 P0_00 P0_01 P0_02 P0_03 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 VCC53 VSS VCC12 P3_00 P3_01 P3_02 P3_03 P3_04 P3_05 P3_06 P0_14 P0_15 P0_16 P3_07 P0_17 P0_18 P0_19 P0_20 VCC53 VSS AVSS DAC_R C_R AVSS AVCC3_DAC DAC_L C_L AVSS VSS S S S S S S S S S S S S S S T T T T T T T S S S T V V V U A A A A - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SDA9 - SCS91_0 SCS90_0 SOT9_0 - - - EINT18_4 PPG11_TOUT0_0 EINT15_4 PPG10_TOUT0_0 PWM2P2 PWM1M2 EINT17_4 PPG10_TOUT2_0 PWM1P2 - AN50 AN49 AN47 - P1_27 P1_26 P1_25 DVCC P P P 136 135 134 133 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SDA10 SCL10 - - - SIN11_0 SCS100_0 SOT10_0 SIN10_0 - - - - EINT22_4 PPG12_TOUT2_0 EINT20_4 PPG6/7/8/9/10/11_TIN1_0 SCK10_0 - - PWM2M3 EINT22_0 PPG13_TOUT0_0 PWM2P3 PWM1M3 EINT21_4 PPG12_TOUT0_0 PWM1P3 PWM2M2 EINT21_0 PPG11_TOUT2_0 - - AN55 AN54 AN53 AN52 AN51 DVCC DVSS P2_00 P1_31 P1_30 P1_29 P1_28 - - P P P P P 143 142 141 140 139 138 137 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL12 - - - SDA11 SCL11 SDA12 SCK12_0 SIN12_0 SCS111_0 SCS110_0 SOT11_0 SCK11_0 SOT12_0 PPG12/13/14/15_TIN1_0 PPG15_TOUT0_0 PPG14_TOUT2_0 PPG14_TOUT0_0 PPG13_TOUT2_0 EINT7_5 EINT23_0 PPG15_TOUT2_0 EINT3_5 EINT0_5 PWM2P5 PWM1M5 EINT6_5 PWM1P5 PWM2M4 EINT4_5 PWM2P4 PWM1M4 EINT2_5 PWM1P4 AN62 AN61 AN60 AN59 AN58 AN57 AN56 P2_07 P2_06 P2_05 P2_04 P2_03 P2_02 P2_01 P P P P P P P 150 149 148 147 146 145 PPG13_TOUT0_1 SCS21_1 PPG12_TOUT2_1 SCS20_1 PPG12_TOUT0_1 SOT2_1 EINT13_5 EINT12_5 EINT11_5 SEG1 SEG0 - - - - 144 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCS120_0 MDATA10 SEG2 MDATA9 MDATA8 - - PWM2M5 EINT9_5 I2S0_WS_1 I2S0_SD_1 I2S0_ECLK_1 - - AN63 P3_26 P3_25 P3_24 DVCC DVSS P2_08 S S S P 156 155 154 153 152 PPG14_TOUT2_1 - - - EINT15_5 EINT14_5 151 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCK3_1 SIN3_1 - - - PPG14_TOUT0_1 SCS23_1 PPG13_TOUT2_1 SCS22_1 EINT16_5 PPG15_TOUT0_1 EINT3_1 - - - SEG4 SEG6 SEG5 - - - MCSX0 MDATA11 SEG3 MDATA13 MDATA12 - DSP0_EN_0 I2S0_SCK_1 P3_29 P3_28 VCC53 - VSS VCC12 - P2_09 - - - P3_27 S S S S 163 162 161 160 159 158 157 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL4 - - SCS32_1 SCS31_1 - - SCK4_0 SIN4_0 SCS33_1 EINT20_5 EINT19_5 SCS30_1 SOT3_1 EINT22_5 EINT0_0 EINT21_5 ADTRG1_2 ADTRG0_1 SEG13 SEG12 SEG11 SEG10 SEG9 EINT18_5 PPG12/13/14/15_TIN1_1 EINT17_5 PPG15_TOUT2_1 MDATA3 MDATA2 MDATA1 MDATA0 MCSX1 SEG8 SEG7 DSP0_R1_0 DSP0_R0_0 DSP0_CLK_0 DSP0_VSYNC_0 DSP0_HSYNC_0 MDATA15 MDATA14 P2_14 P2_10 P3_31 P3_30 S S S S S P2_13 S2 P2_12 S P2_11 170 169 168 167 166 165 164 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LCDD4 LCDD3 - - LCDD0 - SCS43_0 SCS42_0 LCDD2 LCDD1 SDA4 - - - SCS41_0 SCS40_0 SOT4_0 - EINT3_6 EINT2_6 EINT1_6 EINT0_6 EINT23_5 - SEG18 SEG17 SEG16 SEG15 SEG14 - MAD0 MDATA7 MDATA6 MDATA5 MDATA4 - DSP0_R6_0 DSP0_R5_0 DSP0_R4_0 DSP0_R3_0 DSP0_R2_0 VSS P2_19 P2_18 P2_17 P2_16 P2_15 - S S S S S 176 175 174 173 172 171 Figure 4-6: TEQFP-176 (S6J332xJyz *1) 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 TOP VIEW TEQFP-176 P P P P P P P P H H G G G G E E E O D N G G G L2 L2 L2 M L K K - DVSS P1_24 P1_23 P1_22 P1_21 P1_20 P1_19 P1_18 P1_17 DVCC DVSS AVSS AVRL5 AVRH5 AVCC5 P1_16 VCC5 VSS VCC12 VCC12 P1_15 P1_14 P3_23 P3_22 P3_21 P3_20 P3_19 P3_18 VSS C MODE PSC_1 RSTX P3_17 P3_16 P1_13 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_NTRST X0 X1 VSS AN46 AN45 AN44 AN43 AN42 AN41 AN40 AN39 ADTRG0_0 AN32 AN31 AN30 AN29 AN28 EINT2_4 EINT17_1 EINT20_1 AN26 AN25 AN24 - PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 EINT16_0 EINT15_0 EINT4_4 EINT19_1 EINT3_4 PPG6/7/8/9/10/11_TIN1_1 PPG11_TOUT2_1 PPG11_TOUT0_1 EINT0_4 EINT14_1 EINT14_0 - EINT14_4 EINT20_0 EINT13_4 EINT19_0 EINT12_4 EINT18_0 EINT11_4 EINT17_0 EINT9_4 SGA4_0 SGO3_0 TX6_1 RX6_1 TOT49_1 TIN49_1 OCU10_OTD1_1 OCU10_OTD0_1 SGO4_1 SGA4_1 SGA3_0 - PPG9_TOUT2_0 PPG9_TOUT0_0 PPG8_TOUT2_0 PPG8_TOUT0_0 PPG7_TOUT2_0 PPG7_TOUT0_0 PPG6_TOUT2_0 PPG6_TOUT0_0 SGO4_0 PPG5_TOUT2_0 PPG5_TOUT0_0 SCS120_1 SCS91_1 SCS90_1 TX5_1 ICU10_IN1_1 ICU10_IN0_1 PPG10_TOUT2_1 PPG10_TOUT0_1 OCU9_OTD0_0 - SCK9_0 SIN9_0 TX6_0 RX6_0 SCK8_0 SIN8_0 TX5_0 RX5_0 PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD0_0 OCU9_OTD1_0 SOT9_1 RX5_1 SIN9_1 OCU9_OTD1_1 OCU9_OTD0_1 TIN48_0 - SCL9 SCS80_0 SOT8_0 SCL8 SCS171_0 SCS170_0 OCU10_OTD1_0 ICU10_IN1_0 ICU10_IN0_0 SCK9_1 ICU9_IN1_1 ICU9_IN0_1 RX3_0 - SDA8 TOT49_0 TIN49_0 TOT48_0 TOT48_1 TIN48_1 - SOT17_0 SCK17_0 TX3_0 TX3_1 RX3_1 - SDA17 SCK12_1 SIN17_0 - WOT SCL17 SYSC0_CLK_1 - SYSC0_CLK_0 INDICATOR0_1 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 B - - C C C - - - - G G G G G G G G G G G G G G H H I R R - P0_29 M_SDATA1_1 M_DQ5 P0_30 M_SSEL1 VSS P1_00 MLBCLK P1_01 MLBSIG P1_02 MLBDAT VCC12 - VCC12 - VSS P3_08 AN4 P3_09 AN5 P3_10 AN6 P3_11 AN7 P1_03 AN8 P1_04 AN9 P3_12 AN10 P3_13 AN11 P1_05 AN12 P1_06 AN13 P3_14 AN14 P3_15 AN15 P1_07 AN16 P1_08 AN17 P1_09 AN18 P1_10 AN21 NMIX - X1A - VCC5 - X0A - VCC3 - P1_11 P1_12 VCC5 - M_DQ6 P0_31 M_SDATA1_3 M_DQ7 - - CRS_0 - - - - EINT4_0 EINT5_0 EINT12_3 - - - - SGO0_1 SGO1_1 BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) ADTRG1_1 EINT9_0 EINT10_0 AN1(AL1) EINT11_0 AP1(AH1) - - EINT6_3 EINT3_0 EINT7_3 EINT8_3 EINT9_3 - - EINT10_3 SCS32_0 SCS33_0 - - - - - - - - - SCS31_0 - - - - - - - - - - - - - - PPG1_TOUT0_0 ICU1_IN0_0 PPG1_TOUT2_0 ICU1_IN1_0 - - - - - - - - - - - - TOT1_1 AIN8 BIN8 TIN16_1 TOT16_1 ZIN8 AIN9 TIN17_1 TOT17_1 PPG3_TOUT2_0 OCU2_OTD1_0 ICU8_IN1_0 TOT17_0 - PPG3_TOUT0_0 OCU2_OTD0_0 ICU8_IN0_0 TIN17_0 - PPG2_TOUT0_0 OCU1_OTD0_0 ICU2_IN0_0 - - PPG7_TOUT0_1 OCU1_OTD0_1 ICU1_IN0_1 EINT13_0 PPG4_TOUT2_0 OCU8_OTD1_0 ICU9_IN1_0 - - PPG6_TOUT2_1 OCU0_OTD1_1 ICU0_IN1_1 - - - PPG6_TOUT0_1 OCU0_OTD0_1 ICU0_IN0_1 SGO1_0 SCS80_2 PPG9_TOUT2_1 OCU8_OTD1_1 ICU8_IN1_1 - SCS30_0 SOT8_2 PPG9_TOUT0_1 OCU8_OTD0_1 ICU8_IN0_1 SGO2_0 SOT3_0 SCK8_2 PPG8_TOUT2_1 OCU2_OTD1_1 ICU2_IN1_1 SGA2_0 SCK3_0 SIN8_2 PPG8_TOUT0_1 OCU2_OTD0_1 ICU2_IN0_1 BP1(BH1) SIN3_0 - PPG0_TOUT2_0 OCU0_OTD1_0 ICU0_IN1_0 SGA1_0 SCS23_0 - PPG0_TOUT0_0 OCU0_OTD0_0 ICU0_IN0_0 SGO0_0 - PPG7_TOUT2_1 OCU1_OTD1_1 ICU1_IN1_1 SGA0_0 - EINT12_0 PPG4_TOUT0_0 OCU8_OTD0_0 ICU9_IN0_0 - EINT11_3 EINT19_3 SGO3_1 - - EINT12_1 SGA3_1 EINT8_0 - EINT18_3 SGO2_1 EINT7_0 MDIO_0 EINT21_1 SGA2_1 EINT6_0 RXD3_0 EINT17_3 SGA1_1 EINT8_1 RXD2_0 EINT18_1 SGA0_1 EINT6_1 RXD1_0 M_CS#_2 MDC_0 COL_0 - P0_27 M_SDATA1_0 M_RWDS RXD0_0 P0_28 M_SDATA1_2 M_DQ4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TIN1_0 RX0_0 TOT1_0 TX0_0 SOT10_1 SCS100_1 TIN16_0 SCK16_0SCL16 SOT16_0SDA16 SCS161_0 - - - - - - - - - - - - - - - - SCK8_1 SOT8_1 TRACE1_1 TRACE2_1 - SOT0_0 SCS00_0 TOT16_0 - - - - - - - - - - - - - - - - - TRACE0_1 - - SCL0 - - SDA0 TRACE1_0 TRACE2_0 - TRACE_CLK_0 - - TRACE_CTL_0 - - TRACE_CLK_1 - - TRACE_CTL_1 INDICATOR0_0SCS160_0 - - SCK10_1TRACE3_1 - - - SCK0_0 TOT0_0 FRT4/8/9/10_TEXT BIN9 - - SIN0_0 TIN0_0 FRT0/1/2/3_TEXT - - TIN1_1 TX0_1 - - TOT0_1 RX0_1 - - TIN0_1 SIN8_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRACE0_0 - - - - SIN16_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRACE3_0 - - - - - - - 60 B - - - - 59 B - - - - - ZIN9 PPG2_TOUT2_0 OCU1_OTD1_0 ICU2_IN1_0 58 B - VCC3 - - - BN1(BL1) 57 B VSS SCS22_0 - SIN10_1 56 - EINT5_3 - SCS80_1 55 - TXER_0 - 54 M_CK - 53 P0_26 M_SCLK0 - B - 52 - - - - - - SOT9_2 - SIN9_2 - - - SOT2_0 - SCK2_0 - SIN2_0 - - - EINT3_3 - EINT2_3 - EINT1_3 - EINT2_0 - - TXD2_0 - TXD1_0 - TXD0_0 M_DQ0 - - TXEN_0 - - VSS - P0_25 M_SDATA0_3 M_CS#_1 TXD3_0 - P0_24 M_SSEL0 - P0_23 M_SDATA0_1 M_DQ1 - P0_22 M_SDATA0_2 M_DQ2 - P0_21 M_SDATA0_0 M_DQ3 - VCC3 - - - - B - B SCS91_2 B SCS90_2 B SCK9_2 - B - 51 SCS21_0 50 SCS20_0 49 - 48 EINT4_3 47 - 46 - 45 *1: x, y, z are selected from the following parameters: x: E, D, C, B (Memory Size) y: S, A, B, U, C, D, T, E, F, V, G, H (Option) z: C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 21 of 322 - - S6J3310/20/30/40 Series - - LCDD11 LCDD12 - LCDD14 LCDD15 - LCDD7 LCDD10 LCDD13 - LCDD6 LCDD8 LCDD9 SCK0_1 SCS00_1 LCDD16 LCDD17 CS# RS RES# TE - SCS12_0 SCS13_0 SIN17_1 SCS171_1 WR# - SCL1 SDA1 SIN0_1 SOT0_1 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 PPG3_TOUT2_1 RD# SCS43_1 - LCDD5 SIN1_0 SCK1_0 SOT1_0 SCS10_0 SCS11_0 EINT15_1 EINT23_1 EINT0_2 EINT1_2 EINT5_2 EINT6_2 EINT7_2 EINT8_2 SIN1_1 SCK1_1 SOT1_1 SCS10_1 SCS11_1 SCS12_1 SCS13_1 SCK4_1 SCS40_1 SCS41_1 EINT21_2 EINT22_2 EINT23_2 EINT0_3 - EINT0_1 EINT1_0 EINT4_1 EINT5_1 EINT11_1 EINT13_1 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM0 PPG4_TOUT0_1 PPG4_TOUT2_1 PPG5_TOUT0_1 PPG5_TOUT2_1 PPG0/1/2/3/4/5_TIN1_1 SIN4_1 SOT4_1 EINT17_2 EINT18_2 EINT19_2 V0 V1 V2 V3 - SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 EINT1_1 EINT9_2 EINT10_2 EINT11_2 EINT12_2 EINT15_2 EINT16_2 COM1 COM2 COM3 SCS42_1 MDQM0 MCSX2 MCSX3 MRDY - MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 MAD15 MAD16 MAD17 MAD18 MAD19 MAD20 MAD21 MOEX MWEX MCLK EINT20_2 DSP0_B7_0 MDC_1 COL_1 CRS_1 - DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 DSP0_G3_0 DSP0_G4_0 I2S1_ECLK_0 I2S1_SD_0 I2S1_WS_0 I2S1_SCK_0 TXD1_1 TXD2_1 TXD3_1 TXER_1 RXD0_1 RXD3_1 MDIO_1 DSP0_B5_0 DSP0_B6_0 DSP0_B7_1 MDQM1 RXCLK_0 RXER_0 RXDV_0 TXCLK_0 - VCC53 P0_00 P0_01 P0_02 P0_03 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 VCC53 VSS VCC12 P3_00 P3_01 P3_02 P3_03 P3_04 P3_05 P3_06 P0_14 P0_15 P0_16 P3_07 P0_17 P0_18 P0_19 P0_20 VCC53 VSS AVSS AVSS AVCC3_DAC AVSS VSS S S S S S S S S S S S S S S T T T T T T T S S S T V V V U - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SDA9 - SCS91_0 SCS90_0 SOT9_0 - - - EINT18_4 PPG11_TOUT0_0 EINT15_4 PPG10_TOUT0_0 PWM2P2 PWM1M2 EINT17_4 PPG10_TOUT2_0 PWM1P2 - AN50 AN49 AN47 - P1_27 P1_26 P1_25 DVCC P P P 136 135 134 133 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SDA10 SCL10 - - - SIN11_0 SCS100_0 SOT10_0 SIN10_0 - - - - EINT22_4 PPG12_TOUT2_0 EINT20_4 PPG6/7/8/9/10/11_TIN1_0 SCK10_0 - - PWM2M3 EINT22_0 PPG13_TOUT0_0 PWM2P3 PWM1M3 EINT21_4 PPG12_TOUT0_0 PWM1P3 PWM2M2 EINT21_0 PPG11_TOUT2_0 - - AN55 AN54 AN53 AN52 AN51 DVCC DVSS P2_00 P1_31 P1_30 P1_29 P1_28 - - P P P P P 143 142 141 140 139 138 137 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL12 - - - SDA11 SCL11 SDA12 SCK12_0 SIN12_0 SCS111_0 SCS110_0 SOT11_0 SCK11_0 SOT12_0 PPG12/13/14/15_TIN1_0 PPG15_TOUT0_0 PPG14_TOUT2_0 PPG14_TOUT0_0 PPG13_TOUT2_0 EINT7_5 EINT23_0 PPG15_TOUT2_0 EINT3_5 EINT0_5 PWM2P5 PWM1M5 EINT6_5 PWM1P5 PWM2M4 EINT4_5 PWM2P4 PWM1M4 EINT2_5 PWM1P4 AN62 AN61 AN60 AN59 AN58 AN57 AN56 P2_07 P2_06 P2_05 P2_04 P2_03 P2_02 P2_01 P P P P P P P 150 149 148 147 146 145 PPG13_TOUT0_1 SCS21_1 PPG12_TOUT2_1 SCS20_1 PPG12_TOUT0_1 SOT2_1 EINT13_5 EINT12_5 EINT11_5 SEG1 SEG0 - - - - 144 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCS120_0 MDATA10 SEG2 MDATA9 MDATA8 - - PWM2M5 EINT9_5 - - - - - AN63 P3_26 P3_25 P3_24 DVCC DVSS P2_08 S S S P 156 155 154 153 152 PPG14_TOUT2_1 - - - EINT15_5 EINT14_5 151 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCK3_1 SIN3_1 - - - PPG14_TOUT0_1 SCS23_1 PPG13_TOUT2_1 SCS22_1 EINT16_5 PPG15_TOUT0_1 EINT3_1 - - - SEG4 SEG6 SEG5 - - - MCSX0 MDATA11 SEG3 MDATA13 MDATA12 - DSP0_EN_0 - P3_29 P3_28 VCC53 - VSS VCC12 - P2_09 - - - P3_27 S S S S 163 162 161 160 159 158 157 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL4 - - SCS32_1 SCS31_1 - - SCK4_0 SIN4_0 SCS33_1 EINT20_5 EINT19_5 SCS30_1 SOT3_1 EINT22_5 EINT0_0 EINT21_5 ADTRG1_2 ADTRG0_1 SEG13 SEG12 SEG11 SEG10 SEG9 EINT18_5 PPG12/13/14/15_TIN1_1 EINT17_5 PPG15_TOUT2_1 MDATA3 MDATA2 MDATA1 MDATA0 MCSX1 SEG8 SEG7 DSP0_R1_0 DSP0_R0_0 DSP0_CLK_0 DSP0_VSYNC_0 DSP0_HSYNC_0 MDATA15 MDATA14 P2_14 P2_10 P3_31 P3_30 S S S S S P2_13 S2 P2_12 S P2_11 170 169 168 167 166 165 164 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LCDD4 LCDD3 - - LCDD0 - SCS43_0 SCS42_0 LCDD2 LCDD1 SDA4 - - - SCS41_0 SCS40_0 SOT4_0 - EINT3_6 EINT2_6 EINT1_6 EINT0_6 EINT23_5 - SEG18 SEG17 SEG16 SEG15 SEG14 - MAD0 MDATA7 MDATA6 MDATA5 MDATA4 - DSP0_R6_0 DSP0_R5_0 DSP0_R4_0 DSP0_R3_0 DSP0_R2_0 VSS P2_19 P2_18 P2_17 P2_16 P2_15 - S S S S S 176 175 174 173 172 171 Figure 4-7: TEQFP-176 (S6J333xJyz *1) 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 TOP VIEW TEQFP-176 P P P P P P P P H H G G G G E E E O D N G G G L2 L2 L2 M L K K - DVSS P1_24 P1_23 P1_22 P1_21 P1_20 P1_19 P1_18 P1_17 DVCC DVSS AVSS AVRL5 AVRH5 AVCC5 P1_16 VCC5 VSS VCC12 VCC12 P1_15 P1_14 P3_23 P3_22 P3_21 P3_20 P3_19 P3_18 VSS C MODE PSC_1 RSTX P3_17 P3_16 P1_13 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_NTRST X0 X1 VSS AN46 AN45 AN44 AN43 AN42 AN41 AN40 AN39 ADTRG0_0 AN32 AN31 AN30 AN29 AN28 EINT2_4 EINT17_1 EINT20_1 AN26 AN25 AN24 - PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 EINT16_0 EINT15_0 EINT4_4 EINT19_1 EINT3_4 PPG6/7/8/9/10/11_TIN1_1 PPG11_TOUT2_1 PPG11_TOUT0_1 EINT0_4 EINT14_1 EINT14_0 - EINT14_4 EINT20_0 EINT13_4 EINT19_0 EINT12_4 EINT18_0 EINT11_4 EINT17_0 EINT9_4 SGA4_0 SGO3_0 TX6_1 RX6_1 TOT49_1 TIN49_1 OCU10_OTD1_1 OCU10_OTD0_1 SGO4_1 SGA4_1 SGA3_0 - PPG9_TOUT2_0 PPG9_TOUT0_0 PPG8_TOUT2_0 PPG8_TOUT0_0 PPG7_TOUT2_0 PPG7_TOUT0_0 PPG6_TOUT2_0 PPG6_TOUT0_0 SGO4_0 PPG5_TOUT2_0 PPG5_TOUT0_0 SCS120_1 SCS91_1 SCS90_1 TX5_1 ICU10_IN1_1 ICU10_IN0_1 PPG10_TOUT2_1 PPG10_TOUT0_1 OCU9_OTD0_0 - SCK9_0 SIN9_0 TX6_0 RX6_0 SCK8_0 SIN8_0 TX5_0 RX5_0 PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD0_0 OCU9_OTD1_0 SOT9_1 RX5_1 SIN9_1 OCU9_OTD1_1 OCU9_OTD0_1 TIN48_0 - SCL9 SCS80_0 SOT8_0 SCL8 SCS171_0 SCS170_0 OCU10_OTD1_0 ICU10_IN1_0 ICU10_IN0_0 SCK9_1 ICU9_IN1_1 ICU9_IN0_1 RX3_0 - SDA8 TOT49_0 TIN49_0 TOT48_0 TOT48_1 TIN48_1 - SOT17_0 SCK17_0 TX3_0 TX3_1 RX3_1 - SDA17 SCK12_1 SIN17_0 - WOT SCL17 SYSC0_CLK_1 - SYSC0_CLK_0 INDICATOR0_1 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 B - - C C C - - - - G G G G G G G G G G G G G G H H I R R - P0_29 M_SDATA1_1 M_DQ5 P0_30 M_SSEL1 VSS P1_00 MLBCLK P1_01 MLBSIG P1_02 MLBDAT VCC12 - VCC12 - VSS P3_08 AN4 P3_09 AN5 P3_10 AN6 P3_11 AN7 P1_03 AN8 P1_04 AN9 P3_12 AN10 P3_13 AN11 P1_05 AN12 P1_06 AN13 P3_14 AN14 P3_15 AN15 P1_07 AN16 P1_08 AN17 P1_09 AN18 P1_10 AN21 NMIX - X1A - VCC5 - X0A - VCC3 - P1_11 P1_12 VCC5 - M_DQ6 P0_31 M_SDATA1_3 M_DQ7 - - CRS_0 - - - - EINT4_0 EINT5_0 EINT12_3 - - - - SGO0_1 SGO1_1 - - - - ADTRG1_1 EINT9_0 EINT10_0 - EINT11_0 - - - EINT6_3 EINT3_0 EINT7_3 EINT8_3 EINT9_3 - - EINT10_3 SCS32_0 SCS33_0 - - - - - - - - - SCS31_0 - - - - - - - - - - - - - - PPG1_TOUT0_0 ICU1_IN0_0 PPG1_TOUT2_0 ICU1_IN1_0 - - - - - - - - - - - - TOT1_1 AIN8 BIN8 TIN16_1 TOT16_1 ZIN8 AIN9 TIN17_1 TOT17_1 PPG3_TOUT2_0 OCU2_OTD1_0 ICU8_IN1_0 TOT17_0 - PPG3_TOUT0_0 OCU2_OTD0_0 ICU8_IN0_0 TIN17_0 - PPG2_TOUT0_0 OCU1_OTD0_0 ICU2_IN0_0 - - PPG7_TOUT0_1 OCU1_OTD0_1 ICU1_IN0_1 EINT13_0 PPG4_TOUT2_0 OCU8_OTD1_0 ICU9_IN1_0 - - PPG6_TOUT2_1 OCU0_OTD1_1 ICU0_IN1_1 - - - PPG6_TOUT0_1 OCU0_OTD0_1 ICU0_IN0_1 SGO1_0 SCS80_2 PPG9_TOUT2_1 OCU8_OTD1_1 ICU8_IN1_1 - SCS30_0 SOT8_2 PPG9_TOUT0_1 OCU8_OTD0_1 ICU8_IN0_1 SGO2_0 SOT3_0 SCK8_2 PPG8_TOUT2_1 OCU2_OTD1_1 ICU2_IN1_1 SGA2_0 SCK3_0 SIN8_2 PPG8_TOUT0_1 OCU2_OTD0_1 ICU2_IN0_1 - SIN3_0 - PPG0_TOUT2_0 OCU0_OTD1_0 ICU0_IN1_0 SGA1_0 SCS23_0 - PPG0_TOUT0_0 OCU0_OTD0_0 ICU0_IN0_0 SGO0_0 - PPG7_TOUT2_1 OCU1_OTD1_1 ICU1_IN1_1 SGA0_0 - EINT12_0 PPG4_TOUT0_0 OCU8_OTD0_0 ICU9_IN0_0 - EINT11_3 EINT19_3 SGO3_1 - - EINT12_1 SGA3_1 EINT8_0 - EINT18_3 SGO2_1 EINT7_0 MDIO_0 EINT21_1 SGA2_1 EINT6_0 RXD3_0 EINT17_3 SGA1_1 EINT8_1 RXD2_0 EINT18_1 SGA0_1 EINT6_1 RXD1_0 M_CS#_2 MDC_0 COL_0 - P0_27 M_SDATA1_0 M_RWDS RXD0_0 P0_28 M_SDATA1_2 M_DQ4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TIN1_0 RX0_0 TOT1_0 TX0_0 SOT10_1 SCS100_1 TIN16_0 SCK16_0SCL16 SOT16_0SDA16 SCS161_0 - - - - - - - - - - - - - - - - SCK8_1 SOT8_1 TRACE1_1 TRACE2_1 - SOT0_0 SCS00_0 TOT16_0 - - - - - - - - - - - - - - - - - TRACE0_1 - - SCL0 - - SDA0 TRACE1_0 TRACE2_0 - TRACE_CLK_0 - - TRACE_CTL_0 - - TRACE_CLK_1 - - TRACE_CTL_1 INDICATOR0_0SCS160_0 - - SCK10_1TRACE3_1 - - - SCK0_0 TOT0_0 FRT4/8/9/10_TEXT BIN9 - - SIN0_0 TIN0_0 FRT0/1/2/3_TEXT - - TIN1_1 TX0_1 - - TOT0_1 RX0_1 - - TIN0_1 SIN8_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRACE0_0 - - - - SIN16_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRACE3_0 - - - - - - - 60 B - - - - 59 B - - - - - ZIN9 PPG2_TOUT2_0 OCU1_OTD1_0 ICU2_IN1_0 58 B - VCC3 - - - - 57 B VSS SCS22_0 - SIN10_1 56 - EINT5_3 - SCS80_1 55 - TXER_0 - 54 M_CK - 53 P0_26 M_SCLK0 - B - 52 - - - - - - SOT9_2 - SIN9_2 - - - SOT2_0 - SCK2_0 - SIN2_0 - - - EINT3_3 - EINT2_3 - EINT1_3 - EINT2_0 - - TXD2_0 - TXD1_0 - TXD0_0 M_DQ0 - - TXEN_0 - - VSS - P0_25 M_SDATA0_3 M_CS#_1 TXD3_0 - P0_24 M_SSEL0 - P0_23 M_SDATA0_1 M_DQ1 - P0_22 M_SDATA0_2 M_DQ2 - P0_21 M_SDATA0_0 M_DQ3 - VCC3 - - - - B - B SCS91_2 B SCS90_2 B SCK9_2 - B - 51 SCS21_0 50 SCS20_0 49 - 48 EINT4_3 47 - 46 - 45 *1: x, y, z are selected from the following parameters: x: E, D, C, B (Memory Size) y: S, A, B, U, C, D, T, E, F, V, G, H (Option) z: C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 22 of 322 - - S6J3310/20/30/40 Series - - LCDD11 LCDD12 - LCDD14 LCDD15 - LCDD7 LCDD10 LCDD13 - LCDD6 LCDD8 LCDD9 SCK0_1 SCS00_1 LCDD16 LCDD17 CS# RS RES# TE - SCS12_0 SCS13_0 SIN17_1 SCS171_1 WR# - SCL1 SDA1 SIN0_1 SOT0_1 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 PPG3_TOUT2_1 RD# SCS43_1 - LCDD5 SIN1_0 SCK1_0 SOT1_0 SCS10_0 SCS11_0 EINT15_1 EINT23_1 EINT0_2 EINT1_2 EINT5_2 EINT6_2 EINT7_2 EINT8_2 SIN1_1 SCK1_1 SOT1_1 SCS10_1 SCS11_1 SCS12_1 SCS13_1 SCK4_1 SCS40_1 SCS41_1 EINT21_2 EINT22_2 EINT23_2 EINT0_3 - EINT0_1 EINT1_0 EINT4_1 EINT5_1 EINT11_1 EINT13_1 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM0 PPG4_TOUT0_1 PPG4_TOUT2_1 PPG5_TOUT0_1 PPG5_TOUT2_1 PPG0/1/2/3/4/5_TIN1_1 SIN4_1 SOT4_1 EINT17_2 EINT18_2 EINT19_2 V0 V1 V2 V3 - SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 EINT1_1 EINT9_2 EINT10_2 EINT11_2 EINT12_2 EINT15_2 EINT16_2 COM1 COM2 COM3 SCS42_1 MDQM0 MCSX2 MCSX3 MRDY - MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 MAD15 MAD16 MAD17 MAD18 MAD19 MAD20 MAD21 MOEX MWEX MCLK EINT20_2 DSP0_B7_0 - DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 DSP0_G3_0 DSP0_G4_0 I2S1_ECLK_0 I2S1_SD_0 I2S1_WS_0 I2S1_SCK_0 DSP0_B5_0 DSP0_B6_0 DSP0_B7_1 MDQM1 - VCC53 P0_00 P0_01 P0_02 P0_03 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 VCC53 VSS VCC12 P3_00 P3_01 P3_02 P3_03 P3_04 P3_05 P3_06 P0_14 P0_15 P0_16 P3_07 P0_17 P0_18 P0_19 P0_20 VCC53 VSS AVSS AVSS AVCC3_DAC AVSS VSS S S S S S S S S S S S S S S T T T T T T T S S S T V V V U - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SDA9 - SCS91_0 SCS90_0 SOT9_0 - - - EINT18_4 PPG11_TOUT0_0 EINT15_4 PPG10_TOUT0_0 PWM2P2 PWM1M2 EINT17_4 PPG10_TOUT2_0 PWM1P2 - AN50 AN49 AN47 - P1_27 P1_26 P1_25 DVCC P P P 136 135 134 133 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SDA10 SCL10 - - - SIN11_0 SCS100_0 SOT10_0 SIN10_0 - - - - EINT22_4 PPG12_TOUT2_0 EINT20_4 PPG6/7/8/9/10/11_TIN1_0 SCK10_0 - - PWM2M3 EINT22_0 PPG13_TOUT0_0 PWM2P3 PWM1M3 EINT21_4 PPG12_TOUT0_0 PWM1P3 PWM2M2 EINT21_0 PPG11_TOUT2_0 - - AN55 AN54 AN53 AN52 AN51 DVCC DVSS P2_00 P1_31 P1_30 P1_29 P1_28 - - P P P P P 143 142 141 140 139 138 137 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL12 - - - SDA11 SCL11 SDA12 SCK12_0 SIN12_0 SCS111_0 SCS110_0 SOT11_0 SCK11_0 SOT12_0 PPG12/13/14/15_TIN1_0 PPG15_TOUT0_0 PPG14_TOUT2_0 PPG14_TOUT0_0 PPG13_TOUT2_0 EINT7_5 EINT23_0 PPG15_TOUT2_0 EINT3_5 EINT0_5 PWM2P5 PWM1M5 EINT6_5 PWM1P5 PWM2M4 EINT4_5 PWM2P4 PWM1M4 EINT2_5 PWM1P4 AN62 AN61 AN60 AN59 AN58 AN57 AN56 P2_07 P2_06 P2_05 P2_04 P2_03 P2_02 P2_01 P P P P P P P 150 149 148 147 146 145 PPG13_TOUT0_1 SCS21_1 PPG12_TOUT2_1 SCS20_1 PPG12_TOUT0_1 SOT2_1 EINT13_5 EINT12_5 EINT11_5 SEG1 SEG0 - - - - 144 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCS120_0 MDATA10 SEG2 MDATA9 MDATA8 - - PWM2M5 EINT9_5 - - - - - AN63 P3_26 P3_25 P3_24 DVCC DVSS P2_08 S S S P 156 155 154 153 152 PPG14_TOUT2_1 - - - EINT15_5 EINT14_5 151 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCK3_1 SIN3_1 - - - PPG14_TOUT0_1 SCS23_1 PPG13_TOUT2_1 SCS22_1 EINT16_5 PPG15_TOUT0_1 EINT3_1 - - - SEG4 SEG6 SEG5 - - - MCSX0 MDATA11 SEG3 MDATA13 MDATA12 - DSP0_EN_0 - P3_29 P3_28 VCC53 - VSS VCC12 - P2_09 - - - P3_27 S S S S 163 162 161 160 159 158 157 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL4 - - SCS32_1 SCS31_1 - - SCK4_0 SIN4_0 SCS33_1 EINT20_5 EINT19_5 SCS30_1 SOT3_1 EINT22_5 EINT0_0 EINT21_5 ADTRG1_2 ADTRG0_1 SEG13 SEG12 SEG11 SEG10 SEG9 EINT18_5 PPG12/13/14/15_TIN1_1 EINT17_5 PPG15_TOUT2_1 MDATA3 MDATA2 MDATA1 MDATA0 MCSX1 SEG8 SEG7 DSP0_R1_0 DSP0_R0_0 DSP0_CLK_0 DSP0_VSYNC_0 DSP0_HSYNC_0 MDATA15 MDATA14 P2_14 P2_10 P3_31 P3_30 S S S S S P2_13 S2 P2_12 S P2_11 170 169 168 167 166 165 164 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LCDD4 LCDD3 - - LCDD0 - SCS43_0 SCS42_0 LCDD2 LCDD1 SDA4 - - - SCS41_0 SCS40_0 SOT4_0 - EINT3_6 EINT2_6 EINT1_6 EINT0_6 EINT23_5 - SEG18 SEG17 SEG16 SEG15 SEG14 - MAD0 MDATA7 MDATA6 MDATA5 MDATA4 - DSP0_R6_0 DSP0_R5_0 DSP0_R4_0 DSP0_R3_0 DSP0_R2_0 VSS P2_19 P2_18 P2_17 P2_16 P2_15 - S S S S S 176 175 174 173 172 171 Figure 4-8: TEQFP-176 (S6J334xJyz *1) 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 TOP VIEW TEQFP-176 P P P P P P P P H H G G G G E E E O D N G G G L2 L2 L2 M L K K - DVSS P1_24 P1_23 P1_22 P1_21 P1_20 P1_19 P1_18 P1_17 DVCC DVSS AVSS AVRL5 AVRH5 AVCC5 P1_16 VCC5 VSS VCC12 VCC12 P1_15 P1_14 P3_23 P3_22 P3_21 P3_20 P3_19 P3_18 VSS C MODE PSC_1 RSTX P3_17 P3_16 P1_13 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_NTRST X0 X1 VSS AN46 AN45 AN44 AN43 AN42 AN41 AN40 AN39 ADTRG0_0 AN32 AN31 AN30 AN29 AN28 EINT2_4 EINT17_1 EINT20_1 AN26 AN25 AN24 - PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 EINT16_0 EINT15_0 EINT4_4 EINT19_1 EINT3_4 PPG6/7/8/9/10/11_TIN1_1 PPG11_TOUT2_1 PPG11_TOUT0_1 EINT0_4 EINT14_1 EINT14_0 - EINT14_4 EINT20_0 EINT13_4 EINT19_0 EINT12_4 EINT18_0 EINT11_4 EINT17_0 EINT9_4 SGA4_0 SGO3_0 TX6_1 RX6_1 TOT49_1 TIN49_1 OCU10_OTD1_1 OCU10_OTD0_1 SGO4_1 SGA4_1 SGA3_0 - PPG9_TOUT2_0 PPG9_TOUT0_0 PPG8_TOUT2_0 PPG8_TOUT0_0 PPG7_TOUT2_0 PPG7_TOUT0_0 PPG6_TOUT2_0 PPG6_TOUT0_0 SGO4_0 PPG5_TOUT2_0 PPG5_TOUT0_0 SCS120_1 SCS91_1 SCS90_1 TX5_1 ICU10_IN1_1 ICU10_IN0_1 PPG10_TOUT2_1 PPG10_TOUT0_1 OCU9_OTD0_0 - SCK9_0 SIN9_0 TX6_0 RX6_0 SCK8_0 SIN8_0 TX5_0 RX5_0 PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD0_0 OCU9_OTD1_0 SOT9_1 RX5_1 SIN9_1 OCU9_OTD1_1 OCU9_OTD0_1 TIN48_0 - SCL9 SCS80_0 SOT8_0 SCL8 SCS171_0 SCS170_0 OCU10_OTD1_0 ICU10_IN1_0 ICU10_IN0_0 SCK9_1 ICU9_IN1_1 ICU9_IN0_1 RX3_0 - SDA8 TOT49_0 TIN49_0 TOT48_0 TOT48_1 TIN48_1 - SOT17_0 SCK17_0 TX3_0 TX3_1 RX3_1 - SDA17 SCK12_1 SIN17_0 - WOT SCL17 SYSC0_CLK_1 - SYSC0_CLK_0 INDICATOR0_1 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 B - - C C C - - - - G G G G G G G G G G G G G G H H I R R - P0_29 M_SDATA1_1 M_DQ5 P0_30 M_SSEL1 VSS P1_00 - P1_01 - P1_02 - VCC12 - VCC12 - VSS P3_08 AN4 P3_09 AN5 P3_10 AN6 P3_11 AN7 P1_03 AN8 P1_04 AN9 P3_12 AN10 P3_13 AN11 P1_05 AN12 P1_06 AN13 P3_14 AN14 P3_15 AN15 P1_07 AN16 P1_08 AN17 P1_09 AN18 P1_10 AN21 NMIX - X1A - VCC5 - X0A - VCC3 - P1_11 P1_12 VCC5 - M_DQ6 P0_31 M_SDATA1_3 M_DQ7 - - - - - - - EINT4_0 EINT5_0 EINT12_3 - - - - SGO0_1 SGO1_1 - - - - ADTRG1_1 EINT9_0 EINT10_0 - EINT11_0 - - - EINT6_3 EINT3_0 EINT7_3 EINT8_3 EINT9_3 - - EINT10_3 SCS32_0 SCS33_0 - - - - - - - - - SCS31_0 - - - - - - - - - - - - - - PPG1_TOUT0_0 ICU1_IN0_0 PPG1_TOUT2_0 ICU1_IN1_0 - - - - - - - - - - - - TOT1_1 AIN8 BIN8 TIN16_1 TOT16_1 ZIN8 AIN9 TIN17_1 TOT17_1 PPG3_TOUT2_0 OCU2_OTD1_0 ICU8_IN1_0 TOT17_0 - PPG3_TOUT0_0 OCU2_OTD0_0 ICU8_IN0_0 TIN17_0 - PPG2_TOUT0_0 OCU1_OTD0_0 ICU2_IN0_0 - - PPG7_TOUT0_1 OCU1_OTD0_1 ICU1_IN0_1 EINT13_0 PPG4_TOUT2_0 OCU8_OTD1_0 ICU9_IN1_0 - - PPG6_TOUT2_1 OCU0_OTD1_1 ICU0_IN1_1 - - - PPG6_TOUT0_1 OCU0_OTD0_1 ICU0_IN0_1 SGO1_0 SCS80_2 PPG9_TOUT2_1 OCU8_OTD1_1 ICU8_IN1_1 - SCS30_0 SOT8_2 PPG9_TOUT0_1 OCU8_OTD0_1 ICU8_IN0_1 SGO2_0 SOT3_0 SCK8_2 PPG8_TOUT2_1 OCU2_OTD1_1 ICU2_IN1_1 SGA2_0 SCK3_0 SIN8_2 PPG8_TOUT0_1 OCU2_OTD0_1 ICU2_IN0_1 - SIN3_0 - PPG0_TOUT2_0 OCU0_OTD1_0 ICU0_IN1_0 SGA1_0 SCS23_0 - PPG0_TOUT0_0 OCU0_OTD0_0 ICU0_IN0_0 SGO0_0 - PPG7_TOUT2_1 OCU1_OTD1_1 ICU1_IN1_1 SGA0_0 - EINT12_0 PPG4_TOUT0_0 OCU8_OTD0_0 ICU9_IN0_0 - EINT11_3 EINT19_3 SGO3_1 - - EINT12_1 SGA3_1 EINT8_0 - EINT18_3 SGO2_1 EINT7_0 - EINT21_1 SGA2_1 EINT6_0 - EINT17_3 SGA1_1 EINT8_1 - EINT18_1 SGA0_1 EINT6_1 - M_CS#_2 - - - P0_27 M_SDATA1_0 M_RWDS - P0_28 M_SDATA1_2 M_DQ4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TIN1_0 RX0_0 TOT1_0 TX0_0 SOT10_1 SCS100_1 TIN16_0 SCK16_0SCL16 SOT16_0SDA16 SCS161_0 - - - - - - - - - - - - - - - - SCK8_1 SOT8_1 TRACE1_1 TRACE2_1 - SOT0_0 SCS00_0 TOT16_0 - - - - - - - - - - - - - - - - - TRACE0_1 - - SCL0 - - SDA0 TRACE1_0 TRACE2_0 - TRACE_CLK_0 - - TRACE_CTL_0 - - TRACE_CLK_1 - - TRACE_CTL_1 INDICATOR0_0SCS160_0 - - SCK10_1TRACE3_1 - - - SCK0_0 TOT0_0 FRT4/8/9/10_TEXT BIN9 - - SIN0_0 TIN0_0 FRT0/1/2/3_TEXT - - TIN1_1 TX0_1 - - TOT0_1 RX0_1 - - TIN0_1 SIN8_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRACE0_0 - - - - SIN16_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TRACE3_0 - - - - - - - 60 B - - - - 59 B - - - - - ZIN9 PPG2_TOUT2_0 OCU1_OTD1_0 ICU2_IN1_0 58 B - VCC3 - - - - 57 B VSS SCS22_0 - SIN10_1 56 - EINT5_3 - SCS80_1 55 - - - 54 M_CK - 53 P0_26 M_SCLK0 - B - 52 - - - - - - SOT9_2 - SIN9_2 - - - SOT2_0 - SCK2_0 - SIN2_0 - - - EINT3_3 - EINT2_3 - EINT1_3 - EINT2_0 - - - - - - - M_DQ0 - - - - - VSS - P0_25 M_SDATA0_3 M_CS#_1 - - P0_24 M_SSEL0 - P0_23 M_SDATA0_1 M_DQ1 - P0_22 M_SDATA0_2 M_DQ2 - P0_21 M_SDATA0_0 M_DQ3 - VCC3 - - - - B - B SCS91_2 B SCS90_2 B SCK9_2 - B - 51 SCS21_0 50 SCS20_0 49 - 48 EINT4_3 47 - 46 - 45 *1: x, y, z are selected from the following parameters: x: E, D, C, B (Memory Size) y: S, A, B, U, C, D, T, E, F, V, G, H (Option) z: C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 23 of 322 - - S6J3310/20/30/40 Series 4.1.3 TEQFP-144 Pin Assignment - - LCDD11 LCDD12 - ARH0_AIC1_UPCLK ARH0_AIC1_UPDATA1 LCDD14 LCDD15 - LCDD7 LCDD10 ARH0_AIC1_RCK ARH0_AIC1_RDA1 LCDD13 ARH0_AIC0_TCKI ARH0_AIC0_DNDATA1 - LCDD6 ARH0_AIC1_DNDATA1 LCDD8 LCDD9 ARH0_AIC1_DNDATA0 SCK0_1 SCS00_1 ARH0_AIC1_UPDATA0 ARH0_AIC0_DNCLK ARH0_AIC0_TDA1 LCDD16 LCDD17 CS# RS RES# TE - ARH0_AIC1_TCKI ARH0_AIC1_TDA1 ARH0_AIC1_dbg_out_1 ARH0_AIC1_dbg_out_0 ARH0_AIC1_TDA0 SCS12_0 SCS13_0 ARH0_AIC1_RDA0 SIN17_1 SCS171_1 ARH0_AIC0_dbg_out_1 ARH0_AIC0_dbg_out_0 ARH0_AIC0_dbg_select WR# ARH0_AIC0_DNDATA0 ARH0_AIC0_UPCLK ARH0_AIC0_UPDATA1 ARH0_AIC0_UPDATA0 - ARH0_AIC1_DNCLK SCL1 SDA1 SIN0_1 SOT0_1 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 PPG3_TOUT2_1 ARH0_AIC1_dbg_select RD# ARH0_AIC0_TDA0 SCS43_1 ARH0_AIC0_RCK ARH0_AIC0_RDA1 ARH0_AIC0_RDA0 - LCDD5 SIN1_0 SCK1_0 SOT1_0 SCS10_0 SCS11_0 EINT15_1 EINT23_1 EINT0_2 EINT1_2 EINT5_2 EINT6_2 EINT7_2 EINT8_2 SCK4_1 SCS40_1 SCS41_1 EINT21_2 EINT22_2 EINT23_2 EINT0_3 - EINT0_1 EINT1_0 EINT4_1 EINT5_1 EINT11_1 EINT13_1 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM0 EINT17_2 EINT18_2 EINT19_2 V0 V1 V2 V3 - SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 COM1 COM2 COM3 MDQM0 MCSX2 MCSX3 MRDY - MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 MOEX MWEX MCLK DSP0_B7_0 MDC_1 COL_1 CRS_1 - DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 DSP0_G3_0 DSP0_G4_0 I2S1_ECLK_0 I2S1_SD_0 I2S1_WS_0 I2S1_SCK_0 I2S0_ECLK_0 I2S0_SD_0 I2S0_WS_0 I2S0_SCK_0 DSP0_B5_0 DSP0_B6_0 DSP0_B7_1 RXCLK_0 RXER_0 RXDV_0 TXCLK_0 - VCC53 P0_00 P0_01 P0_02 P0_03 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 VCC53 VSS VCC12 P0_14 P0_15 P0_16 P0_17 P0_18 P0_19 P0_20 VCC53 VSS AVSS DAC_R C_R AVSS AVCC3_DAC DAC_L C_L AVSS VSS S S S S S S S S S S S S S S S S S V V V U A A A A - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - - - - - - DVCC 109 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SDA10 SCL10 - - - SDA9 SCS100_0 SOT10_0 SIN10_0 SCS91_0 SCS90_0 SOT9_0 EINT18_4 PPG11_TOUT0_0 EINT15_4 PPG10_TOUT0_0 PWM2P3 PWM1M3 EINT21_4 PPG12_TOUT0_0 PWM1P3 PWM2M2 EINT21_0 PPG11_TOUT2_0 PWM2P2 PWM1M2 EINT17_4 PPG10_TOUT2_0 PWM1P2 AN54 AN53 AN52 AN51 AN50 AN49 AN47 P1_31 P1_30 P1_29 P1_28 P1_27 P1_26 P1_25 P P P P P P P 116 115 114 113 112 111 110 EINT22_4 PPG12_TOUT2_0 EINT20_4 PPG6/7/8/9/10/11_TIN1_0 SCK10_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SDA11 SCL11 - - - SCS111_0 SCS110_0 SOT11_0 SCK11_0 - - EINT3_5 EINT0_5 - - - - SIN11_0 PPG15_TOUT0_0 PPG14_TOUT2_0 PPG14_TOUT0_0 PPG13_TOUT2_0 - - PWM2M4 EINT4_5 PWM2P4 PWM1M4 EINT2_5 PWM1P4 - - PWM2M3 EINT22_0 PPG13_TOUT0_0 AN59 AN58 AN57 AN56 - - AN55 P2_04 P2_03 P2_02 P2_01 DVCC DVSS P2_00 P P P P P 123 122 121 120 119 118 117 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL12 - PPG14_TOUT0_1 SCS23_1 - - - SDA12 EINT15_5 - - SCS120_0 SOT12_0 PPG12/13/14/15_TIN1_0 SEG4 - - EINT7_5 MCSX0 - - PWM2M5 EINT9_5 PWM2P5 PWM1M5 EINT6_5 PWM1P5 DSP0_EN_0 - - AN63 AN62 AN61 AN60 P2_09 DVCC DVSS P2_08 P2_07 P2_06 - - P2_05 - S P P P P 131 130 129 128 127 126 125 124 EINT23_0 PPG15_TOUT2_0 SCK12_0 - - SIN12_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL4 - - SCS32_1 SCS31_1 - - - SCK4_0 SIN4_0 SCS33_1 EINT20_5 EINT19_5 - - - EINT22_5 EINT0_0 EINT21_5 ADTRG1_2 ADTRG0_1 - - - SEG13 SEG12 SEG11 SEG10 SEG9 - - - MDATA3 MDATA2 MDATA1 MDATA0 MCSX1 - - - DSP0_R1_0 DSP0_R0_0 DSP0_CLK_0 DSP0_VSYNC_0 DSP0_HSYNC_0 - P2_14 P2_10 VCC53 - VSS VCC12 - S S S P2_13 S2 P2_12 S P2_11 138 137 136 135 134 133 132 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LCDD4 LCDD3 - - LCDD0 - SCS43_0 SCS42_0 LCDD2 LCDD1 SDA4 - - - SCS41_0 SCS40_0 SOT4_0 - EINT3_6 EINT2_6 EINT1_6 EINT0_6 EINT23_5 - SEG18 SEG17 SEG16 SEG15 SEG14 - MAD0 MDATA7 MDATA6 MDATA5 MDATA4 - DSP0_R6_0 DSP0_R5_0 DSP0_R4_0 DSP0_R3_0 DSP0_R2_0 VSS P2_19 P2_18 P2_17 P2_16 P2_15 - S S S S S 144 143 142 141 140 139 Figure 4-9: TEQFP-144 (S6J331xHyz *1) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TOP VIEW TEQFP-144 P P P P P P P P H H G O D N G L2 L2 L2 M L K K - DVSS P1_24 P1_23 P1_22 P1_21 P1_20 P1_19 P1_18 P1_17 DVCC DVSS AVSS AVRL5 AVRH5 AVCC5 P1_16 VCC5 VSS VCC12 VCC12 P1_15 P1_14 VSS C MODE PSC_1 RSTX P1_13 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_NTRST X0 X1 VSS AN46 AN45 AN44 AN43 AN42 AN41 AN40 AN39 ADTRG0_0 AN32 AN31 AN24 - PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 EINT16_0 EINT15_0 EINT14_0 - EINT14_4 EINT20_0 EINT13_4 EINT19_0 EINT12_4 EINT18_0 EINT11_4 EINT17_0 EINT9_4 SGA4_0 SGO3_0 SGA3_0 - PPG9_TOUT2_0 PPG9_TOUT0_0 PPG8_TOUT2_0 PPG8_TOUT0_0 PPG7_TOUT2_0 PPG7_TOUT0_0 PPG6_TOUT2_0 PPG6_TOUT0_0 SGO4_0 PPG5_TOUT2_0 PPG5_TOUT0_0 OCU9_OTD0_0 - SCK9_0 SIN9_0 TX6_0 RX6_0 SCK8_0 SIN8_0 TX5_0 RX5_0 PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD0_0 OCU9_OTD1_0 TIN48_0 - SCL9 SCS80_0 SOT8_0 SCL8 SCS171_0 SCS170_0 OCU10_OTD1_0 ICU10_IN1_0 ICU10_IN0_0 RX3_0 - SDA8 TOT49_0 TIN49_0 TOT48_0 - SOT17_0 SCK17_0 TX3_0 - SDA17 SCK12_1 SIN17_0 - WOT SCL17 SYSC0_CLK_1 - SYSC0_CLK_0 INDICATOR0_1 - - - X0A X1A P1_11 P1_12 VCC5 - EINT10_0 AN1(AL1) EINT11_0 AP1(AH1) - SGA1_0 BP1(BH1) SGA2_0 SGO2_0 - PPG1_TOUT0_0 ICU1_IN0_0 PPG1_TOUT2_0 ICU1_IN1_0 - AIN8 BIN8 ZIN8 AIN9 PPG3_TOUT0_0 OCU2_OTD0_0 ICU8_IN0_0 PPG3_TOUT2_0 OCU2_OTD1_0 ICU8_IN1_0 - - PPG2_TOUT0_0 OCU1_OTD0_0 ICU2_IN0_0 SGO1_0 - - - - - TIN0_0 TOT0_0 TIN1_0 TOT1_0 BIN9 SCK16_0 SOT16_0 - - - - - TIN16_0 SCL16 SDA16 - - - - - - FRT4/8/9/10_TEXT SCK0_0 TX0_0 - FRT0/1/2/3_TEXT SIN0_0 RX0_0 - SOT0_0 SCS00_0 - TOT16_0 - - - - - - - - - SCL0 SDA0 TRACE_CLK_0 - - - - - - - - - - - - - SIN16_0 - - - - - - - - - - - - - - - - - - - - - - TRACE0_0 - TRACE2_0 - - - TRACE1_0 - TRACE_CTL_0 - - - - - - - TRACE3_0 - - - - - - - NMIX - BN1(BL1) ADTRG1_1 EINT9_0 PPG0_TOUT2_0 OCU0_OTD1_0 ICU0_IN1_0 SGO0_0 - PPG0_TOUT0_0 OCU0_OTD0_0 ICU0_IN0_0 SGA0_0 - - - - - - - - R P1_10 AN21 AP0(AH0) - - - - - - - - - 72 R P1_09 AN18 EINT8_0 AN0(AL0) - - - - - - - - - 71 I P1_08 AN17 EINT7_0 BP0(BH0) - - - - - - - - - - 70 H P1_07 AN16 EINT6_0 BN0(BL0) - - - - - - - - - 69 H P1_06 AN13 EINT5_0 - - - - - - - - - - 68 G P1_05 AN12 EINT4_0 - - - - - - - - - 67 G P1_04 AN9 - - - - - - - - - - 66 G P1_03 AN8 - SCS33_0 - - - - - - - 65 G VCC5 - - - SCS31_0 - - - - - - 64 - EINT12_3 SCS32_0 - - - - - - 63 G VSS - EINT10_3 - SCS80_2 - - - - 62 - G VCC12 - CRS_0 - SCS30_0 SOT8_2 - - - 61 - VCC12 - EINT11_3 - SOT3_0 SCK8_2 - - - 60 - P1_02 MLBDAT COL_0 - M_CS#_2 MDC_0 EINT9_3 SCK3_0 SIN8_2 - - 59 - P1_01 MLBSIG - - EINT8_3 SIN3_0 - - SCS161_0 - 58 C P1_00 MLBCLK MDIO_0 EINT7_3 SCS23_0 - SCS160_0 INDICATOR0_0 57 VCC3 - - RXD3_0 EINT3_0 - - - 56 C - RXD2_0 EINT6_3 - - - 55 - C P0_31 M_SDATA1_3 M_DQ7 VSS M_DQ6 - SCS22_0 - TOT17_0 54 - P0_30 M_SSEL1 - - TIN17_0 53 B P0_29 M_SDATA1_1 M_DQ5 RXD1_0 EINT5_3 - EINT13_0 PPG4_TOUT2_0 OCU8_OTD1_0 ICU9_IN1_0 52 B - P0_27 M_SDATA1_0 M_RWDS RXD0_0 P0_28 M_SDATA1_2 M_DQ4 - - EINT12_0 PPG4_TOUT0_0 OCU8_OTD0_0 ICU9_IN0_0 51 B - TXER_0 - - 50 B - - - 49 B VCC3 - M_CK - - 48 - - - PPG2_TOUT2_0 OCU1_OTD1_0 ICU2_IN1_0 ZIN9 47 - VSS - 46 P0_26 M_SCLK0 - - - B - 45 - 44 - - - - - - SOT9_2 - SIN9_2 - - - SOT2_0 - SCK2_0 - SIN2_0 - - - EINT3_3 - EINT2_3 - EINT1_3 - EINT2_0 - - TXD2_0 - TXD1_0 - TXD0_0 M_DQ0 - - TXEN_0 - - VSS - P0_25 M_SDATA0_3 M_CS#_1 TXD3_0 - P0_24 M_SSEL0 - P0_23 M_SDATA0_1 M_DQ1 - P0_22 M_SDATA0_2 M_DQ2 - P0_21 M_SDATA0_0 M_DQ3 - VCC3 - - - - B - B SCS91_2 B SCS90_2 B SCK9_2 - B - 43 SCS21_0 42 SCS20_0 41 - 40 EINT4_3 39 - 38 - 37 *1: x, y, z are selected from the following parameters: x: E, D, C, B (Memory Size) y: S, A, B, U, C, D, T, E, F, V, G, H (Option) z: C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 24 of 322 S6J3310/20/30/40 Series - - LCDD11 LCDD12 - LCDD14 LCDD15 - LCDD7 LCDD10 LCDD13 - LCDD6 LCDD8 LCDD9 SCK0_1 SCS00_1 LCDD16 LCDD17 CS# RS RES# TE - SCS12_0 SCS13_0 SIN17_1 SCS171_1 WR# - SCL1 SDA1 SIN0_1 SOT0_1 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 PPG3_TOUT2_1 RD# SCS43_1 - LCDD5 SIN1_0 SCK1_0 SOT1_0 SCS10_0 SCS11_0 EINT15_1 EINT23_1 EINT0_2 EINT1_2 EINT5_2 EINT6_2 EINT7_2 EINT8_2 SCK4_1 SCS40_1 SCS41_1 EINT21_2 EINT22_2 EINT23_2 EINT0_3 - EINT0_1 EINT1_0 EINT4_1 EINT5_1 EINT11_1 EINT13_1 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM0 EINT17_2 EINT18_2 EINT19_2 V0 V1 V2 V3 - SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 COM1 COM2 COM3 MDQM0 MCSX2 MCSX3 MRDY - MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 MOEX MWEX MCLK DSP0_B7_0 MDC_1 COL_1 CRS_1 - DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 DSP0_G3_0 DSP0_G4_0 I2S1_ECLK_0 I2S1_SD_0 I2S1_WS_0 I2S1_SCK_0 I2S0_ECLK_0 I2S0_SD_0 I2S0_WS_0 I2S0_SCK_0 DSP0_B5_0 DSP0_B6_0 DSP0_B7_1 RXCLK_0 RXER_0 RXDV_0 TXCLK_0 - VCC53 P0_00 P0_01 P0_02 P0_03 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 VCC53 VSS VCC12 P0_14 P0_15 P0_16 P0_17 P0_18 P0_19 P0_20 VCC53 VSS AVSS DAC_R C_R AVSS AVCC3_DAC DAC_L C_L AVSS VSS S S S S S S S S S S S S S S S S S V V V U A A A A - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL10 - - - SDA9 - SIN10_0 SCS91_0 SCS90_0 - - SOT9_0 EINT20_4 PPG6/7/8/9/10/11_TIN1_0 SCK10_0 EINT18_4 PPG11_TOUT0_0 EINT15_4 PPG10_TOUT0_0 PWM1P3 PWM2M2 EINT21_0 PPG11_TOUT2_0 PWM2P2 PWM1M2 EINT17_4 PPG10_TOUT2_0 PWM1P2 - AN52 AN51 AN50 AN49 AN47 - P1_29 P1_28 P1_27 P1_26 P1_25 DVCC P P P P P 114 113 112 111 110 109 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL11 - - - - SDA10 SCK11_0 - - - - SIN11_0 PPG13_TOUT2_0 - - EINT0_5 - - EINT22_4 PPG12_TOUT2_0 PWM1P4 - - PWM2M3 EINT22_0 PPG13_TOUT0_0 PWM2P3 PWM1M3 EINT21_4 PPG12_TOUT0_0 AN56 - - AN55 AN54 AN53 P2_01 DVCC DVSS P2_00 P1_31 P1_30 P P P P SCS100_0 120 119 118 117 116 115 SOT10_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL12 - - - SDA11 SDA12 SCK12_0 SIN12_0 SCS111_0 SCS110_0 SOT11_0 SOT12_0 PPG12/13/14/15_TIN1_0 PPG15_TOUT0_0 PPG14_TOUT2_0 PPG14_TOUT0_0 EINT7_5 EINT23_0 PPG15_TOUT2_0 EINT3_5 PWM2P5 PWM1M5 EINT6_5 PWM1P5 PWM2M4 EINT4_5 PWM2P4 PWM1M4 EINT2_5 AN62 AN61 AN60 AN59 AN58 AN57 P2_07 P2_06 P2_05 P2_04 P2_03 P2_02 P P P P P P 126 125 124 123 122 - - - - PPG14_TOUT0_1 SCS23_1 - - EINT15_5 - - 121 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCS120_0 - - SEG4 - - - - MCSX0 - - PWM2M5 EINT9_5 - DSP0_EN_0 - - AN63 VSS VCC12 - P2_09 DVCC DVSS P2_08 - - S P 132 131 130 129 - 128 S 127 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL4 - - SCS32_1 SCS31_1 - SCK4_0 SIN4_0 SCS33_1 EINT20_5 EINT19_5 - EINT22_5 EINT0_0 EINT21_5 ADTRG1_2 ADTRG0_1 - SEG13 SEG12 SEG11 SEG10 SEG9 - MDATA3 MDATA2 MDATA1 MDATA0 MCSX1 - DSP0_R1_0 DSP0_R0_0 DSP0_CLK_0 DSP0_VSYNC_0 DSP0_HSYNC_0 P2_14 P2_10 VCC53 - S S P2_13 S2 P2_12 S P2_11 138 137 136 135 134 133 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LCDD4 LCDD3 - - LCDD0 - SCS43_0 SCS42_0 LCDD2 LCDD1 SDA4 - - - SCS41_0 SCS40_0 SOT4_0 - EINT3_6 EINT2_6 EINT1_6 EINT0_6 EINT23_5 - SEG18 SEG17 SEG16 SEG15 SEG14 - MAD0 MDATA7 MDATA6 MDATA5 MDATA4 - DSP0_R6_0 DSP0_R5_0 DSP0_R4_0 DSP0_R3_0 DSP0_R2_0 VSS P2_19 P2_18 P2_17 P2_16 P2_15 - S S S S S 144 143 142 141 140 139 Figure 4-10: TEQFP-144 (S6J332xHyz *1) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TOP VIEW TEQFP-144 P P P P P P P P H H G O D N G L2 L2 L2 M L K K - DVSS P1_24 P1_23 P1_22 P1_21 P1_20 P1_19 P1_18 P1_17 DVCC DVSS AVSS AVRL5 AVRH5 AVCC5 P1_16 VCC5 VSS VCC12 VCC12 P1_15 P1_14 VSS C MODE PSC_1 RSTX P1_13 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_NTRST X0 X1 VSS AN46 AN45 AN44 AN43 AN42 AN41 AN40 AN39 ADTRG0_0 AN32 AN31 AN24 - PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 EINT16_0 EINT15_0 EINT14_0 - EINT14_4 EINT20_0 EINT13_4 EINT19_0 EINT12_4 EINT18_0 EINT11_4 EINT17_0 EINT9_4 SGA4_0 SGO3_0 SGA3_0 - PPG9_TOUT2_0 PPG9_TOUT0_0 PPG8_TOUT2_0 PPG8_TOUT0_0 PPG7_TOUT2_0 PPG7_TOUT0_0 PPG6_TOUT2_0 PPG6_TOUT0_0 SGO4_0 PPG5_TOUT2_0 PPG5_TOUT0_0 OCU9_OTD0_0 - SCK9_0 SIN9_0 TX6_0 RX6_0 SCK8_0 SIN8_0 TX5_0 RX5_0 PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD0_0 OCU9_OTD1_0 TIN48_0 - SCL9 SCS80_0 SOT8_0 SCL8 SCS171_0 SCS170_0 OCU10_OTD1_0 ICU10_IN1_0 ICU10_IN0_0 RX3_0 - SDA8 TOT49_0 TIN49_0 TOT48_0 - SOT17_0 SCK17_0 TX3_0 - SDA17 SCK12_1 SIN17_0 - WOT SCL17 SYSC0_CLK_1 - SYSC0_CLK_0 INDICATOR0_1 - 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 B B B - - C C C - - - - G G G G G G H H I R R - P0_28 M_SDATA1_2 M_DQ4 P0_29 M_SDATA1_1 M_DQ5 P0_30 M_SSEL1 P0_31 M_SDATA1_3 M_DQ7 VSS VCC3 - P1_00 MLBCLK P1_01 MLBSIG P1_02 MLBDAT VCC12 - VCC12 - VSS P1_03 AN8 P1_04 AN9 P1_05 AN12 P1_06 AN13 P1_07 AN16 P1_08 AN17 P1_09 AN18 P1_10 AN21 NMIX - X1A - VCC5 - X0A - P1_11 P1_12 VCC5 - M_DQ6 - - CRS_0 - - - - EINT4_0 EINT5_0 EINT6_0 EINT7_0 EINT8_0 MDIO_0 - - EINT11_3 EINT12_3 - - - - BN0(BL0) BP0(BH0) AN0(AL0) AP0(AH0) BN1(BL1) EINT10_0 AN1(AL1) EINT11_0 AP1(AH1) EINT3_0 EINT7_3 EINT8_3 EINT9_3 - - EINT10_3 SCS32_0 SCS33_0 - - - - SGA1_0 BP1(BH1) SGA2_0 SGO2_0 - SOT3_0 SCS30_0 - - SCS31_0 - - - - - - - - - - - - - - - - TOT17_0 - - - - - - - - - - - - AIN8 BIN8 ZIN8 AIN9 PPG3_TOUT2_0 OCU2_OTD1_0 ICU8_IN1_0 TIN17_0 - PPG3_TOUT0_0 OCU2_OTD0_0 ICU8_IN0_0 - - PPG2_TOUT0_0 OCU1_OTD0_0 ICU2_IN0_0 EINT13_0 PPG4_TOUT2_0 OCU8_OTD1_0 ICU9_IN1_0 SCS80_2 PPG1_TOUT2_0 ICU1_IN1_0 - SOT8_2 PPG1_TOUT0_0 ICU1_IN0_0 SGO1_0 SCK8_2 PPG0_TOUT2_0 OCU0_OTD1_0 ICU0_IN1_0 SGO0_0 SCK3_0 PPG0_TOUT0_0 OCU0_OTD0_0 ICU0_IN0_0 SGA0_0 SIN3_0 EINT12_0 PPG4_TOUT0_0 OCU8_OTD0_0 ICU9_IN0_0 - RXD3_0 ADTRG1_1 EINT9_0 - RXD2_0 M_CS#_2 MDC_0 COL_0 RXD1_0 - - - - - - - - - - - - - - - - - TIN0_0 TOT0_0 TIN1_0 TOT1_0 BIN9 SCK16_0 SOT16_0 - - - - - - - - - - - - - TX0_0 TIN16_0 SCL16 SDA16 - SCS161_0 - - - - - - - - - - - - - FRT4/8/9/10_TEXT SCK0_0 RX0_0 - FRT0/1/2/3_TEXT SIN0_0 SCS160_0 INDICATOR0_0 - - - SOT0_0 SCS00_0 - TOT16_0 - - - - - - - - - - - - - - - SCL0 SDA0 - - - - - - - - - - - - - - - - - - - SIN16_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - TRACE0_0 - TRACE2_0 - - - TRACE1_0 - TRACE_CLK_0 - - - TRACE_CTL_0 - - - - - TRACE3_0 - - - - - - - 50 B - - 49 - - PPG2_TOUT2_0 OCU1_OTD1_0 ICU2_IN1_0 ZIN9 48 - - SIN8_2 - SCS23_0 - EINT6_3 - - P0_27 M_SDATA1_0 M_RWDS RXD0_0 - B - 47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - VCC3 - - VSS - - 46 - - 45 - - - - SCS90_2 - SCK9_2 - SOT9_2 - SIN9_2 - - - SCS20_0 SCS22_0 SOT2_0 EINT5_3 SCK2_0 TXER_0 SIN2_0 M_CK B - P0_26 M_SCLK0 44 EINT3_3 - EINT2_3 - EINT1_3 - EINT2_0 - - - TXD2_0 - TXD1_0 - TXD0_0 - TXEN_0 P0_25 M_SDATA0_3 M_CS#_1 TXD3_0 VSS - - P0_24 M_SSEL0 - P0_23 M_SDATA0_1 M_DQ1 - P0_22 M_SDATA0_2 M_DQ2 - - P0_21 M_SDATA0_0 M_DQ3 - B VCC3 - SCS91_2 B - B SCS21_0 43 B - 42 - B EINT4_3 41 - 40 - 39 M_DQ0 38 - 37 *1: x, y, z are selected from the following parameters: x: E, D, C, B (Memory Size) y: S, A, B, U, C, D, T, E, F, V, G, H (Option) z: C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 25 of 322 - - S6J3310/20/30/40 Series - - LCDD11 LCDD12 - LCDD14 LCDD15 - LCDD7 LCDD10 LCDD13 - LCDD6 LCDD8 LCDD9 SCK0_1 SCS00_1 LCDD16 LCDD17 CS# RS RES# TE - SCS12_0 SCS13_0 SIN17_1 SCS171_1 WR# - SCL1 SDA1 SIN0_1 SOT0_1 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 PPG3_TOUT2_1 RD# SCS43_1 - LCDD5 SIN1_0 SCK1_0 SOT1_0 SCS10_0 SCS11_0 EINT15_1 EINT23_1 EINT0_2 EINT1_2 EINT5_2 EINT6_2 EINT7_2 EINT8_2 SCK4_1 SCS40_1 SCS41_1 EINT21_2 EINT22_2 EINT23_2 EINT0_3 - EINT0_1 EINT1_0 EINT4_1 EINT5_1 EINT11_1 EINT13_1 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM0 EINT17_2 EINT18_2 EINT19_2 V0 V1 V2 V3 - SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 COM1 COM2 COM3 MDQM0 MCSX2 MCSX3 MRDY - MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 MOEX MWEX MCLK DSP0_B7_0 MDC_1 COL_1 CRS_1 - DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 DSP0_G3_0 DSP0_G4_0 I2S1_ECLK_0 I2S1_SD_0 I2S1_WS_0 I2S1_SCK_0 DSP0_B5_0 DSP0_B6_0 DSP0_B7_1 RXCLK_0 RXER_0 RXDV_0 TXCLK_0 - VCC53 P0_00 P0_01 P0_02 P0_03 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 VCC53 VSS VCC12 P0_14 P0_15 P0_16 P0_17 P0_18 P0_19 P0_20 VCC53 VSS AVSS AVSS AVCC3_DAC AVSS VSS S S S S S S S S S S S S S S S S S V V V U - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL10 - - - SDA9 - SIN10_0 SCS91_0 SCS90_0 - - SOT9_0 EINT20_4 PPG6/7/8/9/10/11_TIN1_0 SCK10_0 EINT18_4 PPG11_TOUT0_0 EINT15_4 PPG10_TOUT0_0 PWM1P3 PWM2M2 EINT21_0 PPG11_TOUT2_0 PWM2P2 PWM1M2 EINT17_4 PPG10_TOUT2_0 PWM1P2 - AN52 AN51 AN50 AN49 AN47 - P1_29 P1_28 P1_27 P1_26 P1_25 DVCC P P P P P 114 113 112 111 110 109 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL11 - - - - SDA10 SCK11_0 - - - - SIN11_0 PPG13_TOUT2_0 - - EINT0_5 - - EINT22_4 PPG12_TOUT2_0 PWM1P4 - - PWM2M3 EINT22_0 PPG13_TOUT0_0 PWM2P3 PWM1M3 EINT21_4 PPG12_TOUT0_0 AN56 - - AN55 AN54 AN53 P2_01 DVCC DVSS P2_00 P1_31 P1_30 P P P P SCS100_0 120 119 118 117 116 115 SOT10_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL12 - - - SDA11 SDA12 SCK12_0 SIN12_0 SCS111_0 SCS110_0 SOT11_0 SOT12_0 PPG12/13/14/15_TIN1_0 PPG15_TOUT0_0 PPG14_TOUT2_0 PPG14_TOUT0_0 EINT7_5 EINT23_0 PPG15_TOUT2_0 EINT3_5 PWM2P5 PWM1M5 EINT6_5 PWM1P5 PWM2M4 EINT4_5 PWM2P4 PWM1M4 EINT2_5 AN62 AN61 AN60 AN59 AN58 AN57 P2_07 P2_06 P2_05 P2_04 P2_03 P2_02 P P P P P P 126 125 124 123 122 - - - - PPG14_TOUT0_1 SCS23_1 - - EINT15_5 - - 121 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCS120_0 - - SEG4 - - - - MCSX0 - - PWM2M5 EINT9_5 - DSP0_EN_0 - - AN63 VSS VCC12 - P2_09 DVCC DVSS P2_08 - - S P 132 131 130 129 - 128 S 127 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL4 - - SCS32_1 SCS31_1 - SCK4_0 SIN4_0 SCS33_1 EINT20_5 EINT19_5 - EINT22_5 EINT0_0 EINT21_5 ADTRG1_2 ADTRG0_1 - SEG13 SEG12 SEG11 SEG10 SEG9 - MDATA3 MDATA2 MDATA1 MDATA0 MCSX1 - DSP0_R1_0 DSP0_R0_0 DSP0_CLK_0 DSP0_VSYNC_0 DSP0_HSYNC_0 P2_14 P2_10 VCC53 - S S P2_13 S2 P2_12 S P2_11 138 137 136 135 134 133 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LCDD4 LCDD3 - - LCDD0 - SCS43_0 SCS42_0 LCDD2 LCDD1 SDA4 - - - SCS41_0 SCS40_0 SOT4_0 - EINT3_6 EINT2_6 EINT1_6 EINT0_6 EINT23_5 - SEG18 SEG17 SEG16 SEG15 SEG14 - MAD0 MDATA7 MDATA6 MDATA5 MDATA4 - DSP0_R6_0 DSP0_R5_0 DSP0_R4_0 DSP0_R3_0 DSP0_R2_0 VSS P2_19 P2_18 P2_17 P2_16 P2_15 - S S S S S 144 143 142 141 140 139 Figure 4-11: TEQFP-144 (S6J333xHyz *1) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TOP VIEW TEQFP-144 P P P P P P P P H H G O D N G L2 L2 L2 M L K K - DVSS P1_24 P1_23 P1_22 P1_21 P1_20 P1_19 P1_18 P1_17 DVCC DVSS AVSS AVRL5 AVRH5 AVCC5 P1_16 VCC5 VSS VCC12 VCC12 P1_15 P1_14 VSS C MODE PSC_1 RSTX P1_13 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_NTRST X0 X1 VSS AN46 AN45 AN44 AN43 AN42 AN41 AN40 AN39 ADTRG0_0 AN32 AN31 AN24 - PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 EINT16_0 EINT15_0 EINT14_0 - EINT14_4 EINT20_0 EINT13_4 EINT19_0 EINT12_4 EINT18_0 EINT11_4 EINT17_0 EINT9_4 SGA4_0 SGO3_0 SGA3_0 - PPG9_TOUT2_0 PPG9_TOUT0_0 PPG8_TOUT2_0 PPG8_TOUT0_0 PPG7_TOUT2_0 PPG7_TOUT0_0 PPG6_TOUT2_0 PPG6_TOUT0_0 SGO4_0 PPG5_TOUT2_0 PPG5_TOUT0_0 OCU9_OTD0_0 - SCK9_0 SIN9_0 TX6_0 RX6_0 SCK8_0 SIN8_0 TX5_0 RX5_0 PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD0_0 OCU9_OTD1_0 TIN48_0 - SCL9 SCS80_0 SOT8_0 SCL8 SCS171_0 SCS170_0 OCU10_OTD1_0 ICU10_IN1_0 ICU10_IN0_0 RX3_0 - SDA8 TOT49_0 TIN49_0 TOT48_0 - SOT17_0 SCK17_0 TX3_0 - SDA17 SCK12_1 SIN17_0 - WOT SCL17 SYSC0_CLK_1 - SYSC0_CLK_0 INDICATOR0_1 - 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 B B B - - C C C - - - - G G G G G G H H I R R - P0_28 M_SDATA1_2 M_DQ4 P0_29 M_SDATA1_1 M_DQ5 P0_30 M_SSEL1 P0_31 M_SDATA1_3 M_DQ7 VSS VCC3 - P1_00 MLBCLK P1_01 MLBSIG P1_02 MLBDAT VCC12 - VCC12 - VSS P1_03 AN8 P1_04 AN9 P1_05 AN12 P1_06 AN13 P1_07 AN16 P1_08 AN17 P1_09 AN18 P1_10 AN21 NMIX - X1A - VCC5 - X0A - P1_11 P1_12 VCC5 - M_DQ6 - - CRS_0 - - - - EINT4_0 EINT5_0 EINT6_0 EINT7_0 EINT8_0 MDIO_0 - - EINT11_3 EINT12_3 - - - - - - - - - EINT10_0 - EINT11_0 - EINT3_0 EINT7_3 EINT8_3 EINT9_3 - - EINT10_3 SCS32_0 SCS33_0 - - - - SGA1_0 - SGA2_0 SGO2_0 - SOT3_0 SCS30_0 - - SCS31_0 - - - - - - - - - - - - - - - - TOT17_0 - - - - - - - - - - - - AIN8 BIN8 ZIN8 AIN9 PPG3_TOUT2_0 OCU2_OTD1_0 ICU8_IN1_0 TIN17_0 - PPG3_TOUT0_0 OCU2_OTD0_0 ICU8_IN0_0 - - PPG2_TOUT0_0 OCU1_OTD0_0 ICU2_IN0_0 EINT13_0 PPG4_TOUT2_0 OCU8_OTD1_0 ICU9_IN1_0 SCS80_2 PPG1_TOUT2_0 ICU1_IN1_0 - SOT8_2 PPG1_TOUT0_0 ICU1_IN0_0 SGO1_0 SCK8_2 PPG0_TOUT2_0 OCU0_OTD1_0 ICU0_IN1_0 SGO0_0 SCK3_0 PPG0_TOUT0_0 OCU0_OTD0_0 ICU0_IN0_0 SGA0_0 SIN3_0 EINT12_0 PPG4_TOUT0_0 OCU8_OTD0_0 ICU9_IN0_0 - RXD3_0 ADTRG1_1 EINT9_0 - RXD2_0 M_CS#_2 MDC_0 COL_0 RXD1_0 - - - - - - - - - - - - - - - - - TIN0_0 TOT0_0 TIN1_0 TOT1_0 BIN9 SCK16_0 SOT16_0 - - - - - - - - - - - - - TX0_0 TIN16_0 SCL16 SDA16 - SCS161_0 - - - - - - - - - - - - - FRT4/8/9/10_TEXT SCK0_0 RX0_0 - FRT0/1/2/3_TEXT SIN0_0 SCS160_0 INDICATOR0_0 - - - SOT0_0 SCS00_0 - TOT16_0 - - - - - - - - - - - - - - - SCL0 SDA0 - - - - - - - - - - - - - - - - - - - SIN16_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - TRACE0_0 - TRACE2_0 - - - TRACE1_0 - TRACE_CLK_0 - - - TRACE_CTL_0 - - - - - TRACE3_0 - - - - - - - 50 B - - 49 - - PPG2_TOUT2_0 OCU1_OTD1_0 ICU2_IN1_0 ZIN9 48 - - SIN8_2 - SCS23_0 - EINT6_3 - - P0_27 M_SDATA1_0 M_RWDS RXD0_0 - B - 47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - VCC3 - - VSS - - 46 - - 45 - - - - SCS90_2 - SCK9_2 - SOT9_2 - SIN9_2 - - - SCS20_0 SCS22_0 SOT2_0 EINT5_3 SCK2_0 TXER_0 SIN2_0 M_CK B - P0_26 M_SCLK0 44 EINT3_3 - EINT2_3 - EINT1_3 - EINT2_0 - - - TXD2_0 - TXD1_0 - TXD0_0 - TXEN_0 P0_25 M_SDATA0_3 M_CS#_1 TXD3_0 VSS - - P0_24 M_SSEL0 - P0_23 M_SDATA0_1 M_DQ1 - P0_22 M_SDATA0_2 M_DQ2 - - P0_21 M_SDATA0_0 M_DQ3 - B VCC3 - SCS91_2 B - B SCS21_0 43 B - 42 - B EINT4_3 41 - 40 - 39 M_DQ0 38 - 37 *1: x, y, z are selected from the following parameters: x: E, D, C, B (Memory Size) y: S, A, B, U, C, D, T, E, F, V, G, H (Option) z: C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 26 of 322 - - S6J3310/20/30/40 Series - - LCDD11 LCDD12 - LCDD14 LCDD15 - LCDD7 LCDD10 LCDD13 - LCDD6 LCDD8 LCDD9 SCK0_1 SCS00_1 LCDD16 LCDD17 CS# RS RES# TE - SCS12_0 SCS13_0 SIN17_1 SCS171_1 WR# - SCL1 SDA1 SIN0_1 SOT0_1 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 PPG3_TOUT2_1 RD# SCS43_1 - LCDD5 SIN1_0 SCK1_0 SOT1_0 SCS10_0 SCS11_0 EINT15_1 EINT23_1 EINT0_2 EINT1_2 EINT5_2 EINT6_2 EINT7_2 EINT8_2 SCK4_1 SCS40_1 SCS41_1 EINT21_2 EINT22_2 EINT23_2 EINT0_3 - EINT0_1 EINT1_0 EINT4_1 EINT5_1 EINT11_1 EINT13_1 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM0 EINT17_2 EINT18_2 EINT19_2 V0 V1 V2 V3 - SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 COM1 COM2 COM3 MDQM0 MCSX2 MCSX3 MRDY - MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 MOEX MWEX MCLK DSP0_B7_0 - DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 DSP0_G3_0 DSP0_G4_0 I2S1_ECLK_0 I2S1_SD_0 I2S1_WS_0 I2S1_SCK_0 DSP0_B5_0 DSP0_B6_0 DSP0_B7_1 - VCC53 P0_00 P0_01 P0_02 P0_03 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 VCC53 VSS VCC12 P0_14 P0_15 P0_16 P0_17 P0_18 P0_19 P0_20 VCC53 VSS AVSS AVSS AVCC3_DAC AVSS VSS S S S S S S S S S S S S S S S S S V V V U - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL10 - - - SDA9 - SIN10_0 SCS91_0 SCS90_0 - - SOT9_0 EINT20_4 PPG6/7/8/9/10/11_TIN1_0 SCK10_0 EINT18_4 PPG11_TOUT0_0 EINT15_4 PPG10_TOUT0_0 PWM1P3 PWM2M2 EINT21_0 PPG11_TOUT2_0 PWM2P2 PWM1M2 EINT17_4 PPG10_TOUT2_0 PWM1P2 - AN52 AN51 AN50 AN49 AN47 - P1_29 P1_28 P1_27 P1_26 P1_25 DVCC P P P P P 114 113 112 111 110 109 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL11 - - - - SDA10 SCK11_0 - - - - SIN11_0 PPG13_TOUT2_0 - - EINT0_5 - - EINT22_4 PPG12_TOUT2_0 PWM1P4 - - PWM2M3 EINT22_0 PPG13_TOUT0_0 PWM2P3 PWM1M3 EINT21_4 PPG12_TOUT0_0 AN56 - - AN55 AN54 AN53 P2_01 DVCC DVSS P2_00 P1_31 P1_30 P P P P SCS100_0 120 119 118 117 116 115 SOT10_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL12 - - - SDA11 SDA12 SCK12_0 SIN12_0 SCS111_0 SCS110_0 SOT11_0 SOT12_0 PPG12/13/14/15_TIN1_0 PPG15_TOUT0_0 PPG14_TOUT2_0 PPG14_TOUT0_0 EINT7_5 EINT23_0 PPG15_TOUT2_0 EINT3_5 PWM2P5 PWM1M5 EINT6_5 PWM1P5 PWM2M4 EINT4_5 PWM2P4 PWM1M4 EINT2_5 AN62 AN61 AN60 AN59 AN58 AN57 P2_07 P2_06 P2_05 P2_04 P2_03 P2_02 P P P P P P 126 125 124 123 122 - - - - PPG14_TOUT0_1 SCS23_1 - - EINT15_5 - - 121 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCS120_0 - - SEG4 - - - - MCSX0 - - PWM2M5 EINT9_5 - DSP0_EN_0 - - AN63 VSS VCC12 - P2_09 DVCC DVSS P2_08 - - S P 132 131 130 129 - 128 S 127 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCL4 - - SCS32_1 SCS31_1 - SCK4_0 SIN4_0 SCS33_1 EINT20_5 EINT19_5 - EINT22_5 EINT0_0 EINT21_5 ADTRG1_2 ADTRG0_1 - SEG13 SEG12 SEG11 SEG10 SEG9 - MDATA3 MDATA2 MDATA1 MDATA0 MCSX1 - DSP0_R1_0 DSP0_R0_0 DSP0_CLK_0 DSP0_VSYNC_0 DSP0_HSYNC_0 P2_14 P2_10 VCC53 - S S P2_13 S2 P2_12 S P2_11 138 137 136 135 134 133 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LCDD4 LCDD3 - - LCDD0 - SCS43_0 SCS42_0 LCDD2 LCDD1 SDA4 - - - SCS41_0 SCS40_0 SOT4_0 - EINT3_6 EINT2_6 EINT1_6 EINT0_6 EINT23_5 - SEG18 SEG17 SEG16 SEG15 SEG14 - MAD0 MDATA7 MDATA6 MDATA5 MDATA4 - DSP0_R6_0 DSP0_R5_0 DSP0_R4_0 DSP0_R3_0 DSP0_R2_0 VSS P2_19 P2_18 P2_17 P2_16 P2_15 - S S S S S 144 143 142 141 140 139 Figure 4-12: TEQFP-144 (S6J334xHyz *1) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TOP VIEW TEQFP-144 P P P P P P P P H H G O D N G L2 L2 L2 M L K K - DVSS P1_24 P1_23 P1_22 P1_21 P1_20 P1_19 P1_18 P1_17 DVCC DVSS AVSS AVRL5 AVRH5 AVCC5 P1_16 VCC5 VSS VCC12 VCC12 P1_15 P1_14 VSS C MODE PSC_1 RSTX P1_13 JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_NTRST X0 X1 VSS AN46 AN45 AN44 AN43 AN42 AN41 AN40 AN39 ADTRG0_0 AN32 AN31 AN24 - PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0 EINT16_0 EINT15_0 EINT14_0 - EINT14_4 EINT20_0 EINT13_4 EINT19_0 EINT12_4 EINT18_0 EINT11_4 EINT17_0 EINT9_4 SGA4_0 SGO3_0 SGA3_0 - PPG9_TOUT2_0 PPG9_TOUT0_0 PPG8_TOUT2_0 PPG8_TOUT0_0 PPG7_TOUT2_0 PPG7_TOUT0_0 PPG6_TOUT2_0 PPG6_TOUT0_0 SGO4_0 PPG5_TOUT2_0 PPG5_TOUT0_0 OCU9_OTD0_0 - SCK9_0 SIN9_0 TX6_0 RX6_0 SCK8_0 SIN8_0 TX5_0 RX5_0 PPG0/1/2/3/4/5_TIN1_0 OCU10_OTD0_0 OCU9_OTD1_0 TIN48_0 - SCL9 SCS80_0 SOT8_0 SCL8 SCS171_0 SCS170_0 OCU10_OTD1_0 ICU10_IN1_0 ICU10_IN0_0 RX3_0 - SDA8 TOT49_0 TIN49_0 TOT48_0 - SOT17_0 SCK17_0 TX3_0 - SDA17 SCK12_1 SIN17_0 - WOT SCL17 SYSC0_CLK_1 - SYSC0_CLK_0 INDICATOR0_1 - 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 B B B - - C C C - - - - G G G G G G H H I R R - P0_28 M_SDATA1_2 M_DQ4 P0_29 M_SDATA1_1 M_DQ5 P0_30 M_SSEL1 P0_31 M_SDATA1_3 M_DQ7 VSS VCC3 - P1_00 - P1_01 - P1_02 - VCC12 - VCC12 - VSS P1_03 AN8 P1_04 AN9 P1_05 AN12 P1_06 AN13 P1_07 AN16 P1_08 AN17 P1_09 AN18 P1_10 AN21 NMIX - X1A - VCC5 - X0A - P1_11 P1_12 VCC5 - M_DQ6 - - - - - - - EINT4_0 EINT5_0 EINT6_0 EINT7_0 EINT8_0 - - - EINT11_3 EINT12_3 - - - - - - - - - EINT10_0 - EINT11_0 - EINT3_0 EINT7_3 EINT8_3 EINT9_3 - - EINT10_3 SCS32_0 SCS33_0 - - - - SGA1_0 - SGA2_0 SGO2_0 - SOT3_0 SCS30_0 - - SCS31_0 - - - - - - - - - - - - - - - - TOT17_0 - - - - - - - - - - - - AIN8 BIN8 ZIN8 AIN9 PPG3_TOUT2_0 OCU2_OTD1_0 ICU8_IN1_0 TIN17_0 - PPG3_TOUT0_0 OCU2_OTD0_0 ICU8_IN0_0 - - PPG2_TOUT0_0 OCU1_OTD0_0 ICU2_IN0_0 EINT13_0 PPG4_TOUT2_0 OCU8_OTD1_0 ICU9_IN1_0 SCS80_2 PPG1_TOUT2_0 ICU1_IN1_0 - SOT8_2 PPG1_TOUT0_0 ICU1_IN0_0 SGO1_0 SCK8_2 PPG0_TOUT2_0 OCU0_OTD1_0 ICU0_IN1_0 SGO0_0 SCK3_0 PPG0_TOUT0_0 OCU0_OTD0_0 ICU0_IN0_0 SGA0_0 SIN3_0 EINT12_0 PPG4_TOUT0_0 OCU8_OTD0_0 ICU9_IN0_0 - - ADTRG1_1 EINT9_0 - - M_CS#_2 - - - - - - - - - - - - - - - - - - - - TIN0_0 TOT0_0 TIN1_0 TOT1_0 BIN9 SCK16_0 SOT16_0 - - - - - - - - - - - - - TX0_0 TIN16_0 SCL16 SDA16 - SCS161_0 - - - - - - - - - - - - - FRT4/8/9/10_TEXT SCK0_0 RX0_0 - FRT0/1/2/3_TEXT SIN0_0 SCS160_0 INDICATOR0_0 - - - SOT0_0 SCS00_0 - TOT16_0 - - - - - - - - - - - - - - - SCL0 SDA0 - - - - - - - - - - - - - - - - - - - SIN16_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - TRACE0_0 - TRACE2_0 - - - TRACE1_0 - TRACE_CLK_0 - - - TRACE_CTL_0 - - - - - TRACE3_0 - - - - - - - 50 B - - 49 - - PPG2_TOUT2_0 OCU1_OTD1_0 ICU2_IN1_0 ZIN9 48 - - SIN8_2 - SCS23_0 - EINT6_3 - - P0_27 M_SDATA1_0 M_RWDS - - B - 47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - VCC3 - - VSS - - 46 - - 45 - - - - SCS90_2 - SCK9_2 - SOT9_2 - SIN9_2 - - - SCS20_0 SCS22_0 SOT2_0 EINT5_3 SCK2_0 - SIN2_0 M_CK B - P0_26 M_SCLK0 44 EINT3_3 - EINT2_3 - EINT1_3 - EINT2_0 - - - - - - - - - - P0_25 M_SDATA0_3 M_CS#_1 - VSS - - P0_24 M_SSEL0 - P0_23 M_SDATA0_1 M_DQ1 - P0_22 M_SDATA0_2 M_DQ2 - - P0_21 M_SDATA0_0 M_DQ3 - B VCC3 - SCS91_2 B - B SCS21_0 43 B - 42 - B EINT4_3 41 - 40 - 39 M_DQ0 38 - 37 *1: x, y, z are selected from the following parameters: x: E, D, C, B (Memory Size) y: S, A, B, U, C, D, T, E, F, V, G, H (Option) z: C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 27 of 322 - - S6J3310/20/30/40 Series 4.2 Package Dimensions TEQFP208 4.2.1 Figure 4-13: TEQFP208 Package Type Package Code TEQFP 208 pin LEW208 4 D D1 D2 D3 5 7 E3 E2 E1 E EXPOSED PAD 0.20 C A-B D TOP VIEW BOTTOM VIEW 0.20 C A-B D 2 R1 L2 DETAIL A A A SEATING PLANE A' A1 11 e b M IN. NOM. L1 b SECTION A-A' DETAIL A MAX. 0.15 0.05 D 30.00 BSC D1 28.00 BSC D2 7.05 REF D3 6.05 REF E 30.00 BSC E1 28.00 BSC E2 7.05 REF 6.05 REF E3 R1 0.08 R2 0.08 0.20 0 4 8 c 0.09 b 0.17 0.22 0.27 L 0.45 0.60 0.75 0.20 1.00 REF 0.25 L 2 e R2 L c 1.70 A L 1 D 10 DIMENSION SYMBOL C A-B 8 SIDE VIEW A1 0.08 C 0.08 GAUGE PLANE 0.50 BSC 002-12477 ** PACKAGE OUTLINE, 208 LEAD TEQFP 28.0X28.0X1.7 M M LEW 208 REV** Document Number: 002-10635 Rev. *H Page 28 of 322 S6J3310/20/30/40 Series 4.2.2 TEQFP176 Figure 4-14: TEQFP176 Package Type Package Code TEQFP 176 pin LEV176 4 D D2 D1 5 7 D3 E1 E3 E2 E EXPOSED PAD 0.20 C A-B D 0.20 C A-B D TOP VIEW BOTTO M VIEW 2 DETAIL A L2 R1 A A A' A1 11 e b 0.08 C A-B 10 c R2 0.08 C b L L1 D 8 SID E VIEW GAUGE PLA N E SEATI N G PLA N E SECTION A -A' DETAIL A DIM ENSION SYM BOL M IN. NOM . A1 0.15 0.05 D 26.00 BSC D1 24.00 BSC D2 6.65 REF D3 5.45 REF E 26.00 BSC E1 24.00 BSC E2 6.65 REF 5.45 REF E3 R1 0.08 R2 0.08 M AX. 1.70 A 0 0.20 2 8 c 0.09 b 0.17 0.22 0.27 L 0.45 0.60 0.75 L 1 L 2 e 0.20 1.00 REF 0.25 0.50 BSC 002-13653 ** PACKAGE OUTLINE, 176 LEAD TEQFP 24.0X24.0X1.7 M M LEV176 REV** Document Number: 002-10635 Rev. *H Page 29 of 322 S6J3310/20/30/40 Series 4.2.3 TEQFP144 Figure 4-15: TEQFP144 (0.5 mm Pitch) Package Type Package Code TEQFP 144 pin LEX144 4 D 5 D1 D2 7 D3 E1 E E3 E2 EXPOSED PAD 0.20 C A-B D BOTTOM VIEW 0.20 C A-B D TOP VIEW 2 DETAIL A L2 R1 A A A' A1 e 11 SEATING PLANE 0.08 C b 0.08 C A-B GAUGE PLANE 10 b L1 D c R2 L 8 SIDE VIEW SECTION A-A' DETAIL A DIM ENSION SYM BOL M IN. NOM . A1 0.15 0.05 D 22.00 BSC D1 20.00 BSC D2 5.80 REF D3 4.60 REF E 22.00 BSC E1 20.00 BSC E2 5.80 REF 4.60 REF E3 R1 0.08 R2 0.08 M AX. 1.70 A 0 0.20 4 8 c 0.09 b 0.17 0.22 0.27 L 0.45 0.60 0.75 L 1 L 2 e 0.20 1.00 REF 0.25 0.50 BSC 002-13553 ** PACKAGE OUTLINE, 144 LEAD TEQFP 20.0X20.0X1.7 M M LEX144 REV** Document Number: 002-10635 Rev. *H Page 30 of 322 S6J3310/20/30/40 Series Figure 4-16: TEQFP144 (0.4 mm Pitch) Package Type Package Code TEQFP 144 pin LEK144 4 D D2 5 7 D1 D3 E1 E E3 E2 EXPOSED PAD 0.20 C A-B D BOTTOM VIEW 0.20 C A-B D TOP VIEW 2 DETAIL A L2 A A SEATING PLANE A' 11 A1 R1 10 GAUGE PLANE L e 0.08 C b 0.08 C A-B D 8 c R2 b L1 SECTION A-A' DETAIL A SIDE VIEW SYMBOL DIMENSION 1.70 A A1 0.15 0.05 D 18.00 BSC D1 16.00 BSC D2 5.80 REF D3 4.60 REF E 18.00 BSC E1 16.00 BSC E2 5.80 REF 4.60 REF E3 R1 0.08 R2 0.08 N OTES : M IN. NOM. MAX. 0.20 0 c 0.09 b 0.13 L 0.45 L1 L2 e 4 8 0.20 0.18 0.23 0.60 0.75 1.00 REF 0.25 0.40 BSC 002-11502 ** PACKAGE OUTLINE, 144 LEAD TEQFP 16.0X16.0X1.7 M M LEK144 REV** Document Number: 002-10635 Rev. *H Page 31 of 322 S6J3310/20/30/40 Series 5. IO Circuit Type 5.1 I/O Circuit Type This section explains I/O circuit types. Type A Circuit Analog output - - B Pull-up control Digital output - - - - Digital output - - Remarks Analog output (3 V) Audio DAC output General-purpose I/O port Output 2 mA, 5 mA, 6 mA or 15 mA selectable 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input TTL input Pull-down control CMOS-hys input PSS control TTL input PSS control C Pull-up control Digital output - - - - Digital output - - General-purpose I/O port Output 2 mA, 5 mA, 6 mA or 15 mA selectable 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input MediaLB level hysteresis input Pull-down control CMOS-hys input PSS control MediaLB-hys input PSS control D Digital output - - External 1.2 V regulator control Output 2 mA Digital output E Pull-up control Digital output - - - - Digital output - - General-purpose I/O port Output 1 mA, 2 mA or 5 mA selectable 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input Automotive hysteresis input Pull-down control CMOS-hys input PSS control Automotive input PSS control Document Number: 002-10635 Rev. *H Page 32 of 322 S6J3310/20/30/40 Series Type G Circuit Pull-up control Digital output - - - - Digital output - - Remarks General-purpose I/O port with analog input Output 1 mA, 2 mA or 5 mA selectable 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input Automotive hysteresis input Pull-down control CMOS-hys input PSS control Automotive input PSS control Analog input H Pull-up control - - Digital output - Digital output - - Pull-down control - - General-purpose I/O port with analog input Output 1 mA, 2 mA, 3 mA (I2C) or 5 mA selectable 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input Automotive hysteresis input TTL input CMOS-hys input PSS control Automotive input PSS control TTL input PSS control Analog input I - 50 k with pull-up CMOS hysteresis input - Main oscillation I/O - JTAG_NTRST 50 k with pull-down TTL input - CMOS-hys input K X1 OSC input X0 PSS control L - - TTL input Document Number: 002-10635 Rev. *H Page 33 of 322 S6J3310/20/30/40 Series Type L2 Circuit - - - Remarks JTAG_TDI/TMS/TCK 50 k with pull-up TTL input TTL input M Digital output - - JTAG_TDO Output 5 mA Digital output N - RSTX input 50 k with pull-up CMOS hysteresis input - CMOS hysteresis input - General-purpose I/O port with analog input Output 1 mA, 2 mA, 5 mA or 30 mA selectable 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input Automotive hysteresis input - - O CMOS-hys input P Pull-up control Digital output - - - Digital output - - Pull-down control CMOS-hys input PSS control Automotive input PSS control Analog input Q Pull-up control Digital output - - - - Digital output - - General-purpose I/O port Output 1 mA, 2 mA, 5 mA or 30 mA selectable 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input Automotive hysteresis input Pull-down control CMOS-hys input PSS control Automotive input PSS control Document Number: 002-10635 Rev. *H Page 34 of 322 S6J3310/20/30/40 Series Type R Circuit Pull-up control Digital output - - - Digital output - - Pull-down control - Remarks Sub oscillation I/O shared General-purpose I/O port Output 1 mA, 2 mA or 5 mA selectable 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input Automotive hysteresis input CMOS-hys input PSS/OSC control Automotive input PSS/OSC control OSC input PSS/OSC control Pull-up control Digital output Digital output Pull-down control CMOS-hys input PSS/OSC control Automotive input PSS/OSC control S Pull-up control Digital output - - - Digital output - - Pull-down control - - General-purpose I/O port with LCDC COM/SEG output Output 1 mA, 2 mA or 5 mA selectable 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input Automotive hysteresis input TTL input CMOS-hys input PSS control Automotive input PSS control TTL input PSS control LCDC COM/SEG output Document Number: 002-10635 Rev. *H Page 35 of 322 S6J3310/20/30/40 Series Type S2 Circuit Pull-up control Digital output - - - Digital output - - Pull-down control - - Remarks General-purpose I/O port with LCDC COM/SEG output Output 1 mA, 2 mA, 5 mA or 15 mA selectable 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input Automotive hysteresis input TTL input CMOS-hys input PSS control Automotive input PSS control TTL input PSS control LCDC COM/SEG output T Pull-up control Digital output - - - - Digital output - - Pull-down control - General-purpose I/O port Output 1 mA, 2 mA or 5 mA selectable 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input Automotive hysteresis input TTL input CMOS-hys input PSS control Automotive input PSS control TTL input PSS control U Pull-up control - - - - - Pull-down control - General-purpose input port with LCDC reference voltage input 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input Automotive hysteresis input TTL input CMOS-hys input PSS control; Automotive input PSS control; TTL input PSS control LCDC reference voltage input Document Number: 002-10635 Rev. *H Page 36 of 322 S6J3310/20/30/40 Series Type V Circuit Pull-up control Digital output - - - Digital output - - Pull-down control - - Remarks General-purpose I/O port with LCDC reference voltage input Output 1 mA, 2 mA or 5 mA selectable 50 k with pull-up resistor control 50 k with pull-down resistor control CMOS hysteresis input Automotive hysteresis input TTL input CMOS -hys input PSS control; Automotive input PSS control TTL input PSS control LCDC reference voltage input 5.2 Note Alphabet which shows I/O circuit type is described with corresponding pin number in pin assignment figure. Document Number: 002-10635 Rev. *H Page 37 of 322 S6J3310/20/30/40 Series 6. Port Description 6.1 Port Description List The table shows the port function of description which is supported. The port function which is not described in the table is not supported for the product. Table 6-1 S6J3310 Series Port Name Description VCC12 1.2 V external power supply pin VCC5 5 V external power supply pin VCC3 3 V external power supply pin VCC53 3 V/5 V external power supply pin VSS GND AVCC3_DAC AVCC5 AVRH5 AVRL5 Audio DAC power supply pin A/D converter analog power supply pin A/D converter upper limit reference voltage pin A/D converter lower limit reference voltage pin AVSS A/D converter GND DVCC SMC large current port power supply pin DVSS SMC large current port GND X1 X0 X1A X0A NMIX Main clock oscillator output pin Main clock oscillator input pin Sub-clock oscillator output Sub-clock oscillator input Non-maskable interrupt input pin Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 18, 18, 24, 57, 65, 73, 58, 66, 74, 89, 113, 132, 90, 114, 133, 131 159 191 60, 68, 76, 72, 88, 104, 92 116 135, 37, 45, 53, 46, 54, 62, 53 61 69 1, 1, 1, 16, 16, 22, 26, 34, 42, 133 161 193 17, 17, 23, 27, 35, 43, 36, 44, 52, 43, 51, 59, 45, 53, 61, 52, 60, 68, 59, 67, 75, 73, 89, 105, 86, 104, 121, 91, 115, 134, 132, 160, 192, 144 176 208 32 40 48 94 118 142 95 119 143 96 120 144 28, 36, 44, 31, 39, 47, 35, 43, 51, 97 121 145 99 123 147 109 133 157 119 143 170 129 153 183 98 122 146 108 132 156 118 142 169 128 152 182 74 90 106 75 91 107 71 87 103 70 86 102 69 85 101 Remark Page 38 of 322 S6J3310/20/30/40 Series Port Name Description RSTX PSC_1 MODE C JTAG_NTRST JTAG_TDO JTAG_TDI JTAG_TCK JTAG_TMS TRACE0_0 TRACE1_0 TRACE2_0 TRACE3_0 TRACE_CLK_0 TRACE_CTL_0 TRACE0_1 TRACE1_1 TRACE2_1 TRACE3_1 TRACE_CLK_1 TRACE_CTL_1 ADTRG0_0 ADTRG1_0 ADTRG0_1 ADTRG1_1 ADTRG1_2 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN21 AN24 AN25 AN26 AN28 AN29 AN30 AN31 External reset input pin External Power Supply Control pin Mode Pin External capacity connection output pin JTAG test reset input pin JTAG test data output pin JTAG test data input pin JTAG test clock input pin JTAG test mode state input pin Trace data 0 output pin (0) Trace data 1 output pin (0) Trace data 2 output pin (0) Trace data 3 output pin (0) Trace clock (0) Trace control (0) Trace data 0 output pin (1) Trace data 1 output pin (1) Trace data 2 output pin (1) Trace data 3 output pin (1) Trace clock (1) Trace control (1) A/D converter external trigger input pin (0) A/D converter external trigger input pin (0) A/D converter external trigger input pin (1) A/D converter external trigger input pin (1) A/D converter external trigger input pin (2) ADC Unit0 ch.4 input pin ADC Unit0 ch.5 input pin ADC Unit0 ch.6 input pin ADC Unit0 ch.7 input pin ADC Unit0 ch.8 input pin ADC Unit0 ch.9 input pin ADC Unit0 ch.10 input pin ADC Unit0 ch.11 input pin ADC Unit0 ch.12 input pin ADC Unit0 ch.13 input pin ADC Unit0 ch.14 input pin ADC Unit0 ch.15 input pin ADC Unit0 ch.16 input pin ADC Unit0 ch.17 input pin ADC Unit0 ch.18 input pin ADC Unit0 ch.21 input pin ADC Unit0 ch.24 input pin ADC Unit0 ch.25 input pin ADC Unit0 ch.26 input pin ADC Unit0 ch.28 input pin ADC Unit0 ch.29 input pin ADC Unit0 ch.30 input pin ADC Unit0 ch.31 input pin Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 82 100 117 83 101 118 84 102 119 85 103 120 76 92 108 77 93 109 78 94 110 79 95 111 80 96 112 63 77 89 64 78 90 65 81 93 66 82 94 68 84 98 67 83 95 71 83 72 84 75 87 76 88 80 92 79 91 93 117 139 140 134 166 198 66 82 94 135 167 199 69 81 70 82 71 83 72 84 61 73 85 62 74 86 75 87 76 88 63 77 89 64 78 90 79 91 80 92 65 81 93 66 82 94 67 83 95 68 84 98 81 97 113 98 114 99 115 108 125 109 126 110 127 87 111 128 Remark Page 39 of 322 S6J3310/20/30/40 Series Port Name Description AN32 AN39 AN40 AN41 AN42 AN43 AN44 AN45 AN46 AN47 AN49 AN50 AN51 AN52 AN53 AN54 AN55 AN56 AN57 AN58 AN59 AN60 AN61 AN62 AN63 TX0_0 TX1_0 TX2_0 TX3_0 TX5_0 TX6_0 TX0_1 TX1_1 TX2_1 TX3_1 TX5_1 TX6_1 TX0_2 TX3_2 RX0_0 RX1_0 RX2_0 RX3_0 RX5_0 RX6_0 RX0_1 RX1_1 RX2_1 RX3_1 ADC Unit1 ch.32 input pin ADC Unit1 ch.39 input pin ADC Unit1 ch.40 input pin ADC Unit1 ch.41 input pin ADC Unit1 ch.42 input pin ADC Unit1 ch.43 input pin ADC Unit1 ch.44 input pin ADC Unit1 ch.45 input pin ADC Unit1 ch.46 input pin ADC Unit1 ch.47 input pin ADC Unit1 ch.49 input pin ADC Unit1 ch.50 input pin ADC Unit1 ch.51 input pin ADC Unit1 ch.52 input pin ADC Unit1 ch.53 input pin ADC Unit1 ch.54 input pin ADC Unit1 ch.55 input pin ADC Unit1 ch.56 input pin ADC Unit1 ch.57 input pin ADC Unit1 ch.58 input pin ADC Unit1 ch.59 input pin ADC Unit1 ch.60 input pin ADC Unit1 ch.61 input pin ADC Unit1 ch.62 input pin ADC Unit1 ch.63 input pin CAN transmission data 0 output pin (0) CAN transmission data 1 output pin (0) CAN transmission data 2 output pin (0) CAN transmission data 3 output pin (0) CAN transmission data 5 output pin (0) CAN transmission data 6 output pin (0) CAN transmission data 0 output pin (1) CAN transmission data 1 output pin (1) CAN transmission data 2 output pin (1) CAN transmission data 3 output pin (1) CAN transmission data 5 output pin (1) CAN transmission data 6 output pin (1) CAN transmission data 0 output pin (2) CAN transmission data 3 output pin (2) CAN reception data 0 input pin (0) CAN reception data 1 input pin (0) CAN reception data 2 input pin (0) CAN reception data 3 input pin (0) CAN reception data 5 input pin (0) CAN reception data 6 input pin (0) CAN reception data 0 input pin (1) CAN reception data 1 input pin (1) CAN reception data 2 input pin (1) CAN reception data 3 input pin (1) Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 88 112 129 100 124 148 101 125 149 102 126 150 103 127 151 104 128 152 105 129 153 106 130 154 107 131 155 110 134 158 111 135 160 112 136 161 113 137 162 114 138 164 115 139 165 116 140 166 117 141 168 120 144 171 121 145 173 122 146 174 123 147 175 124 148 177 125 149 178 126 150 179 127 151 181 64 78 90 94 103 87 111 128 101 125 149 129 153 105 71 83 87 92 99 115 107 124 110 127 7 16 63 77 89 93 102 81 97 113 100 124 148 128 152 104 70 82 84 91 98 114 - Remark Page 40 of 322 S6J3310/20/30/40 Series Port Name Description RX5_1 RX6_1 RX0_2 RX3_2 EINT0_0 EINT1_0 EINT2_0 EINT3_0 EINT4_0 EINT5_0 EINT6_0 EINT7_0 EINT8_0 EINT9_0 EINT10_0 EINT11_0 EINT12_0 EINT13_0 EINT14_0 EINT15_0 EINT16_0 EINT17_0 EINT18_0 EINT19_0 EINT20_0 EINT21_0 EINT22_0 EINT23_0 EINT0_1 EINT1_1 EINT2_1 EINT3_1 EINT4_1 EINT5_1 EINT6_1 EINT7_1 EINT8_1 EINT9_1 EINT10_1 EINT11_1 EINT12_1 EINT13_1 EINT14_1 EINT15_1 EINT16_1 EINT17_1 EINT18_1 EINT19_1 EINT20_1 CAN reception data 5 input pin (1) CAN reception data 6 input pin (1) CAN reception data 0 input pin (2) CAN reception data 3 input pin (2) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (0) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 106 123 109 126 6 15 137 169 201 3 3 3 38 46 54 48 56 64 61 73 85 62 74 86 63 77 89 64 78 90 65 81 93 66 82 94 67 83 95 68 84 98 70 86 102 71 87 103 81 97 113 87 111 128 88 112 129 100 124 148 102 126 150 104 128 152 106 130 154 113 137 162 117 141 168 124 148 177 2 2 2 19 25 184 162 194 4 4 4 5 5 5 70 82 6 72 84 7 8 6 6 9 79 91 7 7 10 98 114 8 8 11 136 106 123 69 81 109 126 105 122 Remark Page 41 of 322 S6J3310/20/30/40 Series Port Name Description EINT21_1 EINT22_1 EINT23_1 EINT0_2 EINT1_2 EINT2_2 EINT3_2 EINT4_2 EINT5_2 EINT6_2 EINT7_2 EINT8_2 EINT9_2 EINT10_2 EINT11_2 EINT12_2 EINT13_2 EINT14_2 EINT15_2 EINT16_2 EINT17_2 EINT18_2 EINT19_2 EINT20_2 EINT21_2 EINT22_2 EINT23_2 EINT0_3 EINT1_3 EINT2_3 EINT3_3 EINT4_3 EINT5_3 EINT6_3 EINT7_3 EINT8_3 EINT9_3 EINT10_3 EINT11_3 EINT12_3 EINT13_3 EINT14_3 EINT15_3 EINT16_3 EINT17_3 EINT18_3 EINT19_3 EINT20_3 EINT21_3 External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (1) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (2) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (3) Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 75 87 140 9 9 12 10 10 13 11 11 14 15 16 17 12 12 18 13 13 19 14 14 20 15 15 21 20 26 21 27 22 28 23 29 30 31 24 32 25 33 19 26 34 20 27 35 21 28 36 29 37 22 30 38 23 31 39 24 32 40 25 33 41 39 47 55 40 48 56 41 49 57 42 50 58 44 52 60 47 55 63 49 57 65 50 58 66 51 59 67 54 62 70 55 63 71 56 64 72 77 78 79 80 71 83 76 88 80 92 96 97 Remark Page 42 of 322 S6J3310/20/30/40 Series Port Name Description EINT22_3 EINT23_3 EINT0_4 EINT1_4 EINT2_4 EINT3_4 EINT4_4 EINT5_4 EINT6_4 EINT7_4 EINT8_4 EINT9_4 EINT10_4 EINT11_4 EINT12_4 EINT13_4 EINT14_4 EINT15_4 EINT16_4 EINT17_4 EINT18_4 EINT19_4 EINT20_4 EINT21_4 EINT22_4 EINT23_4 EINT0_5 EINT1_5 EINT2_5 EINT3_5 EINT4_5 EINT5_5 EINT6_5 EINT7_5 EINT8_5 EINT9_5 EINT10_5 EINT11_5 EINT12_5 EINT13_5 EINT14_5 EINT15_5 EINT16_5 EINT17_5 EINT18_5 EINT19_5 EINT20_5 EINT21_5 EINT22_5 External interrupt input pin (3) External interrupt input pin (3) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (4) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) External interrupt input pin (5) Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 99 100 115 99 116 124 107 125 108 127 110 130 131 137 138 93 117 139 141 101 125 149 103 127 151 105 129 153 107 131 155 110 134 158 159 111 135 160 112 136 161 163 114 138 164 115 139 165 116 140 166 167 120 144 171 172 121 145 173 122 146 174 123 147 175 176 125 149 178 126 150 179 180 127 151 181 185 154 186 155 187 156 188 157 189 130 158 190 163 195 164 196 165 197 134 166 198 135 167 199 136 168 200 138 170 202 Remark Page 43 of 322 S6J3310/20/30/40 Series Port Name Description EINT23_5 EINT0_6 EINT1_6 EINT2_6 EINT3_6 SCS00_0 SCS10_0 SCS11_0 SCS12_0 SCS13_0 SCS20_0 SCS21_0 SCS22_0 SCS23_0 SCS30_0 SCS31_0 SCS32_0 SCS33_0 SCS40_0 SCS41_0 SCS42_0 SCS43_0 SCS80_0 SCS90_0 SCS91_0 SCS100_0 SCS110_0 SCS111_0 SCS120_0 SCS160_0 SCS161_0 SCS170_0 SCS171_0 SCS00_1 SCS10_1 SCS11_1 SCS12_1 SCS13_1 SCS20_1 SCS21_1 SCS22_1 SCS23_1 SCS30_1 SCS31_1 SCS32_1 SCS33_1 SCS40_1 SCS41_1 SCS42_1 External interrupt input pin (5) External interrupt input pin (6) External interrupt input pin (6) External interrupt input pin (6) External interrupt input pin (6) Document Number: 002-10635 Rev. *H Multi-function serial ch.0 chip select 0 I/O pin (0) Multi-function serial ch.1 chip select 0 I/O pin (0) Multi-function serial ch.1 chip select 1 output pin (0) Multi-function serial ch.1 chip select 2 output pin (0) Multi-function serial ch.1 chip select 3 output pin (0) Multi-function serial ch.2 chip select 0 I/O pin (0) Multi-function serial ch.2 chip select 1 output pin (0) Multi-function serial ch.2 chip select 2 output pin (0) Multi-function serial ch.2 chip select 3 output pin (0) Multi-function serial ch.3 chip select 0 I/O pin (0) Multi-function serial ch.3 chip select 1 output pin (0) Multi-function serial ch.3 chip select 2 output pin (0) Multi-function serial ch.3 chip select 3 output pin (0) Multi-function serial ch.4 chip select 0 I/O pin (0) Multi-function serial ch.4 chip select 1 output pin (0) Multi-function serial ch.4 chip select 2 output pin (0) Multi-function serial ch.4 chip select 3 output pin (0) Multi-function serial ch.8 chip select 0 I/O pin (0) Multi-function serial ch.9 chip select 0 I/O pin (0) Multi-function serial ch.9 chip select 1 output pin (0) Multi-function serial ch.10 chip select 0 I/O pin (0) Multi-function serial ch.11 chip select 0 I/O pin (0) Multi-function serial ch.11 chip select 1 output pin (0) Multi-function serial ch.12 chip select 0 I/O pin (0) Multi-function serial ch.16 chip select 0 I/O pin (0) Multi-function serial ch.16 chip select 1 output pin (0) Multi-function serial ch.17 chip select 0 I/O pin (0) Multi-function serial ch.17 chip select 1 output pin (0) Multi-function serial ch.0 chip select 0 I/O pin (1) Multi-function serial ch.1 chip select 0 I/O pin (1) Multi-function serial ch.1 chip select 1 output pin (1) Multi-function serial ch.1 chip select 2 output pin (1) Multi-function serial ch.1 chip select 3 output pin (1) Multi-function serial ch.2 chip select 0 I/O pin (1) Multi-function serial ch.2 chip select 1 output pin (1) Multi-function serial ch.2 chip select 2 output pin (1) Multi-function serial ch.2 chip select 3 output pin (1) Multi-function serial ch.3 chip select 0 I/O pin (1) Multi-function serial ch.3 chip select 1 output pin (1) Multi-function serial ch.3 chip select 2 output pin (1) Multi-function serial ch.3 chip select 3 output pin (1) Multi-function serial ch.4 chip select 0 I/O pin (1) Multi-function serial ch.4 chip select 1 output pin (1) Multi-function serial ch.4 chip select 2 output pin (1) Package Pin Number TEQFP TEQFP TEQFP 144 176 208 139 171 203 140 172 204 141 173 205 142 174 206 143 175 207 64 78 90 6 6 9 7 7 10 8 8 11 9 9 12 41 49 57 42 50 58 44 52 60 47 55 63 51 59 67 54 62 70 55 63 71 56 64 72 140 172 204 141 173 205 142 174 206 143 175 207 105 129 153 111 135 160 112 136 161 116 140 166 122 146 174 123 147 175 127 151 181 70 86 102 71 87 103 100 124 148 101 125 149 9 9 12 22 28 23 29 24 32 25 33 155 187 156 188 157 189 130 158 190 165 197 134 166 198 135 167 199 136 168 200 20 27 35 21 28 36 29 37 Remark Page 44 of 322 S6J3310/20/30/40 Series Port Name Description SCS43_1 SCS80_1 SCS90_1 SCS91_1 SCS100_1 SCS120_1 SCS160_1 SCS161_1 SCS170_1 SCS171_1 SCS80_2 SCS90_2 SCS91_2 SCK0_0 SCK1_0 SCK2_0 SCK3_0 SCK4_0 SCK8_0 SCK9_0 SCK10_0 SCK11_0 SCK12_0 SCK16_0 SCK17_0 SCK0_1 SCK1_1 SCK2_1 SCK3_1 SCK4_1 SCK8_1 SCK9_1 SCK10_1 SCK12_1 SCK16_1 SCK17_1 SCK8_2 SCK9_2 SIN0_0 SIN1_0 SIN2_0 SIN3_0 SIN4_0 SIN8_0 SIN9_0 SIN10_0 SIN11_0 SIN12_0 SIN16_0 Multi-function serial ch.4 chip select 3 output pin (1) Document Number: 002-10635 Rev. *H Multi-function serial ch.8 chip select 0 I/O pin (1) Multi-function serial ch.9 chip select 0 I/O pin (1) Multi-function serial ch.9 chip select 1 output pin (1) Multi-function serial ch.10 chip select 0 I/O pin (1) Multi-function serial ch.12 chip select 0 I/O pin (1) Multi-function serial ch.16 chip select 0 I/O pin (1) Multi-function serial ch.16 chip select 1 output pin (1) Multi-function serial ch.17 chip select 0 I/O pin (1) Multi-function serial ch.17 chip select 1 output pin (1) Multi-function serial ch.8 chip select 0 I/O pin (2) Multi-function serial ch.9 chip select 0 I/O pin (2) Multi-function serial ch.9 chip select 1 output pin (2) Multi-function serial ch.0 clock I/O pin (0) Multi-function serial ch.1 clock I/O pin (0) Multi-function serial ch.2 clock I/O pin (0) Multi-function serial ch.3 clock I/O pin (0) Multi-function serial ch.4 clock I/O pin (0) Multi-function serial ch.8 clock I/O pin (0) Multi-function serial ch.9 clock I/O pin (0) Multi-function serial ch.10 clock I/O pin (0) Multi-function serial ch.11 clock I/O pin (0) Multi-function serial ch.12 clock I/O pin (0) Multi-function serial ch.16 clock I/O pin (0) Multi-function serial ch.17 clock I/O pin (0) Multi-function serial ch.0 clock I/O pin (1) Multi-function serial ch.1 clock I/O pin (1) Multi-function serial ch.2 clock I/O pin (1) Multi-function serial ch.3 clock I/O pin (1) Multi-function serial ch.4 clock I/O pin (1) Multi-function serial ch.8 clock I/O pin (1) Multi-function serial ch.9 clock I/O pin (1) Multi-function serial ch.10 clock I/O pin (1) Multi-function serial ch.12 clock I/O pin (1) Multi-function serial ch.16 clock I/O pin (1) Multi-function serial ch.17 clock I/O pin (1) Multi-function serial ch.8 clock I/O pin (2) Multi-function serial ch.9 clock I/O pin (2) Multi-function serial ch.0 serial data input pin (0) Multi-function serial ch.1 serial data input pin (0) Multi-function serial ch.2 serial data input pin (0) Multi-function serial ch.3 serial data input pin (0) Multi-function serial ch.4 serial data input pin (0) Multi-function serial ch.8 serial data input pin (0) Multi-function serial ch.9 serial data input pin (0) Multi-function serial ch.10 serial data input pin (0) Multi-function serial ch.11 serial data input pin (0) Multi-function serial ch.12 serial data input pin (0) Multi-function serial ch.16 serial data input pin (0) Package Pin Number TEQFP TEQFP TEQFP 144 176 208 22 30 38 72 84 108 125 109 126 80 92 110 127 141 140 15 12 12 18 50 58 66 41 49 57 42 50 58 62 74 86 4 4 4 39 47 55 49 57 65 138 170 202 103 127 151 107 131 155 114 138 164 120 144 171 125 149 178 67 83 95 88 112 129 8 8 11 20 26 185 163 195 19 26 34 70 82 106 123 76 88 88 112 129 138 16 48 56 64 40 48 56 61 73 85 3 3 3 38 46 54 48 56 64 137 169 201 102 126 150 106 130 154 113 137 162 117 141 168 124 148 177 66 82 94 Remark Page 45 of 322 S6J3310/20/30/40 Series Port Name Description SIN17_0 SIN0_1 SIN1_1 SIN2_1 SIN3_1 SIN4_1 SIN8_1 SIN9_1 SIN10_1 SIN12_1 SIN16_1 SIN17_1 SIN8_2 SIN9_2 SOT0_0 SOT1_0 SOT2_0 SOT3_0 SOT4_0 SOT8_0 SOT9_0 SOT10_0 SOT11_0 SOT12_0 SOT16_0 SOT17_0 SOT0_1 SOT1_1 SOT2_1 SOT3_1 SOT4_1 SOT8_1 SOT9_1 SOT10_1 SOT12_1 SOT16_1 SOT17_1 SOT8_2 SOT9_2 SCL0 SCL1 SCL4 SCL8 SCL9 SCL10 SCL11 SCL12 SCL16 SCL17 Multi-function serial ch.17 serial data input pin (0) Multi-function serial ch.0 serial data input pin (1) Multi-function serial ch.1 serial data input pin (1) Multi-function serial ch.2 serial data input pin (1) Multi-function serial ch.3 serial data input pin (1) Multi-function serial ch.4 serial data input pin (1) Multi-function serial ch.8 serial data input pin (1) Multi-function serial ch.9 serial data input pin (1) Multi-function serial ch.10 serial data input pin (1) Multi-function serial ch.12 serial data input pin (1) Multi-function serial ch.16 serial data input pin (1) Multi-function serial ch.17 serial data input pin (1) Multi-function serial ch.8 serial data input pin (2) Multi-function serial ch.9 serial data input pin (2) Multi-function serial ch.0 serial data output pin (0) Multi-function serial ch.1 serial data output pin (0) Multi-function serial ch.2 serial data output pin (0) Multi-function serial ch.3 serial data output pin (0) Multi-function serial ch.4 serial data output pin (0) Multi-function serial ch.8 serial data output pin (0) Multi-function serial ch.9 serial data output pin (0) Multi-function serial ch.10 serial data output pin (0) Multi-function serial ch.11 serial data output pin (0) Multi-function serial ch.12 serial data output pin (0) Multi-function serial ch.16 serial data output pin (0) Multi-function serial ch.17 serial data output pin (0) Multi-function serial ch.0 serial data output pin (1) Multi-function serial ch.1 serial data output pin (1) Multi-function serial ch.2 serial data output pin (1) Multi-function serial ch.3 serial data output pin (1) Multi-function serial ch.4 serial data output pin (1) Multi-function serial ch.8 serial data output pin (1) Multi-function serial ch.9 serial data output pin (1) Multi-function serial ch.10 serial data output pin (1) Multi-function serial ch.12 serial data output pin (1) Multi-function serial ch.16 serial data output pin (1) Multi-function serial ch.17 serial data output pin (1) Multi-function serial ch.8 serial data output pin (2) Multi-function serial ch.9 serial data output pin (2) I2C ch.0 clock I/O pin I2C ch.1 clock I/O pin I2C ch.4 clock I/O pin I2C ch.8 clock I/O pin I2C ch.9 clock I/O pin I2C ch.10 clock I/O pin I2C ch.11 clock I/O pin I2C ch.12 clock I/O pin I2C ch.16 clock I/O pin I2C ch.17 clock I/O pin Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 87 111 128 6 6 9 19 25 184 162 194 24 32 69 81 105 122 75 87 131 136 11 11 14 47 55 63 38 46 54 63 77 89 5 5 5 40 48 56 50 58 66 139 171 203 104 128 152 110 134 158 115 139 165 121 145 173 126 150 179 68 84 98 93 117 139 7 7 10 21 27 154 186 164 196 25 33 71 83 107 124 79 91 130 137 17 49 57 65 39 47 55 62 74 86 4 4 4 138 170 202 103 127 151 107 131 155 114 138 164 120 144 171 125 149 178 67 83 95 88 112 129 Remark Page 46 of 322 S6J3310/20/30/40 Series Port Name Description SDA0 SDA1 SDA4 SDA8 SDA9 SDA10 SDA11 SDA12 SDA16 SDA17 PPG0_TOUT0_0 PPG0_TOUT2_0 PPG1_TOUT0_0 PPG1_TOUT2_0 PPG2_TOUT0_0 PPG2_TOUT2_0 PPG3_TOUT0_0 PPG3_TOUT2_0 PPG4_TOUT0_0 PPG4_TOUT2_0 PPG5_TOUT0_0 PPG5_TOUT2_0 PPG6_TOUT0_0 PPG6_TOUT2_0 PPG7_TOUT0_0 PPG7_TOUT2_0 PPG8_TOUT0_0 PPG8_TOUT2_0 PPG9_TOUT0_0 PPG9_TOUT2_0 PPG10_TOUT0_0 PPG10_TOUT2_0 PPG11_TOUT0_0 PPG11_TOUT2_0 PPG12_TOUT0_0 PPG12_TOUT2_0 PPG13_TOUT0_0 PPG13_TOUT2_0 PPG14_TOUT0_0 PPG14_TOUT2_0 PPG15_TOUT0_0 PPG15_TOUT2_0 PPG0_TOUT0_1 PPG0_TOUT2_1 PPG1_TOUT0_1 PPG1_TOUT2_1 PPG2_TOUT0_1 PPG2_TOUT2_1 PPG3_TOUT0_1 I2C ch.0 serial data I/O pin I2C ch.1 serial data I/O pin I2C ch.4 serial data I/O pin I2C ch.8 serial data I/O pin I2C ch.9 serial data I/O pin I2C ch.10 serial data I/O pin I2C ch.11 serial data I/O pin I2C ch.12 serial data I/O pin I2C ch.16 serial data I/O pin I2C ch.17 serial data I/O pin Base timer 0 output pin (0) Base timer 1 output pin (0) Base timer 2 output pin (0) Base timer 3 output pin (0) Base timer 4 output pin (0) Base timer 5 output pin (0) Base timer 6 output pin (0) Base timer 7 output pin (0) Base timer 8 output pin (0) Base timer 9 output pin (0) Base timer 10 output pin (0) Base timer 11 output pin (0) Base timer 12 output pin (0) Base timer 13 output pin (0) Base timer 14 output pin (0) Base timer 15 output pin (0) Base timer 16 output pin (0) Base timer 17 output pin (0) Base timer 18 output pin (0) Base timer 19 output pin (0) Base timer 20 output pin (0) Base timer 21 output pin (0) Base timer 22 output pin (0) Base timer 23 output pin (0) Base timer 24 output pin (0) Base timer 25 output pin (0) Base timer 26 output pin (0) Base timer 27 output pin (0) Base timer 28 output pin (0) Base timer 29 output pin (0) Base timer 30 output pin (0) Base timer 31 output pin (0) Base timer 1 output pin (1) Base timer 1 output pin (1) Base timer 2 output pin (1) Base timer 3 output pin (1) Base timer 4 output pin (1) Base timer 5 output pin (1) Base timer 6 output pin (1) Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 63 77 89 5 5 5 139 171 203 104 128 152 110 134 158 115 139 165 121 145 173 126 150 179 68 84 98 93 117 139 61 73 85 62 74 86 63 77 89 64 78 90 65 81 93 66 82 94 67 83 95 68 84 98 70 86 102 71 87 103 87 111 128 88 112 129 100 124 148 101 125 149 102 126 150 103 127 151 104 128 152 105 129 153 106 130 154 107 131 155 110 134 158 111 135 160 112 136 161 113 137 162 115 139 165 116 140 166 117 141 168 120 144 171 121 145 173 122 146 174 123 147 175 124 148 177 8 8 11 9 9 12 10 10 13 11 11 14 12 12 18 13 13 19 14 14 20 Remark Page 47 of 322 S6J3310/20/30/40 Series Port Name Description PPG3_TOUT2_1 PPG4_TOUT0_1 PPG4_TOUT2_1 PPG5_TOUT0_1 PPG5_TOUT2_1 PPG6_TOUT0_1 PPG6_TOUT2_1 PPG7_TOUT0_1 PPG7_TOUT2_1 PPG8_TOUT0_1 PPG8_TOUT2_1 PPG9_TOUT0_1 PPG9_TOUT2_1 PPG10_TOUT0_1 PPG10_TOUT2_1 PPG11_TOUT0_1 PPG11_TOUT2_1 PPG12_TOUT0_1 PPG12_TOUT2_1 PPG13_TOUT0_1 PPG13_TOUT2_1 PPG14_TOUT0_1 PPG14_TOUT2_1 PPG15_TOUT0_1 PPG15_TOUT2_1 PPG0/1/2/3/4/5_TIN1_0 PPG6/7/8/9/10/11_TIN1_0 PPG12/13/14/15_TIN1_0 PPG0/1/2/3/4/5_TIN1_1 PPG6/7/8/9/10/11_TIN1_1 PPG12/13/14/15_TIN1_1 WOT PWM1M0 PWM1M1 PWM1M2 PWM1M3 PWM1M4 PWM1M5 PWM1P0 PWM1P1 PWM1P2 PWM1P3 PWM1P4 PWM1P5 PWM2M0 PWM2M1 PWM2M2 PWM2M3 PWM2M4 Base timer 7 output pin (1) Base timer 8 output pin (1) Base timer 9 output pin (1) Base timer 11 output pin (1) Base timer 11 output pin (1) Base timer 12 output pin (1) Base timer 13 output pin (1) Base timer 14 output pin (1) Base timer 15 output pin (1) Base timer 16 output pin (1) Base timer 17 output pin (1) Base timer 18 output pin (1) Base timer 19 output pin (1) Base timer 21 output pin (1) Base timer 21 output pin (1) Base timer 22 output pin (1) Base timer 23 output pin (1) Base timer 24 output pin (1) Base timer 25 output pin (1) Base timer 26 output pin (1) Base timer 27 output pin (1) Base timer 28 output pin (1) Base timer 29 output pin (1) Base timer 31 output pin (1) Base timer 31 output pin (1) Base timer 0/2/4/6/8/10 input pin (0) Base timer 12/14/16/18/20/22 input pin (0) Base timer 24/26/28/30 input pin (0) Base timer 0/2/4/6/8/10 input pin (1) Base timer 12/14/16/18/20/22 input pin (1) Base timer 24/26/28/30 input pin (1) RTC overflow output pin SMC ch.0 output pin SMC ch.1 output pin SMC ch.2 output pin SMC ch.3 output pin SMC ch.4 output pin SMC ch.5 output pin SMC ch.0 output pin SMC ch.1 output pin SMC ch.2 output pin SMC ch.3 output pin SMC ch.4 output pin SMC ch.5 output pin SMC ch.0 output pin SMC ch.1 output pin SMC ch.2 output pin SMC ch.3 output pin SMC ch.4 output pin Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 15 15 21 19 25 20 26 21 27 22 28 69 81 70 82 71 83 72 84 75 87 76 88 79 91 80 92 98 114 99 115 105 122 106 123 154 186 155 187 156 188 157 189 130 158 190 162 194 163 195 164 196 93 117 139 114 138 164 125 149 178 23 29 107 124 165 197 93 117 139 101 125 149 105 129 153 111 135 160 115 139 165 121 145 173 125 149 178 100 124 148 104 128 152 110 134 158 114 138 164 120 144 171 124 148 177 103 127 151 107 131 155 113 137 162 117 141 168 123 147 175 Remark Page 48 of 322 S6J3310/20/30/40 Series Port Name Description PWM2M5 PWM2P0 PWM2P1 PWM2P2 PWM2P3 PWM2P4 PWM2P5 OCU0_OTD0_0 OCU0_OTD1_0 OCU1_OTD0_0 OCU1_OTD1_0 OCU2_OTD0_0 OCU2_OTD1_0 OCU8_OTD0_0 OCU8_OTD1_0 OCU9_OTD0_0 OCU9_OTD1_0 OCU10_OTD0_0 OCU10_OTD1_0 OCU0_OTD0_1 OCU0_OTD1_1 OCU1_OTD0_1 OCU1_OTD1_1 OCU2_OTD0_1 OCU2_OTD1_1 OCU8_OTD0_1 OCU8_OTD1_1 OCU9_OTD0_1 OCU9_OTD1_1 OCU10_OTD0_1 OCU10_OTD1_1 ICU0_IN0_0 ICU0_IN1_0 ICU1_IN0_0 ICU1_IN1_0 ICU2_IN0_0 ICU2_IN1_0 ICU8_IN0_0 ICU8_IN1_0 ICU9_IN0_0 ICU9_IN1_0 ICU10_IN0_0 ICU10_IN1_0 ICU0_IN0_1 ICU0_IN1_1 ICU1_IN0_1 ICU1_IN1_1 ICU2_IN0_1 ICU2_IN1_1 SMC ch.5 output pin SMC ch.0 output pin SMC ch.1 output pin SMC ch.2 output pin SMC ch.3 output pin SMC ch.4 output pin SMC ch.5 output pin Output compare 0 ch.0 output pin (0) Output compare 0 ch.1 output pin (0) Output compare 1 ch.0 output pin (0) Output compare 1 ch.1 output pin (0) Output compare 2 ch.0 output pin (0) Output compare 2 ch.1 output pin (0) Output compare 8 ch.0 output pin (0) Output compare 8 ch.1 output pin (0) Output compare 9 ch.0 output pin (0) Output compare 9 ch.1 output pin (0) Output compare 10 ch.0 output pin (0) Output compare 10 ch.1 output pin (0) Output compare 0 ch.0 output pin (1) Output compare 0 ch.1 output pin (1) Output compare 1 ch.0 output pin (1) Output compare 1 ch.1 output pin (1) Output compare 2 ch.0 output pin (1) Output compare 2 ch.1 output pin (1) Output compare 8 ch.0 output pin (1) Output compare 8 ch.1 output pin (1) Output compare 9 ch.0 output pin (1) Output compare 9 ch.1 output pin (1) Output compare 10 ch.0 output pin (1) Output compare 10 ch.1 output pin (1) Input Capture 0 ch.0 input pin (0) Input Capture 0 ch.1 input pin (0) Input Capture 1 ch.0 input pin (0) Input Capture 1 ch.1 input pin (0) Input Capture 2 ch.0 input pin (0) Input Capture 2 ch.1 input pin (0) Input Capture 8 ch.0 input pin (0) Input Capture 8 ch.1 input pin (0) Input Capture 9 ch.0 input pin (0) Input Capture 9 ch.1 input pin (0) Input Capture 10 ch.0 input pin (0) Input Capture 10 ch.1 input pin (0) Input Capture 0 ch.0 input pin (1) Input Capture 0 ch.1 input pin (1) Input Capture 1 ch.0 input pin (1) Input Capture 1 ch.1 input pin (1) Input Capture 2 ch.0 input pin (1) Input Capture 2 ch.1 input pin (1) Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 127 151 181 102 126 150 106 130 154 112 136 161 116 140 166 122 146 174 126 150 179 61 73 85 62 74 86 65 81 93 66 82 94 67 83 95 68 84 98 70 86 102 71 87 103 81 97 113 87 111 128 88 112 129 93 117 139 69 81 70 82 71 83 72 84 75 87 76 88 79 91 80 92 98 114 99 115 105 122 106 123 61 73 85 62 74 86 63 77 89 64 78 90 65 81 93 66 82 94 67 83 95 68 84 98 70 86 102 71 87 103 87 111 128 88 112 129 69 81 70 82 71 83 72 84 75 87 76 88 Remark Page 49 of 322 S6J3310/20/30/40 Series Port Name Description ICU8_IN0_1 ICU8_IN1_1 ICU9_IN0_1 ICU9_IN1_1 ICU10_IN0_1 ICU10_IN1_1 SGA0_0 SGA1_0 SGA2_0 SGA3_0 SGA4_0 SGA0_1 SGA1_1 SGA2_1 SGA3_1 SGA4_1 SGO0_0 SGO1_0 SGO2_0 SGO3_0 SGO4_0 SGO0_1 SGO1_1 SGO2_1 SGO3_1 SGO4_1 AN0 (AL0) AN1 (AL1) AP0 (AH0) AP1 (AH1) BN0 (BL0) BN1 (BL1) BP0 (BH0) BP1 (BH1) I2S0_ECLK_0 I2S0_ECLK_1 I2S1_ECLK_0 I2S0_SCK_0 I2S0_SCK_1 I2S1_SCK_0 I2S0_SD_0 I2S0_SD_1 I2S1_SD_0 I2S0_WS_0 I2S0_WS_1 I2S1_WS_0 Input Capture 8 ch.0 input pin (1) Input Capture 8 ch.1 input pin (1) Input Capture 9 ch.0 input pin (1) Input Capture 9 ch.1 input pin (1) Input Capture 10 ch.0 input pin (1) Input Capture 10 ch.1 input pin (1) Sound generator ch.0 SGA output pin (0) Sound generator ch.1 SGA output pin (0) Sound generator ch.2 SGA output pin (0) Sound generator ch.3 SGA output pin (0) Sound generator ch.4 SGA output pin (0) Sound generator ch.0 SGA output pin (1) Sound generator ch.1 SGA output pin (1) Sound generator ch.2 SGA output pin (1) Sound generator ch.3 SGA output pin (1) Sound generator ch.4 SGA output pin (1) Sound generator ch.0 SGO output pin (0) Sound generator ch.1 SGO output pin (0) Sound generator ch.2 SGO output pin (0) Sound generator ch.3 SGO output pin (0) Sound generator ch.4 SGO output pin (0) Sound generator ch.0 SGO output pin (1) Sound generator ch.1 SGO output pin (1) Sound generator ch.2 SGO output pin (1) Sound generator ch.3 SGO output pin (1) Sound generator ch.4 SGO output pin (1) PCM PWM ch.0 output pin PCM PWM ch.1 output pin PCM PWM ch.0 output pin PCM PWM ch.1 output pin PCM PWM ch.0 output pin PCM PWM ch.1 output pin PCM PWM ch.0 output pin PCM PWM ch.1 output pin I2S external clock ch.0 input pin (0) I2S external clock ch.0 input pin (1) I2S external clock ch.1 input pin (0) I2S continuous serial clock ch.0 I/O pin (0) I2S continuous serial clock ch.0 I/O pin (1) I2S continuous serial clock ch.1 I/O pin (0) I2S serial data ch.0 I/O pin (0) I2S serial data ch.0 I/O pin (1) I2S serial data ch.1 I/O pin (0) I2S word select ch.0 I/O pin (0) I2S word select ch.0 I/O pin (1) I2S word select ch.1 I/O pin (0) Audio DAC external capacity connection output pin (L) Audio DAC external capacity connection output pin (R) C_L C_R Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 79 91 80 92 98 114 99 115 105 122 106 123 63 77 89 65 81 93 67 83 95 81 97 113 88 112 129 69 81 71 83 75 87 79 91 98 114 64 78 90 66 82 94 68 84 98 87 111 128 93 117 139 70 82 72 84 76 88 80 92 99 115 63 77 89 67 83 95 64 78 90 68 84 98 61 73 85 65 81 93 62 74 86 66 82 94 12 12 18 154 186 8 8 11 15 15 21 157 189 11 11 14 13 13 19 155 187 9 9 12 14 14 20 156 188 10 10 13 34 42 50 30 38 46 Remark Page 50 of 322 S6J3310/20/30/40 Series Port Name Description DAC_L DAC_R FRT0/1/2/3_TEXT FRT4/8/9/10_TEXT TIN0_0 TIN1_0 TIN16_0 TIN17_0 TIN48_0 TIN49_0 TIN0_1 TIN1_1 TIN16_1 TIN17_1 TIN48_1 TIN49_1 TOT0_0 TOT1_0 TOT16_0 TOT17_0 TOT48_0 TOT49_0 TOT0_1 TOT1_1 TOT16_1 TOT17_1 TOT48_1 TOT49_1 AIN8 AIN9 BIN8 BIN9 ZIN8 ZIN9 RXD0_0 RXD1_0 RXD2_0 RXD3_0 TXD0_0 TXD1_0 TXD2_0 TXD3_0 COL_0 CRS_0 RXER_0 RXDV_0 RXCLK_0 TXER_0 TXEN_0 Audio DAC output pin (L) Audio DAC output pin (R) Free-run timer ch.0/1/2/3 clock input pin Free-run timer ch.4/8/9/10 clock input pin Reload timer ch.0 event input pin (0) Reload timer ch.1 event input pin (0) Reload timer ch.16 event input pin (0) Reload timer ch.17 event input pin (0) Reload timer ch.48 event input pin (0) Reload timer ch.49 event input pin (0) Reload timer ch.0 event input pin (0) Reload timer ch.1 event input pin (1) Reload timer ch.16 event input pin (1) Reload timer ch.17 event input pin (1) Reload timer ch.48 event input pin (1) Reload timer ch.49 event input pin (1) Reload timer ch.0 output pin (0) Reload timer ch.1 output pin (0) Reload timer ch.16 output pin (0) Reload timer ch.17 output pin (0) Reload timer ch.48 output pin (0) Reload timer ch.49 output pin (0) Reload timer ch.0 output pin (1) Reload timer ch.1 output pin (1) Reload timer ch.16 output pin (1) Reload timer ch.17 output pin (1) Reload timer ch.48 output pin (1) Reload timer ch.49 output pin (1) Up/Down counter AIN input pin ch.8 Up/Down counter AIN input pin ch.9 Up/Down counter BIN input pin ch.8 Up/Down counter BIN input pin ch.9 Up/Down counter ZIN input pin ch.8 Up/Down counter ZIN input pin ch.9 Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 33 41 49 29 37 45 61 73 85 62 74 86 61 73 85 63 77 89 65 81 93 70 86 102 81 97 113 88 112 129 81 69 83 71 87 75 91 79 114 98 124 107 62 74 86 64 78 90 66 82 94 71 87 103 87 111 128 93 117 139 70 82 72 84 76 88 80 92 99 115 108 125 61 73 85 64 78 90 62 74 86 65 81 93 63 77 89 66 82 94 47 55 63 48 56 64 49 57 65 50 58 66 39 47 55 40 48 56 41 49 57 42 50 58 55 63 71 56 64 72 23 31 39 24 32 40 22 30 38 44 52 60 38 46 54 Remark Page 51 of 322 S6J3310/20/30/40 Series Port Name Description TXCLK_0 MDC_0 MDIO_0 RXD0_1 RXD1_1 RXD2_1 RXD3_1 TXD0_1 TXD1_1 TXD2_1 TXD3_1 COL_1 CRS_1 RXER_1 RXDV_1 RXCLK_1 TXER_1 TXEN_1 TXCLK_1 MDC_1 MDIO_1 MLBCLK MLBDAT MLBSIG M_SCLK0 M_SDATA0_0 M_SDATA0_1 M_SDATA0_2 M_SDATA0_3 M_SDATA1_0 M_SDATA1_1 M_SDATA1_2 M_SDATA1_3 M_SSEL0 M_SSEL1 M_CK M_CS#_1 M_CS#_2 M_DQ0 M_DQ1 M_DQ2 M_DQ3 M_DQ4 M_DQ5 M_DQ6 M_DQ7 M_RWDS COM0 COM1 Ethernet pin (0) Ethernet pin (0) Ethernet pin (0) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) Ethernet pin (1) MediaLB pin MediaLB pin MediaLB pin MCU HS-SPI clock output pin MCU HS-SPI0 data 0 I/O pin MCU HS-SPI0 data 1 I/O pin MCU HS-SPI0 data 2 I/O pin MCU HS-SPI0 data 3 I/O pin MCU HS-SPI1 data 0 I/O pin MCU HS-SPI1 data 1 I/O pin MCU HS-SPI1 data 2 I/O pin MCU HS-SPI1 data 3 I/O pin MCU HS-SPI0 select output pin MCU HS-SPI1 select output pin MCU Hyper Bus clock output pin MCU Hyper Bus select 1 output pin MCU Hyper Bus select 2 output pin MCU Hyper Bus Data 0 pin MCU Hyper Bus Data 1 pin MCU Hyper Bus Data 2 pin MCU Hyper Bus Data 3 pin MCU Hyper Bus Data 4 pin MCU Hyper Bus Data 5 pin MCU Hyper Bus Data 6 pin MCU Hyper Bus Data 7 pin MCU Hyper Bus RWDS LCDC Segment (Duty) Common Output Pin LCDC Segment (Duty) Common Output Pin Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 25 33 41 54 62 70 51 59 67 23 29 30 31 24 32 17 19 25 20 26 21 27 24 32 40 25 33 41 7 8 6 22 28 16 15 23 31 39 25 33 54 62 70 56 64 72 55 63 71 44 52 60 38 46 54 40 48 56 39 47 55 42 50 58 47 55 63 49 57 65 48 56 64 51 59 67 41 49 57 50 58 66 44 52 60 42 50 58 54 62 70 41 49 57 40 48 56 39 47 55 38 46 54 48 56 64 49 57 65 50 58 66 51 59 67 47 55 63 15 15 21 19 26 34 Remark Page 52 of 322 S6J3310/20/30/40 Series Port Name Description COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 V0 V1 V2 V3 DSP0_CLK_0 DSP0_EN_0 DSP0_VSYNC_0 DSP0_HSYNC_0 DSP0_R0_0 DSP0_R1_0 DSP0_R2_0 DSP0_R3_0 DSP0_R4_0 DSP0_R5_0 DSP0_R6_0 LCDC Segment (Duty) Common Output Pin LCDC Segment (Duty) Common Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty) Output Pin LCDC Segment (Duty/Static) Output Pin LCDC Segment (Duty/Static) Output Pin LCDC Segment (Duty/Static) Output Pin LCDC Segment (Duty/Static) Output Pin LCDC Segment (Duty/Static) Output Pin LCDC Segment (Duty/Static) Output Pin LCDC Segment (Duty/Static) Output Pin LCDC Segment (Duty/Static) Output Pin LCDC Segment (Duty/Static) Output Pin LCDC Reference Voltage V0 Input Pin LCDC Reference Voltage V1 Input Pin LCDC Reference Voltage V2 Input Pin LCDC Reference Voltage V3 Input Pin Display 0 Clock output pin Display 0 Data Enable output pin Display 0 Vertical Synchronization output pin Display 0 Horizontal Synchronization output pin Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 20 27 35 21 28 36 154 186 155 187 156 188 157 189 130 158 190 162 194 163 195 164 196 165 197 134 166 198 135 167 199 136 168 200 137 169 201 138 170 202 139 171 203 140 172 204 141 173 205 142 174 206 143 175 207 2 2 2 3 3 3 4 4 4 5 5 5 6 6 9 7 7 10 8 8 11 9 9 12 10 10 13 11 11 14 12 12 18 13 13 19 14 14 20 22 30 38 23 31 39 24 32 40 25 33 41 136 168 200 130 158 190 135 167 199 134 166 198 137 169 201 138 170 202 139 171 203 140 172 204 141 173 205 142 174 206 143 175 207 Remark Page 53 of 322 S6J3310/20/30/40 Series Port Name Description DSP0_R7_0 DSP0_G0_0 DSP0_G1_0 DSP0_G2_0 DSP0_G3_0 DSP0_G4_0 DSP0_G5_0 DSP0_G6_0 DSP0_G7_0 DSP0_B0_0 DSP0_B1_0 DSP0_B2_0 DSP0_B3_0 DSP0_B4_0 DSP0_B5_0 DSP0_B6_0 DSP0_B7_0 DSP0_B7_1 LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD16 LCDD17 CS# WR# RD# RS TE RES# ARH0_AIC0_DNCLK ARH0_AIC0_DNDATA0 ARH0_AIC0_DNDATA1 ARH0_AIC0_RCK ARH0_AIC0_RDA0 ARH0_AIC0_RDA1 ARH0_AIC0_TCKI Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (0) Display 0 RGB color output pin (1) LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Data I/O pin LCD Bus IF Chip Select output pin LCD Bus IF Write enable output pin LCD Bus IF Read enable output pin LCD Bus IF Register Select output pin LCD Bus IF Tearing Effect input pin LCD Bus IF Reset Control output pin APIX output pin APIX output pin APIX output pin APIX input pin APIX input pin APIX input pin APIX input pin Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 2 2 2 3 3 3 4 4 4 5 5 5 6 6 9 7 7 10 8 8 11 9 9 12 10 10 13 11 11 14 12 12 18 13 13 19 14 14 20 15 15 21 19 26 34 20 27 35 22 30 38 21 28 36 139 171 203 140 172 204 141 173 205 142 174 206 143 175 207 2 2 2 3 3 3 4 4 4 5 5 5 6 6 9 7 7 10 8 8 11 9 9 12 10 10 13 11 11 14 12 12 18 13 13 19 14 14 20 15 15 21 19 26 34 20 27 35 23 31 39 25 33 41 24 32 40 11 11 14 21 28 36 12 12 18 23 31 39 25 33 41 24 32 40 11 11 14 Remark Page 54 of 322 S6J3310/20/30/40 Series Port Name Description ARH0_AIC0_TDA0 ARH0_AIC0_TDA1 ARH0_AIC0_UPCLK ARH0_AIC0_UPDATA0 ARH0_AIC0_UPDATA1 ARH0_AIC0_dbg_out_0 ARH0_AIC0_dbg_out_1 ARH0_AIC0_dbg_select ARH0_AIC1_DNCLK ARH0_AIC1_DNDATA0 ARH0_AIC1_DNDATA1 ARH0_AIC1_RCK ARH0_AIC1_RDA0 ARH0_AIC1_RDA1 ARH0_AIC1_TCKI ARH0_AIC1_TDA0 ARH0_AIC1_TDA1 ARH0_AIC1_UPCLK ARH0_AIC1_UPDATA0 ARH0_AIC1_UPDATA1 ARH0_AIC1_dbg_out_0 ARH0_AIC1_dbg_out_1 ARH0_AIC1_dbg_select APIX output pin APIX output pin APIX input pin APIX input pin APIX input pin APIX output pin APIX output pin APIX input pin APIX output pin APIX output pin APIX output pin APIX input pin APIX input pin APIX input pin APIX input pin APIX output pin APIX output pin APIX input pin APIX input pin APIX input pin APIX output pin APIX output pin APIX input pin Indicator PWM output pin 0 (It can also obtained from INDICATOR0_1) Indicator PWM output pin 1 (It can also obtained from INDICATOR0_0) System clock output pin (0) System clock output pin (1) External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin INDICATOR0_0 INDICATOR0_1 SYSC0_CLK_0 SYSC0_CLK_1 MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 MAD15 MAD16 MAD17 MAD18 MAD19 MAD20 Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 21 28 36 12 12 18 23 31 39 25 33 41 24 32 40 14 14 20 13 13 19 15 15 21 3 3 3 7 7 10 4 4 4 8 8 11 10 10 13 9 9 12 3 3 3 7 7 10 4 4 4 8 8 11 10 10 13 9 9 12 6 6 9 5 5 5 19 26 34 70 86 102 88 112 129 93 87 143 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 117 111 175 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19 20 21 22 23 24 139 128 207 2 3 4 5 9 10 11 12 13 14 18 19 20 21 25 26 27 28 29 32 Remark Page 55 of 322 S6J3310/20/30/40 Series Port Name Description MAD21 MDATA0 MDATA1 MDATA2 MDATA3 MDATA4 MDATA5 MDATA6 MDATA7 MDATA8 MDATA9 MDATA10 MDATA11 MDATA12 MDATA13 MDATA14 MDATA15 MCLK MOEX MWEX MDQM0 MDQM1 MCSX0 MCSX1 MCSX2 MCSX3 MRDY P0_00 P0_01 P0_02 P0_03 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 P0_14 P0_15 P0_16 P0_17 P0_18 P0_19 P0_20 P0_21 External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin External Bus pin General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose input port General-Purpose I/O port Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 25 33 135 167 199 136 168 200 137 169 201 138 170 202 139 171 203 140 172 204 141 173 205 142 174 206 154 186 155 187 156 188 157 189 162 194 163 195 164 196 165 197 21 28 36 19 26 34 20 27 35 22 30 38 29 37 130 158 190 134 166 198 23 31 39 24 32 40 25 33 41 2 2 2 3 3 3 4 4 4 5 5 5 6 6 9 7 7 10 8 8 11 9 9 12 10 10 13 11 11 14 12 12 18 13 13 19 14 14 20 15 15 21 19 26 34 20 27 35 21 28 36 22 30 38 23 31 39 24 32 40 25 33 41 38 46 54 Remark Page 56 of 322 S6J3310/20/30/40 Series Port Name Description P0_22 P0_23 P0_24 P0_25 P0_26 P0_27 P0_28 P0_29 P0_30 P0_31 P1_00 P1_01 P1_02 P1_03 P1_04 P1_05 P1_06 P1_07 P1_08 P1_09 P1_10 P1_11 P1_12 P1_13 P1_14 P1_15 P1_16 P1_17 P1_18 P1_19 P1_20 P1_21 P1_22 P1_23 P1_24 P1_25 P1_26 P1_27 P1_28 P1_29 P1_30 P1_31 P2_00 P2_01 P2_02 P2_03 P2_04 P2_05 P2_06 General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 39 47 55 40 48 56 41 49 57 42 50 58 44 52 60 47 55 63 48 56 64 49 57 65 50 58 66 51 59 67 54 62 70 55 63 71 56 64 72 61 73 85 62 74 86 63 77 89 64 78 90 65 81 93 66 82 94 67 83 95 68 84 98 70 86 102 71 87 103 81 97 113 87 111 128 88 112 129 93 117 139 100 124 148 101 125 149 102 126 150 103 127 151 104 128 152 105 129 153 106 130 154 107 131 155 110 134 158 111 135 160 112 136 161 113 137 162 114 138 164 115 139 165 116 140 166 117 141 168 120 144 171 121 145 173 122 146 174 123 147 175 124 148 177 125 149 178 Remark Page 57 of 322 S6J3310/20/30/40 Series Port Name Description P2_07 P2_08 P2_09 P2_10 P2_11 P2_12 P2_13 P2_14 P2_15 P2_16 P2_17 P2_18 P2_19 P3_00 P3_01 P3_02 P3_03 P3_04 P3_05 P3_06 P3_07 P3_08 P3_09 P3_10 P3_11 P3_12 P3_13 P3_14 P3_15 P3_16 P3_17 P3_18 P3_19 P3_20 P3_21 P3_22 P3_23 P3_24 P3_25 P3_26 P3_27 P3_28 P3_29 P3_30 P3_31 P4_00 P4_01 P4_02 P4_03 General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port Document Number: 002-10635 Rev. *H Package Pin Number TEQFP TEQFP TEQFP 144 176 208 126 150 179 127 151 181 130 158 190 134 166 198 135 167 199 136 168 200 137 169 201 138 170 202 139 171 203 140 172 204 141 173 205 142 174 206 143 175 207 19 25 20 26 21 27 22 28 23 29 24 32 25 33 29 37 69 81 70 82 71 83 72 84 75 87 76 88 79 91 80 92 98 114 99 115 105 122 106 123 107 124 108 125 109 126 110 127 154 186 155 187 156 188 157 189 162 194 163 195 164 196 165 197 6 7 8 15 Remark Page 58 of 322 S6J3310/20/30/40 Series 6.2 Port Name Description P4_04 P4_05 P4_06 P4_07 P4_08 P4_09 P4_10 P4_11 P4_12 P4_13 P4_14 P4_15 P4_16 P4_17 P4_18 P4_19 P4_20 P4_21 P4_22 P4_23 P4_24 P4_25 P4_26 P4_27 P4_28 P4_29 P4_30 P4_31 General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port General-Purpose I/O port Package Pin Number TEQFP TEQFP TEQFP 144 176 208 16 17 30 31 77 78 79 80 96 97 99 100 116 130 131 136 137 138 140 141 159 163 167 172 176 180 184 185 Remark Remark Notes: - The port description list shows the port function of description which is mounted and supported on the product. The function which is not described in this table is not supported and assured. - See the function list of the product as well. Document Number: 002-10635 Rev. *H Page 59 of 322 S6J3310/20/30/40 Series 7. Port Configuration 7.1 Resource Input Configuration Module The resource input configuration module (RIC) is a function to select input from an external or output from another internal resource as resource input. A resource which supports either a port input relocation or a resource inputs from the other resource has its RIC_RESIN register to configure resource input configuration. The Resource which are available through only one port does not have the multiplexer implemented i.e. No RIC_RESIN register. 7.1.1 RIC (S6J3310) Register (Offset) RIC_RE SIN000 (0x0000) RIC_RE SIN001 (0x0002) Resource SIN16 SCK16 RESSEL [3:0] /PORT SEL[3:0] RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) - - - - - - - - - - - - - - - - P1_08 P4_19 - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) - - - - - - - - - - - - - - - - P1_09 P4_21 - - - - - - - - - - - - - - 80 ns noise filter disable 80 ns noise filter enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 80 ns noise filter disable 80 ns noise filter enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RIC_RE SIN002 (0x0004) SCL16 RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RIC_RE SIN003 (0x0006) SDA16 RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Page 60 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN004 (0x0008) RIC_RE SIN005 (0x000A) RIC_RE SIN007 (0x000E) RIC_RE SIN008 (0x0010) RIC_RE SIN009 (0x0012) Resource MFS16_T RIGGER SCS16 SIN17 SCK17 SCL17 RESSEL [3:0] /PORT SEL[3:0] Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) TOT48 TOT49 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_11 P4_23 - - - - - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P1_14 P0_09 - - - - - - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P1_15 P4_04 - - - - - - - - - - - - - - RESSEL (0-7) 80 ns noise filter disable 80 ns noise filter enable - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Page 61 of 322 S6J3310/20/30/40 Series Register (Offset) Resource RESSEL [3:0] /PORT SEL[3:0] RIC_RE SIN011 (0x0016) RIC_RE SIN012 (0x0018) RIC_RE SIN021 (0x002A) RIC_RE SIN022 (0x002C) SDA17 MFS17_T RIGGER SCS17 SIN0 SCK0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 80 ns noise filter disable 80 ns noise filter enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) TOT48 TOT49 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_17 P4_03 - - - - - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P1_03 P0_04 - - - - - - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P1_04 P0_06 - - - - - - - - - - - - - - RESSEL (0-7) RIC_RE SIN010 (0x0014) Source for Resource Input RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Page 62 of 322 S6J3310/20/30/40 Series Register (Offset) Resource RESSEL [3:0] /PORT SEL[3:0] SCL0 RIC_RE SIN025 (0x0032) RIC_RE SIN026 (0x0034) RIC_RE SIN028 (0x0038) SDA0 MFS0_TR IGGER SCS0 SIN1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 80 ns noise filter enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 80 ns noise filter disable 80 ns noise filter enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) TOT0 TOT1 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_06 P0_07 - - - - - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P0_01 P3_00 - - - - - - - - - - - - - - RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RIC_RE SIN024 (0x0030) 0 80 ns noise filter disable RESSEL (0-7) RIC_RE SIN023 (0x002E) Source for Resource Input RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Page 63 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN029 (0x003A) RIC_RE SIN030 (0x003C) RIC_RE SIN031 (0x003E) RIC_RE SIN032 (0x0040) RIC_RE SIN033 (0x0042) Resource SCK1 SCL1 RESSEL [3:0] /PORT SEL[3:0] MFS1_TR IGGER SCS1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P0_02 P3_01 - - - - - - - - - - - - - - RESSEL (0-7) 80 ns noise filter disable 80 ns noise filter enable - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) 80 ns noise filter disable 80 ns noise filter enable - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - TOT0 TOT1 - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P0_04 P3_03 - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) SDA1 Source for Resource Input PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Page 64 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN035 (0x0046) RIC_RE SIN036 (0x0048) RIC_RE SIN039 (0x004E) RIC_RE SIN040 (0x0050) Resource SIN2 SCK2 MFS2_TR IGGER SCS2 RESSEL [3:0] /PORT SEL[3:0] Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P0_21 P4_30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P0_22 P4_31 - - - - - - PORTSE L (8-15) - - - - - - - - TOT0 TOT1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P0_24 P3_25 - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Page 65 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN042 (0x0054) RIC_RE SIN043 (0x0056) RIC_RE SIN046 (0x005C) RIC_RE SIN047 (0x005E) RIC_RE SIN049 (0x0062) Resource SIN3 SCK3 MFS3_TR IGGER SCS3 SIN4 RESSEL [3:0] /PORT SEL[3:0] Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P0_28 P3_28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P0_29 P3_29 - - - - - - PORTSE L (8-15) - - - - - - - - TOT0 TOT1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P0_31 P3_31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P2_13 P3_05 - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Page 66 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN050 (0x0064) RIC_RE SIN051 (0x0066) RIC_RE SIN052 (0x0068) RIC_RE SIN053 (0x006A) RIC_RE SIN054 (0x006C) Resource SCK4 SCL4 RESSEL [3:0] /PORT SEL[3:0] MFS4_TR IGGER SCS4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P2_14 P0_14 - - - - - - - - - - - - - - RESSEL (0-7) 80 ns noise filter disable 80 ns noise filter enable - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) 80 ns noise filter disable 80 ns noise filter enable - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - TOT0 TOT1 - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P2_16 P0_15 - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) SDA4 Source for Resource Input PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Page 67 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN077 (0x009A) RIC_RE SIN078 (0x009C) RIC_RE SIN079 (0x009E) RIC_RE SIN080 (0x00A0) RIC_RE SIN081 (0x00A2) Resource SIN8 SCK8 SCL8 SDA8 MFS8_TR IGGER RESSEL [3:0] /PORT SEL[3:0] Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P1_19 P3_08 P0_27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_20 P3_09 P0_28 - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) 80 ns noise filter disable 80 ns noise filter enable - - - - - - RESSEL (8-15) - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) 80 ns noise filter disable 80 ns noise filter enable - - - - - - RESSEL (8-15) - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - TOT16 TOT17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Page 68 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN082 (0x00A4) RIC_RE SIN084 (0x00A8) RIC_RE SIN085 (0x00AA) Resource SCS8 SIN9 SCK9 RESSEL [3:0] /PORT SEL[3:0] SCL9 SDA9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - - - - - - - - RESSEL (8-15) - - - - - - - - P1_22 P3_11 P0_30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_23 P3_18 P0_21 - - - - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P1_24 P3_19 P0_23 - - - - - - - - - - - - - 80 ns noise filter disable 80 ns noise filter enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 80 ns noise filter disable 80 ns noise filter enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RIC_RE SIN087 (0x00AE) 0 RESSEL (0-7) RESSEL (0-7) RIC_RE SIN086 (0x00AC) Source for Resource Input RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Page 69 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN088 (0x00B0) RIC_RE SIN089 (0x00B2) RIC_RE SIN091 (0x00B6) RIC_RE SIN092 (0x00B8) RIC_RE SIN093 (0x00BA) Resource MFS9_TR IGGER SCS9 SIN10 SCK10 SCL10 RESSEL [3:0] /PORT SEL[3:0] Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) TOT16 TOT17 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_26 P3_21 P0_24 - - - - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P1_28 P3_12 - - - - - - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P1_29 P3_13 - - - - - - - - - - - - - - RESSEL (0-7) 80 ns noise filter disable 80 ns noise filter enable - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Page 70 of 322 S6J3310/20/30/40 Series Register (Offset) Resource RESSEL [3:0] /PORT SEL[3:0] RIC_RE SIN095 (0x00BE) RIC_RE SIN096 (0x00C0) RIC_RE SIN100 (0x00C8) SDA10 MFS10_T RIGGER SCS10 SCL11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 80 ns noise filter disable 80 ns noise filter enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) TOT16 TOT17 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_31 P3_15 - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) 80 ns noise filter disable 80 ns noise filter enable - - - - - - RESSEL (8-15) - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RIC_RE SIN094 (0x00BC) Source for Resource Input RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Page 71 of 322 S6J3310/20/30/40 Series Register (Offset) Resource RESSEL [3:0] /PORT SEL[3:0] RIC_RE SIN102 (0x00CC) RIC_RE SIN105 (0x00D2) RIC_RE SIN106 (0x00D4) RIC_RE SIN107 (0x00D6) SDA11 MFS11_T RIGGER SIN12 SCK12 SCL12 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 80 ns noise filter disable 80 ns noise filter enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) TOT16 TOT17 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P2_05 P4_18 - - - - - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P2_06 P1_15 - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) 80 ns noise filter disable 80 ns noise filter enable - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) RIC_RE SIN101 (0x00CA) Source for Resource Input RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Page 72 of 322 S6J3310/20/30/40 Series Register (Offset) Resource RESSEL [3:0] /PORT SEL[3:0] RIC_RE SIN109 (0x00DA) RIC_RE SIN110 (0x00DC) RIC_RE SIN133 (0x010A) SDA12 MFS12_T RIGGER SCS12 RX5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) TOT16 TOT17 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P2_08 P3_23 - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) PORT_ PIN MCAN5 _PIN_A ND_TX - - - - - - RESSEL (8-15) - - - - - - - - P1_17 P3_19 - - - - - - - - - - - - - - PORT_ PIN MCAN6 _PIN_A ND_TX - - - - - - - - - - - - - - P1_21 P3_22 - - - - - - - - - - - - - - RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RX6 1 80 ns noise filter enable RESSEL (0-7) RIC_RE SIN134 (0x010C) 0 80 ns noise filter disable RESSEL (0-7) RIC_RE SIN108 (0x00D8) Source for Resource Input RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Page 73 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN136 (0x0110) RIC_RE SIN137 (0x0112) Resource RX0 RX1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN MCAN0 _PIN_A ND_TX - - - - - - RESSEL (8-15) - - - - - - - - PORTSE L (0-7) P1_05 P3_09 P4_00 - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) PORT_ PIN MCAN1 _PIN_A ND_TX - - - - - - RESSEL (8-15) - - - - - - - - P1_07 P3_11 - - - - - - - - - - - - - - PORT_ PIN MCAN2 _PIN_A ND_TX - - - - - - - - - - - - - - P1_11 P3_14 - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN MCAN3 _PIN_A ND_TX - - - - - - RESSEL (8-15) - - - - - - - - PORTSE L (0-7) P1_13 P3_16 P4_03 - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RIC_RE SIN138 (0x0114) RIC_RE SIN139 (0x0116) RX2 RX3 RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 74 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN141 (0x011A) RIC_RE SIN142 (0x011C) RIC_RE SIN144 (0x0120) RIC_RE SIN145 (0x0122) RIC_RE SIN160 (0x0140) Resource TIN48 TIN49 TIN0 TIN1 TIN16 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN TOT49 RLT49_ UFSET - - - - - RESSEL (8-15) - - - - - - - - P1_13 P3_16 - - - - - - - - - - - - - - PORT_ PIN TOT48 RLT48_ UFSET - - - - - - - - - - - - - PORTSE L (0-7) P1_15 P3_20 - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN TOT1 RLT1_U FSET - PPG0_T OUT0 - - - - - - - - - - - P1_03 P3_08 - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN TOT0 RLT0_U FSET - PPG1_T OUT0 - - - RESSEL (8-15) - - - - - - - - P1_05 P3_10 - - - - - - - - - - - - - - PORT_ PIN TOT17 RLT17_ UFSET - PPG6_T OUT0 - - - - - - - - - - - PORTSE L (0-7) P1_07 P3_12 - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 75 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN161 (0x0142) RIC_RE SIN192 (0x0180) RIC_RE SIN193 (0x0182) RIC_RE SIN194 (0x0184) RIC_RE SIN195 (0x0186) Resource TIN17 EINT0 EINT1 EINT2 EINT3 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN TOT16 RLT16_ UFSET - PPG7_T OUT0 - - - RESSEL (8-15) - - - - - - - - P1_11 P3_14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P2_13 P0_00 P0_08 P0_20 P3_17 P2_01 P2_16 - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P0_01 P3_00 P0_09 P0_22 P4_16 P4_27 P2_17 - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P0_21 P4_30 P4_03 P0_23 P3_20 P2_02 P2_18 - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P0_28 P3_28 P4_04 P0_24 P3_21 P2_03 P2_19 - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 76 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN196 (0x0188) RIC_RE SIN197 (0x018A) RIC_RE SIN198 (0x018C) RIC_RE SIN199 (0x018E) RIC_RE SIN200 (0x0190) Resource EINT4 EINT5 EINT6 EINT7 EINT8 RESSEL [3:0] /PORT SEL[3:0] Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P1_03 P0_02 P4_05 P0_25 P3_23 P2_04 - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_04 P0_03 P0_10 P0_26 P4_17 P4_28 - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P1_05 P3_09 P0_11 P0_27 P4_18 P2_06 - - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P1_06 P4_00 P0_12 P0_29 P4_20 P2_07 - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_07 P3_11 P0_13 P0_30 P4_21 P4_29 - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Page 77 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN201 (0x0192) RIC_RE SIN202 (0x0194) RIC_RE SIN203 (0x0196) RIC_RE SIN204 (0x0198) RIC_RE SIN205 (0x019A) Resource EINT9 EINT10 EINT11 EINT12 EINT13 RESSEL [3:0] /PORT SEL[3:0] Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P1_08 P4_01 P3_01 P0_31 P1_16 P2_08 - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_09 P4_02 P3_02 P1_00 P4_23 P4_31 - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P1_10 P0_04 P3_03 P1_01 P1_18 P3_24 - - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P1_11 P3_14 P3_04 P1_02 P1_20 P3_25 - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_12 P0_05 P4_06 P4_08 P1_22 P3_26 - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Page 78 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN206 (0x019C) RIC_RE SIN207 (0x019E) RIC_RE SIN208 (0x01A0) RIC_RE SIN209 (0x01A2) RIC_RE SIN210 (0x01A4) Resource EINT14 EINT15 EINT16 EINT17 EINT18 RESSEL [3:0] /PORT SEL[3:0] Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P1_13 P3_16 P4_07 P4_09 P1_24 P3_27 - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_14 P0_06 P3_05 P4_10 P1_25 P2_09 - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P1_15 P4_19 P3_06 P4_11 P4_24 P3_29 - - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P1_17 P3_19 P0_14 P3_10 P1_26 P3_30 - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_19 P3_08 P0_15 P3_13 P1_27 P3_31 - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Page 79 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN211 (0x01A6) RIC_RE SIN212 (0x01A8) RIC_RE SIN213 (0x01AA) RIC_RE SIN214 (0x01AC) RIC_RE SIN215 (0x01AE) Resource EINT19 EINT20 EINT21 EINT22 EINT23 RESSEL [3:0] /PORT SEL[3:0] Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P1_21 P3_22 P0_16 P3_15 P4_25 P2_10 - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_23 P3_18 P3_07 P4_12 P1_29 P2_11 - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P1_28 P3_12 P0_17 P4_13 P1_30 P2_12 - - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P2_00 P4_22 P0_18 P4_14 P1_31 P2_14 - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P2_05 P0_07 P0_19 P4_15 P4_26 P2_15 - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Page 80 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN216 (0x01B0) RIC_RE SIN217 (0x01B2) RIC_RE SIN218 (0x01B4) RIC_RE SIN219 (0x01B6) RIC_RE SIN220 (0x01B8) Resource TEXT0 TEXT1 TEXT2 TEXT3 TEXT4 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN TOT0 TOT1 PPG0_T OUT2 - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN TOT0 TOT1 PPG1_T OUT2 - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN TOT0 TOT1 PPG2_T OUT2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN TOT0 TOT1 PPG3_T OUT2 - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN TOT0 TOT1 PPG4_T OUT2 - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 81 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN224 (0x01C0) RIC_RE SIN225 (0x01C2) RIC_RE SIN226 (0x01C4) Resource TEXT8 TEXT9 TEXT10 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT16_ UFSET PPG6_T OUT2 - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT16_ UFSET PPG7_T OUT2 - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORT_ PIN RLT0_U FSET RLT16_ UFSET PPG8_T OUT2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 82 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU0_C K0 OCU0_CK 1 IN232 (0x01D0) OCU0_D OWNB0 OCU0_D OWNB1 OCU0_FC MD0 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT0 FRT1 FRT2 FRT3 FRT4 - - - - - - - - - - - - - - - - - - - - - - - - - - - FRT0 FRT1 FRT2 FRT3 FRT4 - - - RESSEL (8-15) - - - - - - - - PORTSE L (0-7) - - - - - - - - - - - - - - - - FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB - - - - - - - - - - - - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB - - - - - - - - - - - - - - - - - - - - - - - - - - - FRT0_F CMD FRT1_F CMD FRT2_F CMD FRT3_F CMD FRT4_F CMD - - - RESSEL (8-15) - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) Document Number: 002-10635 Rev. *H Source for Resource Input Page 83 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU0_FC MD1 OCU0_MT SF0 IN232 (0x01D0) OCU0_MT SF1 OCU0_T0[ 31:0] OCU0_T1[ 31:0] RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT0_F CMD FRT1_F CMD FRT2_F CMD FRT3_F CMD FRT4_F CMD - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) FRT0_T [31:0] FRT1_T [31:0] FRT2_T [31:0] FRT3_T [31:0] FRT4_T [31:0] - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0_T [31:0] FRT1_T [31:0] FRT2_T [31:0] FRT3_T [31:0] FRT4_T [31:0] - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 84 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU0_ZT SF0 IN232 (0x01D0) OCU0_ZT SF1 RIC_RE SIN233 (0x01D2) RIC_RE SIN234 (0x01D4) RIC_RE SIN235 (0x01D6) OCU0_M OD0 OCU0_M OD1 OCU1_CK 0 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - set 1 set 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) set 1 set 0 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0 FRT1 FRT2 FRT3 FRT4 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 85 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU1_CK 1 OCU1_D OWNB0 RIC_RE SIN235 (0x01D6) OCU1_D OWNB1 OCU1_FC MD0 OCU1_FC MD1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT0 FRT1 FRT2 FRT3 FRT4 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) FRT0_F CMD FRT1_F CMD FRT2_F CMD FRT3_F CMD FRT4_F CMD - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0_F CMD FRT1_F CMD FRT2_F CMD FRT3_F CMD FRT4_F CMD - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 86 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU1_MT SF0 OCU1_MT SF1 RIC_RE SIN235 (0x01D6) OCU1_T0[ 31:0] OCU1_T1[ 31:0] RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) FRT0_T [31:0] FRT1_T [31:0] FRT2_T [31:0] FRT3_T [31:0] FRT4_T [31:0] - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) FRT0_T [31:0] FRT1_T [31:0] FRT2_T [31:0] FRT3_T [31:0] FRT4_T [31:0] - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 87 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU1_ZT SF0 RIC_RE SIN235 (0x01D6) OCU1_ZT SF1 RIC_RE SIN236 (0x01D8) RIC_RE SIN237 (0x01DA) OCU1_M OD0 OCU1_M OD1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - set 1 set 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) set 1 set 0 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 88 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU2_CK 0 RIC_RE SIN238 (0x01DC) OCU2_CK 1 OCU2_D OWNB0 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT0 FRT1 FRT2 FRT3 FRT4 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0 FRT1 FRT2 FRT3 FRT4 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 89 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU2_D OWNB1 OCU2_FC MD0 RIC_RE SIN238 (0x01DC) OCU2_FC MD1 OCU2_MT SF0 OCU2_MT SF1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT0_D OWNB FRT1_D OWNB FRT2_D OWNB FRT3_D OWNB FRT4_D OWNB - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0_F CMD FRT1_F CMD FRT2_F CMD FRT3_F CMD FRT4_F CMD - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) FRT0_F CMD FRT1_F CMD FRT2_F CMD FRT3_F CMD FRT4_F CMD - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0_M TSF FRT1_M TSF FRT2_M TSF FRT3_M TSF FRT4_M TSF - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 90 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU2_T0[ 31:0] OCU2_T1[ 31:0] RIC_RE SIN238 (0x01DC) OCU2_ZT SF0 OCU2_ZT SF1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT0_T [31:0] FRT1_T [31:0] FRT2_T [31:0] FRT3_T [31:0] FRT4_T [31:0] - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0_T [31:0] FRT1_T [31:0] FRT2_T [31:0] FRT3_T [31:0] FRT4_T [31:0] - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) FRT0_Z TSF FRT1_Z TSF FRT2_Z TSF FRT3_Z TSF FRT4_Z TSF - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 91 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN239 (0x01DE) RIC_RE SIN240 (0x01E0) Resource OCU2_M OD0 OCU2_M OD1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) set 1 set 0 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - set 1 set 0 - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 92 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU8_CK 0 OCU8_CK 1 RIC_RE SIN256 (0x0200) OCU8_D OWNB0 OCU8_D OWNB1 OCU8_FC MD0 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT8 FRT9 FRT10 - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8 FRT9 FRT10 - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_F CMD FRT9_F CMD FRT10_ FCMD - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 93 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU8_FC MD1 OCU8_MT SF0 RIC_RE SIN256 (0x0200) OCU8_MT SF1 OCU8_T0[ 31:0] OCU8_T1[ 31:0] RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT8_F CMD FRT9_F CMD FRT10_ FCMD - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_M TSF FRT9_M TSF FRT10_ MTSF - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) FRT8_M TSF FRT9_M TSF FRT10_ MTSF - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) FRT8_T [31:0] FRT9_T [31:0] FRT10_ T[31:0] - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_T [31:0] FRT9_T [31:0] FRT10_ T[31:0] - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 94 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU8_ZT SF0 RIC_RE SIN256 (0x0200) OCU8_ZT SF1 RIC_RE SIN257 (0x0202) OCU8_M OD0 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - set 1 set 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 95 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN258 (0x0204) Resource OCU8_M OD1 OCU9_CK 0 RIC_RE SIN259 (0x0206) OCU9_CK 1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) set 1 set 0 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8 FRT9 FRT10 - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - FRT8 FRT9 FRT10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 96 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU9_D OWNB0 OCU9_D OWNB1 RIC_RE SIN259 (0x0206) OCU9_FC MD0 OCU9_FC MD1 OCU9_MT SF0 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) FRT8_F CMD FRT9_F CMD FRT10_ FCMD - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) FRT8_F CMD FRT9_F CMD FRT10_ FCMD - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_M TSF FRT9_M TSF FRT10_ MTSF - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 97 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU9_MT SF1 OCU9_T0[ 31:0] RIC_RE SIN259 (0x0206) OCU9_T1[ 31:0] OCU9_ZT SF0 OCU9_ZT SF1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT8_M TSF FRT9_M TSF FRT10_ MTSF - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_T [31:0] FRT9_T [31:0] FRT10_ T[31:0] - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) FRT8_T [31:0] FRT9_T [31:0] FRT10_ T[31:0] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 98 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN260 (0x0208) RIC_RE SIN261 (0x020A) Resource OCU9_M OD0 OCU9_M OD1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) set 1 set 0 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - set 1 set 0 - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 99 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU10_C K0 OCU10_C K1 RIC_RE SIN262 (0x020C) OCU10_D OWNB0 OCU10_D OWNB1 OCU10_F CMD0 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT8 FRT9 FRT10 - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8 FRT9 FRT10 - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) FRT8_D OWNB FRT9_D OWNB FRT10_ DOWNB - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_F CMD FRT9_F CMD FRT10_ FCMD - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 100 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU10_F CMD1 OCU10_M TSF0 RIC_RE SIN262 (0x020C) OCU10_M TSF1 OCU10_T 0[31:0] OCU10_T 1[31:0] RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT8_F CMD FRT9_F CMD FRT10_ FCMD - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_M TSF FRT9_M TSF FRT10_ MTSF - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) FRT8_M TSF FRT9_M TSF FRT10_ MTSF - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) FRT8_T [31:0] FRT9_T [31:0] FRT10_ T[31:0] - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_T [31:0] FRT9_T [31:0] FRT10_ T[31:0] - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 101 of 322 S6J3310/20/30/40 Series Register (Offset) Resource OCU10_Z TSF0 RIC_RE SIN262 (0x020C) OCU10_Z TSF1 RIC_RE SIN263 (0x020E) RIC_RE SIN264 (0x0210) RIC_RE SIN280 (0x0230) OCU10_M OD0 OCU10_M OD1 ICU0_IN0 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_Z TSF FRT9_Z TSF FRT10_ ZTSF - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - set 1 set 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) set 1 set 0 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN MFS0_L SYN - - - - - - - - - - - - - - PORTSE L (0-7) P1_03 P3_08 - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 102 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN281 (0x0232) Resource ICU0_IN1 ICU0_T0[ 31:0] RIC_RE SIN282 (0x0234) ICU0_T1[ 31:0] RIC_RE SIN283 (0x0236) RIC_RE SIN284 (0x0238) ICU1_IN0 ICU1_IN1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN MFS1_L SYN - - - - - - RESSEL (8-15) - - - - - - - - P1_04 P3_09 - - - - - - - - - - - - - - FRT0_T [31:0] FRT1_T [31:0] FRT2_T [31:0] FRT3_T [31:0] FRT4_T [31:0] - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) FRT0_T [31:0] FRT1_T [31:0] FRT2_T [31:0] FRT3_T [31:0] FRT4_T [31:0] - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN MFS2_L SYN - - - - - - RESSEL (8-15) - - - - - - - - P1_05 P3_10 - - - - - - - - - - - - - - PORT_ PIN MFS3_L SYN - - - - - - - - - - - - - - PORTSE L (0-7) P1_06 P3_11 - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 103 of 322 S6J3310/20/30/40 Series Register (Offset) Resource ICU1_T0[ 31:0] RIC_RE SIN285 (0x023A) ICU1_T1[ 31:0] RIC_RE SIN286 (0x023C) RIC_RE SIN287 (0x023E) ICU2_IN0 ICU2_IN1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT0_T [31:0] FRT1_T [31:0] FRT2_T [31:0] FRT3_T [31:0] FRT4_T [31:0] - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0_T [31:0] FRT1_T [31:0] FRT2_T [31:0] FRT3_T [31:0] FRT4_T [31:0] - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN MFS4_L SYN - - - - - - - - - - - - - - P1_07 P3_12 - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN - - - - - - - RESSEL (8-15) - - - - - - - - P1_08 P3_13 - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 104 of 322 S6J3310/20/30/40 Series Register (Offset) Resource ICU2_T0[ 31:0] RIC_RE SIN288 (0x0240) ICU2_T1[ 31:0] RIC_RE SIN304 (0x0260) RIC_RE SIN305 (0x0262) ICU8_IN0 ICU8_IN1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT0_T [31:0] FRT1_T [31:0] FRT2_T [31:0] FRT3_T [31:0] FRT4_T [31:0] - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT0_T [31:0] FRT1_T [31:0] FRT2_T [31:0] FRT3_T [31:0] FRT4_T [31:0] - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN MFS8_L SYN - - - - - - - - - - - - - - P1_09 P3_14 - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN MFS9_L SYN - - - - - - RESSEL (8-15) - - - - - - - - P1_10 P3_15 - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 105 of 322 S6J3310/20/30/40 Series Register (Offset) Resource ICU8_T0[ 31:0] RIC_RE SIN306 (0x0264) ICU8_T1[ 31:0] RIC_RE SIN307 (0x0266) RIC_RE SIN308 (0x0268) ICU9_IN0 ICU9_IN1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT8_T [31:0] FRT9_T [31:0] FRT10_ T[31:0] - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_T [31:0] FRT9_T [31:0] FRT10_ T[31:0] - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN MFS10_ LSYN - - - - - - - - - - - - - - P1_11 P3_16 - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN MFS11_ LSYN - - - - - - RESSEL (8-15) - - - - - - - - P1_12 P3_17 - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 106 of 322 S6J3310/20/30/40 Series Register (Offset) Resource ICU9_T0[ 31:0] RIC_RE SIN309 (0x026A) ICU9_T1[ 31:0] RIC_RE SIN310 (0x026C) RIC_RE SIN311 (0x026E) ICU10_IN 0 ICU10_IN 1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT8_T [31:0] FRT9_T [31:0] FRT10_ T[31:0] - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_T [31:0] FRT9_T [31:0] FRT10_ T[31:0] - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN MFS12_ LSYN - - - - - - - - - - - - - - P1_14 P3_18 - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN - - - - - - - RESSEL (8-15) - - - - - - - - P1_15 P3_19 - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 107 of 322 S6J3310/20/30/40 Series Register (Offset) Resource ICU10_T0 [31:0] RIC_RE SIN312 (0x0270) ICU10_T1 [31:0] RIC_RE SIN352 (0x02C0) RIC_RE SIN353 (0x02C2) RIC_RE SIN354 (0x02C4) AIN8 BIN8 ZIN8 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) FRT8_T [31:0] FRT9_T [31:0] FRT10_ T[31:0] - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - FRT8_T [31:0] FRT9_T [31:0] FRT10_ T[31:0] - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN TOT0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN TOT1 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN TOT16 PPG6_T OUT0 PPG6_T OUT2 PPG7_T OUT0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 108 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN355 (0x02C6) RIC_RE SIN356 (0x02C8) RIC_RE SIN357 (0x02CA) RIC_RE SIN376 (0x02F0) RIC_RE SIN377 (0x02F2) Resource AIN9 BIN9 ZIN9 PPG0_TI N1 PPG0_TI N2 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN TOT16 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN TOT17 - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN TOT0 PPG6_T OUT0 PPG6_T OUT2 PPG7_T OUT0 - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN TOT0 RLT0_U FSET TOT0 RLT0_U FSET FRT0_M TSF OCU0_ OTD0 - RESSEL (8-15) - - - - - - - - P1_16 P3_04 - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 109 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN378 (0x02F4) RIC_RE SIN379 (0x02F6) RIC_RE SIN380 (0x02F8) RIC_RE SIN381 (0x02FA) RIC_RE SIN382 (0x02FC) Resource PPG0_TI N3 PPG1_TI N1 PPG1_TI N2 PPG1_TI N3 PPG2_TI N1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN TOT0 RLT0_U FSET TOT0 RLT0_U FSET FRT0_M TSF OCU0_ OTD0 - - - - - - - - - PORTSE L (0-7) P1_16 P3_04 - - - - - - PORTSE L (8-15) - - - - - - - - set 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN TOT0 RLT0_U FSET TOT0 RLT0_U FSET FRT0_M TSF OCU0_ OTD0 - - - - - - - - - PORTSE L (0-7) P1_16 P3_04 - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 110 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN383 (0x02FE) RIC_RE SIN384 (0x0300) RIC_RE SIN385 (0x0302) RIC_RE SIN386 (0x0304) RIC_RE SIN387 (0x0306) Resource PPG2_TI N2 PPG2_TI N3 PPG3_TI N1 PPG3_TI N2 PPG3_TI N3 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORT_ PIN TOT0 RLT0_U FSET TOT1 RLT1_U FSET FRT0_M TSF OCU0_ OTD0 - - - - - - - - - P1_16 P3_04 - - - - - - - - - - - - - - RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 111 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN388 (0x0308) RIC_RE SIN389 (0x030A) RIC_RE SIN390 (0x030C) RIC_RE SIN391 (0x030E) RIC_RE SIN392 (0x0310) Resource PPG4_TI N1 PPG4_TI N2 PPG4_TI N3 PPG5_TI N1 PPG5_TI N2 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN TOT0 RLT0_U FSET TOT1 RLT1_U FSET FRT0_M TSF OCU0_ OTD0 - RESSEL (8-15) - - - - - - - - P1_16 P3_04 - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - set 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN TOT0 RLT0_U FSET TOT1 RLT1_U FSET FRT0_M TSF OCU0_ OTD0 - RESSEL (8-15) - - - - - - - - P1_16 P3_04 - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 112 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN393 (0x0312) RIC_RE SIN394 (0x0314) RIC_RE SIN395 (0x0316) RIC_RE SIN396 (0x0318) RIC_RE SIN397 (0x031A) Resource PPG5_TI N3 PPG6_TI N1 PPG6_TI N2 PPG6_TI N3 PPG7_TI N1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN TOT0 RLT0_U FSET TOT16 RLT16_ UFSET FRT8_M TSF OCU8_ OTD0 - - - - - - - - - PORTSE L (0-7) P1_29 P3_20 - - - - - - PORTSE L (8-15) - - - - - - - - set 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN TOT0 RLT0_U FSET TOT16 RLT16_ UFSET FRT8_M TSF OCU8_ OTD0 - - - - - - - - - PORTSE L (0-7) P1_29 P3_20 - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 113 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN398 (0x031C) RIC_RE SIN399 (0x031E) RIC_RE SIN400 (0x0320) RIC_RE SIN401 (0x0322) RIC_RE SIN402 (0x0324) Resource PPG7_TI N2 PPG7_TI N3 PPG8_TI N1 PPG8_TI N2 PPG8_TI N3 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORT_ PIN TOT0 RLT0_U FSET TOT16 RLT16_ UFSET FRT8_M TSF OCU8_ OTD0 - - - - - - - - - P1_29 P3_20 - - - - - - - - - - - - - - RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 114 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN403 (0x0326) RIC_RE SIN404 (0x0328) RIC_RE SIN405 (0x032A) RIC_RE SIN406 (0x032C) RIC_RE SIN407 (0x032E) Resource PPG9_TI N1 PPG9_TI N2 PPG9_TI N3 PPG10_TI N1 PPG10_TI N2 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN TOT0 RLT0_U FSET TOT17 RLT17_ UFSET FRT8_M TSF OCU8_ OTD0 - RESSEL (8-15) - - - - - - - - P1_29 P3_20 - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - set 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN TOT0 RLT0_U FSET TOT17 RLT17_ UFSET FRT8_M TSF OCU8_ OTD0 - RESSEL (8-15) - - - - - - - - P1_29 P3_20 - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 115 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN408 (0x0330) RIC_RE SIN409 (0x0332) RIC_RE SIN410 (0x0334) RIC_RE SIN411 (0x0336) RIC_RE SIN430 (0x035C) Resource PPG10_TI N3 PPG11_TI N1 PPG11_TI N2 PPG11_TI N3 PPG12_TI N1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN TOT0 RLT0_U FSET TOT17 RLT17_ UFSET FRT8_M TSF OCU8_ OTD0 - - - - - - - - - PORTSE L (0-7) P1_29 P3_20 - - - - - - PORTSE L (8-15) - - - - - - - - set 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN TOT0 RLT0_U FSET - - - - - - - - - - - - - PORTSE L (0-7) P2_06 P3_31 - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 116 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN431 (0x035E) RIC_RE SIN432 (0x0360) RIC_RE SIN433 (0x0362) RIC_RE SIN434 (0x0364) RIC_RE SIN435 (0x0366) Resource PPG12_TI N2 PPG12_TI N3 PPG13_TI N1 PPG13_TI N2 PPG13_TI N3 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORT_ PIN TOT0 RLT0_U FSET - - - - - - - - - - - - - P2_06 P3_31 - - - - - - - - - - - - - - RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 117 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN436 (0x0368) RIC_RE SIN437 (0x036A) RIC_RE SIN438 (0x036C) RIC_RE SIN439 (0x036E) RIC_RE SIN440 (0x0370) Resource PPG14_TI N1 PPG14_TI N2 PPG14_TI N3 PPG15_TI N1 PPG15_TI N2 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN TOT0 RLT0_U FSET - - - - - RESSEL (8-15) - - - - - - - - P2_06 P3_31 - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - set 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN TOT0 RLT0_U FSET - - - - - RESSEL (8-15) - - - - - - - - P2_06 P3_31 - - - - - - - - - - - - - - set 0 - - - - - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 118 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN441 (0x0372) RIC_RE SIN490 (0x03D4) RIC_RE SIN491 (0x03D6) RIC_RE SIN492 (0x03D8) RIC_RE SIN493 (0x03DA) Resource PPG15_TI N3 ADC12B0 _HWTRG 0 ADC12B0 _HWTRG 1 ADC12B0 _HWTRG 2 ADC12B0 _HWTRG 3 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) set 0 - - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU1_ OTD0 PPG0_T OUT0 PPG1_T OUT2 PPG3_T OUT2 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU2_ OTD0 PPG0_T OUT2 PPG2_T OUT0 PPG4_T OUT0 - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU8_ OTD0 PPG1_T OUT0 PPG2_T OUT2 PPG4_T OUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU9_ OTD0 PPG1_T OUT2 PPG3_T OUT0 PPG5_T OUT0 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 119 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN494 (0x03DC) RIC_RE SIN495 (0x03DE) RIC_RE SIN496 (0x03E0) RIC_RE SIN497 (0x03E2) RIC_RE SIN498 (0x03E4) Resource ADC12B0 _HWTRG 4 ADC12B0 _HWTRG 5 ADC12B0 _HWTRG 6 ADC12B0 _HWTRG 7 ADC12B0 _HWTRG 8 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU10_ OTD0 PPG2_T OUT0 PPG3_T OUT2 PPG5_T OUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU0_ OTD0 PPG2_T OUT2 PPG4_T OUT0 PPG6_T OUT0 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU2_ OTD0 PPG3_T OUT0 PPG4_T OUT2 PPG6_T OUT2 - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU8_ OTD0 PPG3_T OUT2 PPG5_T OUT0 PPG7_T OUT0 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU9_ OTD0 PPG4_T OUT0 PPG5_T OUT2 PPG7_T OUT2 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 120 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN499 (0x03E6) RIC_RE SIN500 (0x03E8) RIC_RE SIN501 (0x03EA) RIC_RE SIN502 (0x03EC) RIC_RE SIN503 (0x03EE) Resource ADC12B0 _HWTRG 9 ADC12B0 _HWTRG 10 ADC12B0 _HWTRG 11 ADC12B0 _HWTRG 12 ADC12B0 _HWTRG 13 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU10_ OTD0 PPG4_T OUT2 PPG6_T OUT0 PPG8_T OUT0 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU0_ OTD0 PPG5_T OUT0 PPG6_T OUT2 PPG8_T OUT2 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU1_ OTD0 PPG5_T OUT2 PPG7_T OUT0 PPG9_T OUT0 - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU8_ OTD0 PPG6_T OUT0 PPG7_T OUT2 PPG9_T OUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU9_ OTD0 PPG6_T OUT2 PPG8_T OUT0 PPG10_ TOUT0 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 121 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN504 (0x03F0) RIC_RE SIN505 (0x03F2) RIC_RE SIN506 (0x03F4) RIC_RE SIN507 (0x03F6) RIC_RE SIN508 (0x03F8) Resource ADC12B0 _HWTRG 14 ADC12B0 _HWTRG 15 ADC12B0 _HWTRG 16 ADC12B0 _HWTRG 17 ADC12B0 _HWTRG 18 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU10_ OTD0 PPG7_T OUT0 PPG8_T OUT2 PPG10_ TOUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU0_ OTD0 PPG7_T OUT2 PPG9_T OUT0 PPG11_ TOUT0 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU1_ OTD0 PPG8_T OUT0 PPG9_T OUT2 PPG11_ TOUT2 - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU2_ OTD0 PPG8_T OUT2 PPG10_ TOUT0 PPG12_ TOUT0 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU9_ OTD0 PPG9_T OUT0 PPG10_ TOUT2 PPG12_ TOUT2 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 122 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN509 (0x03FA) RIC_RE SIN510 (0x03FC) RIC_RE SIN511 (0x03FE) RIC_RE SIN512 (0x0400) RIC_RE SIN513 (0x0402) Resource ADC12B0 _HWTRG 19 ADC12B0 _HWTRG 20 ADC12B0 _HWTRG 21 ADC12B0 _HWTRG 22 ADC12B0 _HWTRG 23 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU10_ OTD0 PPG9_T OUT2 PPG11_ TOUT0 PPG13_ TOUT0 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU0_ OTD0 PPG10_ TOUT0 PPG11_ TOUT2 PPG13_ TOUT2 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU1_ OTD0 PPG10_ TOUT2 PPG12_ TOUT0 PPG14_ TOUT0 - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU2_ OTD0 PPG11_ TOUT0 PPG12_ TOUT2 PPG14_ TOUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU8_ OTD0 PPG11_ TOUT2 PPG13_ TOUT0 PPG15_ TOUT0 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 123 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN514 (0x0404) RIC_RE SIN515 (0x0406) RIC_RE SIN516 (0x0408) RIC_RE SIN517 (0x040A) RIC_RE SIN518 (0x040C) Resource ADC12B0 _HWTRG 24 ADC12B0 _HWTRG 25 ADC12B0 _HWTRG 26 ADC12B0 _HWTRG 27 ADC12B0 _HWTRG 28 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU10_ OTD0 PPG12_ TOUT0 PPG13_ TOUT2 PPG15_ TOUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU0_ OTD0 PPG12_ TOUT2 PPG14_ TOUT0 - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU1_ OTD0 PPG13_ TOUT0 PPG14_ TOUT2 - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU2_ OTD0 PPG13_ TOUT2 PPG15_ TOUT0 - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU8_ OTD0 PPG14_ TOUT0 PPG15_ TOUT2 - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 124 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN519 (0x040E) RIC_RE SIN520 (0x0410) RIC_RE SIN521 (0x0412) RIC_RE SIN522 (0x0414) RIC_RE SIN523 (0x0416) Resource ADC12B0 _HWTRG 29 ADC12B0 _HWTRG 30 ADC12B0 _HWTRG 31 ADC12B0 _HWTRG 32 ADC12B0 _HWTRG 33 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU9_ OTD0 PPG14_ TOUT2 - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU1_ OTD0 PPG15_ TOUT0 - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU2_ OTD0 PPG15_ TOUT2 - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU8_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU9_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 125 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN524 (0x0418) RIC_RE SIN525 (0x041A) RIC_RE SIN526 (0x041C) RIC_RE SIN527 (0x041E) RIC_RE SIN528 (0x0420) Resource ADC12B0 _HWTRG 34 ADC12B0 _HWTRG 35 ADC12B0 _HWTRG 36 ADC12B0 _HWTRG 37 ADC12B0 _HWTRG 38 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU10_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU0_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU2_ OTD0 - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU8_ OTD0 - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU9_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 126 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN529 (0x0422) RIC_RE SIN530 (0x0424) RIC_RE SIN531 (0x0426) RIC_RE SIN532 (0x0428) RIC_RE SIN533 (0x042A) Resource ADC12B0 _HWTRG 39 ADC12B0 _HWTRG 40 ADC12B0 _HWTRG 41 ADC12B0 _HWTRG 42 ADC12B0 _HWTRG 43 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU10_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU0_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU1_ OTD0 - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU8_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU9_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 127 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN534 (0x042C) RIC_RE SIN535 (0x042E) RIC_RE SIN536 (0x0430) RIC_RE SIN537 (0x0432) RIC_RE SIN538 (0x0434) Resource ADC12B0 _HWTRG 44 ADC12B0 _HWTRG 45 ADC12B0 _HWTRG 46 ADC12B0 _HWTRG 47 ADC12B0 _HWTRG 48 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU10_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU0_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU1_ OTD0 - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU2_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU9_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 128 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN539 (0x0436) RIC_RE SIN540 (0x0438) RIC_RE SIN541 (0x043A) RIC_RE SIN542 (0x043C) RIC_RE SIN543 (0x043E) Resource ADC12B0 _HWTRG 49 ADC12B0 _HWTRG 50 ADC12B0 _HWTRG 51 ADC12B0 _HWTRG 52 ADC12B0 _HWTRG 53 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU10_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU0_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU1_ OTD0 - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU2_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU8_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 129 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN544 (0x0440) RIC_RE SIN545 (0x0442) RIC_RE SIN546 (0x0444) RIC_RE SIN547 (0x0446) RIC_RE SIN548 (0x0448) Resource ADC12B0 _HWTRG 54 ADC12B0 _HWTRG 55 ADC12B0 _HWTRG 56 ADC12B0 _HWTRG 57 ADC12B0 _HWTRG 58 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU10_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU0_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU1_ OTD0 - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU2_ OTD0 - - PPG0_T OUT0 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU8_ OTD0 - - PPG0_T OUT2 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 130 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN549 (0x044A) RIC_RE SIN550 (0x044C) RIC_RE SIN551 (0x044E) RIC_RE SIN552 (0x0450) RIC_RE SIN553 (0x0452) Resource ADC12B0 _HWTRG 59 ADC12B0 _HWTRG 60 ADC12B0 _HWTRG 61 ADC12B0 _HWTRG 62 ADC12B0 _HWTRG 63 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU9_ OTD0 - - PPG1_T OUT0 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU1_ OTD0 - - PPG1_T OUT2 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU2_ OTD0 - PPG0_T OUT0 PPG2_T OUT0 - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU8_ OTD0 - PPG0_T OUT2 PPG2_T OUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU9_ OTD0 - PPG1_T OUT0 PPG3_ OUT0 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 131 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN554 (0x0454) RIC_RE SIN555 (0x0456) RIC_RE SIN556 (0x0458) RIC_RE SIN557 (0x045A) RIC_RE SIN558 (0x045C) Resource ADC12B1 _HWTRG 0 ADC12B1 _HWTRG 1 ADC12B1 _HWTRG 2 ADC12B1 _HWTRG 3 ADC12B1 _HWTRG 4 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU1_ OTD0 PPG0_T OUT0 PPG1_T OUT2 PPG3_T OUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU2_ OTD0 PPG0_T OUT2 PPG2_T OUT0 PPG4_T OUT0 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU8_ OTD0 PPG1_T OUT0 PPG2_T OUT2 PPG4_T OUT2 - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU9_ OTD0 PPG1_T OUT2 PPG3_T OUT0 PPG5_T OUT0 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU10_ OTD0 PPG2_T OUT0 PPG3_T OUT2 PPG5_T OUT2 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 132 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN559 (0x045E) RIC_RE SIN560 (0x0460) RIC_RE SIN561 (0x0462) RIC_RE SIN562 (0x0464) RIC_RE SIN563 (0x0466) Resource ADC12B1 _HWTRG 5 ADC12B1 _HWTRG 6 ADC12B1 _HWTRG 7 ADC12B1 _HWTRG 8 ADC12B1 _HWTRG 9 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU0_ OTD0 PPG2_T OUT2 PPG4_T OUT0 PPG6_T OUT0 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU2_ OTD0 PPG3_T OUT0 PPG4_T OUT2 PPG6_T OUT2 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU8_ OTD0 PPG3_T OUT2 PPG5_T OUT0 PPG7_T OUT0 - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU9_ OTD0 PPG4_T OUT0 PPG5_T OUT2 PPG7_T OUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU10_ OTD0 PPG4_T OUT2 PPG6_T OUT0 PPG8_T OUT0 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 133 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN564 (0x0468) RIC_RE SIN565 (0x046A) RIC_RE SIN566 (0x046C) RIC_RE SIN567 (0x046E) RIC_RE SIN568 (0x0470) Resource ADC12B1 _HWTRG 10 ADC12B1 _HWTRG 11 ADC12B1 _HWTRG 12 ADC12B1 _HWTRG 13 ADC12B1 _HWTRG 14 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU0_ OTD0 PPG5_T OUT0 PPG6_T OUT2 PPG8_T OUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU1_ OTD0 PPG5_T OUT2 PPG7_T OUT0 PPG9_T OUT0 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU8_ OTD0 PPG6_T OUT0 PPG7_T OUT2 PPG9_T OUT2 - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU9_ OTD0 PPG6_T OUT2 PPG8_T OUT0 PPG10_ TOUT0 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU10_ OTD0 PPG7_T OUT0 PPG8_T OUT2 PPG10_ TOUT2 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 134 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN569 (0x0472) RIC_RE SIN570 (0x0474) RIC_RE SIN571 (0x0476) RIC_RE SIN572 (0x0478) RIC_RE SIN573 (0x047A) Resource ADC12B1 _HWTRG 15 ADC12B1 _HWTRG 16 ADC12B1 _HWTRG 17 ADC12B1 _HWTRG 18 ADC12B1 _HWTRG 19 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU0_ OTD0 PPG7_T OUT2 PPG9_T OUT0 PPG11_ TOUT0 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU1_ OTD0 PPG8_T OUT0 PPG9_T OUT2 PPG11_ TOUT2 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU2_ OTD0 PPG8_T OUT2 PPG10_ TOUT0 PPG12_ TOUT0 - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU9_ OTD0 PPG9_T OUT0 PPG10_ TOUT2 PPG12_ TOUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU10_ OTD0 PPG9_T OUT2 PPG11_ TOUT0 PPG13_ TOUT0 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 135 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN574 (0x047C) RIC_RE SIN575 (0x047E) RIC_RE SIN576 (0x0480) RIC_RE SIN577 (0x0482) RIC_RE SIN578 (0x0484) Resource ADC12B1 _HWTRG 20 ADC12B1 _HWTRG 21 ADC12B1 _HWTRG 22 ADC12B1 _HWTRG 23 ADC12B1 _HWTRG 24 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU0_ OTD0 PPG10_ TOUT0 PPG11_ TOUT2 PPG13_ TOUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU1_ OTD0 PPG10_ TOUT2 PPG12_ TOUT0 PPG14_ TOUT0 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU2_ OTD0 PPG11_ TOUT0 PPG12_ TOUT2 PPG14_ TOUT2 - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU8_ OTD0 PPG11_ TOUT2 PPG13_ TOUT0 PPG15_ TOUT0 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU10_ OTD0 PPG12_ TOUT0 PPG13_ TOUT2 PPG15_ TOUT2 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 136 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN579 (0x0486) RIC_RE SIN580 (0x0488) RIC_RE SIN581 (0x048A) RIC_RE SIN582 (0x048C) RIC_RE SIN583 (0x048E) Resource ADC12B1 _HWTRG 25 ADC12B1 _HWTRG 26 ADC12B1 _HWTRG 27 ADC12B1 _HWTRG 28 ADC12B1 _HWTRG 29 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU0_ OTD0 PPG12_ TOUT2 PPG14_ TOUT0 - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU1_ OTD0 PPG13_ TOUT0 PPG14_ TOUT2 - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU2_ OTD0 PPG13_ TOUT2 PPG15_ TOUT0 - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU8_ OTD0 PPG14_ TOUT0 PPG15_ TOUT2 - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU9_ OTD0 PPG14_ TOUT2 - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 137 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN584 (0x0490) RIC_RE SIN585 (0x0492) RIC_RE SIN586 (0x0494) RIC_RE SIN587 (0x0496) RIC_RE SIN588 (0x0498) Resource ADC12B1 _HWTRG 30 ADC12B1 _HWTRG 31 ADC12B1 _HWTRG 32 ADC12B1 _HWTRG 33 ADC12B1 _HWTRG 34 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU1_ OTD0 PPG15_ TOUT0 - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU2_ OTD0 PPG15_ TOUT2 - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU8_ OTD0 - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU9_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU10_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 138 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN589 (0x049A) RIC_RE SIN590 (0x049C) RIC_RE SIN591 (0x049E) RIC_RE SIN592 (0x04A0) RIC_RE SIN593 (0x04A2) Resource ADC12B1 _HWTRG 35 ADC12B1 _HWTRG 36 ADC12B1 _HWTRG 37 ADC12B1 _HWTRG 38 ADC12B1 _HWTRG 39 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU0_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU2_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU8_ OTD0 - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU9_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU10_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 139 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN594 (0x04A4) RIC_RE SIN595 (0x04A6) RIC_RE SIN596 (0x04A8) RIC_RE SIN597 (0x04AA) RIC_RE SIN598 (0x04AC) Resource ADC12B1 _HWTRG 40 ADC12B1 _HWTRG 41 ADC12B1 _HWTRG 42 ADC12B1 _HWTRG 43 ADC12B1 _HWTRG 44 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU0_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU1_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU8_ OTD0 - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU9_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU10_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 140 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN599 (0x04AE) RIC_RE SIN600 (0x04B0) RIC_RE SIN601 (0x04B2) RIC_RE SIN602 (0x04B4) RIC_RE SIN603 (0x04B6) Resource ADC12B1 _HWTRG 45 ADC12B1 _HWTRG 46 ADC12B1 _HWTRG 47 ADC12B1 _HWTRG 48 ADC12B1 _HWTRG 49 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU0_ OTD0 - - -- RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU1_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU2_ OTD0 - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU9_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU10_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 141 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN604 (0x04B8) RIC_RE SIN605 (0x04BA) RIC_RE SIN606 (0x04BC) RIC_RE SIN607 (0x04BE) RIC_RE SIN608 (0x04C0) Resource ADC12B1 _HWTRG 50 ADC12B1 _HWTRG 51 ADC12B1 _HWTRG 52 ADC12B1 _HWTRG 53 ADC12B1 _HWTRG 54 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU0_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU1_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT0_U FSET RLT16_ UFSET OCU9_ OTD0 OCU2_ OTD0 - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT1_U FSET RLT17_ UFSET OCU10_ OTD0 OCU8_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT16_ UFSET RLT0_U FSET OCU0_ OTD0 OCU10_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 142 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN609 (0x04C2) RIC_RE SIN610 (0x04C4) RIC_RE SIN611 (0x04C6) RIC_RE SIN612 (0x04C8) RIC_RE SIN613 (0x04CA) Resource ADC12B1 _HWTRG 55 ADC12B1 _HWTRG 56 ADC12B1 _HWTRG 57 ADC12B1 _HWTRG 58 ADC12B1 _HWTRG 59 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT1_U FSET OCU1_ OTD0 OCU0_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT0_U FSET RLT17_ UFSET OCU2_ OTD0 OCU1_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT1_U FSET RLT0_U FSET OCU8_ OTD0 OCU2_ OTD0 - - - - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT16_ UFSET RLT1_U FSET OCU9_ OTD0 OCU8_ OTD0 - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT17_ UFSET RLT16_ UFSET OCU10_ OTD0 OCU9_ OTD0 - - - - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 143 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN614 (0x04CC) RIC_RE SIN615 (0x04CE) RIC_RE SIN616 (0x04D0) RIC_RE SIN617 (0x04D2) Resource ADC12B1 _HWTRG 60 ADC12B1 _HWTRG 61 ADC12B1 _HWTRG 62 ADC12B1 _HWTRG 63 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN RLT0_U FSET RLT1_U FSET OCU0_ OTD0 OCU1_ OTD0 - - PPG1_T OUT2 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORT_ PIN RLT1_U FSET RLT16_ UFSET OCU1_ OTD0 OCU2_ OTD0 - PPG0_T OUT0 PPG2_T OUT0 - - - - - - - - PORTSE L (0-7) - - - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORT_ PIN RLT16_ UFSET RLT17_ UFSET OCU2_ OTD0 OCU8_ OTD0 - PPG0_T OUT2 PPG2_T OUT2 - - - - - - - - - - - - - - - - - - - - - - - - RESSEL (0-7) PORT_ PIN RLT17_ UFSET RLT0_U FSET OCU8_ OTD0 OCU9_ OTD0 - PPG1_T OUT0 PPG3_T OUT0 RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Document Number: 002-10635 Rev. *H Source for Resource Input Page 144 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN626 (0x04E4) RIC_RE SIN629 (0x04EA) RIC_RE SIN630 (0x04EC) RIC_RE SIN631 (0x04EE) RIC_RE SIN632 (0x04F0) Resource DDRHSS PI_MSTA RT MDIO CRS RXD0 RXD1 RESSEL [3:0] /PORT SEL[3:0] Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) - TOT0 TOT16 - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P0_31 P3_06 - - - - - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P1_02 P0_20 - - - - - - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P0_27 P3_04 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P0_28 P4_06 - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Page 145 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN633 (0x04F2) RIC_RE SIN634 (0x04F4) RIC_RE SIN635 (0x04F6) RIC_RE SIN636 (0x04F8) RIC_RE SIN637 (0x04FA) Resource RXD2 RXD3 COL RXDV RXER RESSEL [3:0] /PORT SEL[3:0] Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P0_29 P4_07 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P0_30 P3_05 - - - - - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P1_01 P0_19 - - - - - - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P0_19 P4_02 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P0_18 P4_01 - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Page 146 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN638 (0x04FC) RIC_RE SIN639 (0x04FE) RIC_RE SIN643 (0x0506) RIC_RE SIN644 (0x0508) RIC_RE SIN645 (0x050A) Resource RXCLK TXCLK I2S0_WS I2S0_SD I2S0_SCK RESSEL [3:0] /PORT SEL[3:0] Source for Resource Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P0_17 P4_00 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P0_20 P4_03 - - - - - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P0_12 P3_26 - - - - - - - - - - - - - - RESSEL (0-7) - - - - - - - - RESSEL (8-15) - - - - - - - - P0_11 P3_25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P0_13 P3_27 - - - - - - PORTSE L (8-15) - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) Document Number: 002-10635 Rev. *H Page 147 of 322 S6J3310/20/30/40 Series Register (Offset) RIC_RE SIN646 (0x050C) RIC_RE SIN650 (0x0514) RIC_RE SIN685 (0x055A) RIC_RE SIN686 (0x055C) Resource I2S0_ECL K I2S1_ECL K ADTRG0 ADTRG1 RESSEL [3:0] /PORT SEL[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESSEL (0-7) PORT_ PIN SYSC1_ CLK_C D4 - - - - - - RESSEL (8-15) - - - - - - - - PORTSE L (0-7) P0_10 P3_24 - - - - - - PORTSE L (8-15) - - - - - - - - RESSEL (0-7) PORT_ PIN SYSC1_ CLK_C D4 - - - - - - RESSEL (8-15) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PORTSE L (0-7) P1_16 P2_10 - - - - - - PORTSE L (8-15) - - - - - - - - - - - - - - - - - - - - - - - - P4_22 P1_08 P2_11 - - - - - - - - - - - - - PORTSE L (0-7) PORTSE L (8-15) RESSEL (0-7) RESSEL (8-15) RESSEL (0-7) RESSEL (8-15) PORTSE L (0-7) PORTSE L (8-15) Source for Resource Input Notes: - When both GPIO_PORTEN.GPORTEN and PPC_PCFGR.PIE are configured as 0, the input signal is disconnected and external interrupt cannot be detected. During disconnecting, I/O internally outputs "low" to internal logic, and if ELVR is configured as low-level-detection, falling-edge-detection, or both-edge-detection it will be detected as external interrupt with EIRR = 1. - "Set 0" (Set 1) means that "0" ("1") is inputted. - OCUx_MODn is described as MODn pin in TraveoTM Platform Hardware Manual. Document Number: 002-10635 Rev. *H Page 148 of 322 S6J3310/20/30/40 Series 7.2 Port Output Function Configuration The port output function configuration (POF) is a function to select a function to output to a port. A resource which supports a port output relocation has its PPC_PCFGR.POF to configure resource output. 7.2.1 Standard Configuration (S6J3310) Register Port (Offset) POF = 0 POF = 1 PPC_PCF GR000 (0x0000) PPC_PCF GR001 (0x0002) PPC_PCF GR002 (0x0004) PPC_PCF GR003 (0x0006) PPC_PCF GR004 (0x0008) P0_00 P0_01 P0_02 P0_03 P0_04 GPIO_PO DR0:POD 00 GPIO_PO DR0:POD 01 GPIO_PO DR0:POD 02 GPIO_PO DR0:POD 03 GPIO_PO DR0:POD 04 Resource Functional Outputs POF = 2 POF = 3 POF = 4 POF = 5 POF = 6 POF = 7 - LCDD5 - - DSP0_R7 _0 - MAD1 - LCDD6 ARH0_AI C1_DNCL K - DSP0_G0 _0 - MAD2 LCDD7 ARH0_AI C1_TDA1 ARH0_AI C1_DND ATA1 DSP0_G1 _0 SCL1 MAD3 - DSP0_G2 _0 SDA1 MAD4 - DSP0_G3 _0 - MAD5 SCK1_0 SOT1_0 LCDD8 SCS10_0 LCDD9 ARH0_AI C1_dbg_ out_1 ARH0_AI C1_dbg_ out_0 PPC_PCF GR005 (0x000A) P0_05 GPIO_PO DR0:POD 05 SCS11_0 LCDD10 ARH0_AI C1_TDA0 ARH0_AI C1_DND ATA0 DSP0_G4 _0 SOT0_1 MAD6 PPC_PCF GR006 (0x000C) P0_06 GPIO_PO DR0:POD 06 SCS12_0 LCDD11 SCK0_1 - DSP0_G5 _0 PPG0_TO UT0_1 MAD7 SCS13_0 LCDD12 SCS00_1 I2S1_SD_ 0 DSP0_G6 _0 PPG0_TO UT2_1 MAD8 - LCDD13 - I2S1_WS _0 DSP0_G7 _0 PPG1_TO UT0_1 MAD9 - LCDD14 ARH0_AI C0_DNCL K I2S1_SC K_0 DSP0_B0 _0 PPG1_TO UT2_1 MAD10 LCDD15 ARH0_AI C0_TDA1 ARH0_AI C0_DND ATA1 DSP0_B1 _0 PPG2_TO UT0_1 MAD11 I2S0_SD_ 0 DSP0_B2 _0 PPG2_TO UT2_1 MAD12 PPC_PCF GR007 (0x000E) PPC_PCF GR008 (0x0010) PPC_PCF GR009 (0x0012) PPC_PCF GR010 (0x0014) PPC_PCF GR011 (0x0016) P0_07 P0_08 P0_09 P0_10 GPIO_PO DR0:POD 07 GPIO_PO DR0:POD 08 GPIO_PO DR0:POD 09 GPIO_PO DR0:POD 10 SCS171_ 1 P0_11 GPIO_PO DR0:POD 11 - LCDD16 ARH0_AI C0_dbg_ out_1 PPC_PCF GR012 (0x0018) P0_12 GPIO_PO DR0:POD 12 - LCDD17 ARH0_AI C0_dbg_ out_0 I2S0_WS _0 DSP0_B3 _0 PPG3_TO UT0_1 MAD13 PPC_PCF GR013 (0x001A) P0_13 GPIO_PO DR0:POD 13 - CS# - I2S0_SC K_0 DSP0_B4 _0 PPG3_TO UT2_1 MAD14 Document Number: 002-10635 Rev. *H Page 149 of 322 S6J3310/20/30/40 Series Register (Offset) Port PPC_PCF GR014 (0x001C) P0_14 PPC_PCF GR015 (0x001E) P0_15 PPC_PCF GR016 (0x0020) P0_16 PPC_PCF GR017 (0x0022) PPC_PCF GR018 (0x0024) PPC_PCF GR019 (0x0026) PPC_PCF GR020 (0x0028) P0_17 P0_18 P0_19 P0_20 Resource Functional Outputs POF = 0 GPIO_PO DR0:POD 14 POF = 1 POF = 2 POF = 3 POF = 4 POF = 5 POF = 6 POF = 7 - WR# - - DSP0_B5 _0 SCK4_1 MOEX GPIO_PO DR0:POD 15 - RD# - - DSP0_B6 _0 SCS40_1 MWEX GPIO_PO DR0:POD 16 DSP0_B7 _1 - ARH0_AI C0_TDA0 ARH0_AI C0_DND ATA0 - SCS41_1 MCLK - - - - DSP0_B7 _0 SCS43_1 MDQM0 - RS - MDC_1 - - MCSX2 - RES# - - - - MCSX3 - - - - - - - GPIO_PO DR0:POD 17 GPIO_PO DR0:POD 18 GPIO_PO DR0:POD 19 GPIO_PO DR0:POD 20 PPC_PCF GR021 (0x002A) P0_21 GPIO_PO DR0:POD 21 - M_SDATA 0_0 TXEN_0 M_DQ3 - - - PPC_PCF GR022 (0x002C) P0_22 GPIO_PO DR0:POD 22 SCK2_0 M_SDATA 0_2 TXD0_0 M_DQ2 SOT9_2 - - SOT2_0 M_SDATA 0_1 TXD1_0 M_DQ1 SCK9_2 - - SCS20_0 M_SSEL0 TXD2_0 M_DQ0 SCS90_2 - - SCS21_0 M_SDATA 0_3 TXD3_0 M_CS#_1 SCS91_2 - - SCS22_0 M_SCLK0 TXER_0 M_CK - - - PPC_PCF GR023 (0x002E) PPC_PCF GR024 (0x0030) PPC_PCF GR025 (0x0032) PPC_PCF GR026 (0x0034) P0_23 P0_24 P0_25 P0_26 GPIO_PO DR0:POD 23 GPIO_PO DR0:POD 24 GPIO_PO DR0:POD 25 GPIO_PO DR0:POD 26 PPC_PCF GR027 (0x0036) P0_27 GPIO_PO DR0:POD 27 SCS23_0 M_SDATA 1_0 - M_RWDS - - - PPC_PCF GR028 (0x0038) P0_28 GPIO_PO DR0:POD 28 - M_SDATA 1_2 - M_DQ4 SCK8_2 - - Document Number: 002-10635 Rev. *H Page 150 of 322 S6J3310/20/30/40 Series Register (Offset) Port PPC_PCF GR029 (0x003A) P0_29 PPC_PCF GR030 (0x003C) P0_30 PPC_PCF GR031 (0x003E) P0_31 PPC_PCF GR100 (0x0040) PPC_PCF GR101 (0x0042) PPC_PCF GR102 (0x0044) PPC_PCF GR103 (0x0046) P1_00 P1_01 P1_02 P1_03 Resource Functional Outputs POF = 0 GPIO_PO DR0:POD 29 POF = 1 POF = 2 POF = 3 POF = 4 POF = 5 POF = 6 POF = 7 SCK3_0 M_SDATA 1_1 - M_DQ5 SOT8_2 - - GPIO_PO DR0:POD 30 SOT3_0 M_SSEL1 - M_DQ6 SCS80_2 - - GPIO_PO DR0:POD 31 SCS30_0 M_SDATA 1_3 MDIO_0 M_DQ7 - - - SCS31_0 - MDC_0 M_CS#_2 - - - SCS32_0 - - - - - MLBSIG SCS33_0 - - - - - MLBDAT - - - OCU0_O TD0_0 - PPG0_TO UT0_0 BN0(BL0) GPIO_PO DR1:POD 00 GPIO_PO DR1:POD 01 GPIO_PO DR1:POD 02 GPIO_PO DR1:POD 03 PPC_PCF GR104 (0x0048) P1_04 GPIO_PO DR1:POD 04 SCK0_0 - SCL0 OCU0_O TD1_0 TOT0_0 PPG0_TO UT2_0 BP0(BH0) PPC_PCF GR105 (0x004A) P1_05 GPIO_PO DR1:POD 05 SOT0_0 SGA0_0 SDA0 TRACE0_ 0 - PPG1_TO UT0_0 AN0(AL0) SCS00_0 SGO0_0 TX0_0 TRACE1_ 0 TOT1_0 PPG1_TO UT2_0 AP0(AH0) - SGA1_0 TRACE2_ 0 OCU1_O TD0_0 - PPG2_TO UT0_0 BN1(BL1) TRACE3_ 0 SGO1_0 TX1_0 OCU1_O TD1_0 TOT16_0 PPG2_TO UT2_0 BP1(BH1) SCK16_0 SGA2_0 SCL16 OCU2_O TD0_0 TRACE_ CTL_0 PPG3_TO UT0_0 AN1(AL1) PPC_PCF GR106 (0x004C) PPC_PCF GR107 (0x004E) PPC_PCF GR108 (0x0050) PPC_PCF GR109 (0x0052) P1_06 P1_07 P1_08 P1_09 GPIO_PO DR1:POD 06 GPIO_PO DR1:POD 07 GPIO_PO DR1:POD 08 GPIO_PO DR1:POD 09 PPC_PCF GR110 (0x0054) P1_10 GPIO_PO DR1:POD 10 SOT16_0 SGO2_0 SDA16 OCU2_O TD1_0 TRACE_ CLK_0 PPG3_TO UT2_0 AP1(AH1) PPC_PCF GR111 (0x0056) P1_11 GPIO_PO DR1:POD 11 SCS160_ 0 INDICAT OR0_0 - OCU8_O TD0_0 - PPG4_TO UT0_0 - Document Number: 002-10635 Rev. *H Page 151 of 322 S6J3310/20/30/40 Series Register (Offset) Port PPC_PCF GR112 (0x0058) P1_12 PPC_PCF GR113 (0x005A) P1_13 PPC_PCF GR114 (0x005C) P1_14 PPC_PCF GR115 (0x005E) PPC_PCF GR116 (0x0060) PPC_PCF GR117 (0x0062) PPC_PCF GR118 (0x0064) P1_15 P1_16 P1_17 P1_18 Resource Functional Outputs POF = 0 GPIO_PO DR1:POD 12 POF = 1 POF = 2 POF = 3 POF = 4 POF = 5 POF = 6 POF = 7 SCS161_ 0 - - OCU8_O TD1_0 TOT17_0 PPG4_TO UT2_0 TX2_0 GPIO_PO DR1:POD 13 - SGA3_0 - OCU9_O TD0_0 - - - GPIO_PO DR1:POD 14 SYSC0_C LK_1 SGO3_0 - OCU9_O TD1_0 TOT48_0 PPG5_TO UT0_0 TX3_0 SCK17_0 SGA4_0 SCL17 OCU10_ OTD0_0 SCK12_1 PPG5_TO UT2_0 INDICAT OR0_1 SOT17_0 SGO4_0 SDA17 OCU10_ OTD1_0 TOT49_0 SYSC0_C LK_0 WOT SCS170_ 0 - - - PWM1P0 PPG6_TO UT0_0 - SCS171_ 0 - - - PWM1M0 PPG6_TO UT2_0 TX5_0 GPIO_PO DR1:POD 15 GPIO_PO DR1:POD 16 GPIO_PO DR1:POD 17 GPIO_PO DR1:POD 18 PPC_PCF GR119 (0x0066) P1_19 GPIO_PO DR1:POD 19 - - - - PWM2P0 PPG7_TO UT0_0 - PPC_PCF GR120 (0x0068) P1_20 GPIO_PO DR1:POD 20 SCK8_0 - SCL8 - PWM2M0 PPG7_TO UT2_0 - SOT8_0 - SDA8 - PWM1P1 PPG8_TO UT0_0 - SCS80_0 - - - PWM1M1 PPG8_TO UT2_0 TX6_0 - - - - PWM2P1 PPG9_TO UT0_0 - SCK9_0 - SCL9 - PWM2M1 PPG9_TO UT2_0 - PPC_PCF GR121 (0x006A) PPC_PCF GR122 (0x006C) PPC_PCF GR123 (0x006E) PPC_PCF GR124 (0x0070) P1_21 P1_22 P1_23 P1_24 GPIO_PO DR1:POD 21 GPIO_PO DR1:POD 22 GPIO_PO DR1:POD 23 GPIO_PO DR1:POD 24 PPC_PCF GR125 (0x0072) P1_25 GPIO_PO DR1:POD 25 SOT9_0 - SDA9 - PWM1P2 PPG10_T OUT0_0 - PPC_PCF GR126 (0x0074) P1_26 GPIO_PO DR1:POD 26 SCS90_0 - - - PWM1M2 PPG10_T OUT2_0 - Document Number: 002-10635 Rev. *H Page 152 of 322 S6J3310/20/30/40 Series Register (Offset) Port PPC_PCF GR127 (0x0076) P1_27 PPC_PCF GR128 (0x0078) P1_28 PPC_PCF GR129 (0x007A) P1_29 PPC_PCF GR130 (0x007C) PPC_PCF GR131 (0x007E) PPC_PCF GR200 (0x0080) PPC_PCF GR201 (0x0082) P1_30 P1_31 P2_00 P2_01 Resource Functional Outputs POF = 0 GPIO_PO DR1:POD 27 POF = 1 POF = 2 POF = 3 POF = 4 POF = 5 POF = 6 POF = 7 SCS91_0 - - - PWM2P2 PPG11_T OUT0_0 - GPIO_PO DR1:POD 28 - - - - PWM2M2 PPG11_T OUT2_0 - GPIO_PO DR1:POD 29 SCK10_0 - SCL10 - PWM1P3 - - SOT10_0 - SDA10 - PWM1M3 PPG12_T OUT0_0 - SCS100_ 0 - - - PWM2P3 PPG12_T OUT2_0 - - - - - PWM2M3 PPG13_T OUT0_0 - SCK11_0 - SCL11 - PWM1P4 PPG13_T OUT2_0 - GPIO_PO DR1:POD 30 GPIO_PO DR1:POD 31 GPIO_PO DR2:POD 00 GPIO_PO DR2:POD 01 PPC_PCF GR202 (0x0084) P2_02 GPIO_PO DR2:POD 02 SOT11_0 - SDA11 - PWM1M4 PPG14_T OUT0_0 - PPC_PCF GR203 (0x0086) P2_03 GPIO_PO DR2:POD 03 SCS110_ 0 - - - PWM2P4 PPG14_T OUT2_0 - SCS111_ 0 - - - PWM2M4 PPG15_T OUT0_0 - - - - - PWM1P5 PPG15_T OUT2_0 - SCK12_0 - SCL12 - PWM1M5 - - SOT12_0 - SDA12 - PWM2P5 - - PPC_PCF GR204 (0x0088) PPC_PCF GR205 (0x008A) PPC_PCF GR206 (0x008C) PPC_PCF GR207 (0x008E) P2_04 P2_05 P2_06 P2_07 GPIO_PO DR2:POD 04 GPIO_PO DR2:POD 05 GPIO_PO DR2:POD 06 GPIO_PO DR2:POD 07 PPC_PCF GR208 (0x0090) P2_08 GPIO_PO DR2:POD 08 SCS120_ 0 - - - PWM2M5 - - PPC_PCF GR209 (0x0092) P2_09 GPIO_PO DR2:POD 09 SCS23_1 - - - DSP0_EN _0 PPG14_T OUT0_1 MCSX0 Document Number: 002-10635 Rev. *H Page 153 of 322 S6J3310/20/30/40 Series Register (Offset) Port PPC_PCF GR210 (0x0094) P2_10 PPC_PCF GR211 (0x0096) P2_11 PPC_PCF GR212 (0x0098) P2_12 PPC_PCF GR213 (0x009A) PPC_PCF GR214 (0x009C) PPC_PCF GR215 (0x009E) PPC_PCF GR216 (0x00A0) P2_13 P2_14 P2_15 P2_16 Resource Functional Outputs POF = 0 GPIO_PO DR2:POD 10 POF = 1 POF = 2 POF = 3 POF = 4 POF = 5 POF = 6 POF = 7 SCS31_1 - - - DSP0_HS YNC_0 - MCSX1 GPIO_PO DR2:POD 11 SCS32_1 - - - DSP0_VS YNC_0 - MDATA0 GPIO_PO DR2:POD 12 SCS33_1 - - - DSP0_CL K_0 - MDATA1 - - - - DSP0_R0 _0 - MDATA2 SCK4_0 - SCL4 - DSP0_R1 _0 - MDATA3 SOT4_0 LCDD0 SDA4 - DSP0_R2 _0 - MDATA4 SCS40_0 LCDD1 - - DSP0_R3 _0 - MDATA5 GPIO_PO DR2:POD 13 GPIO_PO DR2:POD 14 GPIO_PO DR2:POD 15 GPIO_PO DR2:POD 16 PPC_PCF GR217 (0x00A2) P2_17 GPIO_PO DR2:POD 17 SCS41_0 LCDD2 - - DSP0_R4 _0 - MDATA6 PPC_PCF GR218 (0x00A4) P2_18 GPIO_PO DR2:POD 18 SCS42_0 LCDD3 - - DSP0_R5 _0 - MDATA7 SCS43_0 LCDD4 - - DSP0_R6 _0 - MAD0 - TXD1_1 - - - PPG4_TO UT0_1 MAD15 SCK1_1 TXD2_1 - - - PPG4_TO UT2_1 MAD16 SOT1_1 TXD3_1 - - - PPG5_TO UT0_1 MAD17 PPC_PCF GR219 (0x00A6) PPC_PCF GR300 (0x00C0) PPC_PCF GR301 (0x00C2) PPC_PCF GR302 (0x00C4) P2_19 P3_00 P3_01 P3_02 GPIO_PO DR2:POD 19 GPIO_PO DR3:POD 00 GPIO_PO DR3:POD 01 GPIO_PO DR3:POD 02 PPC_PCF GR303 (0x00C6) P3_03 GPIO_PO DR3:POD 03 SCS10_1 TXER_1 - - - PPG5_TO UT2_1 MAD18 PPC_PCF GR304 (0x00C8) P3_04 GPIO_PO DR3:POD 04 SCS11_1 - - - - - MAD19 Document Number: 002-10635 Rev. *H Page 154 of 322 S6J3310/20/30/40 Series Register (Offset) Port PPC_PCF GR305 (0x00CA) P3_05 PPC_PCF GR306 (0x00CC) P3_06 PPC_PCF GR307 (0x00CE) P3_07 PPC_PCF GR308 (0x00D0) PPC_PCF GR309 (0x00D2) PPC_PCF GR310 (0x00D4) PPC_PCF GR311 (0x00D6) P3_08 P3_09 P3_10 P3_11 Resource Functional Outputs POF = 0 GPIO_PO DR3:POD 05 POF = 1 POF = 2 POF = 3 POF = 4 POF = 5 POF = 6 POF = 7 SCS12_1 - - - - - MAD20 GPIO_PO DR3:POD 06 SCS13_1 MDIO_1 - - - SOT4_1 MAD21 GPIO_PO DR3:POD 07 - - - - - SCS42_1 MDQM1 - SGA0_1 PPG6_TO UT0_1 OCU0_O TD0_1 - - - SCK8_1 SGO0_1 PPG6_TO UT2_1 OCU0_O TD1_1 TOT0_1 - - SOT8_1 SGA1_1 PPG7_TO UT0_1 OCU1_O TD0_1 TRACE0_ 1 - TX0_1 SCS80_1 SGO1_1 PPG7_TO UT2_1 OCU1_O TD1_1 TOT1_1 TRACE1_ 1 - GPIO_PO DR3:POD 08 GPIO_PO DR3:POD 09 GPIO_PO DR3:POD 10 GPIO_PO DR3:POD 11 PPC_PCF GR312 (0x00D8) P3_12 GPIO_PO DR3:POD 12 - SGA2_1 PPG8_TO UT0_1 OCU2_O TD0_1 - TRACE2_ 1 TX1_1 PPC_PCF GR313 (0x00DA) P3_13 GPIO_PO DR3:POD 13 SCK10_1 SGO2_1 PPG8_TO UT2_1 OCU2_O TD1_1 TOT16_1 TRACE3_ 1 - SOT10_1 SGA3_1 PPG9_TO UT0_1 OCU8_O TD0_1 - TRACE_ CTL_1 - SCS100_ 1 SGO3_1 PPG9_TO UT2_1 OCU8_O TD1_1 TOT17_1 TRACE_ CLK_1 TX2_1 - SGA4_1 PPG10_T OUT0_1 OCU9_O TD0_1 - - - - SGO4_1 PPG10_T OUT2_1 OCU9_O TD1_1 TOT48_1 - TX3_1 PPC_PCF GR314 (0x00DC) PPC_PCF GR315 (0x00DE) PPC_PCF GR316 (0x00E0) PPC_PCF GR317 (0x00E2) P3_14 P3_15 P3_16 P3_17 GPIO_PO DR3:POD 14 GPIO_PO DR3:POD 15 GPIO_PO DR3:POD 16 GPIO_PO DR3:POD 17 PPC_PCF GR318 (0x00E4) P3_18 GPIO_PO DR3:POD 18 - - PPG11_T OUT0_1 OCU10_ OTD0_1 - - - PPC_PCF GR319 (0x00E6) P3_19 GPIO_PO DR3:POD 19 SCK9_1 - PPG11_T OUT2_1 OCU10_ OTD1_1 - - - Document Number: 002-10635 Rev. *H Page 155 of 322 S6J3310/20/30/40 Series Register (Offset) Port PPC_PCF GR320 (0x00E8) P3_20 PPC_PCF GR321 (0x00EA) P3_21 PPC_PCF GR322 (0x00EC) P3_22 PPC_PCF GR323 (0x00EE) PPC_PCF GR324 (0x00F0) PPC_PCF GR325 (0x00F2) PPC_PCF GR326 (0x00F4) P3_23 P3_24 P3_25 P3_26 Resource Functional Outputs POF = 0 GPIO_PO DR3:POD 20 POF = 1 POF = 2 POF = 3 POF = 4 POF = 5 POF = 6 POF = 7 SOT9_1 - - - - - TX5_1 GPIO_PO DR3:POD 21 SCS90_1 - - - TOT49_1 - - GPIO_PO DR3:POD 22 SCS91_1 - - - - - - - - - - SCS120_ 1 - TX6_1 SOT2_1 - - - - PPG12_T OUT0_1 MDATA8 SCS20_1 - - - I2S0_SD_ 1 PPG12_T OUT2_1 MDATA9 SCS21_1 - - - I2S0_WS _1 PPG13_T OUT0_1 MDATA10 GPIO_PO DR3:POD 23 GPIO_PO DR3:POD 24 GPIO_PO DR3:POD 25 GPIO_PO DR3:POD 26 PPC_PCF GR327 (0x00F6) P3_27 GPIO_PO DR3:POD 27 SCS22_1 - - - I2S0_SC K_1 PPG13_T OUT2_1 MDATA11 PPC_PCF GR328 (0x00F8) P3_28 GPIO_PO DR3:POD 28 - - - - - PPG14_T OUT2_1 MDATA12 SCK3_1 - - - - PPG15_T OUT0_1 MDATA13 SOT3_1 - - - - PPG15_T OUT2_1 MDATA14 SCS30_1 - - - - - MDATA15 - - - - - - - PPC_PCF GR329 (0x00FA) PPC_PCF GR330 (0x00FC) PPC_PCF GR331 (0x00FE) PPC_PCF GR400 (0x0100) P3_29 P3_30 P3_31 P4_00 GPIO_PO DR3:POD 29 GPIO_PO DR3:POD 30 GPIO_PO DR3:POD 31 GPIO_PO DR4:POD 00 PPC_PCF GR401 (0x0102) P4_01 GPIO_PO DR4:POD 01 - - - - TX0_2 - - PPC_PCF GR402 (0x0104) P4_02 GPIO_PO DR4:POD 02 - - - - - - - Document Number: 002-10635 Rev. *H Page 156 of 322 S6J3310/20/30/40 Series Register (Offset) Port PPC_PCF GR403 (0x0106) P4_03 PPC_PCF GR404 (0x0108) P4_04 PPC_PCF GR405 (0x010A) P4_05 PPC_PCF GR406 (0x010C) PPC_PCF GR407 (0x010E) PPC_PCF GR408 (0x0110) PPC_PCF GR409 (0x0112) P4_06 P4_07 P4_08 P4_09 Resource Functional Outputs POF = 0 GPIO_PO DR4:POD 03 POF = 1 POF = 2 POF = 3 POF = 4 POF = 5 POF = 6 POF = 7 - - SCS170_ 1 - - - - GPIO_PO DR4:POD 04 - TXEN_1 SCK17_1 - TX3_2 - - GPIO_PO DR4:POD 05 - TXD0_1 SOT17_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GPIO_PO DR4:POD 06 GPIO_PO DR4:POD 07 GPIO_PO DR4:POD 08 GPIO_PO DR4:POD 09 PPC_PCF GR410 (0x0114) P4_10 GPIO_PO DR4:POD 10 - - - - - - - PPC_PCF GR411 (0x0116) P4_11 GPIO_PO DR4:POD 11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PPC_PCF GR412 (0x0118) PPC_PCF GR413 (0x011A) PPC_PCF GR414 (0x011C) PPC_PCF GR415 (0x011E) P4_12 P4_13 P4_14 P4_15 GPIO_PO DR4:POD 12 GPIO_PO DR4:POD 13 GPIO_PO DR4:POD 14 GPIO_PO DR4:POD 15 PPC_PCF GR416 (0x0120) P4_16 GPIO_PO DR4:POD 16 - - - - - - - PPC_PCF GR417 (0x0122) P4_17 GPIO_PO DR4:POD 17 - - - - SOT12_1 - - Document Number: 002-10635 Rev. *H Page 157 of 322 S6J3310/20/30/40 Series Register (Offset) Port PPC_PCF GR418 (0x0124) P4_18 PPC_PCF GR419 (0x0126) P4_19 PPC_PCF GR420 (0x0128) P4_20 PPC_PCF GR421 (0x012A) PPC_PCF GR422 (0x012C) PPC_PCF GR423 (0x012E) PPC_PCF GR424 (0x0130) P4_21 P4_22 P4_23 P4_24 Resource Functional Outputs POF = 0 GPIO_PO DR4:POD 18 POF = 1 POF = 2 POF = 3 POF = 4 POF = 5 POF = 6 POF = 7 - - - - - - - GPIO_PO DR4:POD 19 - - - - - - - GPIO_PO DR4:POD 20 - - - - SOT16_1 - - - - - - SCK16_1 - - - - - - SCS161_ 1 - - - - - - SCS160_ 1 - - - - - - - - - GPIO_PO DR4:POD 21 GPIO_PO DR4:POD 22 GPIO_PO DR4:POD 23 GPIO_PO DR4:POD 24 PPC_PCF GR425 (0x0132) P4_25 GPIO_PO DR4:POD 25 - - - - - - - PPC_PCF GR426 (0x0134) P4_26 GPIO_PO DR4:POD 26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SCK2_1 - - - - - - PPC_PCF GR427 (0x0136) PPC_PCF GR428 (0x0138) PPC_PCF GR429 (0x013A) PPC_PCF GR430 (0x013C) PPC_PCF GR431 (0x013E) P4_27 P4_28 P4_29 P4_30 P4_31 GPIO_PO DR4:POD 27 GPIO_PO DR4:POD 28 GPIO_PO DR4:POD 29 GPIO_PO DR4:POD 30 GPIO_PO DR4:POD 31 Document Number: 002-10635 Rev. *H Page 158 of 322 S6J3310/20/30/40 Series Notes: - The hyphen indicates that setting is prohibited. If setting the port will be operated as input independent on the register value of the GPIO_DDR. - The register for P0_20 for POF exists though the port only supports input not supports output. The configuration of POF = 0 for the port does not affect anything. Document Number: 002-10635 Rev. *H Page 159 of 322 S6J3310/20/30/40 Series 8. Precautions and Handling Devices 8.1 Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 8.1.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, and so on.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Document Number: 002-10635 Rev. *H Page 160 of 322 S6J3310/20/30/40 Series 8.1.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70 % relative humidity, and at temperatures between 5 C and 30 C. When you open Dry Package that recommends humidity 40 % to 70 % relative humidity. (3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125 C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40 % and 70 %. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 M). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. Document Number: 002-10635 Rev. *H Page 161 of 322 S6J3310/20/30/40 Series (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 8.1.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-10635 Rev. *H Page 162 of 322 S6J3310/20/30/40 Series 8.2 Handling Devices For Latch-Up Prevention The latch-up phenomenon may occur on a CMOS IC in the following cases: the voltage applied to an input or output pin is higher than VCC or lower than VSS; or the voltage applied between a VCC pin and a VSS pin exceeds the rating. A latch-up causes a rapid increase in the power supply current, possibly resulting in thermal damage to an element. When using the device, take sufficient care not to exceed the maximum rating. Also be careful that analog power supplies (AVCC5,AVRH5) and analog inputs do not exceed the digital power supply (VCC) at the analog system power-on and power-off times. The power-on sequence is as follows. Simultaneously turn on the digital supply voltage (VCC) and analog supply voltages (AVCC5,AVRH5), or turn on the digital supply voltage (VCC) and then the analog supply voltages (AVCC5,AVRH5). About Handling Unused Pins Leaving unused input pins open may cause permanent damage from a malfunction or latch-up. Take measures for unused pins, such as pulling up or pulling down the voltage with resistors of 2 kilo ohms or higher. If there are any unused input/output pins, set them to the output state and then open them, or set them to the input state and handle them in the same way as input pins. About Power Supply Pins If the device has multiple VCC and VSS pins, the device is designed in such a way that the pins that should be at the same potential are connected to each other inside the device to prevent malfunctions such as latch-up. However, to reduce unwanted emissions, prevent malfunctions of strobe signals caused by an increase of the ground level, and observe standards on total output current, be sure to connect all the VCC and VSS pins to the power source and ground externally. Also handle all the VSS power supply pins in this way as shown in the following diagram. If there are multiple VCC or VSS systems, the device does not operate normally even within the guaranteed operating range. Figure 8-1 Pin Assignment In addition, consider connecting with low impedance from the power supply source to the VCC and VSS of this device. We recommend connecting a ceramic capacitor as a bypass capacitor between VCC and VSS, near this device. About the Crystal Oscillation Circuit Noise entering the X0 or X1 pin may cause a malfunction. Design the printed circuit board in such a way that the X0 and X1 pins, the crystal oscillator (or ceramic resonator), and a bypass capacitor to ground are located very close to the device. We recommend that the printed circuit board artwork have the X0 and X1 pins enclosed by ground. Document Number: 002-10635 Rev. *H Page 163 of 322 S6J3310/20/30/40 Series About the Mode Pin (MODE) Use mode pin MODE by directly connecting it to a VCC or VSS pin. To prevent noise from causing the device to accidentally enter test mode, reduce the pattern length between each mode pin and a VCC or VSS pin on the printed circuit board, and connect them with low impedance. About the Power-on Time To prevent the internal built-in voltage step-down circuit from malfunctioning, secure a voltage rising time of 50 s (between 0.2 V and 2.7 V) or longer at the power-on time. Point to Note during PLL Clock Operation While a PLL clock is selected, if the oscillator breaks off or input stops, the PLL clock may continue operating with the free running frequency of the internal self-oscillator circuit. This operation is outside of the guaranteed range. Power Supply Pin Processing of an A/D Converter Even when no A/D converter is used, establish a connection such that AVCC5 = AVRH5 = VCC5 and AVSS/AVRL5 = VSS. Points to Note About Using External Clocks External clocks are not supported. External direct clock input cannot be used. Power-on Sequence of the Power Supply Analog Inputs of an A/D Converter Be sure to turn on the digital power supply (VCC) before the application of the power supplies (AVCC, AVRH, and AVRL) and analog inputs (AN0 to AN63) of an A/D converter. At the power-off time, turn off the power supplies and analog inputs of the A/D converter, and then turn off the digital power supply (VCC). Perform these power-on and power-off operations without AVRH exceeding AVCC. Even when using a pin shared with an analog input as an input port, do not allow the input voltage to exceed AVCC. (Turning on or off the analog supply voltage and digital supply voltage simultaneously is not a problem.) Method to Switch Off VCC12 during Power-Off Sequence During power-off sequence, it is necessary to switch off VCC12 by driving PSC1 pin low by entering PSS mode (power domain 2 off). If VCC12 needs to be switched off by other means, RSTX needs to be asserted before switching off VCC12 to inactivate the operation of VCC12 supplied domain below the operation assurance range. About C Pin Processing This device has a built-in voltage step-down circuit. Be sure to connect a capacitor to the C pin for internal stabilization of the device. For the standard values, see "Recommended operating conditions" in the latest data sheet. Precautions on Designing a Mounting Substrate Measures against heat generation from the package must be taken for the mounting substrate to observe the absolute maximum rating (operating temperature). Design a mounting substrate with 4 or more layers. Connect the back of the package stage and the substrate pad with solder paste. Arrange thermal via holes on the substrate pad. Notes on Writing to a Register Containing a Status Flag In writing to a register containing a status flag (particularly an interrupt request flag, etc.) to control a function, it is important to take care not to accidentally clear the status flag. Therefore, before the write operation, configure the status bit such that the flag is not cleared, and then set the control bit to the desired value. Especially for control bits configured as a set of multiple bits, bit instructions cannot be used (bit instructions have only 1-bit access). In such cases, byte, half-word, or word access is used to write to the control bits and a status flag simultaneously. However, at this time, be careful not to accidentally clear bits other than the intended ones (the status flag bit in this case). Note: Bit instructions take this point into account for registers that support bit-band units, so it does not need to be a concern. You need to take care when using bit instructions for registers that do not support bit-band units. Document Number: 002-10635 Rev. *H Page 164 of 322 S6J3310/20/30/40 Series 9. Electric Characteristics 9.1 Electrical Characteristics This chapter contains target values and information. Target values and information are subjects to change without notice. 9.1.1 Absolute Maximum Rating Parameter Power supply voltage*1, *2 Analog supply voltage*1, *2 Analog reference voltage*1 Input voltage*1 Analog pin input voltage*1 Output voltage*1 Maximum clamp current Total maximum clamp current Total maximum clamp current Total maximum clamp current "L"-level maximum output current*3 "L"-level average output current*4 "L"-level total output current*5 Document Number: 002-10635 Rev. *H Symbol Rating Unit Remarks Min Max VCC5 VCC53 VCC3 DVCC VCC12 AVCC5 AVcc3_DAC AVRH VI1 VI2 VI3 VIE VIA VO1 VO2 VO3 VO4 |ICLAMP| |ICLAMP | |ICLAMP | |ICLAMP | IOL1 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 - VSS+6.0 VSS+6.0 VSS+4.0 VSS+6.0 VSS+1.8 VSS+6.0 VSS+4.0 VSS+6.0 VCC5+0.3 DVCC+0.3 VCC3+0.3 VCC53+0.3 VCC5+0.3 VCC5+0.3 DVCC+0.3 VCC3+0.3 VCC53+0.3 4 20 90 65 3.5 V V V V V V V V V V V V V V V V V mA mA mA mA mA IOL2 - 7 mA IOL3 IOL4 IOL6 IOL7 IOL8 IOL9 IOLAV1 - 10 16 40 8 11 21 1 mA mA mA mA mA mA mA IOLAV2 - 2 mA IOLAV3 - 5 mA When setting is 5 mA*9 IOLAV4 - 10 mA When setting is 10 mA*9 IOLAV6 IOLAV7 IOLAV8 IOLAV9 IOL1 IOL2 - 30 3 6 15 50 250 mA mA mA mA mA mA When setting is 30 mA*7 When setting is 3 mA *10 When setting is 6 mA *11 When setting is 15 mA *12 VCC53 VCC5 VCC3 VCC5 VCC12 AVCC5 AVCC5 VCC5 for DAC AVRH AVCC5 5 V pins not shared SMC 5 V pins shared SMC 3 V pins 5 V/3 V pins 5 V pins not shared SMC 5 V pins shared SMC 3 V pins 5 V/3 V pins *13, *A *13, *A *B *C When setting is 1 mA*6, *7, *8 When setting is 2 mA*6, *7, *8, *9 When setting is 5 mA*9 When setting is 10 mA*9 When setting is 30 mA*7 When setting is 3 mA *10 When setting is 6 mA *11 When setting is 15 mA *12 When setting is 1 mA*6, *7, *8 When setting is 2 mA*6, *7, *8, *9 *6, *10 *7 Page 165 of 322 S6J3310/20/30/40 Series Parameter "L"-level total output current*5 "H"-level maximum output current*3 "H"-level average output current*4 "H"-level total output current*5 Symbol Rating Unit Max IOL3 - 50 mA *8 IOL4 - 50 mA *9, *11 IOH1 - -3.5 mA When setting is 1 mA*6, *7, *8 IOH2 - -7 mA IOH3 - -10 mA When setting is 5 mA*9 IOH4 - -16 mA When setting is 10 mA*9 IOH6 - -40 mA When setting is 30 mA*7 IOH8 - -11 mA When setting is 6 mA *11 IOH9 - -21 mA When setting is 15 mA *12 IOHAV1 - -1 mA When setting is 1 mA*6, *7, *8 IOHAV2 - -2 mA IOHAV3 - -5 mA When setting is 5 mA*9 IOHAV4 - -10 mA When setting is 10 mA*9 IOHAV6 - -30 mA When setting is 30 mA*7 IOHAV8 - -6 mA When setting is 6 mA *11 IOHAV9 - -15 mA When setting is 15 mA *12 IOH1 - -50 mA *6, *10 IOH2 - -250 mA *7 IOH3 - -50 mA *8 IOH4 -40 -40 -50 2000 1100 +105 +125 mA mW mW oC oC *9 *11 Theta j-a1 - 17 oC/W TEQFP 208 Theta j-a2 - 19 oC/W TEQFP 176 Power consumption PD Operating temperature TA System Thermal Resistance Package Thermal Resistance Storage temperature Document Number: 002-10635 Rev. *H Remarks Min Theta j-a3 - 20 oC/W Theta j-a4 - 22 oC/W Psi j-t1 Psi j-t2 Psi j-t3 Psi j-t4 Tstg -55 0.6 1.0 2.0 2.0 +150 oC/W oC/W oC/W oC/W o When setting is 2 mA*6, *7, *8, *9 When setting is 2 mA*6, *7, *8, *9 -40 oC TA 105 oC -40 oC TA 125 oC PD 2000 mW PD 1100 mW The minimum value depends on the system specification of heat radiation. The described value is estimated under the condition which is specified at "9.1.2 Recommended Operating ". TEQFP 144 (0.5 mm Pitch) TEQFP 144 (0.4 mm Pitch) TEQFP208 TEQFP176 TEQFP144 (0.5 mm Pitch) TEQFP144 (0.4 mm Pitch) C Page 166 of 322 S6J3310/20/30/40 Series *1 These parameters are based on the condition that VSS = AVSS = DVSS = 0.0 V. *2 Take care that DVCC, AVCC5 do not exceed VCC5 at, for example, the power-on time. *3 The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *4 The average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 10 ms period. The average value is the operation current x the operation ratio. *5 The total output current is defined as the maximum current value flowing through all of corresponding pins. *6 Output of 5 V pins. *7 Output of SMC pins. *8 Output of 5 V/3 V pins. *9 Output of 3 V pins. *10 Output of I2C. *11 Output of Media LB pins *12 Output of DSP0_CLK pins *13 VI or VO should never exceed the specified ratings. However, if the maximum current to/from an input is limited by a suitable external resistor, the ICLAMP rating supersedes the VI rating. *A Relevant pins: All general-purpose ports and analog input pins * * * * * * * * * Corresponding pins: all general-purpose ports Use within recommended operating conditions. Use at DC voltage (current). The +B signal should always be applied by connecting a limiting resistor between the +B signal and the microcontroller. The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the +B signal is input. Note that when the microcontroller drive current is low, such as in the low power consumption modes, the + B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other devices. Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied through the pin, the microcontroller may operate incompletely. Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply voltage. Do not leave + B input pins open. Example of a recommended circuit WARNING: - Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-10635 Rev. *H Page 167 of 322 S6J3310/20/30/40 Series *B Relevant pins: All general-purpose ports and analog input pins * Corresponding pins: all general-purpose ports * Use within recommended operating conditions. * Use at DC voltage (current). MCU is operational, IO is driving LOW level (i.e. NMOS transistor active), there are negative biased pulses (-B signal) applied to active IO according to following specification (must not be exceeded). Pulse condition specification: U_pulse = max -40 V T_pulse = max 1 ms #_pulse = max 5000 Current and Power Dissipation U_peak = -40 V R_serial = 22 k => I_pin = 1.8 mA U_out = -0.1 V (current drawn mainly over NMOS transistor) => I_total = 50 pins x 1.8 mA = 90 mA => P_total = 50 pins x (1.8 mA x 0.1 V) = 9 mW I_total and P_total are within allowed limits of extended specification. * The - B signal should always be applied by connecting a limiting resistor between the - B signal and the microcontroller. * The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the - B signal is input. * Do not leave - B input pins open. Example of a recommended circuit WARNING: - Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-10635 Rev. *H Page 168 of 322 S6J3310/20/30/40 Series *C Relevant pins: All general-purpose ports and analog input pins * Corresponding pins: all general-purpose ports * Use within non operation conditions. The device is not supplied (VCC5: off, VCC12: off, VCC53: off). * Use at DC voltage (current). MCU is non-operational, PCB is in reverse polarity condition (supply of the MCU is off), negative biased voltage level (-B signal) is applied to inactive IO according to following specification (must not be exceeded). Reverse polarity condition specification: U_reverse = max -28 V T_reverse = max 4 h Current and Power Dissipation U_reverse = -28 V R_serial = 22 k => I_pin = 1.3 mA U_out = -0.7 V (current drawn mainly over clamping diodes) => I_total = 50 pins x 1.3 mA = 65 mA => P_total = 50 pins x (1.3 mA x 0.7 V) = 46 mW I_total and P_total are within allowed limits of extended specification. * The - B signal should always be applied by connecting a limiting resistor between the - B signal and the microcontroller. * The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the - B signal is input. * Do not leave - B input pins open. Example of a recommended circuit WARNING: - Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-10635 Rev. *H Page 169 of 322 S6J3310/20/30/40 Series 9.1.2 Recommended Operating Condition Parameter Symbol VCC5 VCC53 Supply voltage Recommended operation assurance range*4 DVCC VCC5 VCC53 DVCC Rating Min Max 4.5 5.5 Unit V 3 3.6 4.5 5.5 V V 3 3.6 4.5 5.5 3.0 3.6 4.5 5.5 V AVCC5 AVCC5 3 3.6 VCC3 VCC3 3 3.6 V VCC12 1.09 1.21 V AVCC3_DAC 3 3.6 V 3.5 5.5 2.7 3.6 2.7 5.5 2.7 3.6 3.5 5.5 2.7 3.6 3.5 5.5 2.7 3.6 VCC12 AVCC3_DAC Supply voltage Operation assurance range Pin Name V VCC5 VCC5 VCC53 VCC53 DVCC DVCC AVCC5 AVCC5 VCC3 VCC3 2.7 3.6 V VCC12 1.09 1.21 V AVCC3_DAC 2.7 3.6 V VCC12 AVCC3_DAC V V V V Remarks *1 *2 *3 *1 *1 *3 *2 *1 *2 *3 *1 *2 *3 *1 *1 *3 *2 *1 *2 *3 *5 -40 105 oC Tolerance of up to 40 % PD 2000 mW TA -40 *1:For S6J33xxxSx or S6J33xxxUx or S6J33xxxTx or S6J33xxxVx option. 125 oC PD 1100 mW Smoothing capacitor* Operating temperature CS C TA - 4.7 F *2:For S6J33xxxBx or S6J33xxxDx or S6J33xxxFx or S6J33xxxHx option. *3:For S6J33xxxAx or S6J33xxxCx or S6J33xxxEx or S6J33xxxGx option. *4:Corresponding functions for Low voltage monitoring of supply voltage are described in CHAPTER 13 Low Voltage Detection of S6J3300 Series Hardware Manual. The detection/release threshold values of following LVD channels are potentially below supply range defined in 9.1.2 Recommended operating condition (refer to "9.1.4.11 Low Voltage Detection (External Voltage)" and "9.1.4.12 Low Voltage Detection (Internal Voltage)" for detection/release threshold values for these LVD channels): LVDL0 LVDL1 LVDL2 LVDH0 LVDH1 LVDH2 Document Number: 002-10635 Rev. *H Page 170 of 322 S6J3310/20/30/40 Series When it is used outside recommended range (this is the range of guaranteed operation), contact your sales representative. The initial detection voltage of the external low voltage detection is 2.6 V 3.5 %*2 *3 (LVDH1/LVDH2) or 0.8 V 3.5 % (LVDL2). This LVD setting and internal LVD (LVDL0/LVDL1) cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. - Please use these LVD channels with your own risk - Please monitor the external power supplies on the PCB if needed *5:When the voltage of Vcc12 is in the out of range against supply voltage operation assurance, the operation of circuit which Vcc12 used as the power source becomes unstable status. In that case, the value of each registers including RESCAUSEUR Register cannot be guaranteed, so these flags should don't care by software processing *: For the connections of smoothing capacitor CS, see the following diagram. C Pin Connection Diagram C CS VSS DVSS AVSS Notes: - The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the electrical characteristics of the device are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact sales representatives beforehand. - Required power supply sequence is the following: {VCC5 -> AVCC5} -> [DVCC or VCC53 or VCC3 or AVCC3_DAC or VCC12] Note that power supplies inside "[ ]" can be turned on in arbitrary order and "{ }" can be turned on in shown sequence or simultaneously. Document Number: 002-10635 Rev. *H Page 171 of 322 S6J3310/20/30/40 Series Notes: - TA: Ambient temperature (JEDEC) - - TC: Case temperature (JEDEC), the maximum measured temperature of package case top. - The following condition should be satisfied in order to facilitate heat dissipation. Both rating of TA and TC should simultaneously be satisfied as maximum operation temperature. 1. Four or more layers PCB should be used. 2. The area of PCB should be 114.3 mm x 76.2 mm or more, and the thickness should be 1.6 mm or more. (JEDEC standard) 3. One layer of middle layers at least should be used for dedicated layer to radiate heat with residual copper rate 90 % or more. The layer can be used for system ground. 4. 35 % or more of the die stage area which is exposed at back surface of package should be soldered to a part of 1st layer. 5. The part of 1st layer should be connected to the dedicated heat radiation layer with more than 10 thermal via holes. Example thermal via holes on PCB - - - The above figure is a schematic diagram showing PCB in section. Thermal via holes should closely be placed and aligned with lands. It is recommended to connect the land pattern to the VSS-ground level (GND plan of inner layer bellow the MCU) as thermal heat sink. Document Number: 002-10635 Rev. *H Page 172 of 322 S6J3310/20/30/40 Series 9.1.3 DC Characteristics (TA: Recommended operating conditions, VCC5,VCC53 = 5.0 V 10 %, VCC3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol VIH1 VIH2 VIH3 VIH4 VIH5 VIH6 "H" level Input voltage VIH7 VIH8 VIH9 VIH10 VIH11 VIH12 Pin Name Conditions P0_00 to P0_20, P2_09 to P2_19, P3_00 to P3_07, P3_24 to P3_31, P4_00 to P4_07 P1_03 to P1_16, P3_08 to P3_23, P4_08 to P4_23 P1_09, P1_10, P1_15, P1_16 P1_17 to P1_31, P2_00 to P2_08, P4_24 to P4_31 RSTX NMIX MD JTAG_NTRST JTAG_TCK JTAG_TDI JTAG_TMS P0_21 to P0_31, P1_00 to P1_02 CMOS hysteresis input level is selected Automotive input level is selected VIH13 P0_21 to P0_31 VIH14 P1_00 to P1_02 Document Number: 002-10635 Rev. *H Value Unit Min Typ Max 0.7xVCC53 - VCC53+0.3 V 0.8xVCC53 - VCC53+0.3 V 2.0 - VCC53+0.3 V 0.7xVCC5 - VCC5+0.3 V 0.8xVCC5 - VCC5+0.3 V 2.0 - VCC5+0.3 V 0.7xDVCC - DVCC+0.3 V 0.8xDVCC - DVCC+0.3 V - 0.7xVCC5 - VCC5+0.3 V - 0.7xVCC5 - VCC5+0.3 V - 2.7 - VCC5+0.3 V 0.7xVCC3 - VCC3+0.3 V 2.0 - VCC3+0.3 V 1.7 - VCC3+0.3 V TTL input level is selected CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected CMOS hysteresis input level is selected Automotive input level is selected CMOS hysteresis input level is selected TTL input level is selected - Remarks MediaLB Page 173 of 322 S6J3310/20/30/40 Series (TA: Recommended operating conditions, VCC5,VCC53 = 5.0 V 10%, VCC3 = 3.3 V 0.3 V, VSS = DVSS = AVSS =0.0 V) Parameter Symbol VIL1 VIL2 VIL3 VIL4 VIL5 VIL6 "L" level Input voltage VIL7 VIL8 VIL9 VIL10 VIL11 VIL12 Pin Name Conditions P0_00 to P0_20, P2_09 to P2_19, P3_00 to P3_07, P3_24 to P3_31, P4_00 to P4_07 P1_03 to P1_16, P3_08 to P3_23, P4_08 to P4_23 P1_09, P1_10, P1_15, P1_16 P1_17 to P1_31, P2_00 to P2_08, P4_24 to P4_31 RSTX NMIX MD JTAG_NTRST JTAG_TCK JTAG_TDI JTAG_TMS P0_21 to P0_31, P1_00 to P1_02 CMOS hysteresis input level is selected Automotive input level is selected VIL13 P0_21 to P0_31 VIL14 P1_00 to P1_02 Document Number: 002-10635 Rev. *H Value Typ Vss-0.3 - Vss-0.3 - Vss-0.3 - 0.8 V Vss-0.3 - 0.3xVCC5 V Vss-0.3 - 0.5xVCC5 V Vss-0.3 - 0.8 V Vss-0.3 - Vss-0.3 - - Vss-0.3 - 0.3xVCC5 V - Vss-0.3 - 0.3xVCC5 V - Vss-0.3 - 0.8 V CMOS hysteresis input level is selected Vss-0.3 - 0.3xVCC3 V Vss-0.3 - 0.8 V Vss-0.3 - 0.7 V TTL input level is selected CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected - Max Unit Min 0.3xVCC5 3 0.5xVCC5 3 0.3xDVC C 0.5xDVC C Remarks V V V V MediaLB Page 174 of 322 S6J3310/20/30/40 Series Parameter Symbol VHYS1 VHYS2 VHYS3 VHYS4 VHYS5 VHYS6 VHYS7 Hysteresis voltage VHYS8 VHYS9 Pin Name Conditions P0_00 to P0_20, P2_09 to P2_19, P3_00 to P3_07, P3_24 to P3_31, P4_00 to P4_07 P1_03 to P1_16, P3_08 to P3_23, P4_08 to P4_23 P1_09, P1_10, P1_15, P1_16 P1_17 to P1_31, P2_00 to P2_08, P4_24 to P4_31 RSTX NMIX CMOS hysteresis input level is selected Automotive input level is selected VHYS10 VHYS11 VHYS12 MD JTAG_NTRST JTAG_TCK JTAG_TDI JTAG_TMS P0_21 to P0_31, P1_00 to P1_02 VHYS13 P0_21 to P0_31 VHYS14 P1_00 to P1_02 Document Number: 002-10635 Rev. *H TTL input level is selected CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected CMOS hysteresis input level is selected Automotive input level is selected Value Min - Typ 0.05xV CC53 0.03xV CC53 0.035 0.05xV CC5 0.03xV CC5 0.035 0.05xD VCC 0.03xD VCC 0.05xV CC5 0.05xV CC5 Max Unit - V - V - V - V - V - V - V - V - V - V - - - - - - 0.035 - V CMOS hysteresis input level is selected - 0.05xV CC3 - V - 0.035 - V - 0.080 - V TTL input level is selected - Remarks MediaLB Page 175 of 322 S6J3310/20/30/40 Series (TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V 10 %, VCC3 = 3.3 V 0.3 V, VSS = DVSS = AVSS =0.0 V) Parameter Symbol Pin Name VOH1 VOH2 P0_00 to P0_19, P2_09 to P2_11, P2_13 to P2_19, P3_00 to P3_07, P3_24 to P3_31, P4_00 to P4_07 VOH3 VOH4 VOH5 P1_03 to P1_16, P3_08 to P3_23, P4_08 to P4_23 VOH6 "H" level output voltage VOH7 PSC_1 VOH8 JTAG_TDO VOH10 VOH11 VOH12 VOH13 P1_17 to P1_31, P2_00 to P2_08, P4_24 to P4_31 VCC53 = 4.5 V IOH = -1.0 mA VCC53 = 3.0 V IOH=-0.5 mA VCC53 = 4.5 V IOH = -2.0 mA VCC53 = 3.0 V IOH = -1.0 mA VCC53 = 4.5 V IOH = -5.0 mA VCC53 = 3.0 V IOH = -2.0 mA VCC5 = 4.5 V IOH = -1.0 mA VCC5 = 4.5 V IOH = -2.0 mA VCC5 = 4.5 V IOH = -5.0 mA VCC5 = 4.5 V IOH = -2.0 mA VCC5 = 4.5 V IOH = -5.0 mA DVCC = 4.5 V IOH = -1.0 mA DVCC = 4.5 V IOH = -2.0 mA DVCC = 4.5 V IOH = -5.0 mA DVCC = 4.5 V IOH = -30.0 mA DVCC = 4.5 V IOH = -40.0 mA VOH14 VOH15 VOH16 Conditions P0_21 to P0_31, P1_00 to P1_02 VOH17 VOH18 Document Number: 002-10635 Rev. *H VCC3 = 3.0 V IOH = -2.0 mA VCC3 = 3.0 V IOH = -5.0 mA VCC3 = 3.0 V IOH = -6.0 mA VCC3 = 3.0 V IOH = -15.0 mA Value Unit Remarks VCC53 V ODR[1:0]= 2b00 - VCC53 V ODR[1:0]= 2b01 VCC53 - 0.5 - VCC53 V ODR[1:0]= 2b10 VCC5 - 0.5 - VCC5 V VCC5 - 0.5 - VCC5 V VCC5 - 0.5 - VCC5 V VCC5 - 0.5 - VCC5 V VCC5 - 0.5 - VCC5 V DVCC - 0.5 - DVCC V DVCC - 0.5 - DVCC V DVCC - 0.5 - DVCC V DVCC - 0.5 - DVCC V SMC DVCC - 0.5 - DVCC V SMC Tj = -40 oC VCC3 - 0.5 - VCC3 V VCC3 - 0.5 - VCC3 V VCC3 - 0.5 - VCC3 V VCC3 - 0. 5 - VCC3 V Min Typ Max VCC53 - 0.5 - VCC53 - 0.5 Page 176 of 322 S6J3310/20/30/40 Series (TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V 10%, VCC3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name VCC53 = 4.5 V IOH = -1.0 mA VOH19 VOH20 VOH21 "H" level output voltage VOH22 Conditions P2_12 VOH23 VOH24 VOH26 Document Number: 002-10635 Rev. *H VCC53 = 3.0 V IOH = -0.5 mA VCC53 = 4.5 V IOH = -2.0 mA VCC53 = 3.0 V IOH = -1.0 mA VCC53 = 4.5 V IOH = -5.0 mA VCC53 = 3.0 V IOH = -2.0 mA VCC53 = 3.0 V IOH = -15.0 mA Value Unit Remarks VCC53 V ODR[1:0] = 2b00 - VCC53 V ODR[1:0] = 2b01 VCC53 - 0.5 - VCC53 V ODR[1:0] = 2b10 VCC53 - 0.5 - Vcc53 V ODR[1:0] = 2b11 Min Typ Max VCC53 - 0.5 - VCC53 - 0.5 Page 177 of 322 S6J3310/20/30/40 Series (TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V 10 %, VCC3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name VOL1 VOL2 P0_00 to P0_19, P2_09 to P2_11, P2_13 to P2_19, P3_00 to P3_07, P3_24 to P3_31, P4_00 to P4_07 VOL3 VOL4 VOL5 P1_03 to P1_16, P3_08 to P3_23, P4_08 to P4_23 VOL6 "L" level output voltage VOL7 PSC_1 VOL8 JTAG_TDO VOL9 P1_09, P1_10, P1_15, P1_16 VOL10 VOL11 VOL12 P1_17 to P1_31, P2_00 to P2_08, P4_24 to P4_31 VOL13 VOL14 VOL15 VOL16 P0_21 to P0_31, P1_00 to P1_02 VOL17 VOL18 Document Number: 002-10635 Rev. *H Conditions VCC53 = 4.5 V IOL = 1.0 mA VCC53 = 3.0 V IOL = 0.5 mA VCC53 = 4.5 V IOL = 2.0 mA VCC53 = 3.0 V IOL = 1.0 mA VCC53 = 4.5 V IOL = 5.0 mA VCC53 = 3.0 V IOL = 2.0 mA VCC5 = 4.5 V IOL = 1.0 mA VCC5 = 4.5 V IOL = 2.0 mA VCC5 = 4.5 V IOL = 5.0 mA VCC5 = 4.5 V IOL = 2.0 mA VCC5 = 4.5 V IOL = 5.0 mA VCC5 = 4.5 V IOL = 3.0 mA DVCC = 4.5 V IOL = 1.0 mA DVCC = 4.5 V IOL = 2.0 mA DVCC = 4.5 V IOL = 5.0 mA DVCC = 4.5 V IOL = 30.0 mA DVCC = 4.5 V IOL = 40.0 mA VCC3 = 3.0 V IOL = 2.0 mA VCC3 = 3.0 V IOL = 5.0 mA VCC3 = 3.0 V IOL = 6.0 mA VCC3 = 3.0 V IOL = 15.0 mA Value Unit Remarks 0.4 V ODR[1:0] = 2b00 - 0.4 V ODR[1:0] = 2b01 0 - 0.4 V ODR[1:0] = 2b10 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V 0 - 0.55 V SMC 0 - 0.55 V SMC Tj = -40 oC 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V 0 - 0.4 V Min Typ Max 0 - 0 I2 C Page 178 of 322 S6J3310/20/30/40 Series (TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V 10 %, VCC3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name VCC53 = 4.5 V IOL = 1.0 mA VOL19 VOL20 VOL21 "L" level output voltage VOL22 Conditions P2_12 VOL23 VOL24 VOL26 Document Number: 002-10635 Rev. *H VCC53 = 3.0 V IOL = 0.5 mA VCC53 = 4.5 V IOL = 2.0 mA VCC53 = 3.0 V IOL = 1.0 mA VCC53 = 4.5 V IOL = 5.0 mA VCC53 = 3.0 V IOL = 2.0 mA VCC53 = 3.0 V IOL = 15.0 mA Value Unit Remarks 0.4 V ODR[1:0] = 2b00 - 0.4 V ODR[1:0] = 2b01 0 - 0.4 V ODR[1:0] = 2b10 0 - 0.4 V ODR[1:0] = 2b11 Min Typ Max 0 - 0 Page 179 of 322 S6J3310/20/30/40 Series (TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V 10 %, VCC3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Input leakage current Symbol IIL RUP1 RUP2 Pull-up resistor RUP3 RUP4 Rdown1 Pull-down resistor Rdown2 Rdown3 CIN1 Input capacitance CIN2 Pin Name P0_00 to P0_20, P1_03 to P1_31, P2_00 to P2_19, P3_00 to P3_31, P4_00 to P4_31 P0_21 to P0_31, P1_00 to P1_02 RSTX, NMIX P0_00 to P0_20, P1_03 to P1_31, P2_00 to P2_19, P3_00 to P3_31, P4_00 to P4_31 P0_21 to P0_31, P1_00 to P1_02 JTAG_TDI, JTAG_TMS, JTAG_TCK P0_00 to P0_20, P1_03 to P1_31, P2_00 to P2_19, P3_00 to P3_31, P4_00 to P4_31 P0_21 to P0_31, P1_00 to P1_02 JTAG_NTRST P0_00 to P0_31, P1_00 to P1_16, P2_09 to P2_19, P3_00 to P3_31, P4_00 to P4_23 P1_17 to P1_31, P2_00 to P2_08, P4_24 to P4_31 Document Number: 002-10635 Rev. *H Conditions Value Unit Remarks +5 A 5 V pins 5 V/3 V pins - +10 A 3 V pins 25 50 100 k Pull-up resistor selected 25 50 100 k 5 V pins 5 V/3 V pins Pull-up resistor selected 17 50 66 k 3 V pins - 25 50 100 k Pull-down resistor selected 25 50 100 k 5 V pins 5 V/3 V pins 17 50 66 k 3 V pins 25 50 100 k - - 5 15 pF - - 15 45 pF VCC5 = VCC53 = DVCC = AVCC = 5.5 V VSS < VI < VCC VCC3 = 3.6 V VSS < VI < VCC3 - Pull-down resistor selected - Min Typ Max -5 - -10 When using SMC Page 180 of 322 S6J3310/20/30/40 Series (TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V 10 %, VCC3 = 3.3 V 0.3 V, VCC12 = 1.15 V 0.06 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions Value Unit Min Typ Max - 315 775 mA - - 395 mA - 320 780 mA - - 420 mA - 25 45 mA - - 60 mA Normal operation ICC12 VCC12 Power supply current Flash write/erase ICCH12 ICC5 VCC5 Document Number: 002-10635 Rev. *H Timer/ Stop Mode Normal operation Flash write/erase Remarks TA = -40 ~ 105 C CPU:240MHz, HPM:120 MHz (CPU:200 MHz, HPM:200 MHz) GDC: 200 MHz Example use case *1 TA = -40 ~ 105 C CPU:60 MHz, HPM:60 MHz GDC: 60 MHz TA = -40 ~ 105 C CPU:240 MHz, HPM:120 MHz (CPU:200 MHz, HPM:200 MHz) GDC: 200 MHz Page 181 of 322 S6J3310/20/30/40 Series (TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V 10 %, VCC3 = 3.3 V 0.3 V, VCC12 = 1.15 V 0.06 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name ICCT5 Power supply current Conditions Timer mode VCC5 ICCH5 Stop mode Value Min Typ Max Unit - 370 810 A - 360 780 A - 350 750 A - 450 890 A - 440 860 A - 430 830 A - 110 430 A - 100 400 A - 90 370 A - 100 400 A - 90 370 A - 80 340 A Remarks TA = 25 C. 4 MHz crystal for main oscillator PD1 = ON, PD4_0 = ON, PD4_1 = ON TA = 25 C. 4 MHz crystal for main oscillator. PD1 = ON, PD4_0 = ON or PD4_1 = ON TA = 25 C. 4 MHz crystal for main oscillator. PD1 = ON TA = 25 C. 8 MHz crystal for main oscillator PD1 = ON, PD4_0 = ON, PD4_1 = ON TA = 25 C. 8 MHz crystal for main oscillator. PD1 = ON, PD4_0 = ON or PD4_1 = ON TA = 25 C. 8 MHz crystal for main oscillator. PD1 = ON TA = 25 C. 32 kHz crystal for sub oscillator PD1 = ON, PD4_0 = ON, PD4_1 = ON TA = 25 C. 32 kHz crystal for sub oscillator. PD1 = ON, PD4_0 = ON or PD4_1 = ON TA = 25 C. 32 kHz crystal for sub oscillator. PD1 = ON TA = 25 C. PD1 = ON, PD4_0 = ON, PD4_1 = ON TA = 25 C. PD1 = ON, PD4_0 = ON or PD4_1 = ON TA = 25 C. PD1 = ON *1: Example use case at following condition CPU:60MHz, HPM:60MHz, GDC: 60MHz Peripherals: - DMAC active (WorkFlash => SystemRAM) - All timers active - 6 SMCs, 1 CAN, 2LIN, 1SPI, PWMs, ADCs Display controller: - 2 (= all) layers active (60 MHz, noise RGBA, 32 bpp, 2048 x 5 pixels) - Any other resources inactive - IOs no toggle Document Number: 002-10635 Rev. *H Page 182 of 322 S6J3310/20/30/40 Series (TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V 10 %, VCC3 = 3.3 V 0.3 V, VCC12 = 1.15 V 0.06 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name ICCT5 Power supply current * Conditions Timer mode VCC5 ICCH5 Stop mode Value Min Typ Max Unit - 345 630 A - 340 625 A - 335 620 A - 420 705 A - 415 700 A - 410 695 A - 80 135 A - 75 130 A - 70 125 A - 75 130 A - 70 125 A - 65 120 A Remarks TA = 25 C. 4 MHz crystal for main oscillator PD1 = ON, PD4_0 = ON, PD4_1 = ON TA = 25 C. 4 MHz crystal for main oscillator. PD1 = ON, PD4_0 = ON or PD4_1 = ON TA = 25 C. 4 MHz crystal for main oscillator. PD1 = ON TA = 25 C. 8 MHz crystal for main oscillator PD1 = ON, PD4_0 = ON, PD4_1 = ON TA = 25 C. 8 MHz crystal for main oscillator. PD1 = ON, PD4_0 = ON or PD4_1 = ON TA = 25 C. 8 MHz crystal for main oscillator. PD1 = ON TA = 25 C. 32 kHz crystal for sub oscillator PD1 = ON, PD4_0 = ON, PD4_1 = ON TA = 25 C. 32 kHz crystal for sub oscillator. PD1 = ON, PD4_0 = ON or PD4_1 = ON TA = 25 C. 32 kHz crystal for sub oscillator. PD1 = ON TA = 25 C. PD1 = ON, PD4_0 = ON, PD4_1 = ON TA = 25 C. PD1 = ON, PD4_0 = ON or PD4_1 = ON TA = 25 C. PD1 = ON * Electric Characteristics for S6J33xxxxE. Document Number: 002-10635 Rev. *H Page 183 of 322 S6J3310/20/30/40 Series (TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V 10 %, VCC3 = 3.3 V 0.3 V, VCC12 = 1.15 V 0.06 V, VSS = DVSS = AVSS = 0.0 V) Parameter High current output drive capacity Phase-to-phase deviation1 High current output drive capacity Phase-to-phase deviation2 LCD divider resistor COM0 to COM3 output impedance SEG00 to SEG31 output impedance Symbol Pin Name Conditions PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn (n = 0 to 5) DVCC = 4.5 V IOH = -30.0 mA Maximum deviation of VOH13 DVCC = 4.5 V IOL = 30.0 mA Maximum deviation of VOL13 RLCD V0 to V1, V1 to V2, V2 to V3 RVCOM RVSEG Delta-VOH13 Delta-VOL13 Value Unit Remarks 90 mV * - 90 mV * 6.25 12.5 25 k - - - 4.5 k - - - 17 k Min Typ Max - - - - COMm (m = 0 to 3) SEGn (n = 00 to 31) V0 to V3, COMm LCDC leak ILCDC (m = 0 to 3), -0.5 +0.5 A TA = 25 C current SEGn (n = 00 to 31) *: If PWM1P0/PWM1M0/PWM2P0/PWM2M0 of ch.0 is turned on simultaneously, the maximum deviation of V OH13 / VOL13 for each pin is defined. Same for other channels. Document Number: 002-10635 Rev. *H Page 184 of 322 S6J3310/20/30/40 Series 9.1.4 AC Characteristics 9.1.4.1 Source Clock Timing (TA: Recommended operating conditions, Vcc5 = 5.0 V 10 %, VSS = DVSS = AVSS = 0.0 V) Parameter Source oscillation clock frequency Source oscillation clock cycle time CAN PLL jitter (when locked) Internal Slow CR oscillation frequency Internal Fast CR oscillation frequency Min Value Typ Max - 3.6 - 16.0 MHz X0, X1 - 62.5 - 277.8 ns tPJ - - -10 - 10 ns FCRS - - 50 100 150 kHz FCRF - - 2.40 4.00 5.61- MHz 3.20 4.00 4.81 MHz Symbol Pin Name Conditions FC X0, X1 tCYL Unit Remarks Before trim After trim Notes: - The maximum/minimum values have been standardized with the main clock and PLL clock in use. - - Jitter of source oscillator must be smaller than 300 ppm. Enough evaluation and adjustment are recommended using oscillator on your system board. - X0 and X1 clock timing tCYL X0 CAN PLL jitter A time difference from the ideal clock is guaranteed for each cycle period within 20,000 cycles. Ideal clock Slow PLL output Fast Document Number: 002-10635 Rev. *H Page 185 of 322 S6J3310/20/30/40 Series 9.1.4.2 Sub Clock Timing (TA: Recommended operating conditions, Vcc5 = 5.0 V 10 %, VSS = DVSS = AVSS = 0.0 V) Parameter Source oscillation clock frequency Source oscillation clock cycle time - Symbol FCL tLCYL Pin Name X0A, X1A X0A, X1A Min Value Typ Max - - 32.768 - kHz - - 30.52 - s Conditions Unit Remarks X0A and X1A clock timing tLCYL X0A Document Number: 002-10635 Rev. *H Page 186 of 322 S6J3310/20/30/40 Series 9.1.4.3 Internal Clock Timing (S6J3310) This chapter shows the TARGET characteristics for internal clock timing at the current stage. In the column symbol, same clock names as described in CHAPTER 5: CLOCK SYSTEM of TraveoTM Platform Hardware Manual are used. Corresponding functions for these clocks are described in CHAPTER 5: CLOCK CONFIGURATION of S6J3300 Series Hardware Manual. (TA: Recommended operating conditions, VCC5 = 5.0 V 10 %, VCC12 = 1.15 V 0.06 V, VSS = 0.0 V) Parameter Symbol Internal clock frequency FSSCG0 FSSCG1 FSSCG2 FSSCG3 FPLL0 FPLL1 FPLL2 FPLL3 FCLK_CPU0 FCLK_SHE FCLK_FCLK FCLK_ATB FCLK_DBG FCLK_HPM FCLK_HPM2 FCLK_DMA FCLK_MEMC FCLK_EXTBUS FCLK_SYSC1 FCLK_HAPP0A0 FCLK_HAPP0A1 FCLK_HAPP1B0 FCLK_HAPP1B1 FCLK_LLPBM FCLK_LLPBM2 FCLK_LCP FCLK_LCP0 FCLK_LCP0A FCLK_LCP1 FCLK_LCP1A FCLK_LAPP0 FCLK_LAPP0A FCLK_LAPP1 FCLK_LAPP1A FCLK_TRC FCLK_CD1 FCLK_CD1A0 FCLK_CD1A1 FCLK_CD1B0 FCLK_CD1B1 FCLK_CD2 FCLK_CD2A0 FCLK_CD2A1 FCLK_CD2B0 FCLK_CD2B1 FCLK_CD3 FCLK_CD3A0 FCLK_CD3A1 Document Number: 002-10635 Rev. *H Max *1 480 400 320 400 480 400 400 480 240 240 80 120 120 120 60 120 120 40 40 40 40 80 40 240 120 80 40 80 40 80 40 40 40 40 100 200 100 100 100 100 200 200 200 200 200 80 80 80 Value Max *2 400 400 320 400 400 400 400 480 200 200 66.7 100 100 200 100 200 200 40 40 40 40 50 50 200 100 50 40 66.7 40 66.7 40 40 40 40 100 200 100 100 100 100 200 200 200 200 200 80 80 80 Max *3 360 400 320 400 360 400 400 480 180 180 90 90 90 180 90 180 180 30 60 30 30 60 30 180 90 60 30 60 30 60 30 30 30 30 100 200 100 100 100 100 200 200 200 200 200 80 80 80 Unit Remarks MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz SSCG0 output clock *4 SSCG1 output clock *4 SSCG2 output clock *4 SSCG3 output clock *4 PLL0 output clock *4 PLL1 output clock *4 PLL2 output clock *4 PLL3 output clock *4 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Page 187 of 322 S6J3310/20/30/40 Series Value Max *1 Max *2 Max *3 FCLK_CD3B0 80 80 80 FCLK_CD3B1 80 80 80 FCLK_CD4 200 200 200 FCLK_CD4A0 200 200 200 FCLK_CD4A1 200 200 200 FCLK_CD4B0 200 200 200 FCLK_CD4B1 200 200 200 FCLK_CD5 240 240 240 FCLK_CD5A0 120 120 120 Internal clock FCLK_CD5A1 120 120 120 frequency FCLK_CD5B0 60 60 60 FCLK_CD5B1 60 60 60 FCLK_HSSPI 200 200 200 FCLK_SYSC0H 80 66.7 60 FCLK_COMH 80 66.7 60 FCLK_RAM0H 80 66.7 60 FCLK_RAM1H 80 66.7 60 FCLK_SYSC0P 80 66.7 60 FCLK_COMP 80 66.7 60 *1: Target maximum clock frequencies when CPU clock = 240MHz Parameter Symbol Unit Remarks MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Unused Unused Unused Unused Unused Unused Unused Unused *2: Target maximum clock frequencies when CPU clock = 200MHz *3: Target maximum clock frequencies when CPU clock = 180MHz *4: The PLLx/SSCGx cannot set under 200MHz. - Note that Ta = 125 condition is not supported in this product type. When using SSCG_PLL output for these internal clock, the MAX value of frequency has the following restrictions. - On the presumption that the modulation mode of SSCG_PLL is used with down spread, the MAX value of the frequency is standardized. - This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated. - "Unused" means a clock source which doesn't have any supply destinations. Configure it as disable with performing at the lower clock frequency than the described maximum. Document Number: 002-10635 Rev. *H Page 188 of 322 S6J3310/20/30/40 Series Operation assurance range Relationship between the internal clock frequency and supply voltage Power supply VCC12 [V] Power supply VCC5 [V] - 5.5 Recommended guaranteed operation range 4.5 3.5 Guaranteed operation range 2 4 2 4 Frequency [MHz] Maximum frequency of each clock Frequency [MHz] Maximum frequency of each clock PLL guaranteed operation range 1.21 1.09 Note: CPU will be reset, when the power supply voltage is equal to or less than LVD setting voltage. Document Number: 002-10635 Rev. *H Page 189 of 322 S6J3310/20/30/40 Series - Relationship between the oscillation clock frequency and internal clock frequency Main Clock Oscillation clock frequency [MHz] - Internal Operation Clock Frequency PLL Clock Multiplied Multiplied Multiplied by 2 by 15 by 30 8 ... 60 120 4 2 Multiplied by 1 4 8 4 8 16 ... 120 16 8 16 32 ... 240 Multiplied by 40 160 Multiplied by 60 240 240 Oscillation circuit example X0 X1 R C1 C2 Note: For the configuration of an oscillation circuit, request the oscillator manufacturer to perform a circuit matching evaluation before starting design. AC characteristics are specified by the following measurement reference voltage values. Input signal waveform Hysteresis input pin (Automotive) - Output signal waveform Output pin - 0.8VCC5 2.4V 0.5VCC5 0.8V Hysteresis input pin (CMOS Schmitt) 0.7VCC5 0.3VCC5 0.7VCC3 0.3VCC3 Hysteresis input pin (TTL) 2.0V 0.8V Document Number: 002-10635 Rev. *H Page 190 of 322 S6J3310/20/30/40 Series 9.1.4.4 Reset Input (TA: Recommended operating conditions, Vcc5 = 5.0 V 10 %, VSS = 0.0 V) Parameter Symbol Pin Name Conditions Reset input time Width for reset input removal tRSTL RSTX - Value Unit Min Max 10 - s 1 - s Remarks tRSTL RSTX 0.2Vcc Document Number: 002-10635 Rev. *H 0.2Vcc Page 191 of 322 S6J3310/20/30/40 Series 9.1.4.5 Power-on Conditions (TA: Recommended operating conditions, VSS = 0.0 V) Parameter Symbol Pin Name Conditions - VCC5 - Power ramp rate Unit Remarks Min Typ Max - 2.2 2.4 2.6 V VCC5 - - 100 - mV - - - - - 40 s *1 tOFF VCC5 - 100 - - s *2 dV/dt VCC5 VCC5: 1.5 V to 2.6 V - - 1 V/s *3 - - 50 mV/s *4 Level detection voltage Level detection hysteresis width Level detection time Power off time Value Maximum ramp VCC5: rate guaranteed to |dV/dt| VCC5 Between 2.4 not generate V and 4.5 V power-on reset *1: This specification is at 1 V/s of power ramp rate. *2: VCC5 must be held below 1.5 V for a minimum period of tOFF. *3: Power ramp rate must be 1 V/us or less from 1.5 V to 2.6 V. Power-on can detect by satisfying power ramp rate when power off time is satisfied. *4: This specification is specified the power supply fluctuation after power on detection. When VCC5 voltage is between 2.4 V and 4.5 V, the power supply fluctuation is below 50 mV/us, the detection of power-on is suppressed. The power-on does not detect in any power fluctuation between 4.5 V and 5.5 V. Notes: When using S6J3310/20/30/40, *2 and *3 must be satisfied. When neither *2 nor *3 can be satisfied, assert external reset (RSTX) at power up and any brownout event. Power off time, Power ramp rate tOFF VCC 2.6V 1.5V 1.5V dV/dt Maximum ramp rate guaranteed to not generate power-on reset VCC |dV/dt| |dV/dt| Document Number: 002-10635 Rev. *H 5.5V 4.5V 2.4V Page 192 of 322 S6J3310/20/30/40 Series 9.1.4.6 Multi-Function Serial UART (asynchronous serial interface) timing (SMR:MD2-0 = 0b000, 0b001) (1) External Clock Selected (BGR:EXT = 1) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10 % /3.3 V 0.3 V, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Serial clock "L" pulse width Serial clock "H" pulse width Symbol Pin Name Value Conditions Unit Min Max SCK0 to SCK4, SCK8 to SCK12 tCLK_LCPnA*1 +10 - ns SCK16 to SCK17 tCLK_COMP +10 - ns SCK0 to SCK4, SCK8 to SCK12 tCLK_LCPnA*1 +10 - ns tCLK_COMP +10 - ns - 5 ns - 5 ns Remarks tSLSH - tSHSL SCK16 to SCK17 SCK falling time tF SCK rising time tR SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 *1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12 tR SCK VIL tF tSHSL VIH VIH tSLSH VIL VIL VIH External clock selected Document Number: 002-10635 Rev. *H Page 193 of 322 S6J3310/20/30/40 Series CSIO timing (SMR:MD2-0 = 0b010) (1) Normal Synchronous Transfer (SCR:SPI = 0) and Mark Level "H" of Serial Clock Output (SMR:SCINV = 0) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10 % /3.3 V 0.3 V, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Serial clock cycle time SCK SOT delay time Symbol Pin Name tSCYC tSLOVI SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12 8tCLK_LCPnA*1 - SCK16 to SCK17 8tCLK_COMP - ns -30 +30 ns 40 - ns 0 - ns 2tCLK_LCPnA*1 - ns -7.5 +7.5 ns SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SOT0, SOT1, SOT2_1, SOT3_1, SOT4, SOT8 to SOT12, SOT16 to SOT17 tSHIXI Serial clock cycle time tSCYC SCK2_0, SCK3_0 SCK SOT delay time tSLOVI SCK2_0, SCK3_0, SOT2_0, SOT3_0 tSHIXI Remarks ns - Master Mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SIN0, SIN1, SIN2_1, SIN3_1, SIN4, SIN8 to SIN12, SIN16 to SIN17 SCK Valid SIN hold time SCK Valid SIN hold time Unit Max tIVSHI tIVSHI Value Min Valid SIN SCK setup time Valid SIN SCK setup time Conditions Master Mode (CL = 20 pF, IOL = -10 mA, IOH = 10 mA) 10 - ns 0 - ns SCK2_0, SCK3_0, SIN2_0, SIN3_0 Document Number: 002-10635 Rev. *H Page 194 of 322 S6J3310/20/30/40 Series Parameter Serial clock "H" pulse width Symbol Pin Name Conditions Value Unit Min Max SCK0 to SCK4, SCK8 to SCK12 4tCLK_LCPnA*1 - ns SCK16 to SCK17 4tCLK_COMP - ns SCK0 to SCK4, SCK8 to SCK12 4tCLK_LCPnA*1 - ns SCK16 to SCK17 4tCLK_COMP - ns - 40 ns 10 - ns 10 - ns - 5 ns - 5 ns Remarks tSHSL - Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK setup time SCK Valid SIN hold time tSLSH tSLOVE SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SOT0 to SOT4, SOT8 to SOT12, SOT16 to SOT17 Slave Mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SIN0 to SIN4, SIN8 to SIN12, tSHIXE SIN16 to SIN17 SCK0 to SCK4, SCK falling time tF SCK8 to SCK12, SCK16 to SCK17 SCK0 to SCK4, SCK rising time tR SCK8 to SCK12, SCK16 to SCK17 *1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12 tIVSHE Notes: - This table provides the alternate current standard for CLK synchronous mode. - - CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the TraveoTM Platform Hardware Manual. Document Number: 002-10635 Rev. *H Page 195 of 322 S6J3310/20/30/40 Series tSCYC SCK VOH VOL tSLOVI VOH VOL SOT tIVSHI tSHIXI VIH VIL SIN VIH VIL Master mode tSLSH SCK VIH VIL tSHSL VIL VIH VIH tR tF SOT tSLOVE VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL Slave mode Document Number: 002-10635 Rev. *H Page 196 of 322 S6J3310/20/30/40 Series (2) Normal Synchronous Transfer (SCR:SPI = 0) and Mark Level "L" of Serial Clock Output (SMR:SCINV = 1) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10% /3.3 V 0.3 V, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Serial clock cycle time SCK SOT delay time Symbol tSCYC tSHOVI Valid SIN SCK setup time tIVSLI SCK Valid SIN hold time tSLIXI Document Number: 002-10635 Rev. *H Pin Name Conditions Value Unit Min Max SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12 8tCLK_LCPnA*1 - ns SCK16 to SCK17 8tCLK_COMP - ns -30 +30 ns 40 - ns 0 - ns SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SOT0, SOT1, SOT2_1, SOT3_1, SOT4, SOT8 to SOT12, SOT16 to SOT17 SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SIN0, SIN1, SIN2_1, SIN3_1, SIN4, SIN8 to SIN12, SIN16 to SIN17 Master Mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) Remarks Page 197 of 322 S6J3310/20/30/40 Series Parameter Symbol Pin Name Serial clock cycle time tSCYC SCK2_0, SCK3_0 SCK SOT delay time tSHOVI SCK2_0, SCK3_0, SOT2_0, SOT3_0 Valid SIN SCK setup time tIVSLI SCK Valid SIN hold time tSLIXI Serial clock "H" pulse width tSHSL Serial clock "L" pulse width tSLSH SCK SOT delay time tSHOVE Valid SIN SCK setup time tIVSLE SCK Valid SIN hold time tSLIXE SCK falling time tF Conditions Unit Max 2tCLK_LCPnA*1 - ns -7.5 +7.5 ns 10 - ns 0 - ns SCK0 to SCK4, SCK8 to SCK12 4tCLK_LCPnA*1 - ns SCK16 to SCK17 4tCLK_COMP - ns SCK0 to SCK4, SCK8 to SCK12 4tCLK_LCPnA*1 - ns SCK16 to SCK17 4tCLK_COMP - ns - 40 ns 10 - ns 10 - ns - 5 ns - 5 ns SCK2_0, SCK3_0, SIN2_0, SIN3_0 SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SOT0 to SOT4, SOT8 to SOT12, SOT16 to SOT17 SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SIN0 to SIN4, SIN8 to SIN12, SIN16 to SIN17 Master Mode (CL = 20 pF, IOL = -10 mA, IOH = 10 mA) Slave Mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 *1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12 SCK rising time Value Min tR Remarks Notes: - This table provides the alternate current standard for CLK synchronous mode. - - CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the TraveoTM Platform Hardware Manual. Document Number: 002-10635 Rev. *H Page 198 of 322 S6J3310/20/30/40 Series tSCYC VOH SCK VOL tSHOVI VOH VOL SOT tIVSLI tSLIXI VIH VIL SIN VIH VIL Master mode tSHSL SCK VIL tR SOT VIH tSLSH VIH VIL tF tSHOVE VOH VOL tIVSLE SIN VIL tSLIXE VIH VIL VIH VIL Slave mode Document Number: 002-10635 Rev. *H Page 199 of 322 S6J3310/20/30/40 Series (3) SPI Supported (SCR:SPI = 1), and Mark Level "H" of Serial Clock Output (SMR:SCINV = 0) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10 % /3.3 V 0.3 V, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Serial clock cycle time Symbol Value Unit Max 8tCLK_LCPnA*1 - ns 8tCLK_COMP - ns -30 +30 ns 40 - ns 0 - ns 4tCLK_LCPnA*1 30 - ns SCK16 to SCK17 SOT16 to SOT17 4tCLK_COMP*1 30 - ns tSCYC SCK2_0, SCK3_0 2tCLK_LCPnA*1 - ns tSHOVI SCK2_0, SCK3_0, SOT2_0, SOT3_0 -7.5 +7.5 ns 10 - ns 0 - ns - ns tSCYC tSHOVI Valid SIN SCK setup time tIVSLI SCK Valid SIN hold time tSLIXI Serial clock cycle time SCK SOT delay time Valid SIN SCK setup time SCK Valid SIN hold time SOT SCK delay time Conditions Min SCK SOT delay time SOT SCK delay time Pin Name tSOVLI tIVSHI SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SOT0, SOT1, SOT2_1, SOT3_1, SOT4, SOT8 to SOT12, SOT16 to SOT17 SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SIN0, SIN1, SIN2_1, SIN3_1, SIN4, SIN8 to SIN12, SIN16 to SIN17 SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SOT0, SOT1, SOT2_1, SOT3_1, SOT4, SOT8 to SOT12, SOT16 to SOT17 SCK2_0, SCK3_0, SIN2_0, SIN3_0 tSHIXI tSOVLI Document Number: 002-10635 Rev. *H SCK2_0, SCK3_0, SOT2_0, SOT3_0 Master Mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) Master Mode (CL = 20 pF, IOL = -10 mA, IOH = 10 mA) tCLK_LCPnA*1 7.5 - Remarks - - - Page 200 of 322 S6J3310/20/30/40 Series Parameter Symbol Pin Name SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK0 to SCK4, Serial clock SCK8 to SCK12 tSLSH "L" pulse width SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12, SCK SOT SCK16 to SCK17 tSHOVE delay time SOT0 to SOT4, SOT8 to SOT12, SOT16 to SOT17 Valid SIN SCK SCK0 to SCK4, tIVSLE SCK8 to SCK12, setup time SCK16 to SCK17 SIN0 to SIN4, SCK Valid SIN8 to SIN12, SIN tSLIXE SIN16 to SIN17 hold time SCK0 to SCK4, SCK falling time tF SCK8 to SCK12 SCK16 to SCK17 SCK0 to SCK4, SCK rising time tR SCK8 to SCK12 SCK16 to SCK17 *1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12 Serial clock "H" pulse width Value Conditions tSHSL Unit Min Max 4tCLK_LCPnA*1 - ns 4tCLK_COMP - ns 4tCLK_LCPnA*1 - ns 4tCLK_COMP - ns - 40 ns 10 - ns 10 - ns - 5 ns - 5 ns Slave Mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) Remarks Notes: - This table provides the alternate current standard for CLK synchronous mode. - - CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the TraveoTM Platform Hardware Manual. tSCYC SCK VOH VOL tSOVLI SOT VOH VOL VOH VOL tIVSLI SIN VOL tSHOVI tSLIXI VIH VIL VIH VIL Master mode Document Number: 002-10635 Rev. *H Page 201 of 322 S6J3310/20/30/40 Series tSHSL tSLSH VIH SCK tR VIH VIH VIL tSHOVE VOH VOL VOH VOL tIVSLE SIN VIL tF * SOT VIL tSLIXE VIH VIL VIH VIL * Changes when writing to the TDR register Slave mode Document Number: 002-10635 Rev. *H Page 202 of 322 S6J3310/20/30/40 Series (4) SPI Supported (SCR:SPI = 1), and Mark Level "L" of Serial Clock Output (SMR:SCINV = 1) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10 % /3.3 V 0.3 V, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Serial clock cycle time Symbol tSCYC SCK -> SOT delay time tSLOVI Valid SIN -> SCK setup time tIVSHI SCK -> Valid SIN hold time tSHIXI SOT -> SCK delay time Serial clock cycle time SCK -> SOT delay time Valid SIN -> SCK setup time SCK -> Valid SIN hold time SOT -> SCK delay time tSOVHI Pin Name SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SOT0, SOT1, SOT2_1, SOT3_1, SOT4, SOT8 to SOT12, SOT16 to SOT17 SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SIN0, SIN1, SIN2_1, SIN3_1, SIN4, SIN8 to SIN12, SIN16 to SIN17 SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SOT0, SOT1, SOT2_1, SOT3_1, SOT4, SOT8 to SOT12, SOT16 to SOT17 SCK16 to SCK17 SOT16 to SOT17 tSCYC SCK2_0, SCK3_0 tSLOVI SCK2_0, SCK3_0, SOT2_0, SOT3_0 tIVSHI SCK2_0, SCK3_0, SIN2_0, SIN3_0 tSHIXI tSOVHI Document Number: 002-10635 Rev. *H SCK2_0, SCK3_0, SOT2_0, SOT3_0 Conditions Master Mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) Master Mode (CL = 20 pF, IOL = -10 mA, IOH = 10 mA) Value Unit Min Max 8tCLK_LCPnA*1 - ns 8tCLK_COMP - ns -30 +30 ns 40 - ns 0 - ns 4tCLK_LCPnA*1 30 - ns 4tCLK_COMP 30 - ns 2tCLK_LCPnA*1 - ns -7.5 +7.5 ns 10 - ns 0 - ns tCLK_LCPnA*1 7.5 - ns Remarks - - Page 203 of 322 S6J3310/20/30/40 Series Parameter Symbol Pin Name SCK0 to SCK4, SCK8 to SCK12 SCK16 to SCK17 SCK0 to SCK4, Serial clock SCK8 to SCK12 tSLSH "L" pulse width SCK16 to SCK17 SCK0 to SCK4, SCK8 to SCK12, SCK -> SOT SCK16 to SCK17 tSLOVE delay time SOT0 to SOT4, SOT8 to SOT12, SOT16 to SOT17 Valid SIN -> SCK SCK0 to SCK4, tIVSHE SCK8 to SCK12, setup time SCK16 to SCK17 SIN0 to SIN4, SCK -> Valid SIN8 to SIN12, SIN tSHIXE SIN16 to SIN17 hold time SCK0 to SCK4, SCK falling time tF SCK8 to SCK12 SCK16 to SCK17 SCK0 to SCK4, SCK rising time tR SCK8 to SCK12 SCK16 to SCK17 *1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12 Serial clock "H" pulse width Value Conditions tSHSL Unit Min Max 4tCLK_LCPnA*1 - ns 4tCLK_COMP - ns 4tCLK_LCPnA*1 - ns 4tCLK_COMP - ns - 40 ns 10 - ns 10 - ns - 5 ns - 5 ns Slave Mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) Remarks - Notes: - This table provides the alternate current standard for CLK synchronous mode. - - CL is the load capability value connected to the pin at the test time. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the TraveoTM Platform Hardware Manual. tSCYC VOH VOH SCK VOL tSOVHI SOT VOH VOL VOH VOL tIVSHI SIN tSLOVI tSHIXI VIH VIL VIH VIL Master mode Document Number: 002-10635 Rev. *H Page 204 of 322 S6J3310/20/30/40 Series tSLSH tSHSL SCK VIL VIH VIH tF tR * SOT VIH tSLOV VOH VOL VOH VOL tSHIXE VIH VIL * Changes when writing to the TDR register Document Number: 002-10635 Rev. *H VIL E tIVSHE SIN VIL VIH VIL Slave mode Page 205 of 322 S6J3310/20/30/40 Series (5) Serial Chip Select Used (SCSCR:CSEN = 1) Mark level "H" of serial clock output (SMR, SCSFR:SCINV = 0) Inactive level "H" of serial chip select (SCSCR, SCSFR:CSLVL = 1) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10% /3.3 V 0.3 V, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Symbol SCS SCK setup time tCSSI SCK SCS hold time tCSHI SCS deselect time tCSDI Pin Name SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SCS0x, SCS1x, SCS2x_1, SCS3x_1, SCS4, SCS8x to SCS12x, SCS16x to SCS17x SCS0x, SCS1x, SCS2x_1, SCS3x_1, SCS4, SCS8x to SCS12x Conditions Master Mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) SCS16x to SCS17x SCS SCK setup time SCK SCS hold time SCS deselect time SCS SCK setup time SCK SCS hold time tCSSI tCSHI tCSDI SCK2_0, SCK3_0, SCS2x_0, SCS3x_0 SCS2x_0, SCS3x_0 SCK0 to SCK4, SCK8 to SCK12 SCS0x to SCS4x, SCS8x to SCS12x SCK16 to SCK17, SCS16x to SCS17x SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17, SCS0x to SCS4x, SCS8x to SCS12x, SCS16x to SCS17x SCS0x to SCS4x, SCS8x to SCS12x tCSSE tCSHE SCS deselect time tCSDE SCS SOT delay time tDSE SCS SOT delay time tDEE SCS16x to SCS17x SCS0x to SCS4x, SCS8x to SCS12x, SCS16x to SCS17x, SOT0 to SOT4, SOT8 to SOT12, SOT16 to SOT17 Document Number: 002-10635 Rev. *H Master Mode (CL = 20 pF, IOL = -10 mA, IOH = 10 mA) Slave Mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) Min Value Max Unit tCSSU*1-15 - ns tCSHD*2+0 - ns tCSDS*3-15 +5tCLK_LCPnA*4 - ns tCSDS*3-15 +5tCLK_COMP - ns tCSSU*1-10 - ns tCSHD*2+0 - ns - ns 4tCLK_LCPnA*4 +15 - ns 4tCLK_COMP +15 - ns 0 - ns - ns - ns - 40 ns 0 - ns tCSDS*3-10 +5tCLK_LCPnA*4 4tCLK_LCPnA*4 +15 4tCLK_COMP +15 Remarks Page 206 of 322 S6J3310/20/30/40 Series Parameter Symbol SCK SCS clock switching time tSCC Pin Name Conditions SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCS0x, SCS1x, SCS2x_1, SCS3x_1, SCS4, SCS8x to SCS12x SCK16 to SCK17 SCS16x to SCS17x Master mode round operation (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) SCK2_0, SCK3_0, SCS2x_0, SCS3x_0 Master mode round operation (CL = 20 pF, IOL = -10 mA, IOH = 10 mA) *1: tCSSU = SCSTR:CSSU[7:0] x serial chip select timing operating clock *2: tCSHD = SCSTR:CSHD[7:0] x serial chip select timing operating clock *3: tCSDS = SCSTR:CSDS[15:0] x serial chip select timing operating clock Value Unit Min Max 4tCLK_LCPnA*4 +0 4tCLK_LCPnA* 4 +15 ns 4tCLK_COMP +0 4tCLK_COMP +15 ns 4tCLK_LCPnA*4 +0 4tCLK_LCPnA* 4 +10 ns Remarks For details on *1, *2, and *3 above, see the TraveoTM Platform Hardware Manual. *4 tCLK_LCPnA n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12 Notes: - This is the AC characteristic in CLK synchronized mode. - - CL is the load capacitance applied to pins during testing. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the TraveoTM Platform Hardware Manual. VOH SCS output VOL VOL tCSHI tCSSI SCK output VOH tCSDI VOH VOL SOT (Normal synchronous transfer) SOT (SPI compatible) Master mode Document Number: 002-10635 Rev. *H Page 207 of 322 S6J3310/20/30/40 Series SCS input VIH VIL VIL tCSHE tCSSE SCK input VIH VIL SOT (Normal synchronous transfer) VIH tCSDE tDEE VOL tDSE VOH VOL SOT (SPI compatible) Slave mode SCSx output tSCC SCSy output VOL SCK output VOL Clock switching example by master mode round operation (x,y=0, 1, 2, 3: x and y are different value) Document Number: 002-10635 Rev. *H Page 208 of 322 S6J3310/20/30/40 Series (6) Serial Chip Select Used (SCSCR:CSEN = 1) Serial clock output signal detect level "L" (SMR, SCSFR:SCINV = 1) Serial chip select inactive level "H" (SCSCR, SCSFR:CSLVL = 1) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10 % /3.3 V 0.3 V, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Symbol SCS SCK setup time tCSSI SCK SCS hold time tCSHI SCS deselect time tCSDI Pin Name SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SCS0x, SCS1x, SCS2x_1, SCS3x_1, SCS4, SCS8x to SCS12x, SCS16x to SCS17x SCS0x, SCS1x, SCS2x_1, SCS3x_1, SCS4, SCS8x to SCS12x Conditions Master mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) SCS16x to SCS17x SCS SCK setup time SCK SCS hold time SCS deselect time SCS SCK setup time SCK SCS hold time tCSSI tCSHI tCSDI SCK2_0, SCK3_0, SCS2x_0, SCS3x_0 SCS2x_0, SCS3x_0 SCK0 to SCK4, SCK8 to SCK12, SCS0x to SCS4x, SCS8x to SCS12x SCK16 to SCK17, SCS16x to SCS17x SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17, SCS0x to SCS4x, SCS8x to SCS12x, SCS16x to SCS17x SCS0x to SCS4x, SCS8x to SCS12x tCSSE tCSHE SCS deselect time tCSDE SCS SOT delay time tDSE SCS SOT delay time tDEE SCS16x to SCS17x SCS0x to SCS4x, SCS8x to SCS12x, SCS16x to SCS17x, SOT0 to SOT4, SOT8 to SOT12, SOT16 to SOT17 Document Number: 002-10635 Rev. *H Master Mode (CL = 20 pF, IOL = -10 mA, IOH = 10 mA) Slave mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) Min Value Max Unit tCSSU*1-15 - ns tCSHD*2+0 - ns tCSDS*3-15 +5tCLK_LCPnA*4 - ns tCSDS*3-15 +5tCLK_COMP - ns tCSSU*1-10 - ns tCSHD*2+0 - ns - ns 4tCLK_LCPnA*4 +15 - ns 4tCLK_COMP +15 - ns 0 - ns - ns - ns - 40 ns 0 - ns tCSDS*3-10 +5tCLK_LCPnA*4 4tCLK_LCPnA*4 +15 4tCLK_COMP +15 Remarks Page 209 of 322 S6J3310/20/30/40 Series Parameter Symbol SCK SCS clock switching time tSCC Pin Name Conditions SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCS0x, SCS1x, SCS2x_1, SCS3x_1, SCS4, SCS8x to SCS12x SCK16 to SCK17 SCS16x to SCS17x Master mode round operation (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) SCK2_0, SCK3_0, SCS2x_0, SCS3x_0 Master mode round operation (CL = 20 pF, IOL = -10 mA, IOH = 10 mA) *1: tCSSU = SCSTR:CSSU[7:0] x serial chip select timing operating clock *2: tCSHD = SCSTR:CSHD[7:0] x serial chip select timing operating clock *3: tCSDS = SCSTR:CSDS[15:0] x serial chip select timing operating clock Value Unit Min Max 4tCLK_LCPnA*4 +0 4tCLK_LCPnA* 4 +15 ns 4tCLK_COMP +0 4tCLK_COMP +15 ns 4tCLK_LCPnA*4 +0 4tCLK_LCPnA* 4 +10 ns Remarks For details on *1, *2, and *3 above, see the TraveoTM Platform Hardware Manual. *4 tCLK_LCPnA n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12 Notes: - This is the AC characteristic in CLK synchronized mode. - - CL is the load capacitance applied to pins during testing. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the TraveoTM Platform Hardware Manual. VOH SCS output VOL tCSHI VOL tCSSI SCK output VOH tCSDI VOH VOL SOT (Normal synchronous transfer) SOT (SPI compatible) Master mode Document Number: 002-10635 Rev. *H Page 210 of 322 S6J3310/20/30/40 Series VIH SCS input VIL tCSSE VIL tCSHE VIH tCSDE VIH SCK input VIL SOT (Normal synchronous transfer) tDSE SOT (SPI compatible) tDEE VOL VOH VOL Slave mode tSCC SCSx output SCSy output VOL VOH SCK output Clock switching example by master mode round operation (x,y=0, 1, 2, 3: x and y are different value) Document Number: 002-10635 Rev. *H Page 211 of 322 S6J3310/20/30/40 Series (7) Serial Chip Select Used (SCSCR:CSEN = 1) Serial clock output signal detect level "H" (SMR, SCSFR:SCINV = 0) Serial Chip select inactive level "L" (SCSCR, SCSFR:CSLVL = 0 (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10 % /3.3 V 0.3 V, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Symbol SCS SCK setup time tCSSI SCK SCS hold time tCSHI SCS deselect time tCSDI Pin Name SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SCS0x, SCS1x, SCS2x_1, SCS3x_1, SCS4, SCS8x to SCS12x, SCS16x to SCS17x SCS0x, SCS1x, SCS2x_1, SCS3x_1, SCS4, SCS8x to SCS12x Conditions Master mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) SCS16x to SCS17x SCS SCK setup time SCK SCS hold time SCS deselect time SCS SCK setup time SCK SCS hold time tCSSI tCSHI tCSDI SCK2_0, SCK3_0, SCS2x_0, SCS3x_0 SCS2x_0, SCS3x_0 SCK0 to SCK4, SCK8 to SCK12 SCS0x to SCS4x, SCS8x to SCS12x SCK16 to SCK17, SCS16x to SCS17x SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17, SCS0x to SCS4x, SCS8x to SCS12x, SCS16x to SCS17x SCS0x to SCS4x, SCS8x to SCS12x tCSSE tCSHE SCS deselect time tCSDE SCS SOT delay time tDSE SCS SOT delay time tDEE SCS16x to SCS17x SCS0x to SCS4x, SCS8x to SCS12x, SCS16x to SCS17x, SOT0 to SOT4, SOT8 to SOT12, SOT16 to SOT17 Document Number: 002-10635 Rev. *H Master Mode (CL = 20 pF, IOL = -10 mA, IOH = 10 mA) Slave mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) Min Value Max Unit tCSSU*1-15 - ns tCSHD*2+0 - ns tCSDS*3-15 +5 tCLK_LCPnA*4 - ns tCSDS*3-15 +5tCLK_COMP - ns tCSSU*1-10 - ns tCSHD*2+0 - ns - ns 4tCLK_LCPnA*4 +15 - ns 4tCLK_COMP +15 - ns 0 - ns - ns - ns - 40 ns 0 - ns tCSDS*3-10 +5tCLK_LCPnA*4 4tCLK_LCPnA*4 +15 4tCLK_COMP +15 Remarks Page 212 of 322 S6J3310/20/30/40 Series Parameter Symbol SCK SCS clock switching time tSCC Pin Name Conditions SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12 SCS0x, SCS1x, SCS2x_1, SCS3x_1, SCS4, SCS8x to SCS12x SCK16 to SCK17 SCS16x to SCS17x Master mode round operation (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) SCK2_0, SCK3_0, SCS2x_0, SCS3x_0 Master mode round operation (CL = 20 pF, IOL = -10 mA, IOH = 10 mA) *1: tCSSU = SCSTR:CSSU[7:0] x serial chip select timing operating clock *2: tCSHD = SCSTR:CSHD[7:0] x serial chip select timing operating clock *3: tCSDS = SCSTR:CSDS[15:0] x serial chip select timing operating clock Value Unit Min Max 4tCLK_LCPnA*4 +0 4tCLK_LCPnA* 4 +15 ns 4tCLK_COMP +0 4tCLK_COMP +15 ns 4tCLK_LCPnA*4 +0 4tCLK_LCPnA* 4 +10 ns Remarks For details on *1, *2, and *3 above, see the TraveoTM Platform Hardware Manual. *4 tCLK_LCPnA n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12 Notes: - This is the AC characteristic in CLK synchronized mode. - - CL is the load capacitance applied to pins during testing. The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the TraveoTM Platform Hardware Manual. tCSDI SCS output VOH SCK output VOH VOL tCSHI tCSSI VOH VOL SOT (Normal synchronous transfer) SOT (SPI compatible) Master mode Document Number: 002-10635 Rev. *H Page 213 of 322 S6J3310/20/30/40 Series tCSDE VIH VIH SCS input VIL tCSHE tCSSE VIH SCK input VIL SOT (Normal synchronous transfer) SOT (SPI compatible) tDEE VOL tDSE VOH VOL Slave mode tSCC SCSx output VOH SCSy output SCK output VOL Clock switching example by master mode round operation (x,y=0, 1, 2, 3: x and y are different value) Document Number: 002-10635 Rev. *H Page 214 of 322 S6J3310/20/30/40 Series (8) Serial Chip Select Used (SCSCR:CSEN = 1) Serial clock output signal detect level "L" (SMR, SCSFR:SCINV = 1) Serial Chip select inactive level "L" (SCSCR, SCSFR:CSLVL = 0) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10 % /3.3 V 0.3 V, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Symbol SCS SCK setup time tCSSI SCK SCS hold time tCSHI SCS deselect time tCSDI Pin Name SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCK16 to SCK17 SCS0x, SCS1x, SCS2x_1, SCS3x_1, SCS4, SCS8x to SCS12x, SCS16x to SCS17x SCS0x, SCS1x, SCS2x_1, SCS3x_1, SCS4, SCS8x to SCS12x Conditions Master mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) SCS16x to SCS17x SCS SCK setup time SCK SCS hold time SCS deselect time SCS SCK setup time SCK SCS hold time tCSSI tCSHI tCSDI SCK2_0, SCK3_0, SCS2x_0, SCS3x_0 SCS2x_0, SCS3x_0 SCK0 to SCK4, SCK8 to SCK12 SCS0x to SCS4x, SCS8x to SCS12x SCK16 to SCK17, SCS16x to SCS17x SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17, SCS0x to SCS4x, SCS8x to SCS12x, SCS16x to SCS17x SCS0x to SCS4x, SCS8x to SCS12x tCSSE tCSHE SCS deselect time tCSDE SCS SOT delay time tDSE SCS SOT delay time tDEE SCS16x to SCS17x SCS0x to SCS4x, SCS8x to SCS12x, SCS16x to SCS17x, SOT0 to SOT4, SOT8 to SOT12, SOT16 to SOT17 Document Number: 002-10635 Rev. *H Master Mode (CL = 20 pF, IOL = -10 mA, IOH = 10 mA) Slave mode (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) Min Value Max Unit tCSSU*1-15 - ns tCSHD*2+0 - ns tCSDS*3-15 +5tCLK_LCPnA*4 - ns tCSDS*3-15 +5tCLK_COMP - ns tCSSU*1-10 - ns tCSHD*2+0 - ns - ns 4tCLK_LCPnA*4+ 15 - ns 4tCLK_COMP+ 15 - ns 0 - ns - ns - ns - 40 ns 0 - ns tCSDS*3-10 +5tCLK_LCPnA*4 4tCLK_LCPnA*4+ 15 4tCLK_COMP+1 5 Remarks Page 215 of 322 S6J3310/20/30/40 Series Parameter SCK SCS clock switching time Symbol tSCC Pin Name Conditions SCK0, SCK1, SCK2_1, SCK3_1, SCK4, SCK8 to SCK12, SCS0x, SCS1x, SCS2x_1, SCS3x_1, SCS4, SCS8x to SCS12x SCK16 to SCK17, SCS16x to SCS17x Master mode round operation (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) SCK2_0, SCK3_0, SCS2x_0, SCS3x_0 Master mode round operation (CL = 20 pF, IOL = -10 mA, IOH = 10 mA) *1: tCSSU = SCSTR:CSSU[7:0] x serial chip select timing operating clock *2: tCSHD = SCSTR:CSHD[7:0] x serial chip select timing operating clock Value Min 4tCLK_LCPnA*4+ 0 Max Unit Remarks 4tCLK_LCPnA* 4 ns +15 4tCLK_COMP+0 4tCLK_COMP +15 ns 4tCLK_LCPnA*4 +0 4tCLK_LCPnA* 4 +10 ns *3: tCSDS = SCSTR:CSDS[15:0] x serial chip select timing operating clock For details on *1, *2, and *3 above, see the TraveoTM Platform Hardware Manual. *4 tCLK_LCPnA n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12 Notes: - This is the AC characteristic in CLK synchronized mode. - CL is the load capacitance applied to pins during testing. - The maximum baud rate is limited by the internal operating clock used and other parameters. For details, see the TraveoTM Platform Hardware Manual. Document Number: 002-10635 Rev. *H Page 216 of 322 S6J3310/20/30/40 Series SCS output tCSDI VOH VOH VOL tCSHI tCSSI VOH SCK output VOL SOT (Normal synchronous transfer) SOT (SPI compatible) Master mode tCSDE SCS input VIH VIL tCSHE tCSSE VIH SCK input VIL SOT (Normal synchronous transfer) tDEE VOL tDSE VOH VOL SOT (SPI compatible) Slave mode tSCC SCSx output VOH SCSy output VOH SCK output Clock switching example by master mode round operation (x,y=0, 1, 2, 3: x and y are different value) Document Number: 002-10635 Rev. *H Page 217 of 322 S6J3310/20/30/40 Series LIN interface (v2.1) (LIN communication control interface (v2.1)) timing (SMR:MD2-0 = 0b011) (1) External Clock Selected (BGR:EXT = 1) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10 % /3.3 V 0.3 V, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Serial clock "L" pulse width Serial clock "H" pulse width Symbol Pin Name Conditions Value Unit Min Max SCK0 to SCK4, SCK8 to SCK12 tCLK_LCPnA*1+10 - ns SCK16 to SCK17 tCLK_COMP +10 - ns SCK0 to SCK4, SCK8 to SCK12 tCLK_LCPnA*1+10 - ns tCLK_COMP +10 - ns - 5 ns - 5 ns Remarks tSLSH - tSHSL SCK16 to SCK17 SCK falling time tF SCK rising time tR SCK0 to SCK4, SCK8 to SCK12, SCK16 to SCK17 *1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12 tR SCK VIL tF tSHSL VIH VIH VIL tSLSH VIL VIH External clock selected Document Number: 002-10635 Rev. *H Page 218 of 322 S6J3310/20/30/40 Series I2C timing (SMR:MD2-0 = 0b100) (TA: Recommended operating conditions, Vcc5 = Vcc53 = 5.0 V 10 %, VCC12 = 1.15 V 0.06 V, VSS = 0.0 V) Parameter SCL clock frequency Repeat "start" condition hold time SDA SCL Symbol fSCL tHDSTA Period of "L" for SCL clock tLOW Period of "H" for SCL clock tHIGH Repeat "start" condition setup time SCL SDA tSUSTA Data hold time SCL SDA tHDDAT Data setup time SDA SCL tSUDAT "Stop" condition setup time SCL SDA Bus-free time between "stop" condition and "start" condition Noise filter Pin Name Conditions SCL0, SCL1, SCL4, SCL8 to SCL12, SCL16 to SCL17 SDA0, SDA1, SDA4 SDA8 to SDA12, SDA16 to SDA17, SCL0, SCL1, SCL4, SCL8 to SCL12, SCL16 to SCL17 SCL0, SCL1, SCL4, SCL8 to SCL12, SCL16 to SCL17 CL = 50 pF, R = (Vp/IOL)*1 SDA0, SDA1, SDA4 SDA8 to SDA12, SDA16 to SDA17, SCL0, SCL1, SCL4, SCL8 to SCL12, SCL16 to SCL17 tSUSTO Fast Mode Standard Mode Unit Min Max Min Max 0 100 0 400 kHz 4.0 - 0.6 - s 4.7 - 1.3 - s 4.0 - 0.6 - s 4.7 - 0.6 - s 0 3.45*2 0 0.9*3 s 250 - 100 - ns 4.0 - 0.6 - s tBUF - 4.7 - 1.3 - s tSP - tNFT*4 - tNFT*4 - ns Remarks Notes: Only ch.16 and ch.17 are standard mode/high-speed mode correspondence. In ch.0, ch.1, ch.4, and ch.8 to ch.12, only a standard mode is correspondence. *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively. Vp shows that the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current. *2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal. *3: A fast mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT 250 ns". *4: tNFT = (NFCR:NFT[4:0]+1) x 2 x tCLK_LCP0A (ch.0, ch.1, ch4) tNFT = (NFCR:NFT[4:0]+1) x 2 x tCLK_LCP1A (ch.8 to ch.12) tNFT = (NFCR:NFT[4:0]+1) x 2 x tCLK_COMP (ch.16 to ch.17) Document Number: 002-10635 Rev. *H Page 219 of 322 S6J3310/20/30/40 Series SDA tSUDAT tSUSTA tBUF tLOW SCL tHDSTA tHDDAT Document Number: 002-10635 Rev. *H tHIGH tHDSTA tSP tSUSTO Page 220 of 322 S6J3310/20/30/40 Series Timer Input 9.1.4.7 (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10 %, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Symbol Pin Name Value Conditions Min Max Unit Remarks ns 4tCLK_LCPnA*1 100 ns 4tCLK_LCPnA*1 <100 ns 4tCLK_LCPnA* PPG0_TIN1 to PPG31_TIN1 Input pulse width tTWH, tTWL 1 - - 100 ICU0_IN0 to ICU2_IN0, ICU8_IN0 to ICU10_IN0, ICU0_IN1 to ICU2_IN1, ICU8_IN1 to ICU10_IN1 FRT0_TEXT to FRT4_TEXT, FRT8_TEXT to FRT10_TEXT 4tCLK_LCPnA* 4tCLK_LCPnA*2 100 ns 2 - 100 ns 4tCLK_LCPnA*2 <100 ns 4tCLK_LCPnA* 4tCLK_LCPnA*3 100 ns ns 4tCLK_LCPnA*3 <100 100 ns 4tCLK_LCPnA* 4tCLK_LCPnA*4 100 4 ns ns 4tCLK_LCPnA*4 <100 100 ns 4tCLK_COMP 100 4tCLK_COMP ns ns 4tCLK_COMP <100 100 ns *1: n = 0: unit.0 to unit.5, unit.12 to unit.31, n = 1:unit.6 to unit.11 3 TIN0 to TIN1, TIN16 to TIN17 TIN48 to TIN49 *2: n = 0:unit.0 to unit.2, n = 1:unit.8 to unit.10 *3: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.10 *4: n = 0:ch.0 to ch.1, n = 1:ch.16 to ch.17 - Timer input timing PPGx_TIN1 ICUx_IN0/1 FRTx_TEXT TINx Document Number: 002-10635 Rev. *H tTIWH VIH tTIWL VIH VIL VIL Page 221 of 322 S6J3310/20/30/40 Series 9.1.4.8 QPRC timing (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10 %, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Symbol Pin Name Conditions AIN pin "H" width AIN pin "L" width BIN pin "H" width BIN pin "L" width tAHL tALL tBHL tBLL - Time from AIN pin "H" level to BIN rise tAUBU Time from BIN pin "H" level to AIN fall tBUAD Time from AIN pin "L" level to BIN fall tADBD Time from BIN pin "L" level to AIN rise tBDAU Time from BIN pin "H" level to AIN rise tBUAU AIN8 to AIN9 AIN8 to AIN9 BIN8 to BIN9 BIN8 to BIN9 AIN8 to AIN9, BIN8 to BIN9 AIN8 to AIN9, BIN8 to BIN9 AIN8 to AIN9, BIN8 to BIN9 AIN8 to AIN9, BIN8 to BIN9 AIN8 to AIN9, BIN8 to BIN9 AIN8 to AIN9, BIN8 to BIN9 AIN8 to AIN9, BIN8 to BIN9 AIN8 to AIN9, BIN8 to BIN9 ZIN8 to ZIN9 ZIN8 to ZIN9 AIN8 to AIN9, BIN8 to BIN9, ZIN8 to ZIN9 AIN8 to AIN9, BIN8 to BIN9, ZIN8 to ZIN9 Time from AIN pin "H" level to BIN fall tAUBD Time from BIN pin "L" level to AIN fall tBDAD Time from AIN pin "L" level to BIN rise tADBU ZIN pin "H" width ZIN pin "L" width tZHL tZLL Time from determined ZIN level to AIN/BIN rise and fall tZABE Time from AIN/BIN rise and fall time to determined ZIN level tABEZ Document Number: 002-10635 Rev. *H Value Min Max Unit Remarks PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 4tCLK_LCP1 A 4tCLK_LCP1 - ns A 100 ns PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 QCR:CGSC = "0" QCR:CGSC = "0" QCR:CGSC = "1" QCR:CGSC = "1" Page 222 of 322 S6J3310/20/30/40 Series tALL tAHL AIN tAUBU tADBD tBUAD tBDAU BIN tBHL tBLL tBLL tBHL BIN tBUAU tBDAD tAUBD tADBU AIN tAHL Document Number: 002-10635 Rev. *H tALL Page 223 of 322 S6J3310/20/30/40 Series ZIN ZIN AIN/BIN Document Number: 002-10635 Rev. *H Page 224 of 322 S6J3310/20/30/40 Series 9.1.4.9 Trigger Input (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, Vcc5 = DVcc = 5.0 V 10 %, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = DVSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Parameter Input pulse width - Symbol Pin Name Conditions EINT0 to EINT23 ADTRG0 to ADTRG1 EINT0 to EINT23 - tTRGH, tTRGL - Value Min 100 5tCLK_LCP1A 100 1 Max - Unit Remarks ns - ns - s 5tCLK_LCP1A 100 ns 5tCLK_LCP1A <100 ns Stop mode Trigger input timing tTRGH EINTx ADTRGx VIH Document Number: 002-10635 Rev. *H tTRGL VIH VIL VIL Page 225 of 322 S6J3310/20/30/40 Series 9.1.4.10 NMI Input (TA: Recommended operating conditions, Vcc5 = 5.0 V 10 %, VSS = 0.0 V) Parameter Symbol Pin Name Conditions tNMIL NMIX - Input pulse width - Value Min 300 Max - Unit Remarks ns NMIX input timing tNMIL NMIX VIH VIH VIL Document Number: 002-10635 Rev. *H VIL Page 226 of 322 S6J3310/20/30/40 Series 9.1.4.11 Low Voltage Detection (External Voltage) Low-voltage detection (external low-voltage detection) (TA: Recommended operating conditions, VSS = AVSS = 0.0 V) Parameter Supply voltage range Symbol Pin Name Conditions VDP5 VCC5 - VDP3 VCC3 VCC5 Detection voltage (before trimming) Min 3.5 *3 Value Typ - Max 5.5 *3 2.7 *4 - 3.6 *4 - 2.7 - 3.6 *1 3.6 *3 4.0 *3 4.4 *3 *4 *4 *4 *1 *5 2.3 2.6 2.9 Unit V V V VDLBT *1 *5 2.3 2. 6 2.9 *1 3.86 *3 4.0 *3 4.14 *3 *1 *5 2.51 *4 2.6 *4 2.69 *4 VCC3 *1 *5 2.51 2.6 2.69 V VCC5 - - 100 - mV VCC3 VCC5 Detection voltage (after trimming) VDLAT Hysteresis width VHYS Remarks V V When powersupply voltage falls and detection level is set initially When powersupply voltage falls and detection level is set initially Typ 3.5 % When powersupply voltage rises Low-voltage Td 40 s detection time Power supply VCC5 -2 2 V/ms *2 voltage regulation *1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: Please suppress the change of the power supply within the range of the power-supply voltage regulation to do a low-voltage detection by detecting voltage (VDL) *3: For S6J33xxxSx or S6J33xxxUx or S6J33xxxTx or S6J33xxxVx option. *4: For S6J33xxxAx or S6J33xxxBx or S6J33xxxCx or S6J33xxxDx or S6J33xxxEx or S6J33xxxFx or S6J33xxxGx or S6J33xxxHx option. *5: These LVD settings cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage (2.7 V). Notes: - The detection/release threshold values of following LVD channels are potentially below supply range defined in 9.1.2 Recommended Operating Condition. LVDH1 (VCC5) LVDH2 (VCC3) - - - Please use these LVD channels with your own risk. Please monitor the external power supplies on the PCB if needed. For S6J33xxxSC or S6J33xxxUC or S6J33xxxTC or S6J33xxxVC options: Depending on the threshold setting, LVDH1 can always detect VCC5 low voltage before the supply drops below the level defined in 9.1.2 Recommended Operating Condition. Please refer to S6J3300 series Hardware Manual for available list of LVDH1 threshold settings. Document Number: 002-10635 Rev. *H Page 227 of 322 S6J3310/20/30/40 Series Low-voltage detection (1.15 V power supply low-voltage detection) (TA: Recommended operating conditions, VSS = AVSS = 0.0 V) Parameter Min Value Typ Max - 1.09 - 1.21 V VCC12 *1 *2 0.7125 0.8125 0.9125 V VRDLAT VCC12 *1 *2 0.7841 0.8125 0.8410 V VRHYS - - - 75 - mV Symbol Pin Name Conditions Supply voltage range VRDP12 VCC12 Detection voltage (before trimming) * VRDLBT Detection voltage (after trimming) Hysteresis width Unit Remarks When powersupply voltage falls When powersupply voltage falls Typ 3.5 % When powersupply voltage rises Low-voltage TRd 30 s detection time *1: If the power fluctuation time is less than the low-voltage detection time (TRd) and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range. *2: These LVD settings cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage (1.09 V). Notes: - The detection/release threshold values of LVDL2 channel is potentially below supply range defined in 9.1.2 Recommended Operating Condition. - - Please use this LVDL2 channel with your own risk. Please monitor the external power supplies on the PCB if needed. Document Number: 002-10635 Rev. *H Page 228 of 322 S6J3310/20/30/40 Series 9.1.4.12 Low Voltage Detection (Internal Voltage) Low-voltage detection (internal low-voltage detection for LVDL0) (TA: Recommended operating conditions, VSS = AVSS = 0.0 V) Parameter Supply voltage range Min Value Typ Max 1.05 - 1.21 Symbol Pin Name Conditions VRDP5 - - 0.75 0.85 0.95 V - 75 - mV Detection voltage VRDL - *1 *2 Hysteresis width VRHYS - - Unit Remarks V When powersupply voltage falls When powersupply voltage rises Low-voltage *3 TRd 30 s detection time *1: If the power fluctuation time is less than the low-voltage detection time (TRd) and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range. *2: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage (1.05 V). *3: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may occur or be canceled. Notes: - The detection/release threshold values of LVDL0 channel is potentially below supply range defined in 9.1.2 Recommended Operating Condition. Low-voltage detection (internal low-voltage detection for LVDL1) (TA: Recommended operating conditions, VSS = AVSS = 0.0 V) Parameter Min Value Typ Max - 1.05 - 1.21 V - *1 *2 0.775 0.875 0.975 V VRDLAT - *1 *2 0.844 0.875 0.906 V VRHYS - - - 75 - mV Symbol Pin Name Conditions Supply voltage range VRDP5 - Detection voltage (before trimming) VRDLBT Detection voltage (after trimming) Hysteresis width Unit Remarks When powersupply voltage falls When powersupply voltage falls Typ 3.5 % When powersupply voltage rises Low-voltage *3 TRd 30 s detection time *1: If the power fluctuation time is less than the low-voltage detection time (TRd) and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range. *2: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage (1.05 V). *3: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may occur or be canceled. Notes: - The detection/release threshold values of LVDL1 channel is potentially below supply range defined in 9.1.2 Recommended Operating Condition. Document Number: 002-10635 Rev. *H Page 229 of 322 S6J3310/20/30/40 Series 9.1.4.13 High Current Output Slew Rate (TA: Recommended operating conditions, VCC5,VCC53,DVCC = 5.0 V 10 %, VCC3 = 3.3 V 0.3 V, VCC12 = 1.15 V 0.06 V, VSS = DVSS = AVSS = 0.0 V) Parameter Output rise / fall time Symbol Pin Name Conditions tR2,tF2 P1_17 to P1_31, P2_00 to P2_08 - Min Value Typ Max 15 - 100 Unit Remarks ns Load capacitance 85 pF VH=VOL8+0.9 x (VOH8-VOL8) VL=VOL8+0.1 x (VOH8-VOL8) Document Number: 002-10635 Rev. *H Page 230 of 322 S6J3310/20/30/40 Series 9.1.4.14 Display Controller (1) Display Controller0 Timing (TTL Mode) (TA: Recommended operating conditions, Vcc53 = 5.0 V 10 %, 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Clock Cycle Output delay from DSP0_CLK Symbol Pin Name Conditions tDC0CYC DSP0_CLK (CL = 20 pF, IOL = -15 mA, IOH = 15 mA), |tDC0D| Output data valid time tDC0V DSP0_R7-0 DSP0_G7-0 DSP0_B7-0 DSP0_EN DSP0_HSYN C DSP0_VSYN C DSP0_R7-0 DSP0_G7-0 DSP0_B7-0 DSP0_EN DSP0_HSYN C DSP0_VSYN C Value Unit Min Max 25 - ns - 3.2 ns 21.8 - ns Remarks (CL = 20 pF, IOL = -5 mA, IOH = 5 mA) tDC0CYC - 3.3 ns+0.1 ns Notes: This is Target Spec. DSP0_CLK VOH VOH tDC0V tDC0D DSP0_DATA0_11-0 DSP0_DATA1_11-0 DSP0_CTRL11-0 Document Number: 002-10635 Rev. *H valid Page 231 of 322 S6J3310/20/30/40 Series 9.1.4.15 External Bus Interface Timing Clock Output Timing (TA: Recommended operating conditions, Vcc53 = 5.0 V 10 %, VSS = 0.0 V) (External load capacitance 16 pF) Parameter Symbol Pin Name Cycle time Clock high width *1 tCYC tCHCL MCLK MCLK Clock low width *2 tCLCH MCLK Conditions 2 mA is selected in ODR bit in PPC_PCFG R register. Value Min 62.5 dHtcyc - 7 Max dHtcyc + 7 dLtcyc - 7 dLtcyc + 7 Unit Remarks ns ns ns *1: If division-ratio is even value, dH is equivalent to 0.5. Otherwise, dH is calculated as the following. dH = The number rounding "division-ratio x 0.5" down to the nearest integer / division-ratio division-ratio is multiplication value among SYSDIV bit, HPMDIV bit and EXTBUSDIV bit setting. ex). Setting SYSDIV to 1-division, HPMDIV to 7-division, EXTBUSDIV to 1-division, dH is calculated as 0.429. *2: If division-ratio is even value, dL is equivalent to 0.5. Otherwise, dL is calculated as the following. dL = The number rounding "division-ratio x 0.5" up to the nearest integer / division-ratio division-ratio is multiplication value among SYSDIV bit, HPMDIV bit and EXTBUSDIV bit setting. ex). Setting SYSDIV to 1-division, HPMDIV to 7-division, EXTBUSDIV to 1-division, dL is calculated as 0.571. - Clock output timing Document Number: 002-10635 Rev. *H Page 232 of 322 S6J3310/20/30/40 Series Common Timing between Read and Write (TA: Recommended operating conditions, Vcc53 = 5.0 V 10 %, VSS = 0.0 V) (External load capacitance 16 pF) Parameter Cycle time (without MRDY) Symbol tCYC Cycle time (with MRDY) tCYC CS delay time tCSO Pin Name MCLK MCLK Address delay time RDY setup time tRDYS MCLK, MCSX0 to MCSX3 MCLK, MAD00 to MAD23 MCLK, MRDY RDY hold time tRDYH MCLK, MRDY tAO Conditions Value Min Max 62.5 2 mA is selected in ODR bit in PPC_PCFGR register. "CMOS Schmitt input" and "Disable noise filter" are selected in PPC_PCFGR register. - Unit Remarks ns 62.5 - ns 0.5 18 ns 0.5 18 ns 21 - ns 0 - ns If using MRDY, set MCLK to 20 MHz or less. Notes: This is Target Spec. - External bus I/F common timing Document Number: 002-10635 Rev. *H Page 233 of 322 S6J3310/20/30/40 Series Read Timing (TA: Recommended operating conditions, Vcc53 = 5.0 V 10 %, VSS = 0.0 V) (External load capacitance 16 pF) Parameter Symbol Data setup time tDSR Data hold time tDHR MOEX delay time tRDO Pin Name MOEX, MDATA00 to MDATA15 MOEX, MDATA00 to MDATA15 MCLK, MOEX Conditions "CMOS Schmitt input" and "Disable noise filter" are selected in PPC_PCFGR register. 2 mA is selected in ODR bit in PPC_PCFGR register. Value Min Max 21+tcy Unit - ns 0 - ns 0.5 18 ns c Remarks Notes: This is Target Spec. - External bus I/F read timing Document Number: 002-10635 Rev. *H Page 234 of 322 S6J3310/20/30/40 Series Write Timing (TA: Recommended operating conditions, Vcc53 = 5.0 V 10 %, VSS = 0.0 V) (External load capacitance 16 pF) Parameter Symbol MWEX delay time tWEO Byte mask delay time tWRO Data delay time tDO Data delay time (Hi-Z output) tDOZ Pin Name MCLK, MWEX MCLK, MDQM0 to MDQM1 MCLK, MDATA00 to MDATA15 MCLK, MDATA00 to MDATA15 Conditions 2 mA is selected in ODR bit in PPC_PCFGR register. Value Min Max 0.5 18 Unit Remarks ns 0.5 18 ns 0.5 18 ns - 18 ns Notes: This is Target Spec. - External bus I/F write timing Document Number: 002-10635 Rev. *H Page 235 of 322 S6J3310/20/30/40 Series 9.1.4.16 DDR-HSSPI (1) DDR-HSSPI Interface Timing (SDR Mode) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter HSSPI clock cycle M_SCLK -> delayed sample clock M_SDATA -> M_SLCK Input setup time M_SLCK -> M_SDATA Input hold time M_SCLK -> M_SDATA Output delay time M_SCLK -> M_SDATA Output hold time Symbol Pin Name Conditions Value Min 10 20 Max - Unit ns when Quad Page Program tcyc M_SCLK0 tspcnt - 0 31.5 ns tisdata M_SDATA0_0-3 M_SDATA1_0-3 *1 - ns tihdata M_SDATA0_0-3 M_SDATA1_0-3 *1 - ns toddata M_SDATA0_0-3 M_SDATA1_0-3 - tcyc/2 + 2 ns tohdata M_SDATA0_0-3 M_SDATA1_0-3 tcyc/2 - 3 - ns - ns - ns (CL = 20 pF, IOL = -10 mA, IOH = 10 mA), M_SCLK -> M_SSEL Output delay time todsel M_SSEL0, 1 12.00+(SS 2CD+0.5)* tcyc M_SCLK -> M_SSEL Output hold time tohsel M_SSEL0, 1 tcyc - 2 Remarks Notes: This is Target Spec. - SS2CD [1:0] should be configured as 01, 10, or 11. - For *1, the delay of the delay sample clock can be configured (DLP function). Document Number: 002-10635 Rev. *H Page 236 of 322 S6J3310/20/30/40 Series tcyc VOH VOH G_SCLK0 M_SCLK0 tspcnt delayed sample clock VOH VIH G_SDATA0_0-3, M_SDATA0_0-3, M_SDATA1_0-3 G_SDATA1_0-3 VIH valid VIL (input timing) tisdata tihdata VIL toddata tohdata VOH G_SDATA0_0-3, M_SDATA0_0-3, M_SDATA1_0-3 G_SDATA1_0-3 VOH valid VOL VOL (output timing) todsel tohsel VOH GSSEL0, 1 M_SSEL0,1 (output timing) VOH valid VOL VOL (2) DDR-HSSPI Interface Timing (DDR Mode) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter HSSPI clock cycle M_SCLK -> delayed sample clock M_SDATA -> M_SLCK Input setup time M_SLCK -> M_SDATA Input hold time M_SCLK -> M_SDATA Output delay time M_SCLK -> M_SDATA Output hold time M_SCLK -> M_SSEL Output delay time M_SCLK -> M_SSEL Output hold time Symbol Pin Name tcyc M_SCLK0 Conditions tspcnt Min 12.5 Value Max - Unit ns 0 31.5 ns tisdata M_SDATA0_0-3 M_SDATA1_0-3 *1 - ns tihdata M_SDATA0_0-3 M_SDATA1_0-3 *1 - ns toddata M_SDATA0_0-3 M_SDATA1_0-3 - tcyc/4 + 1.5 ns tohdata M_SDATA0_0-3 M_SDATA1_0-3 Tcyc/4 - 1.0 - ns todsel M_SSEL0, 1 15.75+(SS2C D+0.5)*tcyc - ns tohsel M_SSEL0, 1 0.75*tcyc 2.0 - ns (CL = 20 pF, IOL = -10 mA, IOH = 10 mA), Remarks Notes: This is Target Spec. Document Number: 002-10635 Rev. *H Page 237 of 322 S6J3310/20/30/40 Series - - SS2CD [1:0] should be configured as 01, 10, or 11. For *1, the delay of the delay sample clock can be configured (DLP function) tcyc M_SCLK0 G_SCLK0 VOH VOH VOL tspcnt delayed sample clock VOH VIH tisdata tihdata G_SDATA0_0-3, M_SDATA0_0-3, M_SDATA1_0-3 G_SDATA1_0-3 (input timing) G_SDATA0_0-3, M_SDATA0_0-3, M_SDATA1_0-3 G_SDATA1_0-3 (output timing) VIH valid VIL toddata VIL toddata tohdata VOH valid VOL todsel VOH valid VOL tohsel VOH GSSEL0, 1 M_SSEL0,1 VOH valid (output timing) VOL Document Number: 002-10635 Rev. *H tohdata VOL Page 238 of 322 S6J3310/20/30/40 Series 9.1.4.17 Hyper BUS (1) Hyper Bus Write Timing (HyperFlash) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Hyper Bus clock cycle CS -> CK Chip Select setup time DQ -> CK Input setup time CK -> DQ Input hold time CK -> CS Chip select hold time Symbol Pin Name Conditions tCKCYC M_CK tCSS M_CS#_1,2 Min (CL = 20 pF, IOL = -10 mA, IOH = 10 mA), Value Max Unit 10.0 - ns tCKCYC -2.0 - ns 1.25 - ns tIS M_DQ7-0 tIH M_DQ7-0 1.25 - ns tCSH M_CS#_1,2 tCKCYC/2 - ns Remarks Notes: This is Target Spec tCSHI G_CS#_1,2 M_CS#_1,2 VOH VOL tCKCYC tCSS VOH G_CK M_CK tCSH tCSS VOL tDSV tDSZ G_RWDS M_RWDS tIS G_DQ7~0 M_DQ7~0 CA0 47-40 CA0 3932 CA1 31-24 CA1 23-16 tIH VIH CA2 15-8 CA2 7-0 Dn 15-8 Dn 7-0 VIL Document Number: 002-10635 Rev. *H Page 239 of 322 S6J3310/20/30/40 Series (2) Hyper Bus Write Timing (HyperRAM) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name Hyper Bus clock tCKCYC cycle CS -> CK Chip Select setup tCSS time DQ -> CK tIS Input setup time CK -> DQ tIH Input hold time CK -> CS tCSH Chip select hold time RWDS-> CK tDMV Data Mask Valid CK -> RWDS Refresh Indicator tRIV Valid CK -> RWDS (Hi-z) Refresh Indicator tRIH Hold Notes: This is Target Spec. Conditions Value Unit Min Max M_CK 10.0 - ns M_CS#_1,2 tCKCYC - 2.0 - ns M_DQ7-0 1.25 - ns 1.25 - ns tCKCYC/2 - ns M_RWDS 1 - ns M_RWDS - 6 ns M_RWDS 0 - ns M_DQ7-0 (CL = 20 pF, IOL = -10 mA, IOH = 10 mA), M_CS#_1,2 Remarks tCSM tRWR G_CS#_1,2 M_CS#_1,2 G_CK M_CK tCSHI tPO VIH VIL tCSS tCKCYC tCSH VOH tCSS VOL tRIH tRIV tDMV tIS VOH G_RWDS M_RWDS tIH VOL tIS G_DQ7~0 M_DQ7~0 tIH VIH CA0 47-40 CA0 3932 CA1 31-24 CA1 23-16 CA2 15-8 CA2 7-0 Dn 15-8 Dn 7-0 VIL Document Number: 002-10635 Rev. *H Page 240 of 322 S6J3310/20/30/40 Series (3) Hyper Bus Read Timing (HyperFlash) (TA: Recommended operating conditions, Vcc3 = 3.3 V 3.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name Hyper Bus clock tRDSCYC cycle CS -> CK Chip Select setup tCSS time DQ -> CK tIS Setup time CK -> DQ tIH Hold time CK -> CS tCSH Chip select hold time RDS> DQ tDSS Setup time RDS> DQ tDSH Hold time Notes: This is Target Spec. Conditions Value Unit Min Max M_CK 10.0 - ns M_CS#_1,2 tRDSCYC -2.0 - ns 1.25 - ns 1.25 - ns M_CS#_1,2 tRDSCYC / 2 - ns M_DQ7-0 -0.8 - ns M_DQ7-0 -0.8 - ns M_DQ7-0 (CL = 20 pF, IOL = -10 mA, IOH = 10 mA), M_DQ7-0 Remarks tCSHI tACC G_CS#_1,2 M_CS#_1,2 VOH VOL tCSH tCSS G_CK M_CK VOH VOL tDSV tDQLZ tCKDS tRDSCYC G_RWDS M_RWDS tDSZ tOZ VOH tIH tIS tDSH VIH G_DQ7~0 M_DQ7~0 tCSS CA0 47-40 CA0 3932 CA1 31-24 CA1 23-16 CA2 15-8 VIL Document Number: 002-10635 Rev. *H tDSS VOH CA2 7-0 Dn 15-8 Dn 7-0 Dn+1 15-8 Dn+1 7-0 VOL Page 241 of 322 S6J3310/20/30/40 Series (4) Hyper Bus Read Timing (HyperRAM) (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name Hyper Bus clock tRDSCYC cycle CS -> CK Chip Select setup tCSS time DQ -> CK tIS Setup time CK -> DQ tIH Hold time CK -> CS tCSH Chip select hold time RWDS> DQ (valid) tDSS Setup time RWDS> DQ (invalid) tDSH Hold time CK -> RWDS Refresh Indicator tRIV Valid CK -> RWDS (Hi-z) Refresh Indicator tRIH Hold Notes: This is Target Spec. Value Conditions Max M_CK 10.0 - ns M_CS#_1,2 tRDSCYC -2.0 - ns M_DQ7-0 1.25 - ns M_DQ7-0 1.25 - ns tRDSCYC /2 - ns -0.8 - ns M_DQ7-0 -0.8 - ns M_RWDS - 6 ns M_RWDS 0 - ns M_CS#_1,2 M_DQ7-0 (CL = 20 pF, IOL = -10 mA, IOH = 10 mA), tCSM tRWR G_CS#_1,2 M_CS#_1,2 G_CK M_CK Remarks tCSHI tPO VOH VOL tCSS tCSH VOH VOL tCSS tCKDS tRIH tRIV tDQLZ tDSZ tRDSCYC tOZ VOH G_RWDS M_RWDS tIS tIH VIH G_DQ7~0 M_DQ7~0 Unit Min CA0 47-40 CA0 3932 CA1 31-24 CA1 23-16 CA2 15-8 CA2 7-0 VIL Document Number: 002-10635 Rev. *H tDSH VOH Dn 15-8 tDSS Dn 7-0 Dn+1 15-8 Dn+1 7-0 VOL Page 242 of 322 S6J3310/20/30/40 Series 9.1.4.18 Ethernet AVB (1) Ethernet Receive Timing (TA: Recommended operating conditions, Vcc53 = Vcc3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name RXCLK cycle tRXCYC RX setup time tRXS RXCLK RXER RXDV RXD0-3 RXER RXDV RXD0-3 RX hold time tRXH Value Conditions Unit Remarks ns - - ns tRXCYC -30 ns - ns - Min 40.0 Max - 10.0 0 - Notes: This is Target Spec. tRXCYC RXCLK VIH VIH tRXS RXER RXDV RXD0-3 Document Number: 002-10635 Rev. *H tRXH VIH valid VIL Page 243 of 322 S6J3310/20/30/40 Series (2) Ethernet Transmit Timing (TA: Recommended operating conditions, Vcc53 = Vcc3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name TXCLK cycle COL/CRS input setup time COL/CRS input hold time tTXCYC TXCLK COL CRS COL CRS TXER TXEN TXD0-3 tCRXS tCRXH Tx delay time tTXD Conditions (CL = 20 pF, IOL = -5 mA, IOH = 5 mA), Value Unit Remarks ns - - ns - 0.5 - ns - 0.5 25 ns - Min 40.0 Max - 12.0 Notes: This is Target Spec. tTXCYC VIH VIH VIH VIH TXCLK tCRXS tCRXH VIH COL CRS valid VIL TXEN TXER TXDV TXD0-3 Document Number: 002-10635 Rev. *H tTXD tTXD VOH valid VOL Page 244 of 322 S6J3310/20/30/40 Series (3) MDIO Timing (TA: Recommended operating conditions, Vcc53 = Vcc3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol MDC cycle tMDCYC MDIO input setup tMDIS time MDIO input hold time tMDIH MDIO output delay tMDOD time Notes: This is Target Spec. Pin Name Conditions MDC MDIO (CL = 20 pF, IOL = -5 mA, IOH = 5 mA), MDIO MDIO Value Unit Min 400.0 Max - 100.0 - ns 0.0 - ns 10.0 190.0 ns Remarks ns - tMDCYC MDC VOH VOH VOH VOH VOL tMDIS tMDIH VIH MDIO (in) valid VIL tMDOD tMDOD VOH MDIO (out) valid VOL Document Number: 002-10635 Rev. *H Page 245 of 322 S6J3310/20/30/40 Series 9.1.4.19 MediaLB (1) MediaLB Input Timing (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions MLBCLK cycle tmckc MLBCLK MLBSIG, MLBDAT MLBSIG tdsmcf Input setup MLBDAT MLBSIG, MLBDAT MLBSIG tdhmcf Input hold MLBDAT Notes: This is Target Spec. - CLK_HAPP1B0 (internal) frequency > MLBCLK (external) frequency Min 40.0 Value Max - Unit Remarks ns 1.0 - ns 4.0 - ns - tmckc MLBCLK VIH VIH VIL tdsmcf tdhmcf VIH MLBDAT, MLBSIG VIH valid VIL VIL Input (2) MediaLB Output Timing (TA: Recommended operating conditions, Vcc3 = 3.3 V 0.3 V, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions MLBCLK cycle tmckc MLBCLK MLBSIG, MLBDAT MLBSIG (CL = 20 pF, tmcfdz output stop MLBDAT IOL = -6 mA, IOH = 6 mA), MLBSIG, MLBDAT MLBSIG tdout output delay MLBDAT Notes: This is Target Spec. - CLK_HAPP1B0 (internal) frequency > MLBCLK (external) frequency Min 40.0 Value Max - Unit Remarks ns - 26.5 - ns tmckc - tdout 0 13.5 ns - tmckc MLBCLK VIH VIH tdout tmcfdz VOH MLBDAT, MLBSIG valid VOL Document Number: 002-10635 Rev. *H VOH VOL Page 246 of 322 S6J3310/20/30/40 Series 9.1.4.20 Port Noise Filter (TA: Recommended operating conditions, VCC5,VCC53,DVCC5 = 5.0 V 10 %, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions Min Value Max Width for input ALL GPIO 17 removal * Input pulse width less than at least 17 nm is removed when Port noise filter is enabled. Document Number: 002-10635 Rev. *H Unit ns Remarks - Page 247 of 322 S6J3310/20/30/40 Series 9.1.4.21 LCD Bus I/F (TA: Recommended operating conditions, Vcc53 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = 0.0 V, VCC12 = 1.15 V 0.06 V) Value Parameter Symbol Pin Name Conditions Unit Remarks Min Max Clock cycle time tCLK WR#, RD# 12.5 ns - (CL = 20 pF, Signal-to-Signal tUNCERT CS# 5.0 ns - uncertainty IOL = -5 mA, Output to input IOH = 5 mA), tOUT2IN LCDD0-17 25.0 ns - duration tUNCERT CS# WR#, RD# n x tCLK LCDD (write) For setup, active and hold calculation the following has to be considered: -> signal-to-signal uncertainty has to be added to tAW, tAH, tDS, tDH -> max_input_delay and max_output_delay has to be added to tACC LCDD (read) tOUT2IN + tACC Note: - In order to calculate interface timing, refer to the LCD controller specification of the external display for the required AC characteristics and S6J3300 Series Hardware Manual. Document Number: 002-10635 Rev. *H Page 248 of 322 S6J3310/20/30/40 Series 9.1.4.22 Power and Reset Sequence VCC5 and VCC12 sequence (TA: Recommended operating conditions, VSS = 0.0 V) Parameter Wait time from LVDH1 level detection to falling VCC12 VCC12 stabilization time during power-on Value Symbol Pin Name Conditions tFV12 VCC12 - 0.6 - ms - tRV12 VCC12 - - 14.2 ms - VCC5 Min Unit Max Remarks VDLAT tFV12 PSC_1 VOH7 tRV12 VCC12 VRDLAT RSTX VRDLBT+VRHYS No timing specification of VCC12 and RSTX Note: - VDLAT, VRDLAT, VRDLBT and VRHYS are referred to "9.1.4.11 Low Voltage Detection (External Voltage)". VOH7 is referred to "9.1.3 DC Characteristics". - - LVDH1 reset need to be "always enable". For details, see the TraveoTM Platform Hardware Manual. The above sequence needs not to be applied in the following cases the application enters PSS mode: "VCC12 is controlled by PSC_1 at entry and exit from PSS mode" (Normal Sequence). Document Number: 002-10635 Rev. *H Page 249 of 322 S6J3310/20/30/40 Series Case1) "PSC_1 H --> L --> H transition by VCC5" Note: - RSTX controlled by VCC5. - - - VCC12 and AVCC5 controlled by PSC_1. VCC53, VCC3, AVCC3_DAC and DVCC controlled by PSC_1. Can be controlled by VCC5 GPIO also. VDLAT, VDLBT and VHYS are referred to "9.1.4.11 Low Voltage Detection (External Voltage)". VRDLAT, VRDLBT and VRHYS are referred to "9.1.4.12 Low Voltage Detection (Internal Voltage)". VOH7, VIL9 and VIH9 are referred to "9.1.3 DC Characteristics". tRV12, tFV12RST and tRV12RST are referred to "9.1.4.22 Power and Reset Sequence". *1: Battery Disconnect: All supplies fall together. *2: VCC12 can be fully depleted or not full depleted. *3: DVCC, VCC53 and VCC3 can start before or after VCC12. *4:VCC5 is higher than level detection voltage: VDLAT+VHYS VCC5 is lower than level detection voltage: VDLBT+VHYS VDLAT, VDLBT and VHYS are referred to "9.1.4.11 Low Voltage Detection (External Voltage)". *5:VCC5 is higher than level detection voltage: VRDLAT+VRHYS VCC5 is lower than level detection voltage: VRDLBT+VRHYS VRDLAT, VRDLBT and VRHYS are referred to "9.1.4.11 Low Voltage Detection (External Voltage)". Document Number: 002-10635 Rev. *H Page 250 of 322 S6J3310/20/30/40 Series Case2-1) "PSC_1 H --> L --> H transition by User Program" VCC5 > VDLAT VCC5 PSC_1 VCC12 RSTX Transition VRDLAT+VRHYS VRDLAT No timing specification of VCC12 and RSTX PSC_1=L VCC12=OFF PSC_1 =H VCC12=ON Note: - VCC12 controlled by PSC_1. - VCC12 can be fully deplete Document Number: 002-10635 Rev. *H Page 251 of 322 S6J3310/20/30/40 Series Case2-2) "PSC_1 H --> L --> H transition by User Program" Note: - VCC12 and AVCC5 controlled by PSC_1. - VCC53, VCC3, AVCC3_DAC and DVCC controlled by PSC_1. Can be controlled by VCC5 GPIO also. *1: VCC12 can be fully depleted or not full depleted. Document Number: 002-10635 Rev. *H Page 252 of 322 S6J3310/20/30/40 Series VCC12 and RSTX Sequence (TA: Recommended operating conditions, VSS = 0.0 V) Parameter RSTX -> VCC12 fall interval time VCC12 -> RSTX rise interval time Symbol tFV12RST tRV12RST Pin Name Conditions VCC12, RSTX VCC12, RSTX - Min Value Max Unit Remarks 5 - us - 35 - us - VCC5 > VDLAT *1 VCC5 H PSC_1 tFV12RST VCC12 RSTX VRDLAT tRV12RST VRDLAT+VRHYS VIL9 VIH9 Note: - If the sequence given in "VCC5 and VCC12 sequence" cannot be applied, this sequence can be applied. - VDLAT VRDLAT, VRDLAT and VRHYS are referred to "9.1.4.11 Low Voltage Detection (External Voltage)". VIL9 and VIH9 is referred to "9.1.3 DC Characteristics". - - This sequence is applied in case of VCC12 power on/off and assertion of RSTX is controlled by application. This sequence is applied under the condition VCC5 > VDLAT and PSC_1 = H. Document Number: 002-10635 Rev. *H Page 253 of 322 S6J3310/20/30/40 Series RSTX and MODE Sequence (TA: Recommended operating conditions, Vcc5 = 5.0 V 10 % / 3.3 V 0.3 V, VSS = 0.0 V) Parameter RSTX -> MODE delay time Reset and mode input time Width for reset and mode input removal Symbol Pin Name Conditions tMOD RSTX, MODE - tRSTMDL RSTX, MODE - Min Value Max Unit Remarks -5 5 ns - 10 - us - 1 - us - 0.7*VCC5 RSTX MODE RSTX tRSTMDL 0.7*VCC5 MODE 0.2*VCC5 0.2*VCC5 tMOD Note: - If the sequence given in "VCC5 and VCC12 sequence" and "VCC12 and RSTX Sequence" cannot be applied, this sequence can be applied. - Connect RSTX signal and MODE signal outside of the MCU and shorten the trace length between MCU and these two signal lines. - The following assumptions are made with regard to the workaround described above. 1. After the reset the MCU state is equivalent to the "cold start state" usually reached by power-on-reset. 2. Debugger interface and PC writer interface are not enabled. 3. The RAM retention cannot be guaranteed when applying this workaround 4. Pin PSC_1 will be driven low while RSTX is active (RSTX at low level) Document Number: 002-10635 Rev. *H Page 254 of 322 S6J3310/20/30/40 Series 9.1.5 A/D Converter 9.1.5.1 Electrical Characteristics (TA: Recommended operating conditions, VCC5 = 5.0 V 10 %, VCC12 = 1.15 V 0.06 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name - - Resolution Total Error - - Integral Non linearity - - Differential Non linearity - - VZT AN0 to AN63 Zero transition voltage Full-scale transition voltage VFST Sampling time Compare time tSMP tCMP - A/D conversion time Resumption Time tCNV - Analog port input current IAIN AN0 to AN30, AN32 to AN38 AN31, AN39 to AN63 AN0 to AN63 Analog input voltage Reference voltage VAIN AN0 to AN63 Min - Conditions Typ - Max 12 bit - - - 12 *6 LSB *3 - - 15 *7 4.0 LSB LSB - AVRL -11.5LSB *6 AVRL -14.5LSB *7 AVRH -13.5LSB *6 AVRH -16.5LSB *7 0.3 0.8 - LSB *4 - 1.9 AVRL +12.5LSB *6 AVRL +15.5LSB *7 AVRH +10.5LSB *6 AVRH +13.5LSB *7 26 1. 1 - - -1.0 - Unit Remarks *4 V V *5 V V - s s *1 1 s s *1 - 1.0 A -2.0 - 2.0 A AVRL - AVRH V - 4.5 *6 - 5.5 *6 3.0 *7 - 3.6 *7 V AVcc5 AVRH - *1 - AVSS VAIN AVCC5 AVRH AVRH5 AVRL AVRL5/AVSS - 0.0 - V AVCC5 - 500 1.0 900 (Target) 200 (Target) A A 1 unit IA IAH Power supply current IR AVRH5 IRH Variation between channels *1: Time per channel - AN0 to AN63 *6 *2 - 1.0 1.0 3.5 (Target) 2.5 (Target) *7 mA mA 1 unit 1 unit - - 9.0 (Target) A *2 - - 4.0 LSB - *2: Definition of the power supply current (when Vcc5 = AVcc5 = 5.0 V) while the A/D converter is not operating and in stop mode *3: Total Error is a comprehensive static error that includes the linearity after trimming by software. 1 LSB = (AVRH-AVRL)/4096 *4: 1 LSB = (VFST-VZT)/4094 *5: 1 LSB = (AVRH-AVRL)/4096 *6: For S6J33xxxSx or S6J33xxxUx or S6J33xxxTx or S6J33xxxVx option. *7: For S6J33xxxAx or S6J33xxxBx or S6J33xxxCx or S6J33xxxDx or S6J33xxxEx or S6J33xxxFx or S6J33xxxGx or S6J33xxxHx option. Document Number: 002-10635 Rev. *H Page 255 of 322 S6J3310/20/30/40 Series 9.1.5.2 Notes on A/D Converters About the Output Impedance of an External Circuit for Analog Input When the external impedance is too high, the analog voltage sampling time may become insufficient. In this case, we recommend attaching a capacitor (about 0.1 F) to an analog input pin. Analog input circuit model Comparator R Analog input Sampling ON C R C 12-bit A/D 3.9 kiloohms (max) 11.0 pF (max) Note: Use the numerical values provided here simply as a guide. Document Number: 002-10635 Rev. *H (4.5 V AVCC5 5.5 V) Page 256 of 322 S6J3310/20/30/40 Series 9.1.5.3 Glossary Resolution: Analog change that can be identified by an A/D converter Integral linearity error: Deviation of the straight line connecting the zero transition point ("0000 0000 0000" <--> "0000 0000 0001") and full-scale transition point ("1111 1111 1110" <--> "1111 1111 1111") from actual conversion characteristics includes zero transition error, full-scale transition error, and non linearity error. Differential linearity error: Deviation from the ideal value of the input voltage required for changing the output code by 1 LSB Total error: Difference between the actual value and the theoretical value. The total error Total error FFF FFE Actual conversion characteristics 1.5LSB {1 LSB (N - 1) + 0.5LSB} Digital output FFD VNT (Actually-measured value) 004 003 Actual conversion characteristics 002 (measured value) Ideal characteristics 001 0.5LSB AVRL Analog input Total error of digital output N = 1LSB (Ideal value) = AVRH VNT- {1 LSB x (N-1) + 0.5LSB} 1LSB AVRH - AVRL 4096 [LSB] [V] N: A/D converter digital output value. VZT (Ideal value) = AVRL + 0.5LSB[V] VFST (Ideal value) = AVRH - 1.5LSB[V] VNT: Voltage at which the digital output changes from "(N - 1)" to "N". Document Number: 002-10635 Rev. *H Page 257 of 322 S6J3310/20/30/40 Series Integral linearity error Differential linearity error Ideal characteristics FFE Actual conversion characteristics FFD {1 LSB (N - 1) + VZT} 004 003 002 N+1 VFST (measured value) Digital output Digital output FFF VNT (measured value) Actual conversion characteristics Ideal characteristics Actual conversion characteristics N N-1 V(N+1)T (measured VNT(measured value)value) (measured value) Actual conversion characteristics N-2 001 VZT (measured value) AVRL AVRH Analog input Integral linearity error of digital output N = Differential linearity error of digital output N = 1LSB = AVRL VNT- {1 LSB x (N-1) + VZT} 1LSB V(N+1)T- VNT 1LSB VFST - VZT Analog input AVRH [LSB] -1 LSB [LSB] [V] 4094 VZT: Voltage for which digital output changes from "0x000" to "0x001" VFST: Voltage for which digital output changes from "0xFFE" to "0xFFF". Document Number: 002-10635 Rev. *H Page 258 of 322 S6J3310/20/30/40 Series Audio DAC 9.1.6 9.1.6.1 Electrical Characteristics (TA: Recommended operating conditions, AVCC3_DAC = 3.3 V 0.3 V, VCC12 = 1.15 V 0.06 V, VSS = AVSS = 0.0 V) Parameter system clock frequency sampling clock Analog output load resistance *2 Analog output load capacitance *2 capacitance Analog output single-end output range (full scale) Analog output voltage (zero) Value Typ - 2.048 - - 8 - Max 18.43 2 48 - 20 - - k - - - - 100 pF - - 1.1 2.2 10 F - RL = 20 k CL = 100 pF - 0.673 AVCC3_DAC - VP-P - - - 0.5 AVCC3_DAC - V - - -82 -72 dB - 85 89 - dB - 83 86 - dB - 150 80 200 -33 250 dB dB - - -35 - dB - - -50 - dB - - -40 - dB - - -13 - dB - Pin Name Conditions *1 FCLKDA0 - fs - RL CL DAC_L DAC_R C_L C_R - DAC_L DAC_R - THD+N *3 - - SNR *3 - - Dynamic range *3 - - Out-of-Band Energy Channel Separation Output impedance - - PSRR Min Symbol - - signal frequency: 1 kHz LPF (fc: 20 kHz) signal frequency: 1 kHz LPF (fc: 20 kHz)-- -- A-weighting filter 20 kHz to 64 fs noise 50 Hz digital noise input: 1 kHz zero noise 20 kHz digital input: full scale sine Unit MH z kHz Remarks - Supply current AVCC3 2.2 3.2 mA normal operation _DAC Supply current AVCC3 100 A power-down _DAC *4 *6 Startup Time DAE 650 ms *1: All parameters specified fs = 44.1 kHz, system clock 256 fs and 16-bit data, RL-20 k, CL = 100 pF, unless otherwise noted. *2: Refer to notes *5 *3: These values do not include the noise caused by the analog power supply. (Refer to *7. Use examples) *4: 2.2 F is connected to C_L, C_R. *5: Load connection RL is connected to AVCC3_DAC /2 (Figure 9.1). If RL is connected to ground, the coupling capacitance must be inserted as shown in (Figure 9.3) Document Number: 002-10635 Rev. *H Page 259 of 322 S6J3310/20/30/40 Series Figure 9-1: Connection between RL and AVCC_DAC/2 (Example) DAC macro LOUT/ROUT RL :20K CL :100pF Vavd/2 *6: Start up time Figure 9-2: Startup Time Last Voltage AOUTS [V] 10mV EN [V] 0V VDD Startup Time 0V Time [sec] *Start up time can be calculated as follows. 1.Start up time (TYP) = 650[ms] (*4) 2.CCOM = 10 F x (1 /100) CCOM is a capacitor connected to Terminal C_L/C_R including capacitance variance. = Capacitance variance[%] 3.Start up time = Start up time (TYP) x (1) [ms] For example, CCOM = 2.42 F then = (2.42 F - 2.2 F)/2.2 F = 10[%] So, Start up time = 650 ms x (1+10/100) = 715[ms] Document Number: 002-10635 Rev. *H Page 260 of 322 S6J3310/20/30/40 Series *7 Use examples Figure 9-3: Coupling Capacitance (Example) Low Noise Regulator AVCC3DAC C1 C2 AVSS AVSS AVSS C_R DAC_R Post LPF / Buffer C_L DAC_L Post LPF / Buffer C3 C4 Notes: - C1: more than 10 F low ESR capacitors - - - C2: 0.1 F ceramic capacitors C3,C4: 2.2 F low ESR capacitors Impedance of each power line must be as low as possible. Notes: - When DAC is not used in your system, the related pins should be - - - AVCC3_DAC = GND and AVSS = GND C_L = OPEN and C_R = OPEN DAC_L = OPEN and DAC_R = OPEN Document Number: 002-10635 Rev. *H Page 261 of 322 S6J3310/20/30/40 Series 9.1.7 FLASH Memory 9.1.7.1 Electrical Characteristics Parameter Min Rating Typ Max Unit Remarks Large sector*1 Internal preprogramming time included 8 kB sector*1 Internal preprogramming time included 4 kB sector*2 Internal preprogramming time included - 120 180 ms - 120 180 ms - 120 180 ms 16-bit write time (Program) - 30 60 s System-level overhead time excluded*1 32-bit write time (Program) - 30 60 s System-level overhead time excluded*1 64-bit write time (Program) 256-bit write time (Program) Page mode write time (Program) 32-bit write time (Work) Erase count / Data retention time (Program) - 30 s System-level overhead time excluded*1 - 40 60 70 s System-level overhead time excluded*1 - 320 s System-level overhead time excluded*1 - 30 60 s 1,000/20 years - - - System-level overhead time excluded*2 Temperature at write/erase time Average temperature TA = +85 degrees Celsius - - - Sector erase time 1,000/20 years Erase count / 10,000/1 Data retention time (Work) 0 years 100,000/ 5 years *1: Guaranteed value for up to 1,000 erases 600 Temperature at write/erase time Average temperature TA = +85 degrees Celsius *2: Guaranteed value for up to 100,000 erases 9.1.7.2 Notes While the Flash memory is written or erased, shutdown of the external power (Vcc5) is prohibited. In the application system where Vcc5 might be shut down while writing or erasing, be sure to turn the power off by using an external voltage detection function. To put it concretely, after the external power supply voltage falls below the detection voltage (VDL), hold Vcc5 at 2.7 V or more within the duration calculated by the following expression: Td*1 [s] + ( 1 / FCRF*2[MHz] ) x 1029 + 25 [s] *1: See "9.1.4.11 Low Voltage Detection (External Voltage)" *2: See "9.1.4.1 Source Clock Timing" Document Number: 002-10635 Rev. *H Page 262 of 322 S6J3310/20/30/40 Series 10. Acronyms Acronym A/D converter ADC AHB AMBATM APB ATCM AXI B0TCM B1TCM BBU BDR BTL CAN CD CPU CR CRC CSV DAC DAP DED DMA DMAC EAM ECC ETM EXT-IRC FIQ FPU FRT GPIO HPM HW-WDT I/O I2S ICU IPCU IRC IRQ ISR JTAG LLPP LVD MCU MFS NF NMI Document Number: 002-10635 Rev. *H Description Analog digital converter Analog digital converter Advanced high performance bus Advanced microcontroller bus architecture Advanced peripheral bus TCM-A port Advanced extensible interface TCM B0 port TCM B1 port Bit banding unit Boot description record Bridge-tied load Control are network Clock domain Central processing unit CR Oscillator Cyclic redundancy check Clock supervisor Digital analog converter Debug access port Dual error detection Direct memory access DMA controller Exclusive access memory Error correction code Embedded trace macro External interrupt controller Fast interrupt request Floating point unit Free run timer General purpose I/O High performance matrix Hardware watchdog timer Input or output Inter-IC sound Input capture unit Inter-processor communication unit Interrupt controller Interrupt request Interrupt service routine Joint test action group Low latency peripheral port Low voltage detector Microcontroller unit Multi-function serial interface Noise filter Non maskable interrupt Page 263 of 322 S6J3310/20/30/40 Series Acronym OCU OSC PCM PLL PONR PPC PSS PWM RAM RIC ROM RTC RVD SCT SEC SECDED SHE SMC SMIX SRAM SWFG SW-WDT SYSC TCFLASH TCM TCRAM TPU UDC VIC VRAM WDR WDT WFG WorkFLASH Document Number: 002-10635 Rev. *H Description Output compare unit Oscillator Pulse coded module Phase locked loop Power on reset Port pin configuration Power saving state Pulse width modulation Random access memory Resource input configuration Read only memory Real time clock Low voltage detection and reset for RAM retention Source clock timer Single error correction Single error correction and dual error detection Secure Hardware Extension Stepper motor controller Sound mixer Static RAM Sound waveform generator Software watchdog timer System controller FLASH connected to TCM Tightly coupled memory RAM connected to TCM Timing protection unit Up-down counter Vectored interrupt controller Video RAM Watchdog description record Watchdog timer Waveform generator Work FLASH memory Page 264 of 322 S6J3310/20/30/40 Series 11. Ordering Information Part Number S6J331EKSESE20000 S6J332CKSDSE20000 S6J334CKSESE20000 S6J331EJSESE20000 S6J332EJBDSE20000 S6J332EJTDSE20000 S6J332EJBESE20000 S6J332EJTESE20000 S6J332DJEESE20000 S6J334BJDDSE20000 S6J334EJBESE20000 S6J334EJTESE20000 S6J334EJEESE20000 S6J334DJTESE20000 S6J334DJEESE20000 S6J334CJBESE20000 S6J334CJEESE20000 S6J334BJDESE20000 S6J334EJTCSE2000A S6J334EJEDSE2000A S6J332EHBESE20000 S6J334EHEESE20000 S6J334DHEESE20000 S6J334DHFESE20000 S6J334CHEESE20000 S6J334CHFESE20000 Document Number: 002-10635 Rev. *H Package 208-pin plastic TEQFP (LEW208) 208-pin plastic TEQFP (LEW208) 208-pin plastic TEQFP (LEW208) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 144-pin plastic TEQFP (LEX144, LEK144) 144-pin plastic TEQFP (LEX144, LEK144) 144-pin plastic TEQFP (LEX144, LEK144) 144-pin plastic TEQFP (LEX144, LEK144) 144-pin plastic TEQFP (LEX144, LEK144) 144-pin plastic TEQFP (LEX144, LEK144) Page 265 of 322 S6J3310/20/30/40 Series 12. Appendix 12.1 Application 1: JTAG Tool Connection This is an application example of JTAG tool connection. See the relevant application note 002-03898 in detail. Document Number: 002-10635 Rev. *H Page 266 of 322 S6J3310/20/30/40 Series 13. Major Changes Page Rev. *A 7 Section Change Results 2.Function List Revised CHIP-ID and Revision as below: 2.2Optional Error) Function Digit Revision Chip ID function S,U,T,V B 0x10120000 A,C,E,G B 0x1012A000 B,D,F,H B 0x10122000 Correct) 8 Function Digit Revision Chip ID S,U,T,V C 0x10122100 A,C,E,G C 0x10128100 B,D,F,H C 0x10120100 2.Function List Revised as below: 2.2Optional Error) TEQFP144 function Analog input port(12bit-ADC) AN4~7, AN10~11, AN14~15, AN19~20, AN22~23, AN25~30, AN33~38, AN48 Correct) TEQFP144 Analog input port(12bit-ADC) AN4~7, AN10~11, AN14~15, AN25~26, AN28~30 10 3.Product Description 3.2Product description Revised 4MHz to 16MHz as below: Error) -A wide range of 3.6 - 4MHz is available for main oscillator Correct) -A wide range of 3.6 - 16MHz is available for main oscillator 13 3. Product Description 3.2Product description Added Note of a function as below: Multi-Functional Serial (MFS) Correct) CTS/RTS is not mounted (hardware flow control is not supported for this series.) 14 3. Product Description 3.2Product description Revised Graphics Subsystem clock frequency as below: Error) 200 MHz maximum clock frequency Video modes up to 50 MHz pixel clock Correct) 80 MHz maximum clock frequency Video modes up to 25 MHz pixel clock Document Number: 002-10635 Rev. *H Page 267 of 322 S6J3310/20/30/40 Series Page Section 81 7. Port Configuration 7.1 Resource Input Configuration Module Change Results Revised as below: Error) RIC_RESIN235(0x01D6) OCU1_CK0, OCU1_CK1, OCU1_DOWNB0, OCU1_DOWNB1, OCU1_FCMD0, OCU1_FCMD1, OCU1_MTSF0, OCU1_MTSF1, OCU1_T0[31:0], OCU1_T1[31:0] RIC_RESIN236(0x01D8) OCU1_ZTSF0, OCU1_ZTSF1, OCU1_MOD0 Correct) RIC_RESIN235(0x01D6) OCU1_CK0, OCU1_CK1, OCU1_DOWNB0, OCU1_DOWNB1, OCU1_FCMD0, OCU1_FCMD1, OCU1_MTSF0, OCU1_MTSF1, OCU1_T0[31:0], OCU1_T1[31:0], OCU1_ZTSF0, OCU1_ZTSF1 RIC_RESIN236(0x01D8) OCU1_MOD0 155 8.Precautions and Handling Devices 8.1.1Precautio ns for Product Design Revised as below: Error) (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. Correct) (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 156 159 8.Precautions and Handling Devices 8.1.2Precautio ns for Package Mounting Revised as below: Error) Surface Mount Type 9.Electric Characteristics 9.1.1 Absolute Maximum Rating Deleted Remarks comment as below: Error) Correct) Surface Mount Type Supply voltage Operation assurance range, DVCC, Remarks "DVCCVCC5" Correct) Power supply voltage, DVCC, Remarks "" 159 8.2Handling Devices Added Note of a function as below: Method to Switch off VCC12 during Power-off Sequence During power-off sequence, it is necessary to switch off VCC12 by driving PSC1 pin low by entering PSS mode (power domain 2 off). If VCC12 needs to be switched off by other means, RSTX needs to be asserted before switching off VCC12 to inactivate the operation of VCC12 supplied domain below the operation assurance range. Document Number: 002-10635 Rev. *H Page 268 of 322 S6J3310/20/30/40 Series Page Section 159 9.Electric 160 Characteristics 9.1.1 Absolute Maximum Rating Change Results Added Note of a comment as below: Maximum clamp current, Total maximum clamp current Correct) *13 VI or VO should never exceed the specified ratings. However, if the maximum current to/from an input is limited by a suitable external resistor, the ICLAMP rating supersedes the VI rating. 161 9.Electric Characteristics 9.1.1 Absolute Maximum Rating Revised Warning of a comment as below: Error) Note: - Application of stress (e.g., voltage, current, temperature) exceeding the absolute maximum rating may cause damage to the semiconductor device. Therefore, make sure that nothing exceeds the rating. Correct) WARNING: - Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. 162 9.Electric Characteristics 9.1.2Recomme nded operating condition Revised Rating Min Spec as below: Error) Power supply voltage, VCC5 , Rating, Min, 2.6 Power supply voltage, VCC3 , Rating, Min, 2.6 Correct) Power supply voltage, VCC5 , Rating, Min, 2.7 Power supply voltage, VCC3 , Rating, Min, 2.7 162 163 9.Electric Characteristics 9.1.2Recomme nded operating condition Added comment as below: Supply voltage Operation assurance range,VCC12, VCC12 Correct) *5:When the voltage of Vcc12 is in the out of range against supply voltage operation assurance, the operation of circuit which Vcc12 used as the power source becomes unstable status. In that case, the value of each registers including RESCAUSEUR Register cannot be guaranteed, so these flags should don't care by software processing 162 163 215 236 9.Electric Characteristics 9.1.2Recomme nded operating condition 9.1.4.11Low Voltage Detection (External Voltage) 9.1.5 A/D converter Revised device revision from B to C as below: Error) S6J33xxxSB , S6J33xxxUB, S6J33xxxTB, S6J33xxxVB, S6J33xxxBB, S6J33xxxDB, S6J33xxxFB, S6J33xxxHB, S6J33xxxAB, S6J33xxxCB, S6J33xxxEB, S6J33xxxGB Correct) S6J33xxxSC, S6J33xxxUC, S6J33xxxTC, S6J33xxxVC, S6J33xxxBC, S6J33xxxDC, S6J33xxxFC, S6J33xxxHC, S6J33xxxAC, S6J33xxxCC, S6J33xxxEC, S6J33xxxGC Document Number: 002-10635 Rev. *H Page 269 of 322 S6J3310/20/30/40 Series Page Section 167 9.Electric Deleted VOH25 Spec as below: Characteristics Error) VOH25 9.1.3 DC characteristics Correct) Change Results Non 169 9.Electric Deleted VOL25 Spec as below: Characteristics Error) VOL25 9.1.3 DC characteristics Correct) Non 175 180 9.1 Electrical Characteristics 9.1.4 AC characteristics 9.1.4.3 Inter nal clock timing (S6J3310) Revised as below: Error) Internal clock frequency, FCLK_HAPP1B0, Value, Max *1, 60MHz Correct) Internal clock frequency, FCLK_HAPP1B0, Value, 9.Electric Revised as below: Characteristics Error) 9.1.4.5 PowerParameter on Conditions Power off time Symbol Pin Name - VCC5 Power ramp rate dV/dt VCC5 Undetected power ramp rate |dV/dt| VCC5 Max *1, 80MHz Conditions VCC5: 0.2V to 2.6V VCC5: Between 2.4V and 4.5V Value Min Typ Max Unit Remarks 50 - - ms *2 - - 1 V/s *3 - - 50 mV/s *4 Correct) - Pin Name VCC5 Power ramp rate dV/dt VCC5 Maximum ramp rate guaranteed to not generate power-on reset |dV/dt| VCC5 Parameter Power off time Document Number: 002-10635 Rev. *H Symbol Conditions VCC5: 1.5V to 2.6V VCC5: Between 2.4V and 4.5V Value Min 100 Typ - Max - - - - - Unit Remarks s *2 1 V/s *3 50 mV/s *4 Page 270 of 322 S6J3310/20/30/40 Series Page Section 180 9.Electric Characteristics 9.1.4.5 Poweron Conditions Change Results Revised device revision as below: Error) *1: This specification is at 1V/s of power ramp rate. *2: VCC5 must be held below 0.2V for a minimum period of tOFF. *3: Power ramp rate must be 1V/us or less from 0.2V to 2.6V. Power-on can detect by satisfying power ramp rate when power off time is satisfied. *4: This specification is specified the power supply fluctuation after power on detection. When VCC5 voltage is between 2.4V and 4.5V, the power supply fluctuation is below 50mV/us, the detection of power-on is suppressed. The power-on does not detect in any power fluctuation between 4.5V and 5.5V. Notes: When using S6J3310/20/30/40, *2 and *3 must be satisfied. When neither *2 nor *3 can be satisfied, assert external reset (RSTX) at power up and any brownout event. Power off time, Power ramp rate tOFF VCC 2.6V 0.2V 0.2V dV/dt Correct) *1: This specification is at 1V/s of power ramp rate. *2: VCC5 must be held below 1.5V for a minimum period of tOFF. *3: Power ramp rate must be 1V/us or less from 1.5V to 2.6V. Power-on can detect by satisfying power ramp rate when power off time is satisfied. *4: This specification is specified the power supply fluctuation after power on detection. When VCC5 voltage is between 2.4V and 4.5V, the power supply fluctuation is below 50mV/us, the detection of power-on is suppressed. The power-on does not detect in any power fluctuation between 4.5V and 5.5V. Notes: When using S6J3310/20/30/40, *2 and *3 must be satisfied. When neither *2 nor *3 can be satisfied, assert external reset (RSTX) at power up and any brownout event. Power off time, Power ramp rate tOFF VCC 2.6V 1.5V Document Number: 002-10635 Rev. *H 1.5V dV/dt Page 271 of 322 S6J3310/20/30/40 Series Page Section 185 9.Electric 186 Characteristics 9.1.4.6MultiFunction Serial Change Results Deleted Remarks comment as below: (2) Normal synchronous transfer (SCR:SPI=0) and mark level "L" of serial clock output (SMR:SCINV=1) Error) Master Mode(CL=20pF, IOL=-5mA, IOH=5mA) Master Mode(CL=20pF, IOL=-10mA, IOH=10mA) @20MHz, @16MHz, 12.5MHz Correct) Non 215 9.Electric Characteristics 9.1.4.11 Low Voltage Detection (External Voltage) Revised Max of Low-voltage detection time as below: Low-voltage detection (external low-voltage detection) Error) Low-voltage detection time - - - - 30 s Td - - - - 40 s Correct) Low-voltage detection time 216 Td 9.Electric Revised as below: Characteristics Low-voltage detection (1.15 V power supply low-voltage detection) 9.1.4.11 Low Error) Value Pin Voltage Parameter Symbol Conditions Name Min Typ Max Detection 0.784 0.8125 0.841 Detection voltage *1 VRDLAT VCC12 (External (after trimming) 0.888 0.95 0.984 Voltage) Unit Remarks V When power-supply voltage falls Typ3.5% Unit Remarks V When powersupply voltage falls Typ3.5% Correct) 217 Parameter Symbol Pin Name Conditions Detection voltage (after trimming) VRDLAT VCC12 *1 Value Min Typ Max 0.7841 0.8125 0.8410 9.Electric Revised as below: Characteristics Low-voltage detection (internal low-voltage detection for LVDL0) 9.1.4.12Low Error) Value Voltage Parameter Symbol Pin Name Conditions Min Typ Detection Hysteresis width VRHYS 100 (Internal Voltage) Correct) Parameter Hysteresis width Document Number: 002-10635 Rev. *H Symbol VRHYS Pin Name - Conditions - Max - Value Min - Typ 75 Max - Unit mV Unit mV Remarks When powersupply voltage rises Remarks When powersupply voltage rises Page 272 of 322 S6J3310/20/30/40 Series Page Section 218 9.Electric Revised as below: Characteristics Error) 9.1.4.12 Low Parameter Voltage Supply voltage Detection range (Internal Voltage) Detection voltage Hysteresis width Change Results Sym bol Pin Name Conditi ons Min Value Typ Max Uni t VRDP5 - - 1.05 - 1.21 V VRDL - *1 0.75 0.85 0.95 V VRHYS - - - 75 - mV Remarks When powersupply voltage falls When powersupply voltage rises Low-voltage TRd 30 s detection time *1: If the power fluctuation time is less than the low-voltage detection time (TRd) and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range. Correct) Parameter Sym bol Pin Name Conditi ons Min Value Typ Max Uni t Supply voltage range VRDP5 - - 1.05 - 1.21 V Detection voltage VRDL - *1 0.75 0.85 0.95 V Remarks When powersupply voltage falls *2 Hysteresis width VRHYS - - - 75 - mV When powersupply voltage rises Low-voltage *3 TRd 30 s detection time *1: If the power fluctuation time is less than the low-voltage detection time (TRd) and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range. *2: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. *3: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may occur or be canceled. Document Number: 002-10635 Rev. *H Page 273 of 322 S6J3310/20/30/40 Series Page Section 218 9.Electric Revised as below: Error) Symb Characteristics Parameter ol 9.1.4.12 Low Supply voltage VRDP5 Voltage range Detection Detection voltage VRDLBT (Internal (before trimming) Voltage) Change Results Pin Name Conditio ns Min Value Typ Max - - 1.05 - 1.21 V - *1 0.775 0.875 0.975 V Unit Detection voltage (after trimming) VRDLAT - *1 0.844 0.875 0.906 V Hysteresis width VRHYS - - - 75 - mV Low-voltage detection time TRd - - - - 30 s Remarks When powersupply voltage falls When powersupply voltage falls Typ3.5% When powersupply voltage rises *1: If the power fluctuation time is less than the low-voltage detection time (TRd) and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range. Correct) Parameter Symb ol Pin Name Conditio ns Min Value Typ Max Supply voltage range VRDP5 - - 1.05 - 1.21 - *1 Detection voltage (before trimming) VRDLBT 0.775 0.875 0.975 Unit Remarks V V When powersupply voltage falls *3 Detection voltage (after trimming) VRDLAT - *1 0.844 0.875 0.906 V When powersupply voltage falls Typ3.5% *2 *3 Hysteresis width VRHYS - - - 75 - mV Low-voltage detection time TRd - - - - 30 s When powersupply voltage rises *4 *1: If the power fluctuation time is less than the low-voltage detection time (TRd) and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range. *2: This detection voltage level setting is below the minimum operation assurance voltage . Between this detection voltage and the minimum operation assurance voltage, MCU functions are not guaranteed except for the low voltage detector. Note that although the detection level is below the minimum operation guarantee voltage, the LVD reset factor flag is set as the voltage drops below the detection level. *3: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. *4: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may occur or be canceled. Document Number: 002-10635 Rev. *H Page 274 of 322 S6J3310/20/30/40 Series Page Section 219 9.Electric Characteristics 9.1.4.14 Display Controller Change Results Revised as below: Error) (13-1) Display controller0 Timing (TTL mode) Correct) (1) Display controller0 Timing (TTL mode) 224 9.Electric Revised as below: Characteristics Error) 9.1.4.16 DDR- (16-1) DDR-HSSPI Interface Timing (SDR mode) HSSPI Parameter Symbol Pin Name HSSPI clock cycle M_SCLK -> delayed sample clock M_SDATA -> delayed sample clock Input setup time delayed sample clock -> M_SDATA Input hold time M_SCLK -> M_SDATA Output delay time M_SCLK -> M_SDATA Output hold time M_SCLK -> M_SSEL Output delay time M_SCLK -> M_SSEL Output hold time Conditions Value M_SCLK0 tspcnt - 0 tcyc ns tisdata M_SDATA0_0-3 M_SDATA1_0-3 3.5 - ns tihdata M_SDATA0_0-3 M_SDATA1_0-3 2.0 - ns - 6.5 ns 3.5 - ns toddata tohdata M_SDATA0_0-3 M_SDATA1_0-3 M_SDATA0_0-3 M_SDATA1_0-3 (CL = 20pF, IOL=-10mA, IOH=10mA), Max - Unit tcyc Min 10 Remarks ns todsel M_SSEL0, 1 - 5.5 ns tohsel M_SSEL0, 1 4.5 - ns tcyc -3.5ns tcyc -4.5ns Notes: This is Target Spec. Correct) (1)DDR-HSSPI Interface Timing (SDR mode) Parameter HSSPI clock cycle M_SCLK -> delayed sample clock M_SDATA -> M_SLCK Input setup time M_SCLK -> M_SDATA Input hold time M_SCLK -> M_SDATA Output delay time M_SCLK -> M_SDATA Output hold time Symbol Pin Name tcyc M_SCLK0 tspcnt tisdata tihdata toddata tohdata Conditions M_SDATA0_0-3 M_SDATA1_0-3 M_SDATA0_0-3 M_SDATA1_0-3 M_SDATA0_0-3 M_SDATA1_0-3 M_SDATA0_0-3 M_SDATA1_0-3 (CL = 20pF, IOL=-10mA, IOH=10mA), Value Unit Remarks ns when Quad Page Program Min 10 Max - 20 - 0 31.5 ns *1 - ns *1 - ns - tcyc/2 + 2 ns tcyc/2 - 3 - ns - ns - ns M_SCLK -> M_SSEL Output delay time todsel M_SSEL0, 1 -12.00+ (SS2CD+0.5)* tcyc M_SCLK -> M_SSEL Output hold time tohsel M_SSEL0, 1 tcyc - 2 Notes: This is Target Spec. - - SS2CD [1:0] should be configured as 01, 10, or 11. For *1, the delay of the delay sample clock can be configured (DLP function).. Document Number: 002-10635 Rev. *H Page 275 of 322 S6J3310/20/30/40 Series Page Section Change Results 225 9.Electric Revised as below: Characteristics Error) (16-2) DDR-HSSPI Interface Timing (DDR mode) 9.1.4.16 DDRParameter Symbol Pin Name Conditions HSSPI HSSPI clock cycle M_SCLK -> delayed sample clock M_SDATA -> delayed sample clock Input setup time delayed sample clock -> M_SDATA Input hold time M_SCLK -> M_SDATA Output delay time M_SCLK -> M_SDATA Output hold time M_SCLK -> M_SSEL Output delay time M_SCLK -> M_SSEL Output hold time tcyc M_SCLK0 tspcnt Value Unit Min Max 10 - ns 0 tcyc ns 1.0 - ns 1.0 - ns - 3.5 ns 1.5 - ns tisdata M_SDATA0_0-3 M_SDATA1_0-3 tihdata M_SDATA0_0-3 M_SDATA1_0-3 (CL = 20pF, toddata M_SDATA0_0-3 M_SDATA1_0-3 IOH=10mA), tohdata M_SDATA0_0-3 M_SDATA1_0-3 todsel M_SSEL0, 1 - 7.0 ns tohsel M_SSEL0, 1 3.0 - ns Remarks IOL=-10mA, tcyc/2-1.5ns tcyc -3.0ns Notes: This is Target Spec. Correct) (2)DDR-HSSPI Interface Timing (DDR mode) Parameter HSSPI clock cycle M_SCLK -> delayed sample clock M_SDATA -> M_SLCK Input setup time M_SLCK -> M_SDATA Input hold time M_SCLK -> M_SDATA Output delay time M_SCLK -> M_SDATA Output hold time Symbol Pin Name tcyc M_SCLK0 Conditions tspcnt tisdata M_SDATA0_0-3 M_SDATA1_0-3 tihdata M_SDATA0_0-3 M_SDATA1_0-3 toddata M_SDATA0_0-3 M_SDATA1_0-3 tohdata M_SDATA0_0-3 M_SDATA1_0-3 M_SCLK -> M_SSEL Output delay time todsel M_SSEL0, 1 M_SCLK -> M_SSEL Output hold time tohsel M_SSEL0, 1 (CL = 20pF, IOL=-10mA, IOH=10mA), Value Min Max Unit 12.5 - ns 0 31.5 ns *1 - ns *1 - ns - tcyc/4 + 1.5 ns Tcyc/4 - 1.0 - ns - ns - ns -15.75+ (SS2CD+0.5)*tcyc 0.75*tcyc - 2.0 Remark s Notes: This is Target Spec. - - SS2CD [1:0] should be configured as 01, 10, or 11. For *1, the delay of the delay sample clock can be configured (DLP function) Document Number: 002-10635 Rev. *H Page 276 of 322 S6J3310/20/30/40 Series Page Section 227 9.Electric Revised as below: Characteristics Error) (16-1) Hyper Bus Write Timing (HyperFlash) 9.1.4.17 Hyper Parameter Symbol Pin Name BUS CS -> CK Chip Select setup time tCSS M_CS#_1,2 CK -> CS Chip select hold time tCSH M_CS#_1,2 Change Results Value Conditions Unit Min Max 3.0 - ns 0 - ns (CL = 20pF, IOL=-10mA, IOH=10mA), Remarks Correct) (1)Hyper Bus Write Timing (HyperFlash) Parameter 228 Symbol Pin Name CS -> CK Chip Select setup time tCSS M_CS#_1,2 CK -> CS Chip select hold time tCSH M_CS#_1,2 9.Electric Revised as below: Characteristics Error) 9.1.4.17 Hyper (16-2) Hyper Bus Write Timing (HyperRAM) BUS Parameter Symbol Pin Name CS -> CK Chip Select setup time CK -> CS Chip select hold time RWDS-> CK Data Mask Valid tCSS (CL = 20pF, IOL=-10mA, IOH=10mA), Conditions M_CS#_1,2 tCSH M_CS#_1,2 tDMV M_RWDS Value Conditions (CL = 20pF, IOL=-10mA, IOH=10mA), Unit Min Max tCKCYC -2.0 - ns tCKCYC/2 - ns Value Unit Min Max 3.0 - ns 0 - ns 0 - ns Remarks Remarks Correct) (2) Hyper Bus Write Timing (HyperRAM) Parameter Symbol Pin Name CS -> CK Chip Select setup time CK -> CS Chip select hold time RWDS-> CK Data Mask Valid tCSS M_CS#_1,2 tCSH M_CS#_1,2 tDMV M_RWDS Document Number: 002-10635 Rev. *H Conditions (CL = 20pF, IOL=-10mA, IOH=10mA), Value Unit Min Max tCKCYC - 2.0 - ns tCKCYC/2 - ns 1 - ns Remarks Page 277 of 322 S6J3310/20/30/40 Series Page Section 229 9.Electric Revised as below: Characteristics Error) 9.1.4.17 Hyper (16-3) Hyper Bus Read Timing (HyperFlash) BUS Parameter Symbol Pin Name CS -> CK Chip Select setup time DQ -> CK Input setup time CK -> DQ Input hold time CK -> CS Chip select hold time RDS> DQ (valid) RDS transition to DQ valid RDS> DQ (invalid) RDS transition to DQ invalid Change Results Conditions Value Min Max Unit tCSS M_CS#_1,2 3.0 - ns tIS M_DQ7-0 1.25 - ns 1.25 - ns 0 - ns tIH M_DQ7-0 tCSH M_CS#_1,2 tDSS M_DQ7-0 -0.8 +0.8 ns tDSH M_DQ7-0 -0.8 +0.8 ns (CL = 20pF, IOL=-10mA, IOH=10mA), Remarks Correct) (3) Hyper Bus Read Timing (HyperFlash) Parameter CS -> CK Chip Select setup time DQ -> CK Setup time CK -> DQ Hold time CK -> CS Chip select hold time RDS> DQ Setup time RDS> DQ Hold time Document Number: 002-10635 Rev. *H Symbol Pin Name tCSS Conditions Value Unit Min Max M_CS#_1,2 tRDSCYC -2.0 - ns tIS M_DQ7-0 1.25 - ns tIH M_DQ7-0 1.25 - ns tCSH M_CS#_1,2 tRDSCYC / 2 - ns tDSS M_DQ7-0 -0.8 - ns tDSH M_DQ7-0 -0.8 - ns (CL = 20pF, IOL=-10mA, IOH=10mA), Remarks Page 278 of 322 S6J3310/20/30/40 Series Page Section 230 9.Electric Revised as below: Characteristics Error) 9.1.4.17 Hyper (16-4) Hyper Bus Read Timing (HyperRAM) BUS Parameter Symbol Pin Name CS -> CK Chip Select setup time DQ -> CK Input setup time CK -> DQ Input hold time CK -> CS Chip select hold time RWDS> DQ (valid) RWDS transition to DQ valid RWDS> DQ (invalid) RWDS transition to DQ invalid CK -> RWDS Refresh Indicator Valid CK -> RWDS(Hi-z) Refresh Indicator Hold Change Results Conditions Value Min Max Unit tCSS M_CS#_1,2 3.0 - ns tIS M_DQ7-0 1.25 - ns tIH M_DQ7-0 1.25 - ns tCSH M_CS#_1,2 0 - ns tDSS M_DQ7-0 -0.8 +0.8 ns tDSH M_DQ7-0 -0.8 +0.8 ns tRIV M_RWDS - 6 ns tRIH M_RWDS 0 - ns (CL = 20pF, IOL=-10mA, IOH=10mA), Remarks Correct) (4) Hyper Bus Read Timing (HyperRAM) Parameter CS -> CK Chip Select setup time DQ -> CK Setup time CK -> DQ Hold time CK -> CS Chip select hold time RWDS> DQ (valid) Setup time RWDS> DQ (invalid) Hold time CK -> RWDS Refresh Indicator Valid CK -> RWDS(Hi-z) Refresh Indicator Hold Document Number: 002-10635 Rev. *H Symbol Pin Name tCSS Conditions Value Unit Min Max M_CS#_1,2 tRDSCYC -2.0 - ns tIS M_DQ7-0 1.25 - ns tIH M_DQ7-0 1.25 - ns tCSH M_CS#_1,2 tRDSCYC /2 - ns (CL = 20pF, IOL=-10mA, IOH=10mA), tDSS M_DQ7-0 -0.8 - ns tDSH M_DQ7-0 -0.8 - ns tRIV M_RWDS - 6 ns tRIH M_RWDS 0 - ns Remarks Page 279 of 322 S6J3310/20/30/40 Series Page Section 234 9.Electric Revised as below: Characteristics Error) (19-1) MediaLB Input Timing 9.1.4.19 MediaLB Parameter Symbol MLBCLK cycle MLBSIG, MLBDAT Input hold tmckc Change Results Pin Name Conditions MLBCLK MLBSIG MLBDAT - Symbol Pin Name Conditions tmckc MLBCLK MLBSIG MLBDAT tdhmcf Value Min 19.53 Max - 0 - Unit Remarks ns ns - Unit Remarks Notes: This is Target Spec. (19-2) MediaLB Output Timing Parameter MLBCLK cycle MLBSIG, MLBDAT output stop tmcfdz MLBSIG, MLBDAT output delay (CL = 20pF, IOL=-6mA, IOH=6mA), tdout MLBSIG MLBDAT Symbol Pin Name Conditions tmckc MLBCLK MLBSIG MLBDAT - Value Min 19.53 Max - ns - 10.73 - ns tmckc -8.8ns 0 8.8 ns - Unit Remarks Notes: This is Target Spec. Correct) (1) MediaLB Input Timing Parameter MLBCLK cycle MLBSIG, MLBDAT Input hold tdhmcf Value Min 40.0 Max - 4.0 - ns ns - Notes: This is Target Spec. - CLK_HAPP1B0(internal) frequency > MLBCLK(external) frequency (2) MediaLB Output Timing Parameter MLBCLK cycle MLBSIG, MLBDAT output stop MLBSIG, MLBDAT output delay Symbol Pin Name tmckc MLBCLK MLBSIG MLBDAT MLBSIG MLBDAT tmcfdz tdout Conditions (CL = 20pF, IOL=-6mA, IOH=6mA), Value Min 40.0 Max - 26.5 0 Unit Remarks ns - - ns tmckc - tdout 13.5 ns - Notes: This is Target Spec. - 246 11.Ordering Information CLK_HAPP1B0(internal) frequency > MLBCLK(external) frequency Revised part number as below: Error) S6J331EKCB******* S6J331EKBB******* S6J331EKAB******* S6J331EJCB******* S6J332EJCB******* S6J331EJAB******* S6J332EJAB******* S6J332EHSB******* Correct) S6J331EKCC******* S6J331EKBC******* S6J331EKAC******* S6J331EJCC******* S6J332EJCC******* S6J331EJAC******* S6J332EJAC******* S6J332EHSC******* Document Number: 002-10635 Rev. *H Page 280 of 322 S6J3310/20/30/40 Series Page Section Rev. *B 3.Product 13 Description 3.2.Product description Change Results Revised the below: Error) (None) 12bit resolution, 2 unit 48 channels of analog input for TEQFP208 48 channels of analog input for TEQFP176 35 channel of analog input for TEQFP144 24 channels of them are shared with the SMC for TEQFP208/176/144 External trigger and timer trigger are available. The description of the A/D converter function should be referred in the S6J3300 hardware manual. Though the chapter of I/O port in TraveoTM Platform hardware manual describes another A/D converter function, do not refer it. Correct) 15 3.Product 12bit resolution, 2 unit(Unit0 is possible to select channels 4-31. Unit1 is possible to select channels 32-63.) 48 channels of analog input for TEQFP208 48 channels of analog input for TEQFP176 35 channel of analog input for TEQFP144 24 channels of them are shared with the SMC for TEQFP208/176/144 External trigger and timer trigger are available. The description of the A/D converter function should be referred in the S6J3300 hardware manual. Though the chapter of I/O port in TraveoTM Platform hardware manual describes another A/D converter function, do not refer it. A/D Channel Control Register (ADC12Bn_CHCTRL0)[bit5:0] ANIN[5:0] : Analog Input Selection bits. This register setting is possible of channel 0-31 (the register value is 00_0000 to 01_1111). Revised as below: Description Correct) 3.2.Product PSC (PSC_1) output is used for external 1.2V power supply module control and automatically switched with the following description condition. "High": Request to supply VCC12 Power Supply Control (PSC) - "Power ON Reset" is released - CPU wakes up from PSS shutdown mode "Low": Request to stop supplying VCC12 - CPU transfers from RUN mode to PSS shutdown mode. For timing chart of output signals include PSC in detail, see the "S6J3300 hardware manual" and chapter "State Transition" 22 23 4.2.Package Revised as below: 4.2.3.TEQFP144 Error) Dimensions Figure 4 6: TEQFP144 4.Package and Pin Assignment Figure 4 7: TEQFP144 The package dimension of TEQFP144 (0.4mm Pitch) is the provisional version. Correct) Figure 4 6: TEQFP144 (0.5mm Pitch) Figure 4 7: TEQFP144 (0.4mm Pitch) The package dimension of TEQFP144 (0.4mm Pitch) is the formal version. 31 32 Description Revised the below: Error) 6.1 Port ADC Analog [4 to18, 21, 24 to 26, 28 to 32, 39 to 47, 49 to 63] input pin 6.Port Description list Correct) ADC Unit0 [ch.4 to ch.18, ch.21, ch.24 to ch.26, ch.28 to ch.31] input pin ADC Unit1 [ch.32, ch.39 to ch.47, ch.49 to ch.63] input pin Document Number: 002-10635 Rev. *H Page 281 of 322 S6J3310/20/30/40 Series Page Section 8.Precautions 155 Change Results and Handling Revised the below: Error) Devices (1) Preventing Over-Voltage and Over-Current Conditions 8.1.1.Precaution Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the s for Product device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over- Design current conditions at the design stage. Correct) (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or overcurrent conditions at the design stage. 159 8.Precautions Revised as below: and Handling 8.2.Handling Correct) Method to Switch Off VCC12 during Power-Off Sequence Devices During power-off sequence, it is necessary to switch off VCC12 by driving PSC1 pin low by entering PSS mode Devices (power domain 2 off). If VCC12 needs to be switched off by other means, RSTX needs to be asserted before switching off VCC12 to inactivate the operation of VCC12 supplied domain below the operation assurance range. 164 Characteristics Revised as below: Error) 9.1.2 The detection/release threshold values of following LVD channels are potentially below supply range defined in 9.1.2 Recommended Recommended operating condition (refer to "9.1.4.11 Low Voltage Detection (External Voltage)" and "9.1.4.12 Low operating Voltage Detection (Internal Voltage)" for detection/release threshold values for these LVD channels): LVDL0 LVDL1 LVDL2 LVDH0 LVDH1 LVDH2 9.Electric condition Correct) The detection/release threshold values of following LVD channels are potentially below supply range defined in 9.1.2 Recommended operating condition (refer to "9.1.4.11 Low Voltage Detection (External Voltage)" and "9.1.4.12 Low Voltage Detection (Internal Voltage)" for detection/release threshold values for these LVD channels): LVDL0 LVDL1 LVDL2 LVDH0 LVDH1 LVDH2 Detection voltage of the external low voltage detection reset (initial) is 2.6V3.5% *2 *3 or 4.0V3.5%*1. This detection voltage level setting is below the minimum operation assurance voltage (2.7V *2 *3 or 4.0V*1) . Between this detection voltage and the minimum operation assurance voltage, MCU functions are not guaranteed except for the low voltage detector. Note that although the detection level is below the minimum operation guarantee voltage, the LVD reset factor flag is set as the voltage drops below the detection level. Document Number: 002-10635 Rev. *H Page 282 of 322 S6J3310/20/30/40 Series Page Section 9.Electric 174 Change Results Characteristics Revised as below: Error) 9.1.4.1.Source Notes: clock timing - The maximum/minimum values have been standardized with the main clock and PLL clock in use. - Jitter of source oscillator must be smaller than 300ppm. Correct) Notes: - The maximum/minimum values have been standardized with the main clock and PLL clock in use. - Jitter of source oscillator must be smaller than 300ppm. - Enough evaluation and adjustment are recommended using oscillator on your system board. 177 Characteristics Revised as below: Error) 9.1.4.3.Internal - Note that Ta=125 condition is not supported in this product type. 9.Electric clock timing When using SSCG_PLL output for these internal clock, the MAX value of frequency has the following restrictions. On the presumption that the modulation mode of SSCG_PLL is used with down spread, the MAX value of the frequency is standardized. This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated. Correct) - Note that Ta=125 condition is not supported in this product type. When using SSCG_PLL output for these internal clock, the MAX value of frequency has the following restrictions. On the presumption that the modulation mode of SSCG_PLL is used with down spread, the MAX value of the frequency is standardized. This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated. "Unused" means a clock source which doesn't have any supply destinations. Configure it as disable with performing at the lower clock frequency than the described maximum. 179 9.Electric Characteristics 9.1.4.3.internal Added Oscillation clock frequency as below: Correct) Internal Operation Clock Frequency clock timing Main Clock Oscillation clock PLL Clock Multiplied by Multiplied by Multiplied by Multiplied by Multiplied by 1 2 15 30 40 60 160 240 4 2 4 8 ... 60 120 8 4 8 16 ... 120 240 16 8 16 32 ... 240 Multiplied by frequency [MHz] Document Number: 002-10635 Rev. *H Page 283 of 322 S6J3310/20/30/40 Series Page Section 9.Electric 208 Characteristics 9.1.4.6MultiFunction Serial Change Results Revised as below: Error) I2C timing (SMR:MD2-0=0b100) (TA: Recommended operating conditions, Vcc5=Vcc53=5.0 V 10%, V CC12=1.15V 0.06V, VSS=0.0 V) Parameter Symbol Pin Name Conditions SCL0, SCL1, SCL4, SCL clock frequency fSCL SCL8 to SCL12, Min Max Min Max 0 100 0 400 CL=50pF, R=(Vp/IOL)*1 SCL16 to SCL17 High-Speed Mode Standard Mode Unit Remarks kHz Correct) I2C timing (SMR:MD2-0=0b100) (TA: Recommended operating conditions, Vcc5=Vcc53=5.0 V 10%, V CC12=1.15V 0.06V, VSS=0.0 V) Parameter Symbol Pin Name SCL0, SCL1, SCL4, SCL clock frequency fSCL SCL8 to SCL12, SCL16 to SCL17 Standard Mode Conditions Fast Mode Unit Min Max Min Max 0 100 0 400 CL=50pF, R=(Vp/IOL)*1 Remarks kHz Error) *3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT 250 ns". Correct) *3: A fast mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT 250 ns". 216 9.Electric Added *5 and *5 sentences as below: Characteristics 9.1.4.11.Low Voltage Error) Parameter Symbol Pin Name Conditions VCC5 *1 Detection (External Voltage) Detection voltage (after trimming) Value Min Typ Max 3.86 *3 4.0 *3 4.14 *3 *4 *4 *4 VCC3 *1 Pin Name Conditions VCC5 *1 2.51 2.6 2.6 2.69 2.69 Remarks When power- V 2.51 VDLAT Unit supply voltage falls and detection level V is set initially Typ3.5% Correct) Parameter Detection voltage (after trimming) Symbol VDLAT VCC3 *1 Value Min Typ Max 3.86 *3 4.0 *3 4.14 *3 Unit When powerV 2.51 *4 2.6 *4 2.69 *4 2.51 2.6 2.69 Remarks supply voltage falls and detection level V is set initially Typ3.5% *5 *5: This detection voltage level setting is below the minimum operation assurance voltage (2.7V *4 or 4.0V*3) . Between this detection voltage and the minimum operation assurance voltage, MCU functions are not guaranteed except for the low voltage detector. Note that although the detection level is below the minimum operation guarantee voltage, the LVD reset factor flag is set as the voltage drops below the detection level. Document Number: 002-10635 Rev. *H Page 284 of 322 S6J3310/20/30/40 Series Page Section 9.Electric 217 Change Results Added *2 and *2 sentences as below: Characteristics 9.1.4.11.Low Voltage Error) Parameter Symbol Pin Name Conditions VCC12 *1 Detection (External Voltage) Value Min Typ Max Unit Remarks When power- Detection voltage (after trimming) VRDLAT 0.7841 0.8125 0.8410 V supply voltage falls Typ3.5% Correct) Parameter Symbol Pin Name Conditions Value Min Typ Max Unit Remarks When power- Detection voltage (after trimming) VRDLAT VCC12 *1 0.7841 0.8125 0.8410 V supply voltage falls Typ3.5% *2 *2: This detection voltage level setting is below the minimum operation assurance voltage . Between this detection voltage and the minimum operation assurance voltage, MCU functions are not guaranteed except for the low voltage detector. Note that although the detection level is below the minimum operation guarantee voltage, the LVD reset factor flag is set as the voltage drops below the detection level. 218 9.Electric Added *2 and *2 sentences as below: Characteristics 9.1.4.12.Low Voltage Error) Parameter Symbol Pin Name Conditions VRDLAT - *1 Detection (Internal Voltage) Detection voltage (after trimming) Value Min Typ Max 0.844 0.875 0.906 Unit Remarks When power- V supply voltage falls Typ3.5% Correct) Parameter Detection voltage (after trimming) Symbol Pin Name Conditions VRDLAT - *1 Value Min Typ Max 0.844 0.875 0.906 Unit Remarks When power- V supply voltage falls Typ3.5% *2 *2: This detection voltage level setting is below the minimum operation assurance voltage . Between this detection voltage and the minimum operation assurance voltage, MCU functions are not guaranteed except for the low voltage detector. Note that although the detection level is below the minimum operation guarantee voltage, the LVD reset factor flag is set as the voltage drops below the detection level. Document Number: 002-10635 Rev. *H Page 285 of 322 S6J3310/20/30/40 Series Page 238 239 240 241 Section 9.Electric Change Results Added AC specification of LCD bus I/F as below. Characteristics 9.1.4.21 Correct) LCDCbus I/F 9.1.4.21 LCDbus I/F (1) Intel-8080 (TA: Recommended operating conditions, Vcc3=3.3 V 0.3V, VSS=DVSS=AVSS=0.0 V) Value Parameter Symbol Address hold time Pin Name tAH Address setup time Conditions D/C# Unit Min Max 20 - ns tAW D/C# 20 - ns Write cycle time tCYCW CS#, WR# 100 - ns Write, Enable pulse H width tCCHW CS#, WR# 35 - ns Write, Enable pulse L width tCCLW CS#, WR# 35 - ns tDS DB 20 - ns Write data set time Write data hold time (CL = 20pF, IOL=-5mA, tDH DB Read cycle time tCYCR CS#, RD# 20 - ns 255 - ns Read pulse H width tCCHR Read pulse L width tCCLR CS#, RD# 90 - ns CS#, RD# 150 - Read data access time ns tACC DB - 145 ns Read data disable time tOH DB 15 - ns tAW IOH=5mA), Remarks tAH D/C# tCYCW tCYCR CS# tCCL tCCH WR#,RD# tCYCW, tCYCR WR#,RD# tCCL tCCH CS# tDS tDH DB(write) tACC tOH DB(read) Document Number: 002-10635 Rev. *H Page 286 of 322 S6J3310/20/30/40 Series Page Section Change Results (2) Motorola-6800 (TA: Recommended operating conditions, Vcc3=3.3 V 0.3V, VSS=DVSS=AVSS=0.0 V) Value Parameter Symbol Pin Name Address hold time tAH D/C#, R/W# Address setup time tAW D/C#, R/W# Conditions (CL = 20pF, Unit Min Max 20 - ns 20 - ns 100 - ns 35 - ns Remarks IOL=-5mA, Write cycle time tCYCW CS#, E Write, Enable pulse H width tEH CS#, E IOH=5mA), Write, Enable 35 CS#, E pulse H - ns widthtEH Write, Enable pulse L width tEL CS#,E 35 - ns Write data set time tDS DB 20 - ns Write data hold time tDH DB 20 - ns - ns Read cycle time tCYCR CS#, E 255 Read pulse H width tEH CS#, E 90 - ns Read pulse L width tEL CS#,E 150 - ns Read data access time tACC DB - 145 ns Read data disable time tOH DB 15 - ns tAW tAH D/C#, R/W# tCYCW CS# tEH tCYCR tEL E tCYCW, tCYCR tEH E tEL CS# tDS tDH DB(write) tACC tOH DB(read) Document Number: 002-10635 Rev. *H Page 287 of 322 S6J3310/20/30/40 Series Page Section Rev. *C 1 Features 4 1.Overview 1.2 Document definition Change Results Error) General purpose I/O port : up to 146 Correct) General purpose I/O port : up to 148 Error) Document Type Definition Primary User Document Code S6J3310/20/30/40 Datasheet The function and its characteristics are specified quantitatively. Investigator and hardware engineer 002-10635 S6J3300 hardware manual The function and its operation of S6J3300 series are described. Software engineer 002-10185 TraveoTM Platform hardware manual The function and its operation of CPU core platform are described. The reference software, sample application, the reference board design and so on are explained. Software engineer Software and hardware engineer Document Type Definition Primary User S6J3310/20/30/40 Datasheet The function and its characteristics are specified quantitatively. S6J3300 hardware manual TraveoTM Platform hardware manual The function and its operation of S6J3300 series are described. The function and its operation of CPU core platform are described. Application note 002-07884 Under consideration Correct) Application note Document Number: 002-10635 Rev. *H The reference software, sample application, the reference board design and so on are explained. Investigator and hardware engineer Software engineer Software engineer Software and hardware engineer Document Code 002-10635 002-10185 002-07884 002-03898 002-04455 002-04446 002-09716 002-04452 002-04096 002-12061 002-02495 Page 288 of 322 S6J3310/20/30/40 Series Page Section 5 2.Function List Error) 6 2.1 Product Function lineup Sound waveform generator Change Results S6J3310 S6J3320 5 6 S6J3310 S6J3340 Remark 1 unit x 5 outputs See 2.2.1 2 ch One only supports an output as a function of the sound system. I2S Correct) Function S6J3330 S6J3320 S6J3330 S6J3340 Remark Sound waveform generator 1 unit x 5 outputs No See 2.2.1 I2S 2 ch 1ch One only supports an output as a function of the sound system. 2.Function List Error) 2.1 Product Function lineup S6J3310 S6J3320 S6J3330 S6J3340 Remark General Purpose I/O Option See 2.2.2 12bit-A/D converter 2 unit - 48 input ports (Max) See 2.2.2 LCD controller 4COM x 32 SEG (Max) See 2.2.2 Correct) Function S6J3310 S6J3320 S6J3330 S6J3340 Remark General Purpose I/O Option See 2.2.3 12bit-A/D converter 2 unit - 48 input ports (Max) See 2.2.3 LCD controller 4COM x 32 SEG (Max) See 2.2.3 Document Number: 002-10635 Rev. *H Page 289 of 322 S6J3310/20/30/40 Series Page Section 8 2.Function List Error) 2.2.2 ID Function Digit Change Results Revision Chip ID JTAG ID S,U,T,V C 0x10122100 0x1000B5CF A,C,E,G C 0x10128100 0x1000B5CF B,D,F,H C 0x10120100 0x1000B5CF Function Digit Revision Chip ID JTAG ID S,U,T,V C 0x10122100 0x1000B5CF D 0x10122200 C 0x10128100 D 0x10128200 C 0x10120100 D 0x10120200 Correct) A,C,E,G B,D,F,H 10 3.Product Description 3.2 Product description Error) Power Domain (PD) The product series supports the power off control of PD1, PD2 (including PD3 and 5) and PD6. Correct) Power Domain (PD) The product series supports the power off control of PD1, PD2 (including PD3 and 5), PD4_0, PD4_1 and PD6. 17 18 19 20 4.Package and Pin Assignment 4.1.1 TEQFP208 Pin Assignment 21 22 23 24 4. Package and Pin Assignment 4.1.2 TEQFP176 Pin Assignment Error) 4.1.1 TEQFP-208 Pin Assignment(S6J3310) Figure 4 1: TEQFP-208 Correct) 4.1.1 TEQFP-208 Pin Assignment Figure 4-1: TEQFP-208 (S6J331xKyz) Figure 4-2: TEQFP-208 (S6J332xKyz) add Figure 4-3: TEQFP-208 (S6J333xKyz) add Figure 4-4: TEQFP-208 (S6J334xKyz) add Error) 4.1.2 TEQFP-176 Pin Assignment(S6J3310) Figure 4-2: TEQFP-176 Correct) 4.1.2 TEQFP-176 Pin Assignment Figure 4-5: TEQFP-176 (S6J331xJyz) Figure 4-6: TEQFP-176 (S6J332xJyz) add Figure 4-7: TEQFP-176 (S6J333xJyz) add Figure 4-8: TEQFP-176 (S6J334xJyz) add Document Number: 002-10635 Rev. *H Page 290 of 322 S6J3310/20/30/40 Series Page 25 26 27 28 Section 4.Package and Pin Assignment 4.1.3 TEQFP144 Pin Assignment 29 4.Package and Change Results Error) 4.1.3 TEQFP-144 Pin Assignment(S6J3310) Figure 4-2: TEQFP-144 Correct) 4.1.3 TEQFP-144 Pin Assignment Figure 4-9: TEQFP-144 (S6J331xHyz) Figure 4-10: TEQFP-144 (S6J332xHyz) add Figure 4-11: TEQFP-144 (S6J333xHyz) add Figure 4-12: TEQFP-144 (S6J334xHyz) add Error) 4.2.1 TEQFP208 Correct) Revised PKG figure. Added PKG Code. Pin Assignment 30 Error) 4.2.2 TEQFP176 Correct) Revised PKG figure. Added PKG Code. 4.Package and Error) Pin Assignment 4.2.3 TEQFP144 Correct) Revised PKG figure. Added PKG Code. 5.IO Circuit Error) Type Type N 5.1. I/O Circuit Type 4.Package and Pin Assignment 31 32 35 Reset input Correct) Type N Document Number: 002-10635 Rev. *H Page 291 of 322 S6J3310/20/30/40 Series Page Section 170 9. Electric Error) Characteristics Power consumption 9.1.1 Absolute Operating temperature Maximum Rating Change Results PD - 1500 mW TA -40 -40 105 125 oC - 2000 mW -40oCTA105oC -40 1100 105 mW oC -40oCTA125oC PD2000mW -40 125 oC oC PD2000mW PD1200mW Correct) 172 172 Power consumption PD Operating temperature TA 9. Electric Error) Characteristics Operating temperature 9.1.2 Recommended operating Correct) condition Operating temperature 9.Electric Characteristics 9.1.2Recomme nded operating condition PD1100mW TA - -40 105 oC PD2000mW TA - -40 125 oC PD1200mW TA - -40 105 oC PD2000mW 125 oC PD1100mW TA - -40 Error) S6J33xxxSC, S6J33xxxUC, S6J33xxxTC, S6J33xxxVC, S6J33xxxBC, S6J33xxxDC, S6J33xxxFC, S6J33xxxHC, S6J33xxxAC, S6J33xxxCC, S6J33xxxEC, S6J33xxxGC Correct) S6J33xxxSx, S6J33xxxUx, S6J33xxxTx, S6J33xxxVx, S6J33xxxBx, S6J33xxxDx, S6J33xxxFx, S6J33xxxHx, S6J33xxxAx, S6J33xxxCx, S6J33xxxEx, S6J33xxxGx Document Number: 002-10635 Rev. *H Page 292 of 322 S6J3310/20/30/40 Series Page Section Change Results 173 9. Electric Error) Characteristics LVDL0 9.1.2 LVDL1 Recommended LVDL2 operating LVDH0 condition LVDH1 LVDH2 Detection voltage of the external low voltage detection reset (initial) is 2.6V3.5%*2 *3 or 4.0V3.5%*1. This detection voltage level setting is below the minimum operation assurance voltage (2.7V*2 *3 or 4.0V*1) . Between this detection voltage and the minimum operation assurance voltage, MCU functions are not guaranteed except for the low voltage detector. Note that although the detection level is below the minimum operation guarantee voltage, the LVD reset factor flag is set as the voltage drops below the detection level. Correct) LVDL0 LVDL1 LVDL2 LVDH0 LVDH1 LVDH2 When it is used outside recommended range (this is the range of guaranteed operation), contact your sales representative.The initial detection voltage of the external low voltage detection is 2.6V3.5%*2 *3(LVDH1/LVDH2) or 0.8V3.5%(LVDL2). This LVD setting and internal LVD (LVDL0/LVDL1) cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Document Number: 002-10635 Rev. *H Page 293 of 322 S6J3310/20/30/40 Series Page Section 181 9. Electric Error) 182 Characteristics 9.1.3 DC characteristics Change Results ICCT5 - 370 810 - 360 780 - 100 400 A Timer mode VCC5 ICCH5 Stop mode A A TA=25C. Power only supplies to Backup RAM and system controllers. When using 4MHz crystal for main oscillator. TA=25C. Power only supplies to Backup RAM and system controllers. When shutting down 16kB Backup RAM and using 4MHz crystal for main oscillator. TA=25C. Power only supplies to Backup RAM and system controllers. Correct) ICCT5 ICCH5 Document Number: 002-10635 Rev. *H VCC5 VCC5 Timer mode Stop mode - 370 810 A TA=25C. 4MHz crystal for main oscillator PD1=ON, PD4_0=ON, PD4_1=ON - 360 780 A TA=25C. 4MHz crystal for main oscillator. PD1=ON, PD4_0=ON or PD4_1=ON - 350 750 A TA=25C. 4MHz crystal for main oscillator. PD1=ON - 450 890 A - 440 860 A - 430 830 A - 110 430 A - 100 400 A - 90 370 A - 100 400 A - 90 370 A - 80 340 A TA=25C. 8MHz crystal for main oscillator PD1=ON, PD4_0=ON, PD4_1=ON TA=25C. 8MHz crystal for main oscillator. PD1=ON, PD4_0=ON or PD4_1=ON TA=25C. 8MHz crystal for main oscillator. PD1=ON TA=25C. 32kHz crystal for sub oscillator PD1=ON, PD4_0=ON, PD4_1=ON TA=25C. 32kHz crystal for sub oscillator. PD1=ON, PD4_0=ON or PD4_1=ON TA=25C. 32kHz crystal for sub oscillator. PD1=ON TA=25C. PD1=ON, PD4_0=ON, PD4_1=ON TA=25C. PD1=ON, PD4_0=ON or PD4_1=ON TA=25C. PD1=ON Page 294 of 322 S6J3310/20/30/40 Series Page Section 191 9. Electric Error) Characteristics Power off time 9.1.4.5 Poweron Conditions Correct) Power off time 226 253 9.Electric Characteristics 9.1.4.11Low Voltage Detection (External Voltage) 9.1.5 A/D converter Change Results tOFF VCC5 - 100 - - s *2 VCC5 - 100 - - s *2 Error) S6J33xxxSC, S6J33xxxUC, S6J33xxxTC, S6J33xxxVC, S6J33xxxAC, S6J33xxxBC, S6J33xxxCC, S6J33xxxDC, S6J33xxxEC, S6J33xxxFC, S6J33xxxGC, S6J33xxxHC Correct) S6J33xxxSx, S6J33xxxUx, S6J33xxxTx, S6J33xxxVx, S6J33xxxAx, S6J33xxxBx, S6J33xxxCx, S6J33xxxDx, S6J33xxxGx, S6J33xxxFx, S6J33xxxGx, S6J33xxxHx Document Number: 002-10635 Rev. *H Page 295 of 322 S6J3310/20/30/40 Series Page Section Change Results 226 9. Electric Low-voltage detection (external low-voltage detection) Characteristics Error) 9.1.4.11 Low Value Pin Parameter Symbol Conditions Voltage Name Min Typ Detection Supply 3.5 *3 (External voltage VDP5 VCC5 2.7 *4 Voltage) range Detection voltage (before VCC5 V 4.0 *3 4.4 *3 *4 *4 *4 When powerV 2.6 Remarks 3.6 *4 3.6 *3 2.3 2.9 supply voltage falls and detection level is VCC3 Detection (after Unit 5.5 *3 *1 VDLBT trimming) voltage Max VCC5 *1 VCC3 2. 6 2.9 V 3.86 *3 4.0 *3 4.14 *3 *1 VDLAT trimming) 2.3 *1 When powerV 2.51 *4 2.6 *4 2.69 *4 2.51 2.6 2.69 set initially supply voltage falls and detection level is V set initially Typ3.5% *5 *5: This detection voltage level setting is below the minimum operation assurance voltage (2.7V*4 or 4.0V*3) .Between this detection voltage and the minimum operation assurance voltage, MCU functions are not guaranteed except for the low voltage detector. Note that although the detection level is below the minimum operation guarantee voltage, the LVD reset factor flag is set as the voltage drops below the detection level. Correct) Parameter Supply voltage range Symbol Pin Name VDP5 VCC5 VDP3 VCC3 (before trimming) Min Typ Max 3.5 *3 - 5.5 *3 *4 - 3.6 *4 2.7 3.6 - *3 4.0 3.6 *3 4.4 VCC3 VCC3 V V *1 *5 2.3 *4 2.6 *4 2.9 *4 *1 *5 2.3 2. 6 2.9 *1 3.86 *3 4.0 *3 4.14 *3 *4 *4 *4 V V *1 *5 *1 *5 2.51 2.51 2.6 2.6 2.69 Remarks V VCC5 VDLAT Unit *3 VCC5 VDLBT Detection (after *1 trimming) voltage - Value 2.7 Detection voltage Conditions 2.69 V When powersupply voltage falls and detection level is set initially When powersupply voltage falls and detection level is set initially Typ3.5% *5: These LVD settings cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage(2.7V). Document Number: 002-10635 Rev. *H Page 296 of 322 S6J3310/20/30/40 Series Page Section Change Results 227 9. Electric Low-voltage detection (1.15 V power supply low-voltage detection) Characteristics Error) 9.1.4.11 Low Value Pin Parameter Symbol Conditions Voltage Name Min Typ Max Detection Supply (External voltage VRDP12 VCC12 1.09 1.21 Voltage) range Unit V Detection voltage (before When powerVRDLBT VCC12 *1 0.7125 0.8125 0.9125 V Detection (after supply voltage falls trimming) voltage Remarks When powerVRDLAT VCC12 *1 0.7841 0.8125 0.841 V supply voltage falls Typ3.5% *2 trimming) *2: This detection voltage level setting is below the minimum operation assurance voltage . Between this detection voltage and the minimum operation assurance voltage, MCU functions are not guaranteed except for the low voltage detector. Note that although the detection level is below the minimum operation guarantee voltage, the LVD reset factor flag is set as the voltage drops below the detection level. Correct) Parameter Symbol Pin Name Value Conditions Unit Min Typ Max Remarks Supply voltage VRDP12 VCC12 - 1.09 - 1.21 V VRDLBT VCC12 *1 *2 0.7125 0.8125 0.9125 V range Detection voltage (before When powerfalls trimming) Detection voltage (after trimming) supply voltage When powerVRDLAT VCC12 *1 *2 0.7841 0.8125 0.841 V supply voltage falls Typ3.5% *2: These LVD settings cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage (1.09V). Document Number: 002-10635 Rev. *H Page 297 of 322 S6J3310/20/30/40 Series Page Section Change Results 228 9. Electric Low-voltage detection (internal low-voltage detection for LVDL1) Characteristics Error) 9.1.4.12 Low Value Pin Parameter Symbol Conditions Voltage Name Min Typ Detection Supply (Internal voltage VRDP5 1.05 Voltage) range Detection voltage Max 1.21 Unit Remarks V When powerVRDLBT - *1 0.775 0.875 0.975 V supply voltage falls *3 When power- Detection voltage VRDLAT - *1 0.844 0.875 0.906 V supply voltage falls Typ3.5% *2 *3 Hysteresis width When powerVRHYS - - - 75 - mV supply voltage rises Lowvoltage detection TRd - - - - 30 s *4 time *2: This detection voltage level setting is below the minimum operation assurance voltage . Between this detection voltage and the minimum operation assurance voltage, MCU functions are not guaranteed except for the low voltage detector. Note that although the detection level is below the minimum operation guarantee voltage, the LVD reset factor flag is set as the voltage drops below the detection level. *3: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. *4: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may occur or be canceled. Document Number: 002-10635 Rev. *H Page 298 of 322 S6J3310/20/30/40 Series Page Section Change Results Correct) Parameter Symbol Pin Name Value Conditions Unit Min Typ Max Remarks Supply voltage VRDP5 - - 1.05 - 1.21 V VRDLBT - *1 *2 0.775 0.875 0.975 V range Detection voltage (before When powerfalls trimming) Detection voltage (after When powerVRDLAT - *1 *2 0.844 0.875 0.906 V trimming) Hysteresis width supply voltage supply voltage falls Typ3.5% When power- VRHYS - - - 75 - mV supply voltage rises Lowvoltage detection TRd - - - - 30 s *3 time 248 249 250 251 252 *2: This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. *3: After the brown-out event where the voltage level dips below the detection threshold for less than this time, the detection may occur or be canceled. 9. Electric Error) Characteristics 9.1.4.21 LCD Correct) bus I/F All change 9. Electric Characteristics 9.1.4.22 Pow er and Reset Sequence Error) Correct) Newly added Document Number: 002-10635 Rev. *H Page 299 of 322 S6J3310/20/30/40 Series Page Section 263 11. Ordering Information Change Results Error) Part Number S6J331EKCC******* S6J331EKBC******* S6J331EKAC******* S6J331EJCC******* S6J332EJCC******* S6J331EJAC******* S6J332EJAC******* S6J332EHSC******* S6J332EHSC******* Document Number: 002-10635 Rev. *H Package 208-pin plastic TEQFP (TEQFP208) 208-pin plastic TEQFP (TEQFP208) 208-pin plastic TEQFP (TEQFP208) 176-pin plastic TEQFP (TEQFP176) 176-pin plastic TEQFP (TEQFP176) 176-pin plastic TEQFP (TEQFP176) 176-pin plastic TEQFP (TEQFP176) 144-pin plastic TEQFP (TEQFP144) 144-pin plastic TEQFP (TEQFP144) Page 300 of 322 S6J3310/20/30/40 Series Page Section Change Results Correct) Part Number *1 Package S6J331EKEx******* 208-pin plastic TEQFP (LEW208) S6J332CKSx******* 208-pin plastic TEQFP (LEW208) S6J334CKSx******* S6J331EJAx******* S6J332CJBx******* S6J332CJTx******* 208-pin plastic TEQFP (LEW208) 176-pin plastic TEQFP (LEW176) 176-pin plastic TEQFP (LEW176) 176-pin plastic TEQFP (LEW176) S6J332EJBx******* 176-pin plastic TEQFP (LEW176) S6J334BJDx******* 176-pin plastic TEQFP (LEW176) S6J334CJEx******* S6J334CJTx******* S6J334DJEx******* S6J334DJTx******* 176-pin plastic TEQFP (LEW176) 176-pin plastic TEQFP (LEW176) 176-pin plastic TEQFP (LEW176) 176-pin plastic TEQFP (LEW176) S6J334EJAx******* 176-pin plastic TEQFP (LEW176) S6J334EJEx******* 176-pin plastic TEQFP (LEW176) 176-pin plastic TEQFP (LEW176) 144-pin plastic TEQFP S6J334CHBx******* (LEX144, LEK144) *1: x is selected from the following parameter. x : C, D (Revision) S6J334EJTx******* Rev. *E 6 2. Function List Revised the below: 2.1 Function list CAN-FD RAM (ECC supported) Error) 16KB/ch It equivalents to 128 message buffer per channel of CCAN module Correct) 16KB/ch It equivalents to 128 message buffer per channel of MCAN module Document Number: 002-10635 Rev. *H Page 301 of 322 S6J3310/20/30/40 Series Page Section 12 3. Product Description 3.2 Product description Change Results Error) Power Supply 3V external power supply should be controlled by GPIO. Correct) Power Supply 3V external power supply could be controlled by GPIO. 61 7. Port configuration 7.1 Resource Input Configuration Module Error) Correct) The Resource which are available through only one port does not have the multiplexer implemented i.e. No RIC_RESIN register. 169 9. Electric Error) Characteristics 9.1.1 Absolute Power supply voltage*1, *2 Maximum Rating Correct) Power supply voltage*1, *2 169 170 9. Electric Error) Characteristics Total maximum clamp current 9.1.1 Absolute Maximum Correct) Rating Total maximum clamp current Total maximum clamp current 9. Electric Error) Characteristics 9.1.1 Absolute Correct) Maximum Rating System Thermal Resistance Package Thermal Resistance Document Number: 002-10635 Rev. *H VCC12 VSS-0.3 VSS+1.8 V VCC12 VCC53 VCC12 VCC3 VCC12 DVCC VCC12 AVCC5 VCC12 VSS-0.3 VSS+1.8 V VCC12 AVCC5 |ICLAMP | - 50 mA SPECIAL SPEC*A |ICLAMP | |ICLAMP | - 90 65 mA mA *B *C Theta j-a1 - 17 oC/W TEQFP 208 Theta j-a2 - 19 oC/W TEQFP 176 Theta j-a3 - 20 oC/W Theta j-a4 - 22 oC/W Psi j-t1 Psi j-t2 Psi j-t3 Psi j-t4 - 0.6 1.0 2.0 2.0 oC/W oC/W oC/W oC/W The minimum value depends on the system specification of heat radiation. The described value is estimated under the condition which is specified at "9.1.2 Recommended Operating Conditions". TEQFP 144 (0.5mm Pitch) TEQFP 144 (0.4mm Pitch) TEQFP208 TEQFP176 TEQFP144 (0.5mm Pitch) TEQFP144 (0.4mm Pitch) Page 302 of 322 S6J3310/20/30/40 Series Page Section 172 9. Electric 173 Characteristics 174 9. 1 Electric Characteristics Change Results Error) Correct) Newly added *B Relevant pins: All general-purpose ports and analog input pins *C Relevant pins: All general-purpose ports and analog input pins 176 9. Electric Characteristics 9.1.2 Recommended operating condition Error) - In the case of use in VCC5 = AVCC5 = DVCC of conditions, please launch the power supply in the following sequence. Required power supply sequence is the following: VCC5 -> [DVCC or VCC53 or AVCC5 or VCC3 or AVCC3_DAC] -> VCC12 Note that power supplies inside "[ ]" can be turned on in arbitrary order. Corresponding Part number is S6J33xxxSC or S6J33xxxUC or S6J33xxxTC or S6J33xxxVC or S6J33xxxBC or S6J33xxxDC or S6J33xxxFC or S6J33xxxHC. - In the case of use in VCC5 = AVCC5 < DVCC of conditions, please launch the power supply in the following sequence. Required power supply sequence is the following: VCC5 -> DVCC -> [VCC53 or AVCC5 or VCC3 or AVCC3_DAC] -> VCC12. Note that power supplies inside "[ ]" can be turned on in arbitrary order. Corresponding Part number is S6J33xxxAC or S6J33xxxCC or S6J33xxxEC or S6J33xxxGC. Correct) - Required power supply sequence is the following: {VCC5 -> AVCC5} -> [DVCC, VCC12, VCC3, AVCC3_DAC] Note that power supplies inside "[ ]" can be turned on in arbitrary order and "{ }" can be turned on in shown sequence or simultaneously. Document Number: 002-10635 Rev. *H Page 303 of 322 S6J3310/20/30/40 Series Page Section 177 9. Electric Characteristics 9.1.2 Recommended operating condition Change Results Error) Correct) Note: -TA: Ambient temperature (JEDEC) -TC: Case temperature (JEDEC), the maximum measured temperature of package case top. -Both rating of TA and TC should simultaneously be satisfied as maximum operation temperature. -The following condition should be satisfied in order to facilitate heat dissipation. 1. Four or more layers PCB should be used. 2. The area of PCB should be 114.3 mm x 76.2 mm or more, and the thickness should be 1.6 mm or more. (JEDEC standard) 3. One layer of middle layers at least should be used for dedicated layer to radiate heat with residual copper rate 90% or more. The layer can be used for system ground. 4. 35% or more of the die stage area which is exposed at back surface of package should be soldered to a part of 1st layer. 5. The part of 1st layer should be connected to the dedicated heat radiation layer with more than 10 thermal via holes. Example thermal via holes on PCB <Figure> - The above figure is a schematic diagram showing PCB in section. - Thermal via holes should closely be placed and aligned with lands. - It is recommended to connect the land pattern to the VSS-ground level (GND plan of inner layer bellow the MCU) as thermal heat sink. Document Number: 002-10635 Rev. *H Page 304 of 322 S6J3310/20/30/40 Series Page Section 185 9. Electric Error) Characteristics 9.1.3 DC Parameter characteristics Power supply current Change Results Symbol ICC12 Pin Name Value Conditions Unit Min Typ Normal operation - 500 1000 mA Flash write/erase - 550 1050 mA Timer/ Stop Mode - - 650 mA VCC 12 ICCH12 Remarks Max TA=-40 ~ 105C CPU:240MHz, HPM:120MHz (CPU:200MHz, HPM:200MHz) GDC : 200MHz TA=-40 ~ 105C CPU:240MHz, HPM:120MHz (CPU:200MHz, HPM:200MHz) GDC : 200MHz Correct) Parameter Symbol Pin Name Value Conditions Min - Typ 320 Unit Remarks mA TA=-40 ~ 105C CPU:240MHz, HPM:120MHz (CPU:200MHz, HPM:200MHz) GDC : 200MHz mA Example use case *1 TA=-40 ~ 105C CPU:60MHz, HPM:60MHz GDC : 60MHz TA=-40 ~ 105C CPU:240MHz, HPM:120MHz (CPU:200MHz, HPM:200MHz) GDC : 200MHz Max 800 Normal operation Power supply current ICC12 ICCH12 186 9. Electric Characteristics 9.1.3 DC characteristics - VCC 12 - 395 Flash write/erase - 350 850 mA Timer/ Stop Mode - - 430 mA Error) Correct) *1 : Example use case at following condition CPU:60MHz, HPM:60MHz, GDC : 60MHz Peripherals: - DMAC active (WorkFlash => SystemRAM) - All timers active - 6 SMCs, 1 CAN, 2LIN, 1SPI, PWMs, ADCs Display controller: - 2 (= all) layers active (60 MHz, noise RGBA, 32 bpp, 2048 x 5 pixels) - Any other resources inactive - IOs no toggle Document Number: 002-10635 Rev. *H Page 305 of 322 S6J3310/20/30/40 Series Page Section 254 9. Electric 255 Characteristics 256 9.1.4.22 Power and Reset Sequence 266 9. Electric Characteristics 9.1.7.1 Electrical Characteristics Change Results Error) Correct) Newly added Case-1, Case2-1 and Case2-2 Error) Parameter Sector erase time 16bit write time(Program) 32bit write time(Program) 64bit write time(Program) 256bit write time(Program) Page mode write time(Program) 32bit write time(Work) Min Rating Typ Max*3 Unit - 120 480 ms - 120 480 ms - 120 480 ms - 30 384 s - 30 384 s - 30 384 s - 40 - 320 - 30 Min Rating Typ Max*3 Unit - 120 180 ms - 120 180 ms - 120 180 ms - 30 60 s - 30 60 s - 30 60 s - 40 - 320 - 30 512 4096 384 s s s Remarks Large sector*1 Internal preprogramming time included 8kB sector*1 Internal preprogramming time included 4kB sector*1 Internal preprogramming time included System-level overhead time excluded*1 System-level overhead time excluded*1 System-level overhead time excluded*1 System-level overhead time excluded*1 System-level overhead time excluded*1 System-level overhead time excluded*1 Correct) Parameter Sector erase time 16bit write time(Program) 32bit write time(Program) 64bit write time(Program) 256bit write time(Program) Page mode write time(Program) 32bit write time(Work) Document Number: 002-10635 Rev. *H 70 600 60 s s s Remarks Large sector*1 Internal preprogramming time included 8kB sector*1 Internal preprogramming time included 4kB sector*1 Internal preprogramming time included System-level overhead time excluded*1 System-level overhead time excluded*1 System-level overhead time excluded*1 System-level overhead time excluded*1 System-level overhead time excluded*1 System-level overhead time excluded*1 Page 306 of 322 S6J3310/20/30/40 Series Page Section 270 12. Appendix 12.1 Application 1: JTAG tool connection Rev. *F 4 1. Overview 1.2 Document Definition Change Results Error) Correct) Newly added this section Error) Table 1-1 Correct) Table 1-1: Document Definition 5 2. Function List Error) 2.1 Function Table 2-1 List Correct) Table 2-1: Function Lineup 7 2. Function List Error) 2.2.1 Basic Figure 2-1 option Correct) Figure 2-1: Option and Part Number for S6J3310/20/30/40 Series 2. Function List Error) 2.2.1 Basic Revision: Revision version option Correct) Revision: 7 Digit C D E Description Fixed Operation frequency of embedded Program Flash and CPU, Fixed Stabilization time for sub oscillator Fixed TCFLASH Sector Write Permission and Data Retention after Reset Leakage current improvement 8 2. Function List Error) 2.2.3 Table 2-2 Restriction Correct) Table 2-2: Pin Restriction 10 3. Product Description 3.2 Product Description Error) Table 3-1 Correct) Table 3-1: Product Features Document Number: 002-10635 Rev. *H Page 307 of 322 S6J3310/20/30/40 Series Page 17 18 19 20 21 22 23 24 25 26 27 28 Section 4. Package and Pin Assignment 4.1 Pin Assignment Change Results Error) z : C, D (Revision) Correct) z : C, D, E (Revision) Document Number: 002-10635 Rev. *H Page 308 of 322 S6J3310/20/30/40 Series Page Section 185 9. Electric Error) Characteristics 9.1.3 DC Parameter characteristics Change Results Symbol Pin Name Value Conditions Unit Min Typ - 320 800 mA - - 395 mA - 350 850 mA - - 430 mA - 45 85 mA - - 100 mA Normal operation ICC12 Power supply current VCC1 2 Flash write/erase ICCH12 ICC5 VCC5 Timer/ Stop Mode Normal operation Flash write/erase Remarks Max TA=-40 ~ 105C CPU:240MHz, HPM:120MHz (CPU:200MHz, HPM:200MHz) GDC : 200MHz Example use case *1 TA=-40 ~ 105C CPU:60MHz, HPM:60MHz GDC : 60MHz TA=-40 ~ 105C CPU:240MHz, HPM:120MHz (CPU:200MHz, HPM:200MHz) GDC : 200MHz Correct) Parameter Symbol Pin Name Value Conditions Unit Min Typ - 315 775 mA - - 395 mA - 320 780 mA - - 420 mA - 25 45 mA - - 60 mA Normal operation ICC12 Power supply current VCC1 2 Flash write/erase ICCH12 ICC5 Document Number: 002-10635 Rev. *H VCC5 Timer/ Stop Mode Normal operation Flash write/erase Remarks Max TA=-40 ~ 105 C CPU: 240 MHz, HPM: 120 MHz (CPU: 200 MHz, HPM: 200 MHz) GDC: 200 MHz Example use case *1 TA=-40 ~ 105 C CPU:60 MHz, HPM:60 MHz GDC : 60 MHz TA=-40 ~ 105C CPU: 240 MHz, HPM: 120 MHz (CPU: 200 MHz, HPM: 200 MHz) GDC : 200 MHz Page 309 of 322 S6J3310/20/30/40 Series Page Section 187 9. Electric Error) Characteristics 9.1.3 DC characteristics Correct) Paramete r Change Results Symb ol Pin Name Timer mode ICCT5 Power supply current * Condition s VCC5 ICCH5 Stop mode Value Min Typ Max Unit - 345 630 A - 340 625 A - 335 620 A - 420 705 A - 415 700 A - 410 695 A - 80 135 A - 75 130 A - 70 125 A - 75 130 A - 70 125 A - 65 120 A Remarks TA=25 C. 4 MHz crystal for main oscillator PD1=ON, PD4_0=ON, PD4_1=ON TA=25 C. 4 MHz crystal for main oscillator. PD1=ON, PD4_0=ON or PD4_1=ON TA=25C. 4 MHz crystal for main oscillator. PD1=ON TA=25 C. 8 MHz crystal for main oscillator PD1=ON, PD4_0=ON, PD4_1=ON TA=25 C. 8 MHz crystal for main oscillator. PD1=ON, PD4_0=ON or PD4_1=ON TA=25 C. 8 MHz crystal for main oscillator. PD1=ON TA=25 C. 32 kHz crystal for sub oscillator PD1=ON, PD4_0=ON, PD4_1=ON TA=25 C. 32 kHz crystal for sub oscillator. PD1=ON, PD4_0=ON or PD4_1=ON TA=25 C. 32 kHz crystal for sub oscillator. PD1=ON TA=25 C. PD1=ON, PD4_0=ON, PD4_1=ON TA=25 C. PD1=ON, PD4_0=ON or PD4_1=ON TA=25 C. PD1=ON * Electric Characteristics for S6J33xxxxE. Document Number: 002-10635 Rev. *H Page 310 of 322 S6J3310/20/30/40 Series Page Section 264 9. Electric 265 Characteristics 9.1.6 Audio DAC Change Results Error) Figure 9-1 Figure 9-2 Figure 9-3 Correct) Figure 9-1: Connection between RL and AVCC_DAC/2 (Example) Figure 9-2: Startup Time Figure 9-3: Coupling Capacitance (Example) 270 11. Ordering Information Error) x : C,D (Revision) Correct) x : C,D, E (Revision) Rev. *G 6 2. Function List Function: CRC 2.1. Function List Error) 1 unit Correct) 4 units 6 2. Function List Function: DDR HSSPI 2.1. Function List Error) 2 ch Correct) 1 ch 8 2. Function List 2.2.2 ID Error) Function Digit S,U,T,V A,C,E,G B,D,F,H Revision Chip ID C 0x10122100 D 0x10122200 C 0x10128100 D 0x10128200 C 0x10120100 D 0x10120200 JTAG ID 0x1000B5CF Correct) Function Digit S,U,T,V A,C,E,G B,D,F,H Document Number: 002-10635 Rev. *H Revision Chip ID C 0x10122100 D, E 0x10122200 C 0x10128100 D, E 0x10128200 C 0x10120100 D, E 0x10120200 JTAG ID 0x1000B5CF Page 311 of 322 S6J3310/20/30/40 Series Page 10 Section Change Results 3: Product Feature: Clock Description Error) 3.2. Product - Description Correct) Main Oscillation Stabilization Wait Time (at 4 MHz):8.19ms (Initial value) 10 3: Product Error) Description - 3.2. Product Description Correct) Feature: Embedded CR oscillation See the TraveoTM Platform hardware manual in detail. Stabilization time is as followings. - 0.35 ms to 0.8 ms for 4 MHz (Fast clock) - 0.43 ms to 1.28 ms for 100 kHz (Slow clock) 11 3: Product Description 3.2. Product Description Feature: Reset Error) Based on Cortex R5F platform Following resets are not mounted on this device. - INITX - SRSTX Correct) RSTX pin + MD pin simultaneous assert INITX (Same as INITX pin input) - Occurrence factor: Simultaneously inputting "L" level to RSTX pin and inputting "L" level to MD pin - Release factor: Inputting "H" level to RSTX pin See the TraveoTM Platform hardware manual in detail. Following resets are not mounted on this device. - SRSTX (and nSRST pin) The product series does not support EX5VRST and writing EX5VRSTCNT bits in SYSC0_SPECFGR has no effect. 11 3: Product Feature: PLL / SSCG PLL Description Error) 3.2. Product Down spread mode is only supported and available. Description Correct) Product supports down spread and center spread modes with the conditions defined in 9.1.4.3 "Internal Clock Timing". 12 3: Product Feature: Embedded Program/Work Flash Memory Description Error) 3.2. Product Work Flash can be accessed with 0-wait-cycle if CPU frequency is 12.5MHz or less. Description 7-wait-cycle: 80MHz or less. 13-wait-cycle: 160MHz or less. Correct) Work Flash can be accessed with 0-wait-cycle if CPU frequency is 12.5MHz or less. 6-wait-cycle: 80MHz or less. 12-wait-cycle: 160MHz or less. Document Number: 002-10635 Rev. *H Page 312 of 322 S6J3310/20/30/40 Series Page 13 Section Change Results 3: Product Feature: I2S Description Error) 3.2. Product - I2S has its own PPU, but the function is fixed to disable. Description Correct) - 14 3: Product Feature: Multi-Functional Serial (MFS) Description Error) Some ports of MFS have the dedicated I/O for I2C. See Port description list in detail. When the voltage supply of I2C interface is 5.0 V, it cannot use the I/O cells of 3.3 V voltage supply for the I2C terminal. CTS/RTS is not mounted (hardware flow control is not supported for this series.) 3.2. Product Description Correct) Only 2 ports of MFS have the dedicated I/O for I2C. See I2C timing in 9.1.4.6 Multi-Function Serial in detail. The I2C is not designed to be hot swappable. CTS/RTS is not mounted (hardware flow control is not supported for this series.) 14 3: Product Feature: Hyper BUS I/F Description Error) 3.2. Product The following register is not supported and cannot be used. Description - Controller Status Register (HYPERBUSIn_CSR) - Interrupt Status Register (HYPERBUSIn_ISR) - Write Protection Register (HYPERBUSIn_WPR) - Test Register (HYPERBUSIn_TEST) Correct) The following register is not supported and cannot be used. - Controller Status Register (HYPERBUSIn_CSR) - Interrupt Enable Register (HYPERBUSIn_IEN) - Interrupt Status Register (HYPERBUSIn_ISR) - Write Protection Register (HYPERBUSIn_WPR) - Test Register (HYPERBUSIn_TEST) Document Number: 002-10635 Rev. *H Page 313 of 322 S6J3310/20/30/40 Series Page 266 Section 9. Electric Change Results Error) Characteristics Parameter 9.1.7.1 Electrical Min Rating Typ Max*3 Unit Remarks Large sector*1 Internal preprogramming time included - 120 180 ms - 120 180 ms - 120 180 ms 16bit write time(Program) - 30 60 s System-level overhead time excluded*1 32bit write time(Program) - 30 60 s System-level overhead time excluded*1 64bit write time(Program) - 30 60 s System-level overhead time excluded*1 256bit write time(Program) - 40 70 s System-level overhead time excluded*1 Page mode write time(Program) - 320 s System-level overhead time excluded*1 - 30 60 s System-level overhead time excluded*1 1,000/20 years - - - Temperature at write/erase time Average temperature TA=+85 degrees Celsius - - - Temperature at write/erase time Average temperature TA=+85 degrees Celsius Characteristics Sector erase time 32bit write time(Work) Erase count / Data retention time(Program)*3 1,000/20 years Erase count / 10,000/10 Data retention time(Work)*3 years 100,000/5 years *1: Guaranteed value for up to 1,000 erases 600 8kB sector*1 Internal preprogramming time included 4kB sector*1 Internal preprogramming time included *2: Guaranteed value for up to 100,000 erases *3: Target Value Correct) Parameter Min Rating Typ Max Unit Remarks Large sector*1 Internal preprogramming time included - 120 180 ms - 120 180 ms - 120 180 ms 16-bit write time (Program) - 30 60 s System-level overhead time excluded*1 32-bit write time (Program) - 30 60 s System-level overhead time excluded*1 64-bit write time (Program) - 30 60 s System-level overhead time excluded*1 256-bit write time (Program) - 40 70 s System-level overhead time excluded*1 Page mode write time (Program) - 320 s System-level overhead time excluded*1 32-bit write time (Work) - 30 60 s System-level overhead time excluded*2 - - - Temperature at write/erase time Average temperature TA = +85 degrees Celsius - - - Temperature at write/erase time Average temperature TA = +85 degrees Celsius Sector erase time Erase count / Data retention time (Program) 1,000/20 years 1,000/20 years Erase count / 10,000/10 Data retention time (Work) years 100,000/5 years *1: Guaranteed value for up to 1,000 erases 600 8 kB sector*1 Internal preprogramming time included 4 kB sector*2 Internal preprogramming time included *2: Guaranteed value for up to 100,000 erases Document Number: 002-10635 Rev. *H Page 314 of 322 S6J3310/20/30/40 Series Page Section Rev. *H 1. Overview 4 Change Results Added the Document Definition as below. 1.2 Document Definition Error Document Type S6J3310/20/30/40 Datasheet S6J3300 Hardware Manual TraveoTM Platform Hardware Manual Definition The function and its characteristics are specified quantitatively. Primary User Investigator and hardware engineer Document Code 002-10635 The function and its operation of S6J3300 Software engineer 002-10185 Software engineer 002-07884 series are described. The function and its operation of CPU core platform are described. Correct Document Type Definition Primary User Document Code This document. S6J3310/20/30/40 The function and its Investigator and hardware Datasheet characteristics are engineer 002-10635 specified quantitatively. S6J3300 Hardware Manual S6J3300 Series 32-bit Microcontroller TraveoTM Family Hardware Manual The function and its Software engineer 002-10185 Software engineer 002-07884 operation of S6J3300 series are described. TraveoTM Platform 32-Bit Microcontroller TraveoTM Family S6J33xx, S6J34xx, S6J35xx Series Hardware Manual Platform Part Hardware Manual The function and its operation of CPU core platform are described. 14 3: Product Deleted as below. Description 3.2. Product -Note: The description of the preliminary documentation will be changed without any notification. Description Document Number: 002-10635 Rev. *H Page 315 of 322 S6J3310/20/30/40 Series Page 175 Section 9. Electric Change Results Added the Hysteresis voltage as below. Characteristics 9.1.3 DC Correct) Characteristics VHYS1 VHYS2 VHYS3 VHYS4 VHYS5 VHYS6 Hysteresis voltage VHYS7 VHYS8 VHYS9 VHYS10 VHYS11 Document Number: 002-10635 Rev. *H P0_00 to P0_20, P2_09 to P2_19, P3_00 to P3_07, P3_24 to P3_31, P4_00 to P4_07 P1_03 to P1_16, P3_08 to P3_23, P4_08 to P4_23 P1_09, P1_10, P1_15, P1_16 P1_17 to P1_31, P2_00 to P2_08, P4_24 to P4_31 RSTX NMIX MD JTAG_NTRST JTAG_TCK JTAG_TDI JTAG_TMS VHYS12 P0_21 to P0_31, P1_00 to P1_02 VHYS13 P0_21 to P0_31 VHYS14 P1_00 to P1_02 CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected CMOS hysteresis input level is selected Automotive input level is selected TTL input level is selected CMOS hysteresis input level is selected Automotive input level is selected - 0.05xVCC53 - V - 0.03xVCC53 - V - 0.035 - V - 0.05xVCC5 - V - 0.03xVCC5 - V - 0.035 - V - 0.05xDVCC - V - 0.03xDVCC - V - - 0.05xVCC5 - V - - 0.05xVCC5 - V - - 0.035 - V - 0.05xVCC3 - V - 0.035 - V - 0.080 - V CMOS hysteresis input level is selected TTL input level is selected - MediaL B Page 316 of 322 S6J3310/20/30/40 Series Page 187 Section 9. Electric Change Results Added the *4 in "Remarks" column Characteristics 9.1.4.3 Internal Error) Clock Timing SSCG0 output clock SSCG1 output clock SSCG2 output clock SSCG3 output clock PLL0 output clock PLL1 output clock PLL2 output clock PLL3 output clock Correct) SSCG0 output clock *4 SSCG1 output clock *4 SSCG2 output clock *4 SSCG3 output clock *4 PLL0 output clock *4 PLL1 output clock *4 PLL2 output clock *4 PLL3 output clock *4 188 9. Electric Added the below *4 sentence. Characteristics 9.1.4.3 Internal Error) Clock Timing (none) Correct) *4: The PLLx/SSCGx cannot set under 200MHz. 195, 9. Electric 198, Characteristics Modified the shading document name as below. 201, 9.1.4 AC Error) 204, Characteristics For details, see the hardware manual. 207, 210, Correct) 213, For details, see the TraveoTM Platform Hardware Manual. 216, 249 227 9. Electric Modified the shading document name as below. Characteristics 9.1.4 AC Error) Characteristics Please refer to Product Hardware Manual for available list. Correct) Please refer to S6J3300 series Hardware Manual for available list. Document Number: 002-10635 Rev. *H Page 317 of 322 S6J3310/20/30/40 Series Page 265 Section 11. Ordering Change Results Revised as below. Information Error) Document Number: 002-10635 Rev. *H Part Number *1 Package S6J331EKEx******* 208-pin plastic TEQFP (LEW208) S6J332CKSx******* 208-pin plastic TEQFP (LEW208) S6J334CKSx******* 208-pin plastic TEQFP (LEW208) S6J331EJAx******* 176-pin plastic TEQFP (LEV176) S6J332CJBx******* 176-pin plastic TEQFP (LEV176) S6J332CJTx******* 176-pin plastic TEQFP (LEV176) S6J332EJBx******* 176-pin plastic TEQFP (LEV176) S6J334BJDx******* 176-pin plastic TEQFP (LEV176) S6J334CJEx******* 176-pin plastic TEQFP (LEV176) S6J334CJTx******* 176-pin plastic TEQFP (LEV176) S6J334DJEx******* 176-pin plastic TEQFP (LEV176) S6J334DJTx******* 176-pin plastic TEQFP (LEV176) S6J334EJAx******* 176-pin plastic TEQFP (LEV176) S6J334EJEx******* 176-pin plastic TEQFP (LEV176) S6J334EJTx******* 176-pin plastic TEQFP (LEV176) S6J334CHBx******* 144-pin plastic TEQFP (LEX144, LEK144) Page 318 of 322 S6J3310/20/30/40 Series Page 265 Section 11. Ordering Change Results Correct) Information Part Number S6J331EKSESE20000 S6J332CKSDSE20000 S6J334CKSESE20000 S6J331EJSESE20000 S6J332EJBDSE20000 S6J332EJTDSE20000 S6J332EJBESE20000 S6J332EJTESE20000 S6J332DJEESE20000 S6J334BJDDSE20000 S6J334EJBESE20000 S6J334EJTESE20000 S6J334EJEESE20000 S6J334DJTESE20000 S6J334DJEESE20000 S6J334CJBESE20000 S6J334CJEESE20000 S6J334BJDESE20000 S6J334EJTCSE2000A S6J334EJEDSE2000A S6J332EHBESE20000 S6J334EHEESE20000 S6J334DHEESE20000 S6J334DHFESE20000 S6J334CHEESE20000 S6J334CHFESE20000 Document Number: 002-10635 Rev. *H Package 208-pin plastic TEQFP (LEW208) 208-pin plastic TEQFP (LEW208) 208-pin plastic TEQFP (LEW208) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 176-pin plastic TEQFP (LEV176) 144-pin plastic TEQFP (LEX144, LEK144) 144-pin plastic TEQFP (LEX144, LEK144) 144-pin plastic TEQFP (LEX144, LEK144) 144-pin plastic TEQFP (LEX144, LEK144) 144-pin plastic TEQFP (LEX144, LEK144) 144-pin plastic TEQFP (LEX144, LEK144) Page 319 of 322 S6J3310/20/30/40 Series Document History Document Title: S6J3310 Series/S6J3320 Series/S6J3330 Series/S6J3340 Series, 32-bit Microcontroller TraveoTM Family Document Number: 002-10635 Revision ECN Orig. of Change Submission Date ** 5063970 TMOR 01/25/2016 *A 5203759 TMOR 04/06/2016 Description of Change New Spec. Correct device revision, Chip ID, LVD spec, DDR-HSSPI spec, Hyper BUS spec, and MediaLB spec For detail, see "Major Changes". Additional Handling Devices comments(Method to Switch off VCC12 during Poweroff Sequence), LCD BUS I/F AC spec, Internal operation clock frequency comments, LVD comments, and ADC Units vs channel comments *B 5371697 TMOR 07/25/2016 The package dimension of TEQFP144 (0.4mm Pitch) correct from the provisional version to the formal version. TYPO: I2C Fast Mode For detail, see "Major Changes" - ID add -ICCT, ICCH spec add -LCD bus I/F spec revise *C 5622186 MATO 02/07/2017 -Power and RSTX sequence add -Ordering Information revise For detail, see "Major Changes" *D 5691761 HARA 04/27/2017 Updated logo and copyright. -Special spec of total maximum clamp current add -Icc12, Icch12 spec change *E 5782663 MATO 06/26/2017 -Power sequence add -Flash write/erase spec change For detail, see "Major Changes" -Revision change -Power supply current for S6J33xxxxE add *F 5947678 MATO 10/27/2017 -Ordering Information change For detail, see "Major Changes" -Function list and Product Description change *G 5969954 MATO Document Number: 002-10635 Rev. *H 11/20/2017 For detail, see "Major Changes" Page 320 of 322 S6J3310/20/30/40 Series Revision ECN Orig. of Change Submission Date Description of Change -Document Definition change -Hysteresis voltage add in DC Characteristics *H 6136290 GSHI 04/17/2018 -PLLx/SSCGx minimum clock frequencies add in Internal Clock Timing -Ordering Information change For detail, see "Major Changes Document Number: 002-10635 Rev. *H Page 321 of 322 S6J3310/20/30/40 Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. 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Document Number: 002-10635 Rev. *H April 17, 2018 Page 322 of 322