DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 1
© 1998–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
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Features
• Optimized for high-performance 3.3V systems
- 5 ns pin-to-pin logic delays, with internal system
frequency up to 208 MHz
- Small footprint packages including VQFPs, TQFPs
and CSPs (Chip Scale Package)
- Pb-free available for all packages
- Lower power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
FastFLASH technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
FastCONNECT II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Supports hot-plugging capability
- Full IEEE Std 1149.1 boundary-scan (JTAG)
support on all devices
• Four pin-compatible device densities
- 36 to 288 macrocells, with 800 to 6400 usable
gates
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- 10,000 program/erase cycles endurance rating
- 20 year data retention
• Pin-compatible with 5V core XC9500 family in common
package footprints
0
XC9500XL High-Performance CPLD
Family Data Sheet
DS054 (v2.5) May 22, 2009 00 Product Specification
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Table 1: XC9500XL Device Family
XC9536XL XC9572XL XC95144XL XC95288XL
Macrocells 36 72 144 288
Usable Gates 800 1,600 3,200 6,400
Registers 36 72 144 288
TPD (ns) 5556
TSU (ns) 3.7 3.7 3.7 4.0
TCO (ns) 3.5 3.5 3.5 3.8
fSYSTEM (MHz) 178 178 178 208
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 2
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Table 2: XC9500XL Packages and User I/O Pins (not including 4 dedicated JTAG pins)
Package(1) XC9536XL XC9572XL XC95144XL XC95288XL
PC44 34 34 - -
PCG44 34 34
VQ44 34 34 - -
VQG44 34 34
CS48 36 38 - -
CSG48 36 38
VQ64 36 52 - -
VQG64 36 52
TQ100 - 72 81 -
TQG100 72 81
CS144 - - 117 -
CSG144 117
TQ144 - - 117 117
TQG144 117 117
PQ208 - - - 168
PQG208 168
BG256 - - - 192
BGG256 192
FG256 - - - 192
FGG256 192
CS280 - - - 192
CSG280 192
Notes:
1. The letter "G" as the third character indicates a Pb-free package.
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 3
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Family Overview
The FastFLASH XC9500XL family is a 3.3V CPLD family
targeted for high-performance, low-voltage applications in
leading-edge communications and computing systems,
where high device reliability and low power dissipation is
important. Each XC9500XL device supports in-system pro-
gramming (ISP) and the full IEEE Std 1149.1 (JTAG) bound-
ary-scan, allowing superior debug and design iteration
capability for small form-factor packages. The XC9500XL
family is designed to work closely with the Xilinx® Virtex®,
Spartan®-XL and XC4000XL FPGA families, allowing sys-
tem designers to partition logic optimally between fast inter-
face circuitry and high-density general purpose logic. As
shown in Ta bl e 1 , logic density of the XC9500XL devices
ranges from 800 to 6400 usable gates with 36 to 288 regis-
ters, respectively. Multiple package options and associated
I/O capacity are shown in Ta bl e 2 . The XC9500XL family
members are fully pin-compatible, allowing easy design
migration across multiple density options in a given package
footprint.
The XC9500XL architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. In-system program-
ming throughout the full commercial operating range and a
high programming endurance rating provide worry-free
reconfigurations of system field upgrades. Extended data
retention supports longer and more reliable system operat-
ing life.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. Each user pin is compatible with 5V, 3.3V, and 2.5V
inputs, and the outputs may be configured for 3.3V or 2.5V
Figure 1: XC9500XL Architecture
Note: Function block outputs (indicated by the bold lines) drive the I/O blocks directly.
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
54
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2 or 4
1
I/O
I/O
I/O
I/O
3
DS054_01_042001
Function
Block 2
54
Function
Block 3
54
18
18
18
18
Function
Block N
54
FastCONNECT II Switch Matrix
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 4
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operation. The XC9500XL device exhibits symmetric full
3.3V output voltage swing to allow balanced rise and fall
times. Additional details can be found in the application
notes listed in "Further Reading" on page 17.
Architecture Description
Each XC9500XL device is a subsystem consisting of multi-
ple Function Blocks (FBs) and I/O Blocks (IOBs) fully inter-
connected by the FastCONNECT II switch matrix. The IOB
provides buffering for device inputs and outputs. Each FB
provides programmable logic capability with extra wide
54inputs and 18 outputs. The FastCONNECT II switch
matrix connects all FB outputs and input signals to the FB
inputs. For each FB, up to 18 outputs (depending on pack-
age pin-count) and associated output enable signals drive
directly to the IOBs. See Figure 1.
Function Block
Each Function Block, as shown in Figure 2 is comprised of
18 independent macrocells, each capable of implementing
a combinatorial or registered function. The FB also receives
global clock, output enable, and set/reset signals. The FB
generates 18 outputs that drive the FastCONNECT switch
matrix. These 18 outputs and their corresponding output
enable signals also drive the IOB.
Logic within the FB is implemented using a sum-of-products
representation. Fifty-four inputs provide 108 true and com-
plement signals into the programmable AND-array to form
90 product terms. Any number of these product terms, up to
the 90 available, can be allocated to each macrocell by the
product term allocator.
Macrocell
Each XC9500XL macrocell may be individually configured
for a combinatorial or registered function. The macrocell
and associated FB logic is shown in Figure 3.
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, clock enable, set/reset, and output enable.
The product term allocator associated with each macrocell
selects how the five direct terms are used.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
are initialized to the user-defined preload state (default to 0
if unspecified).
Figure 2: XC9500XL Function Block
Macrocell 18
Macrocell 1
Programmable
AND-Array
Product
Term
Allocators
From
FastCONNECT II
Switch Matrix
DS054_02_042101
54
1
To FastCONNECT II
Switch Matrix
To I/O Blocks
OUT
Global
Set/Reset
3
18
PTOE
18
18
Global
Clocks
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 5
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All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in Figure 4, the macrocell register clock
originates from either of three global clocks or a product
term clock. Both true and complement polarities of the
selected clock source can be used within each macrocell. A
GSR input is also provided to allow user registers to be set
to a user-defined state.
Figure 3: XC9500XL Macrocell Within Function Block
DS054_03_042101
To
FastCONNECTII
Switch Matrix
Additional
Product
Terms
(from other
macrocells)
Global
Set/Reset
Global
Clocks
Additional
Product
Terms
(from other
macrocells)
To
I/O Blocks
OUT
1
0
54
3
PTOE
D/T Q
S
R
Product
Term
Allocator
Product Term Set
Product Term Clock
Product Term Reset
Product Term OE
Product Term Clock Enable
CE
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 6
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Figure 4: Macrocell Clock and Set/Reset Capability
D/T
CE
S
R
Macrocell
DS054_04_052209
I/O/GSR
Product Term Set
Product Term Clock
Product Term Reset
Global Set/Reset
Global Clock 1
Global Clock 2
Global Clock 3
I/O/GCK3
I/O/GCK2
I/O/GCK1
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 7
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Product Term Allocator
The product term allocator controls how the five direct prod-
uct terms are assigned to each macrocell. For example, all
five direct terms can drive the OR function as shown in
Figure 5.
The product term allocator can re-assign other product
terms within the FB to increase the logic capacity of a mac-
rocell beyond five direct terms. Any macrocell requiring
additional product terms can access uncommitted product
terms in other macrocells within the FB. Up to 15 product
terms can be available to a single macrocell with only a
small incremental delay of tPTA, as shown in Figure 6.
Note that the incremental delay affects only the product
terms in other macrocells. The timing of the direct product
terms is not changed.
Figure 5: Macrocell Logic Using Direct Product Term
Product Term
Allocator
Macrocell
Product Term
Logic
DS054_05_042101
Figure 6: Product Term Allocation With 15 Product
Terms
Macrocell Logic
With 15
Product Terms
Product Term
Allocator
Product Term
Allocator
DS054_06_042101
Product Term
Allocator
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 8
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The product term allocator can re-assign product terms
from any macrocell within the FB by combining partial sums
of products over several macrocells, as shown in Figure 7.
In this example, the incremental delay is only 2*TPTA. All 90
product terms are available to any macrocell, with a maxi-
mum incremental delay of 8*TPTA.
Figure 7: Product Term Allocation Over Several
Macrocells
Macrocell Logic
With 18
Product Terms
Macrocell Logic
With 2
Product Terms
Product Term
Allocator
Product Term
Allocator
DS054_07 _042101
Product Term
Allocator
Product Term
Allocator
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 9
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The internal logic of the product term allocator is shown in
Figure 8.
Figure 8: Product Term Allocator Logic
D/T Q
S
R
From Upper
Macrocell
To Upper
Macrocell
Product Term Set
Product Term Clock
Product Term Reset
Global Set/Reset
Global Set/Reset
Global Clocks
Product Term OE
Product Term
Allocator
To Lower
Macrocell
From Lower
Macrocell
DS054_08_042101
1
0
CE
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 10
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FastCONNECT II Switch Matrix
The FastCONNECT II Switch Matrix connects signals to the
FB inputs, as shown in Figure 9. All IOB outputs (corre-
sponding to user pin inputs) and all FB outputs drive the
FastCONNECT II matrix. Any of these (up to a fan-in limit of
54) may be selected to drive each FB with a uniform delay.
Figure 9: FastCONNECT II Switch Matrix
DS054_09_042101
Function Block
FastCONNECT II
Switch Matrix
(54)
I/O
Function Block
I/O Block
18
18
I/O Block
(54)
I/O
D/T Q
D/T Q
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 11
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I/O Block
The I/O Block (IOB) interfaces between the internal logic
and the device user I/O pins. Each IOB includes an input
buffer, output driver, output enable selection multiplexer,
and user programmable ground control. See Figure 10 for
details.
The input buffer is compatible with 5V CMOS, 5V TTL, 3.3V
CMOS, and 2.5V CMOS signals. The input buffer uses the
internal 3.3V voltage supply (VCCINT) to ensure that the
input thresholds are constant and do not vary with the
VCCIO voltage. Each input buffer provides input hysteresis
(50 mV typical) to help reduce system noise for input signals
with slow rise or fall edges.
Figure 10: I/O Block and Output Enable Capability
I/O Block
Macrocell
DS054_10_042101
Product Term OE PTOE
Switch Matrix
OUT
(Inversion in
AND-array)
Global OE 1
1
To other
Macrocells
Slew Rate
Control
0
Global OE 2
Available in XC95144XL
and XC95288XL
Global OE 3
Global OE 4
I/O/GTS1
I/O
I/O/GTS2
I/O/GTS3
I/O/GTS4
To FastCONNECT
User-
Programmable
Ground
Bus-Hold
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 12
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Each output driver is designed to provide fast switching with
minimal power noise. All output drivers in the device may be
configured for driving either 3.3V CMOS levels (which are
compatible with 5V TTL levels as well) or 2.5V CMOS levels
by connecting the device output voltage supply (VCCIO) to a
3.3V or 2.5V voltage supply. Figure 11 shows how the
XC9500XL device can be used in 3.3V only systems and
mixed voltage systems with any combination of 5V, 3.3V
and 2.5V power supplies.
Each output driver can also be configured for slew-rate lim-
ited operation. Output edge rates may be slowed down to
reduce system noise (with an additional time delay of tSLEW)
under user control. See Figure 12.
The output enable may be generated from one of four
options: a product term signal from the macrocell, any of the
global output enable signals (GTS), always “1,” or always
“0.” There are two global output enables for devices with 72
or fewer macrocells, and four global output enables for
devices with 144 or more macrocells. Any selected output
enable signal may be inverted locally at each pin output to
provide maximal design flexibility.
Each IOB provides user programmable ground pin capabil-
ity. This allows device I/O pins to be configured as additional
ground pins in order to force otherwise unused pins to a low
voltage state, as well as provide for additional device
grounding capability. This grounding of the pin is achieved
by internal logic that forces a logic low output regardless of
the internal macrocell signal, so the internal macrocell logic
is unaffected by the programmable ground pin capability.
Each IOB also provides for bus-hold circuitry (also called a
“keeper”) that is active during valid user operation. The
bus-hold feature eliminates the need to tie unused pins
either high or low by holding the last known state of the input
until the next input signal is present. The bus-hold circuit
drives back the same state via a nominal resistance (RBH)
of 50 kΩ. See Figure 13. Note the bus-hold output will drive
no higher than VCCIO to prevent overdriving signals when
interfacing to 2.5V components.
When the device is not in valid user operation, the bus-hold
circuit defaults to an equivalent 50 kΩ pull-up resistor in
order to provide a known repeatable device state. This
occurs when the device is in the erased state, in program-
ming mode, in JTAG INTEST mode, or during initial
power-up. A pull-down resistor (1 kΩ) may be externally
added to any pin to override the default RBH resistance to
force a low state during power-up or any of these other
modes.
5V Tolerant I/Os
The I/Os on each XC9500XL device are fully 5V tolerant
even though the core power supply is 3.3 volts. This allows
5V CMOS signals to connect directly to the XC9500XL
inputs without damage. The 3.3V VCCINT power supply
must be at least 1.5V before 5V signals are applied to the
I/Os. In mixed 3.3V/2.5V systems, the user pins, the core
power supply (VCCINT), and the output power supply
(VCCIO) may have power applied in any order.
Xilinx proprietary ESD circuitry and high impedance initial
state permit hot plugging cards using these devices.
Pin-Locking Capability
The capability to lock the user defined pin assignments dur-
ing design iteration depends on the ability of the architec-
ture to adapt to unexpected changes. The XC9500XL
devices incorporate architectural features that enhance the
ability to accept design changes while maintaining the same
pinout.
Figure 11: XC9500XL Devices in (a) 3.3V only and (b) Mixed 5V/3.3V/2.5V Systems
IN OUT
2.5V3.3V
GND
(b)
2.5V CMOS
IN OUT
XC9500XL
CPLD
XC9500XL
CPLD
VCCINT VCCIO VCCINT VCCIO
3.3V
GND
(a)
3.3V
0V
5V
0V
3.3V
0V
2.5V
0V
2.5V
0V
3.3V CMOS, 5V TTL
DS054_11_042101
2.5V CMOS
3.3V CMOS or
5V TTL or
5V
0V
5V CMOS
5V
0V
3.3V
0V
2.5V
0V
2.5V CMOS
3.3V CMOS or
5V TTL or
5V
0V
5V CMOS
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 13
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The XC9500XL architecture provides for superior pin-lock-
ing characteristics with a combination of large number of
routing switches in the FastCONNECT II switch matrix, a
54-wide input Function Block, and flexible, bidirectional
product term allocation within each macrocell. These fea-
tures address design changes that require adding or chang-
ing internal routing, including additional signals into existing
equations, or increasing equation complexity, respectively.
For extensive design changes requiring higher logic capac-
ity than is available in the initially chosen device, the new
design may be able to fit into a larger pin-compatible device
using the same pin assignments. The same board may be
used with a higher density device without the expense of
board rework.
In-System Programming
WARNING: Programming temperature range of
TA = 0° C to +70° C
One or more XC9500XL devices can be daisy chained
together and programmed in-system via a standard 4-pin
JTAG protocol, as shown in Figure 14. In-system program-
ming offers quick and efficient design iterations and elimi-
nates package handling. The Xilinx development system
provides the programming data sequence using a Xilinx
download cable, a third-party JTAG development system,
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence.
All I/Os are 3-stated and pulled high by the bus-hold cir-
cuitry during in-system programming. If a particular signal
must remain low during this time, then a pull-down resistor
may be added to the pin.
External Programming
XC9500XL devices can also be programmed by the Xilinx
HW-130 device programmer as well as third-party program-
mers. This provides the added flexibility of using pre-pro-
grammed devices during manufacturing, with an in-system
programmable option for future enhancements and design
changes.
Reliability and Endurance
All XC9500XL CPLDs provide a minimum endurance level
of 10,000 in-system program/erase cycles and a minimum
data retention of 20 years. Each device meets all functional,
performance, and data retention specifications within this
endurance limit.
IEEE Std 1149.1 Boundary-Scan (JTAG)
XC9500XL devices fully support IEEE Std 1149.1 bound-
ary-scan (JTAG). EXTEST, SAMPLE/PRELOAD, BYPASS,
USERCODE, INTEST, IDCODE, HIGHZ and CLAMP
Figure 12: Output Slew-Rate Control For (a) Rising and (b) Falling Outputs
Time
00
1.5V
Standard
Output
Voltage
(a)
Slew-Rate Limited
Time
Output
Voltage
(b)
Standard
Slew-Rate Limited
VCCIO
TSLEW TSLEW
1.5V
DS054_12_042101
Figure 13: Bus-Hold Logic
RBH
I/O
Set to PIN
during valid user
operation Drive to
VCCIO Level
PIN
0
DS054_13_042101
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 14
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instructions are supported in each device. Additional
instructions are included for in-system programming opera-
tions.
Design Security
XC9500XL devices incorporate advanced data security fea-
tures which fully protect the programming data against
unauthorized reading or inadvertent device erasure/repro-
gramming. Ta b l e 3 shows the four different security settings
available.
The read security bits can be set by the user to prevent the
internal programming pattern from being read or copied.
When set, they also inhibit further program operations but
allow device erase. Erasing the entire device is the only way
to reset the read security bit.
The write security bits provide added protection against
accidental device erasure or reprogramming when the
JTAG pins are subject to noise, such as during system
power-up. Once set, the write-protection may be deacti-
vated when the device needs to be reprogrammed with a
valid pattern with a specific sequence of JTAG instructions.
Low Power Mode
All XC9500XL devices offer a low-power mode for individual
macrocells or across all macrocells. This feature allows the
device power to be significantly reduced.
Each individual macrocell may be programmed in
low-power mode by the user. Performance-critical parts of
the application can remain in standard power mode, while
other parts of the application may be programmed for
low-power operation to reduce the overall power dissipation.
Macrocells programmed for low-power mode incur addi-
tional delay (tLP) in pin-to-pin combinatorial delay as well as
register setup time. Product term clock to output and prod-
uct term output enable delays are unaffected by the macro-
cell power-setting. Signals switching at rates less than 50 ns
rise/fall time should be assigned to the macrocells config-
ured in low power mode.
Timing Model
The uniformity of the XC9500XL architecture allows a sim-
plified timing model for the entire device. The basic timing
model, shown in Figure 15, is valid for macrocell functions
that use the direct product terms only, with standard power
setting, and standard slew rate setting. Ta b le 4 shows how
each of the key timing parameters is affected by the product
term allocator (if needed), low-power setting, and slew-lim-
ited setting.
The product term allocation time depends on the logic span
of the macrocell function, which is defined as one less than
the maximum number of allocators in the product term path.
If only direct product terms are used, then the logic span is
0. The example in Figure 6 shows that up to 15 product
terms are available with a span of 1. In the case of Figure 7,
the 18 product term function has a span of 2.
Tabl e 3 : Data Security Options
Read Security
Default Set
Write Security
Default
Read Allowed
Program/Erase
Allowed
Read Inhibited
Program Inhibited
Erase Allowed
Set
Read Allowed
Program/Erase
Allowed
Read Inhibited
Program/Erase
Inhibited
Figure 14: System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
DS054_14_052209
GND
V
CC
(a) (b)
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 15
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Detailed timing information may be derived from the full tim-
ing model shown in Figure 16. The values and explanations
for each parameter are given in the individual device data
sheets.
Figure 15: Basic Timing Model
Figure 16: Detailed Timing Model
Combinatorial
Logic
Propagation Delay = T
PD
(a)
Combinatorial
Logic
Setup Time = T
SU
TCO
TPSU
TPCO
Clock to Out Time = T
CO
(b)
D/T Q
Combinatorial
Logic
Internal System Cycle Time = T
SYSTEM
DS054_15_042101
(d)
D/T Q
Combinatorial
Logic
Setup Time = TPSU
Clock to Out Time = T
PCO
(c)
P-Term Clock
Path
D/T Q
D/T Q
SR
TIN
TLOGILP S*TPTA
TF
TPDI
TSUI TCOI
THI
TAOI
TRAI
TOUT
TSLEW
TEN
DS054_16_042101
TLOGI
TPTCK
TPTSR
TPTTS
TGCK
TGSR
TGTS
Macrocell
CE
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 16
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Power-Up Characteristics
During power-up, the XC9500XL device I/Os may be unde-
fined until VCCINT rises above 1 Volt. This time period is
called the subthreshold region, as transistors have not yet
fully turned on. If VCCIO is powered before or simultaneously
with VCCINT
, I/Os may drive during this voltage transition
range. If VCCIO is powered after VCCINT has passed through
the subthreshold region, I/Os will be in 3-state with a weak
pull-up until VCCINT reaches the threshold of the User Oper-
ation state (approximately 2.5V). When VCCINT reaches this
point, user registers are initialized (typically within 200 μs)
after which I/Os will assume the behavior determined by the
user pattern, as shown in Figure 17.
If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with
weak pull-up. The JTAG pins are enabled to allow the device
to be programmed at any time. All devices are shipped in
the erased state from the factory.
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or bound-
ary-scan tests at any time.
Development System Support
The XC9500XL family and associated in-system program-
ming capabilities are fully supported in either software solu-
tions available from Xilinx.
The Foundation Series is an all-in-one development system
containing schematic entry, HDL (VHDL, Verilog, and
ABEL), and simulation capabilities. It supports the
XC9500XL family as well as other CPLD and FPGA fami-
lies.
The Alliance Series includes CPLD and FPGA implementa-
tion technology as well as all necessary libraries and inter-
faces for Alliance partner EDA solutions.
FastFLASH Technology
An advanced 0.35 micron feature size CMOS Flash process is
used to fabricate all XC9500XL devices. The FastFLASH pro-
cess provides high performance logic capability, fast pro-
gramming times, and superior reliability and endurance
ratings.
Figure 17: Device Behavior During Power-up
VCCINT
No
Power
3.8 V
(Typ)
0V
No
Power
State
Quiescent
State
User Operation
Initialization of User Registers
DS054_17_042101
2.5V
(Typ)
1.0V
Subthreshold
State
Quiescent
Tabl e 4 : Timing Model Parameters
Parameter Description
Product Term
Allocator(1)
Macrocell
Low-Power Setting
Output Slew-Limited
Setting
TPD Propagation Delay + TPTA * S+ T
LP + TSLEW
TSU Global Clock Setup Time + TPTA * S+ T
LP –
TCO Global Clock-to-output - - + TSLEW
TPSU Product Term Clock Setup Time + TPTA * S+ T
LP -
TPCO Product Term Clock-to-output - - + TSLEW
TSYSTEM Internal System Cycle Period + TPTA * S+ T
LP -
Notes:
1. S = the logic span of the function, as defined in the text.
Tabl e 5 : XC9500XL Pin Characteristics
Device Circuitry Subthreshold State Quiescent State
Erased Device
Operation Valid User Operation
IOB Bus-Hold Undetermined Pull-up Pull-up Bus-Hold
Device I/O and Clocks Undetermined Disabled Disabled As Configured
JTAG Controller Undetermined Disabled Enabled Enabled
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 17
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Further Reading
Further information on the XC9500XL CPLD family can be found at:
http://www.xilinx.com/support/documentation/xc9500xl.htm.
This site includes:
• Pinouts contained in the density-specific data sheets
• Package electrical and thermal characteristics in UG112, Device Package User Guide
• Termination, logic thresholds, power sequencing, and slew rate information in UG445, CPLD IO User Guide
• Timing model in XAPP111, Using the XC9500XL Timing Model
• Good design practices in XAPP784, Bulletproof CPLD Design Practices
• Package drawings and dimensions at http://www.xilinx.com/support/documentation/package_specifications.htm
Revision History
The following table shows the revision history for this document.
Date Version Revision
09/28/98 1.0 Initial Xilinx release.
10/02/98 1.1 Figure 1 correction.
02/03/99 1.2 Included hot socket reference; revised layout; BGA package change for XC95288XL.
04/02/99 1.3 Minor typesetting corrections.
06/07/99 1.4 Minor typesetting corrections.
06/07/99 1.5 Added CS280 package.
01/25/02 1.6 Added DS054 data sheet number. Added 44-pin VQFP package. Updated Device Family
table.
02/07/03 1.7 Added "Further Reading" section.
08/02/04 1.8 Added Pb-free documentation.
11/11/04 1.9 Changes to package designations in Table 2 on page 2.
07/15/05 2.0 Move to Product Specification.
03/22/06 2.1 Add Warranty Disclaimer.
07/25/06 2.2 Added Subthreshold State to Figure 17 and Table 5, page 16.
04/03/07 2.3 Added warning on programming temperature range, page 13.
11/20/08 2.4 Updated "Further Reading" section.
05/22/09 2.5 Updated description of power sequencing for 5V tolerance in "5V Tolerant I/Os" section.
XC9500XL High-Performance CPLD Family Data Sheet
DS054 (v2.5) May 22, 2009 www.xilinx.com
Product Specification 18
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Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE
TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT
http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN
AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA
SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR
INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS
LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT
TO APPLICABLE LAWS AND REGULATIONS.
