BM29F040-90TC - Winbond Electronics

BRIGHT Preliminary BM29F040

Microelectronics

Inc.

4 MEGABIT (512K x 8)

5 VOLT SECTOR ERASE CMOS FLASH MEMORY

A Winbond Company Publication Release Date: May 1999

- 1 - Revision A1

GENERAL DESCRIPTION

The BM29F040 is a 4 Megabit, 5.0 Volts only Flash memory device organized as 512K × 8 bits each.

The BM29F040 is offered in an Industry standard 32-pin package which is backward compatible to 1

Megabit and also pin compatible to EEPROMs. The device is offered in PDIP, PLCC and TSOP

packages. The device is designed to be programmed and erased in system with the standard system

5 Volt Vcc supply. An external 12.0 Volts Vpp is not required for program and erase operation. The

device can also be reprogrammed in standard EPROM programmers.

The BM29F040 offers access times between 70 to 150 nS. The device has separate chip enable

(CE), write enable (

) and output enable (OE) controls to eliminate bus contention.

BMI flash memory technology reliably stores memory information even after 100,000 erase and

program cycles. The BMI proprietary cell technology enhances the programming speeds and

eliminates over erase problems seen in the classical ETOX™ type of Flash cell technologies. The

combination of cell technology and internal circuit design techniques give reduced internal electrical

fields and this provides improved reliability and endurance. The BM29F040 is entirely pin and

command set compatible to the JEDEC standard 4 Megabit EEPROM. The commands are written to

the Command State machine using standard microprocessor write timings. The internal Programming

and Erase Algorithms are automatically implemented based on the input commands.

The BM29F040 is programmed by executing the program command sequence. This will start the

internal automatic program Algorithm that times the program pulse width and also verifies the proper

cell margin. Erase is accomplished by executing the erase command sequence. The internal Power

Switching State Machine automatically executes the algorithms and generates the necessary voltages

and timings for the erase operation. The program and erase verify is also done internally and proper

margin testing is automatically performed. This scheme unburdens the microprocessor or

microcontroller from generating the program and erase algorithms by controlling all the necessary

timings and voltages. The entire memory is typically erased in 1.5 seconds. No preprogramming is

necessary in this technology.

The BM29F040 also features a sector erase architecture. It is divided into 8 sectors of 64K bytes

each. Each sector can be erased individually without affecting the data in other sectors or they can be

erased in a random combination of groups. This multiple sector erase capability or full chip erase

makes it very flexible to alter the data in BM29F040. To protect the data from accidental program or

erase the device also has a sector protect or multiple sector protect function.

The device features a single 5 Volt power supply for read, program and erase operation. Internally

generated and well regulated voltages are provided for the program and erase operation. A low Vcc

detector inhibits write operations during power transitions. The end of program or erase is detected by

Data polling of DQ7 or by the Toggle Bit feature on DQ6. Once the program or erase cycle has been

successfully completed, the device internally resets to Read mode.

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FEATURES

•5.0 V +/- 10% Program and Erase

−Minimizes system power consumption

−Simplifies the system design

•Compatible with JEDEC standard commands

−Uses same software commands as

EEPROMs

•Compatible with JEDEC-standard byte wide

pinout

−32 pin PLCC/TSOP

−32 pin DIP

•Automated sector/chip Erase Algorithms

−No programming before Erase needed

−Internal program and Erase Margin Check

•Data Polling and Toggle Bit

−useful for detection of Program and Erase

cycle completion

•Sector Erase architecture

−8 Equal sectors of 64K bytes each

−Any combination of multiple Sector Erase

−Full Chip Erase

•Sector Protection

−Any number of sectors can be protected from

Program and Erase operation

•Low Power Consumption

•Typically 100,000 Program/Erase cycles

•Erase Suspend and Resume

−Suspend the Sector Erase Operation to

allow a READ in another sector

• Low Vcc Write inhibit < 3.2 volts

• Single Cycle reset command

Product Selection Guide

FAMILY PART NO: -75* -90 -120 -150

Maximum Access Time (nS) 70 90 120 150

CE (E) Access time (nS) 70 90 120 150

OE (G) Access time (nS) 30 35 50 60

Table 1

*This speed is available with Vcc = 5V +/- 5% variation

BRIGHT Preliminary BM29F040

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A Winbond Company Publication Release Date: May 1999

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PIN CONFIGURATIONS

DIP Top View

A18

A16

A15

A12

I/O0

I/O1

I/O2

GND

Vcc

A17

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

PLCC Top View

14 15 16 17 18 19 20

A14

A13

A11

A10

I/O7

I/O's 1 2 3 4 5 6

GND

A15 A18 WE

I/O0

3031

A12 A16 Vcc A17

TSOP Top View

TYPE 1

A11

A13

A14

A17

VCC

A18

A16

A15

A12

A10

I/07

I/06

I/05

I/04

I/03

GND

I/02

I/01

I/00

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Flexible Sector-erase Architecture:

64K bytes per sector

Individual sector, multiple sector or bulk erase capability.

Individual or multiple-sector protection is user definable.

Table 2. Sector Definition

64K byte sector 70000H-7FFFFH

64K byte sector 60000H-6FFFFH

64K byte sector 50000H-5FFFFH

64K byte sector 40000H-4FFFFH

64K byte sector 30000H-3FFFFH

64K byte sector 20000H-2FFFFH

64K byte sector 10000H-1FFFFH

64K byte sector 00000H-0FFFFH

PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

A0 - A18 IADDRESS INPUTS: for memory addresses. Addresses are internally

latched during a write cycle.

A9IADDRESS INPUT: When A9 is at 12 Volts the ID mode is accessed. During

this mode A0 decodes between the manufacturer and device ID′s.

DQ0-DQ7I/O DATA INPUTS / OUTPUTS: Inputs array data on the fourth CE and WE

cycle during a program command. Inputs commands WE to the Command

program cycles. Outputs are from Array and Intelligent Identifier

information. The output pins float to tri-state when the chip is deselected or

the outputs are disabled.

CE ICHIP ENABLE: Activates the device's control logic, input buffers, decoders

and sense amplifiers. CE is active low control; CE high deselects the

memory device and reduces power consumption to standby levels.

IOUTPUT ENABLE: OE is active low control signal. This pin gates the

device’s outputs through the data buffers during a read cycle. When CE is

low and OE is high the outputs are tri-state.

IWRITE ENABLE: Controls writes to the Command state Machine and

memory array. WE is active low signal. Addresses and Data are latched

during the rising edge of the WE pulse.

Vcc DEVICE POWER SUPPLY: Main power source to the device. It′s value is

5V ± 10% or 5V ± 5%.

GND GROUND: The device ground for the internal circuitry.

Table 3

BRIGHT Preliminary BM29F040

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A Winbond Company Publication Release Date: May 1999

- 5 - Revision A1

BLOCK DIAGRAM

DQ0 - DQ 7

A0 - A18

Data

latch

Input / output

Buffers

Chip Enable

Output Enable

Logic

Y-MUX / SENSING

ARRAY

Y-Decode

X-decode

State

Control

Command

Vcc

GND

Vcc Detect

Timer

Erase Voltage

Generator

Program Voltage

Generator

Figure 1

BUS OPERATION

Operation CE OE WE A0 A1 A6 A9 I/O

Auto select Manufacturers ID (1) L L HL L L VID Code

Auto select Device ID (1) L L H H L L VID Code

Read L L HA0A1A6A9Dout

Standby HX X X X X X High Z

Output Disable LH H X X X X High Z

Write LHLA0A1A6A9Din (2)

Enable Sector Protect LVID LX X X VID X

Verify Sector Protect (3) L L HLHLVID Code

Table 4

Notes:

1. LEGENDS: L = VIL, H = VIH, X = don't care, VID = +12V.

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to table 6 for

Command definitions.

3. Refer to Table 4 for valid Din during a write operation.

4. Refer to the section on sector protection.

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Autoselect Codes

TYPE A18 A17 A16

Manufacturer Code

BM29F040 Device code

Sector Protection (1) Sector Addresses

A0Code

(Hex) DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0

Vil

Vih

Vil

Vih

ADH

40H

01H

1 0 01

0 1 0 0 0

110 1

000

0000

00 1

Vil

Table 5

PRODUCT FAMILY PRINCIPLES OF OPERATION

Flash memory devices are electrically alterable non-volatile memory products. The BM29F040

augments this feature by not requiring an additional Vpp power supply. The 4 Megabit flash family

uses a Command register and internally generated voltages and timing algorithms to make program

and erase operations simple. The user need not worry about generating tightly controlled high

voltages on board or tying up the microcontroller to generate program and erase algorithms.

The Command register allows for 100% TTL-level control inputs, and maximum compatibility with the

Flash memory functions.

The device provides standard EPROM read, standby and output disable operations. Manufacturer

Identification and Device Identification data can be accessed through the Command register or

through the standard EPROM ″A9″ high voltage access (VID) for PROM programming equipment.

A Command register and Power Switching State Machine are built inside the device. Their purpose is

to completely automate the program and erase operation. The command register receives the

commands given by the user and internally controls the power switching state machine.

Read Mode

The BM29F040 has three control pins and they should all be logically active to obtain valid data at the

outputs. Chip-Enable (CE) is the device selection control. Output Enable (OE ) is the data

input/output control. This pin when high (VIH) brings the output drivers to the tristate and allows data

into the device. Data input is then controlled by

. When the OE pin is low (VIL) it enables the

output buffers and valid array data becomes available at the output pins. The Write Enable (

) pin

has to be high during the READ mode.

Standby Mode

The BM29F040 has two standby modes: a CMOS standby mode (CE input = Vcc +0.5V) when the

current consumed is less than 100 µA; and a TTL standby mode (CE is held at VIH) when the current

consumed is approximately 1 mA. In the standby mode the outputs are in a high impedance state

independent of the OE input.

If the device is deselected during erasure or programming, the device will draw active current until the

erase or programming operation is complete.

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A Winbond Company Publication Release Date: May 1999

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Autoselect Mode

The Autoselect mode allows access to the manufacturers and the device code. This mode can be

enabled by either taking the address pin A9 to VID (11.5 to 12.5 volts) or by giving the Autoselect

Command sequence as shown in Table 5. Once the Autoselect mode is enabled two identifier bytes

can be read on the device outputs by toggling A0 from VIL to VIH. Byte 0 (A0 = VIL) represents the

manufacturers code (ADH for BMI). Byte 1 (A0 = VIH) represents the device identifier and this is 40H

for the BM29F040. A READ command must be written to the Command register to return to the Read

mode after the Autoselect mode.

Write Operations

The on-chip state machines control the Chip Erase, Sector Erase and byte Write operations. This

frees the system processor to do other tasks. All the Programming and Erase voltages are generated

internally. The Write and Erase timings and algorithms are also built into the device. The byte write/

sector erase or Chip Erase Command Interface provides additional data protection to avoid

accidental Write or Erase.

Commands are written to the Command register using standard microprocessor write timings. The

Command register recognizes Read mode, Autoselect mode, Chip Erase, Sector Erase (64K bytes

per sector) and Program commands. The Command register does not occupy an addressable

memory location. The interface register is a latch used to store the command and address and data

information needed to execute the command.

Command Definitions

Device operations are selected by writing specific address and data sequences into the Command

Read/ Reset Command

The read or reset operation is initiated by writing the read/reset command sequence to the command

reads until the command register contents are changed.

The device will automatically power-up in the read/reset mode. In this case, a command sequence is

not needed to read the memory data. This default power up to read mode ensures that no spurious

changes of the data can take place during power-up. As shown in this data sheet, the timing

parameters and A.C. read waveforms should be referenced.

A single cycle reset is also available as shown in table.

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Table 6. Command Definitions

Command

Sequence

Bus

Write

cycles

First Bus

Write

cycle

Second

Bus Write

cycle

Third Bus

Write cycle Fourth Bus

Write cycle Fifth Bus

Write

cycle

Sixth Bus

Write

cycle

required Address Data Address Data Address Data Address Data Address Data

Addres

sData

Read /Reset 1XXXXH F0H

Read /Reset 45555H AAH 2AAAH 55H 5555H F0H RA RD

Auto Select 45555H AAH 2AAAH 55H 5555H 90H 00H ADH

01H 40H

Auto Select

Sector 45555H AAH 2AAAH 55H 5555H 90H SA 00

Protect

Verify X02 01

Byte

Program 45555H AAH 2AAAH 55H 5555H A0H PA PD

Chip Erase 65555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Sector Erase 65555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H

Sector Erase

Suspend 1XXXXH B0H

Sector Erase

Resume 1XXXXH 30H

Notes:

1. Address bit A15, A16, A17 and A18 = X = don′t care for all address commands except for Program

address (PA) and sector address (SA).

2. Bus operations are defined in Table 4.

3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed.

Addresses are latched on the falling edge of WE. SA = Address of the sector to be erased. The combination

of A16, A17 and A18 will uniquely select the sector.

4. RD = Data from the selected address location (RA) during read operation. PD = Data to be programmed at the

selected memory location (PA). Data is latched at the falling edge of /WE.

5. Auto select command can be used to evaluate whether a block is protected or not by using at the fourth address 02H.

This is similar to placing A9 to High Voltage.

Auto Select Command

The BM29F040 contains two different procedures for the autoselect mode. One is the traditional

PROM programmer methodology (by taking Address pin A9 to VID) and the other is by writing the

Auto Select command sequence into the command register. Following the third bus cycle write

command, a read cycle from Address 00H retrieves the BMI manufacturer code ADH, and a read

cycle at 01H retrieves the device code of 40H. Scanning the sector addresses (A16, A17, A18) while

(A6, A1, A0) = (0, 1, 0) will produce a logical at device output DQ0 for a protected sector. See table 5

for more details.

BRIGHT Preliminary BM29F040

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A Winbond Company Publication Release Date: May 1999

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To terminate this operation, it is necessary to write the read/ reset command to the command

Byte Write or Byte program

The BM29F040 is programmed one byte at a time. Programming is a four bus cycle operation. There

are two ″unlock″ write cycles which are followed by a program set-up command and data write cycles.

Addresses are latched on the falling edge of

and data is latched on the rising edge of

. The

rising edge of

begins programming. During the execution of the embedded program algorithm

the host system is not required to provide any other controls or timings. The device also provides

adequate program margin and all the necessary voltages and timings. When completed, the

automatic programming will provide the equivalent of the written data on DQ7. After a successful

programming

operation the device returns back to read mode. Data polling must be performed at the memory

location which is being programmed.

Figure 3 illustrates the Embedded Programming Algorithm and the waverforms are shown in figures 9

and 10.

Chip Erase

Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by

writing the ″setup″ command. Two more ″unlock″ write cycles are then followed by the chip erase

command.

Chip erase does not require the user to program the device prior to erase. BM29F040's technology is

immune to overerase and it does not need any internal programming algorithm before erase. This can

save erase time in many applications.

The automatic Chip erase begins on the rising edge of the last

pulse in the command sequence

and terminates when the data on DQ7 is "1", and which time the device returns back to the read

mode.

Figure 4 illustrates the Auto Erase Algorithm and the Erase Waveforms are shown in Figure 11.

Sector Erase

Sector erase is a six bus cycle operation. There are two "unlock" write cycles followed by writing the

sector erase setup command. Two more "unlock" write cycles are then followed by the sector erase

confirm command. The sector address is latched on the failing edge of

, and the command data

is latched on the rising edge of

. An 80 µS time-out from the rising edge of

of the last sector

erase command is initiated. The actual sector erase starts 100 uS after the last rising edge of

Multiple sectors can be erased simultaneously. After writing the six bus cycle command for sector

erase additional sector address and sector erase command can be inserted within the 80 uS time-out

period. The timer is reset every time and additional sector erase command is inserted. The sectors

can be added to be erased in any random sequence. Any command other than the sector erase

command or Erase Suspend command during the time-out period will reset the device to the read

mode and ignoring the previous command string. During the execution of the Sector Erase command,

only the Erase Suspend and Erase Resume commands are allowed. All other commands will reset

the device to the Read mode. Once the device resets to the Read mode due to command error during

Sector Erase, the data in this sector has lost its integrity. The sector should be properly erased again.

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Sector erase does not require the user to program the sector before erase. When erasing a sector or

multiple sectors the data in the unselected sectors remains unchanged. After the sector erase

operation is completed the data on DQ7 becomes ″1″, and the device returns to the read mode. Data

polling must be performed at an address within any of the sectors being erased.

Figure 4 shows the Embedded Erase Algorithm and Figure 11 shows the Sector Erase Waveforms.

Erase Suspend and Resume

The Erase suspend command allows the user to interrupt the sector erase function and then read

data from the other sectors which were not being erased. This command is not applicable during the

Chip erase operation or during the program mode. The Erase suspend command (B0H) will terminate

the Sector erase operation and it may require form 0.1 µS to 70 µS to suspend the erase operation

and go into the read mode (pseudo read mode). The user must use the toggle bit to determine if the

chip has entered the erase suspended read mode, at which time the toggle bit will stop toggling. An

address of a sector not being erased must be used to read the toggle bit. The user must keep the

information whether the device is in pseudo read mode or read mode. Every time an Erase suspend

command followed by an Erase resume command is written the internal counters are reset. The erase

suspend command is allowed during the 100 uS time out window before the actual sector erase

operation starts. The Erase resume command will start the erase operation immediately and there is

no time out window during erase resume. Note that any other command during the time out will reset

the device to read mode.

To resume the Sector erase operation after pseudo read mode the Resume command (30H) should

be written. The sector erase will start immediately. Another Erase suspend command can be written

after the chip has resumed the erase operation. Note that a data "0" can not be programmed back to

"1." Attempting to do so may give erroneous results or may hang up the device. Only an erase

operation can change the data from a "0" to "1".

The system may also write the Autoselect Command during the Erase Suspend mode. This allows the

host system to correctly read the autoselect codes during Erase Suspend since this data is not stored

in the memory array.

Sector Protection

The BM29F040 has a hardware sector protection. This feature will disable both Program and Erase

operation of the protected sector or group of sectors. The device is shipped with all sectors

unprotected.

To verify if a sector is protected, the programming equipment must force VID on the address pin A9,

and A6 = CE = OE = VIL and

= VIH. Reading the device at a particular sector address (A16,

A17 and A18) and XXX2H will produce 01H at the data outputs for a protected sector. See Figure 14

for the AC Waveforms and Figure 16 for the algorithm.

Please use the appropriate approved Programmer or contact Bright for the BM29F040 Programmers

Guide for the specification for protecting individual sectors.

Sector Unprotection

The BM29F040 also features a sector unprotect mode, so that a protected sector may be

unprotected. All sectors are unprotected at the same time. Please use the appropriate approved

Programmer or contact Bright for the BM29F040 Programmers Guide for the specification to

unprotect the sectors.

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It is also possible to determine if a sector is unprotected in the system by writing the autoselect

command and A6 is set to VIH. Performing a read operation at XXX2H and the sector address

(defined by A16, A17 and A18) will produce 00H at the Data outputs for an unprotected sector.

Table 7 Sector Address Table

Sector A18 A17 A16 Address Range

SA0 0 0 0 00000H - 0FFFFH

SA1 0 0 1 10000H - 1FFFFH

SA2 0 1 0 20000H - 2FFFFH

SA3 0 1 1 30000H - 3FFFFH

SA4 1 0 0 40000H - 4FFFFH

SA5 1 0 1 50000H - 5FFFFH

SA6 1 1 0 60000H - 6FFFFH

SA7 1 1 1 70000H - 7FFFFH

Data Flags

DQ7 Data polling

The BM29F040 features Data polling to indicate to the host system that the Embedded Algorithms are

in progress or completed. During the Embedded Program Algorithm, an attempt to read the device

will produce the complement of the Data last written to DQ7. Upon completion of the Embedded

Programming Algorithm an attempt to read the device will produce the true data last written to DQ7.

Data polling is valid after the rising edge of the fourth

pulse in the four write pulse sequence.

During the Embedded Erase Algorithm, DQ7 will be "0" until the Erase operation is completed. Upon

completion of Erase the data at DQ7 is "1". For sector erase, the Data polling is valid after the last

rising edge of the sector erase

pulse. For Chip erase, the Data polling is valid after the last rising

edge of the sixth Chip erase

pulse. Data polling must be performed at a sector address within

any of the sectors being erased and not a protected sector. Once the Embedded operation is close to

being completed, the BM29F040 data pins (DQ7) may change asynchronously while the OE pin is

asserted low. This means that the device is driving status information on DQ7 at one time and bytes

of valid data at other times. Depending on when the system samples the DQ7 output it may read the

status or it may read the valid data.

See Figure 12 for the Data polling timing diagram.

DQ6 Toggle Bit

The BM29F040 also features the "Toggle Bit" as a method to indicate to the host system that the

Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read data from the

device will result in DQ6 toggling between "1" and "0". Once the Embedded Program or Erase

algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on successive

attempts. During programming the toggle bit is valid after the rising edge of the fourth

pulse in

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the four write pulse sequence. During Chip and Sector Erase, the toggle bit is valid after the rising

edge of the sixth

pulse in the six write pulse sequence.

In programming, if the sector being written to is protected, the toggle bit may toggle for about 2 µS

and then will stop toggling without the data being changed. During erase the device will erase all the

sectors except the sector being protected. If all the sectors are protected the chip will toggle the

toggle bit for about 2 µS and then drop back to read mode without changing the data.

Either CE or OE toggling will cause the DQ6 to toggle. The toggle bit is valid in the time out period

during sector erase.

See Figure 13 for the Toggle bit timing diagrams.

DQ5 Exceeded The Timing Limits

DQ5 indicates if the program or erase time has exceeded the specified timing limits. Under these

conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data polling is the only operating function of the device under

this condition. The CE circuit will partially power down the device under these conditions. The OE

and

pins will control the output disable function as shown in Table 4.

If this failure condition occurs during the sector erase operation, it indicates that the particular sector

is bad and may not be reused. The other sectors are still functioning properly and can be used. The

device must be reset to use the other good sectors. To reset the device, write the Reset command

sequence to the device. This will allow the system to use the other active sectors in the device.

If this failure condition occurs during chip erase, it indicates that the entire chip is bad or many sectors

are bad.

If this condition occurs during byte write it indicates that the sector containing this byte is bad.

This failure condition can also occur if the user tries to program a non-blank location without erasing.

In this case the device locks out and never completes the operation. Please note that this is not a

device failure.

DQ3 Sector Erase Timer

After the completion of the Sector erase command sequence the sector erase time-out begins. DQ3

will remain low until the time-out is complete. Data polling and the Toggle bit are valid after the initial

sector erase command sequence.

If Data polling or the Toggle bit indicates the device has been written with a valid erase command,

DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is "1" the

internally controlled erase cycle has begun. If DQ3 is ″0″ the device will accept additional sector

erase commands. To ensure that the command has been accepted, the user should check the status

of DQ3 prior to and following each sector erase command. If DQ3 is "1" on the second status check,

the command may not be accepted.

Once the internal erase cycle begins the device will not accept any other command until the internal

erase cycle is completed.

The BM29F040 is designed to offer protection against accidental programming or erasure. During

power-up the device automatically resets to the read mode. The multi-bus command sequences also

provide data protection for accidental write. The device also provides additional features to prevent

inadvertent write operations during power-up and power-down transitions or system noise.

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DQ2 Toggle Bit II

The BM29F040 also features the "Toggle Bit II" as a method to indicate to the host system whether a

specific sector is actively erasing or whether the sector is erase-suspended. The Toggle Bit II is valid

after the rising edge of the final

pulse in the command sequence.

DQ2 toggles when the host system reads addresses within a sector that have been selected for erase.

The system may use OE or

to control the read cycles. But, DQ2 can not distinguish between a

sector erasing or erase-suspended. However, Toggle Bit DQ6 can be used to determine if a sector is

actively erasing or erase-suspended. As a result, both Toggle Bits are required for the host system to

determine the current mode information. Refer to Table 7 for a further comparison of DQ6 and DQ2.

Whenever the host system begins to read the erase status using the toggle bits, they must be read at

least twice in a row. Typically, the system would store the first value and compare it to the second. If

the bits are still toggling, the system should also check DQ5(see the DQ5 description).

If DQ5 is high, the system should re-check the toggle bits since toggling may have just finished. If the

toggle bits have stopped toggling, the device has successfully completed the erase. If the toggle bits

are still toggling, the device has not successfully completed the erase operation and the host should

issue a Reset Command to the device before continuing.

If DQ5 is low, the host system should continue to monitor the toggle bits and DQ5 or issue an erase

suspend command if performing a single or multiple sector erase command.

Write Operation Status

Status DQ7 DQ6 DQ5 DQ3 DQ2

Standard Auto-Programming ____

DQ7 Toggle 0N/A No Toggle

Auto-Erase 0Toggle 0 1 Toggle

Erase

Suspend Reading an Erase

Suspended Sector 1No Toggle 0N/A Toggle

Reading a Non-Erase

Suspended Sector Data Data Data Data Data

Auto-Programming

Erase Suspend ____

DQ7 Toggle 0N/A N/A

Exceeded Auto-Programming ____

DQ7 Toggle 1 1 Reserved for

Time Limits Auto-Erasing 0Toggle 1 1 Future use

Table 8. Hardware Sequence Flags

Low Vcc Write Inhibit

During Vcc power-up or power-down, a write cycle is inhibited for Vcc values of less than 3.2 Volts

(3.8 Volts typical). If Vcc < Vlko (Vlko = lock out Voltage) the command register is disabled and all

internal program/erase circuits are disabled. Under this condition the device will reset to the read

mode. If a write command is given during Vcc < Vlko, the writes will be ignored. It is the users

responsibility to ensure that the control pins are logically correct to prevent unintentional writes when

Vcc > Vlko.

Write Pulse Glitch Protection

BRIGHT Preliminary BM29F040

Microelectronics

Inc.

- 14 -

Noise pulses of less than 5 nS on OE,

or CE will not initiate a write cycle.

Power-up Wtire Inhibit

Power-up of the device with

= CE = VIL and OE = VIH will not accept commands at the rising

edge of

. The internal state machine is automatically reset to the read mode on power-up.

Logical Inhibit

Writing is inhibited by holding any one of the control pins to OE = VIL,

= VIH or CE = VIH. To

initiate a write cycle, CE and

must be logical "0" and OE must be logical "1".

Sector Protect

Sectors of the BM29F040 may be hardware protected by the user. The protection circuitry will disable

both program and erase functions for the protected sectors. The program and erase commands will

be ignored if given to the protected sectors. The Chip erase command will also not erase the

protected sectors.

Parallel Device Erasure

The BM29F040 is a fully self timed device. This makes it feasible to Erase or Program many devices

in parallel.

Program Command Sequence

(Address/Data)

5555H/ AAH

2AAAH/ 55H

5555H/ A0H

Program Add./Program

Data

Fourth Write cycle

Third Write cycle

Second Write cycle

First Write cycle

Figure: 3A

Embedded Programming Flow Chart

Start

Write Program Command Sequence

(see Fig. 3a)

Data poll Device

Verify Byte

Byte Write

Completed

Yes

Figure: 3B

Note: See Data Polling Algorithm in Figure 10 and 11.

BRIGHT Preliminary BM29F040

Microelectronics

Inc.

A Winbond Company Publication Release Date: May 1999

- 15 - Revision A1

Embedded Erase Algorithm

Start

Write Program Command Sequence

(see below)

Data poll Device

Data = FFH

Erasure

Completed

Yes

Figure 3. Embedded Programming Algorithm

Note: See Data Polling Algorithm in Figure 5

Chip Erase Command Sequence

(Address/Data)

5555H/ AAH

2AAAH/ 55H

5555H/ 80H

Fourth Write cycle

Third Write cycle

Second Write cycle

First Write cycle

2AAAH/ 55H

5555H/ AAH

5555H/ 10H

Fifth Write cycle

Sixth Write cycle

Individual Sector/Multiple Sector Erase

Command Sequence (Address/Data)

5555H/ AAH

2AAAH/ 55H

5555H/ 80H

Fourth Write cycle

Third Write cycle

Second Write cycle

First Write cycle

2AAAH/ 55H

5555H/ AAH

Sector Address/ 30H

Fifth Write cycle

Sixth Write cycle

Sector Address/ 30H

Additional

Sector erase

commands are

optional

Figure 4. Automated Erase Flow Chart and Sequence

BRIGHT Preliminary BM29F040

Microelectronics

Inc.

- 16 -

Data Polling Algorithm

Start

Yes

DQ7= Data

DQ5=1

DQ7= Data

Yes

Fail

Pass

Yes

Note 1

Note: DQ7 is rechecked even if DQ5 = "1" because DQ7 may

change simultaneously with DQ5.

Toggle Bit Algorithm

Start

Yes

DQ6= Toggle

DQ5=1

DQ6= Toggle

Yes

Fail

Pass

Yes

Note 2

Note: DQ6 is rechecked even if DQ5 = "1" because DQ6 may

stop toggling at the same time as DQ5 is changed to "1".

Figure 5. Data Polling and Toggle Bit Algorithm

Absolute Maximum Ratings:

Storage Temperature -65°C to +125°C

Operating Temperature (Note 1)

During Read -55°C to +125°C

During Program/Erase -55°C to +125°C

Temperature under Bias

(With Power Applied) -55°C to +125°C

Voltages with Respect to GND.

All pins except A9 (Note 2, 3) -2V to +7V

Vcc (Note 2) -2V to +7V

A9 (Note 3) -2V to +14V

Output short circuit current (Note 4) 200mA

Operating Ranges:

Commercial (C) Devices

Temperature Range 0°C to +70°C

Vcc supply voltage during 4.5V to 5.5V or

all operations 4.75V to 5.25V

Industrial (I) Devices

Temperature Range -40°C to +85°C

Vcc supply voltage during 4.5V to 5.5V

all operations

Notes :

1. The datasheet defines the operation at specific temperature ranges.

2. Minimum DC voltage on input / output pins is -0.5V. During voltage transitions, inputs can undershoot to -2 Volts for periods

of up to 20 nS. The maximum DC voltage on these pins is Vcc +0.5V. During transitions, inputs may overshoot to Vcc +2.0V

for periods < 20 nS.

3. Maximum DC voltage on A9 may overshoot to 14.0V for periods < 20 nS.

4. Outputs may be shorted for no more than one second. Only one/output can be shorted at a time.

*Notice: Stresses above those listed under "Absolute Maximum Ratingsz" may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect

device reliability.

BRIGHT Preliminary BM29F040

Microelectronics

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A Winbond Company Publication Release Date: May 1999

- 17 - Revision A1

Maximum Overshoot

Maximum Negative Overshoot

-2.0 V

-0.5 V

+0.8 V

20 nS 20 nS

20 nS

Maximum Negative Overshoot Waveform

Vcc + 2.0 V

Vcc + 0.5 V

2.0 V

Maximum positive Overshoot Waveform

20 nS

Figure 6. Maximum Overshoot Waveforms

DC Characteristics

Symbo

lParameter Min Max Unit Test Conditions

Vil Input Low Level -0.5 0.8 V

Vih Input High Level 2.0 Vcc + 0.5 V

Vol Output Low Voltage 0.45 Vlol = 12mA Vcc = Vcc Min.

Voh Output High Voltage 2.4 Vloh = -2.5mA Vcc = Vcc Min.

Voh 2 Output High Voltage Vcc - 0.4 Vlohl = -100uA Vcc = Vcc Min.

lli Input Load Current +/- 1.0 uA Vin = Vcc or GND Vcc = Vcc Max.

llo Output Leakage Current +/- 10 uA Vout = Vcc or GND Vcc = Vcc

Max.

los Output Short Circuit Current 100 mA Vout = 0.5V Vcc = Vcc Max.

lsb1Vcc Standby Current (CMOS) 4 100 uA CE = Vcc +/- 0.5V Vcc = Vcc Max.

lsb2Vcc Standby Current (TTL) 4 1.0 mA CE = Vih Vcc = Vcc Max.

lcc1Vcc Active Current Read 1,3 40 mA CE = Vil, f = 6MHz, OE = Vih

lcc2Vcc Active Current Program or 2 60 mA CE = Vil, OE = Vih

Vid A9 Intelligent Identifier Volatge 11.5 12.5 V

lid A9 Intelligent Identifier Current 50 uA A9 = Vid

Table 9

Notes:

1. All Currents are in RMS unless otherwise noted. Typical values are Vcc = +5.0V, T = 25° C.

2. These parameters are sampled but not 100% tested.

3. Automatic power saving reduces the Iccr to 1 mA.

4. CMOS inputs are Vcc +0.5V. TTL inputs are either VIL or VIH.

BRIGHT Preliminary BM29F040

Microelectronics

Inc.

- 18 -

Capacitance:

TA = 25° C, f = 1 MHZ (2)

Symbol Parameter Conditiontion Typical Max Unit

Cin Input Capacitance Vin = 0V 6 8 pF

Cout Output Capacitance Vout = 0V 10 12 pF

AC Testing Input/Output Waveform

AC test inputs are driven at Voh ( 2.4V VTTL) for a

logic "1" and Vol ( 0.4V VTTL) for a logic "0". Input

timing measurement begins at Vih ( 2.0V VTTL) for an

input "1" and Vil ( 0.8V VTTL) fir an input "0".

Output timing measurement ends ar 2.0V for an output

"1" and 0.8V for an output "0". Input Rise and fall times

(10% to 90%) < 10ns.

2.4

0.45

Input 2.0

0.8

Test

Points 2.0

0.8 Output

AC Testing Load Circuit

Device Under

Test

CLRL

6.2K

2.7K

C = 100 pF

C includes Jig Capacitance

The diodes are 1N3064 or

wequivalent.

Figure 7. A.C.Testing Load and Waveforms

BRIGHT Preliminary BM29F040

Microelectronics

Inc.

A Winbond Company Publication Release Date: May 1999

- 19 - Revision A1

AC Characteristics - Read Only Operations (1)

SYMBOL (4) DESCRIPTION -75 -90 -120 -150 UNITS

JEDEC Standard

tAVAV tRC Read Cycle Time 70 90 120 150 nS

tAVQV tACC Address to Output Delay 70 90 120 150 nS

tELQV tCE CE low to Output Delay (2) 70 90 120 150 nS

tGLQV tOE OE low to Output Delay 30 35 50 55 nS

tELQX tLZ CE low to Output LOW Z (3) 0 0 0 0 nS

tEHQZ tHZ CE high to Output HIGH Z 20 20 30 35 nS

tGLQX tOLZ OE low to Output LOW Z 0 0 0 0 nS

tGHQZ tDF OE high to Output HIGH Z (3) 20 20 30 35 nS

tAXQX tOH Output Hold from Address,

CE or OE , whichever is

first

(1) 0 0 0 0 nS

Table 11

Notes:

1. See A.C. Input/Output Reference Waveforms for timing measurements.

2. OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE.

3. Sampled, not 100% tested.

4. See A.C. Input/Output Reference Waveforms and A.C. Testing Load Circuits for testing characteristics.

DATA (D/Q)

GHQZ

tGLQV

Valid Output

tAXQX

High Z

tAVQV

High Z

Vih

Vil

OE (G)

CE (E)

Address Valid

Vih

Vil

Addresses

Vih

Vil

Vih

tELQV

Vil

Vih

WE (W)

tELQX

tGLQX

5.0 V

VCC

GND

EHQZ

tAVAV

Vcc Power-

up Standby Device &

Address Select. Outputs

Enabled Data Valid Standby Vcc Power-

down

Figure 8. A.C.Waveforms for Read Operations

BRIGHT Preliminary BM29F040

Microelectronics

Inc.

- 20 -

AC CHARACTERISTICS - for

Controlled Write Operation

SYMBOL DESCRIPTION -75 -90 -120 -150 UNITS

JEDEC Standard

tAVAV tWC Write Cycle Time

(4) 70 90 120 150 nS

tELWL tCS CE Setup 0 0 0 0 nS

tAVWL tAS Address Setup Time 0 0 0 0 nS

tDVWH tDS Data Setup Time 30 45 50 55 nS

tWLWH tDH Data Hold Time 0 0 0 0 nS

tWHEH tCH CE Hold Time 0 0 0 0 nS

tWLAX tAH Address Hold Time 45 45 50 50 nS

tWLWH tWP Write Pulase Width 35 45 50 50 nS

tWHWL tWPH WE Pulse Width High 20 20 20 25 nS

tOES Output Enable Setup Time 0 0 0 0 nS

tOEH Output Enable Read (4) 0 0 0 0 nS

Hold Time Toggle and Data

Polling 10 10 10 10 nS

tGHWL tGHWL Read Recover Time Before

Write 0 0 0 0 nS

tWHWH1 tWHWH1 Programming Operation 16 16 16 16 uS

tWHWH2 tWHWH2 Erase Operation (min.) (1) typ 1.5 1.5 1.5 1.5 sec

max 30 30 30 30 sec

tVCS Vcc Setup Time (4) 50 50 50 50 uS

tVLHT Voltage Transition Time (2,4) 4 4 4 4 uS

tWPP1 Write Pulse Width (2) 100 100 100 100 uS

tWPP2 Write Pulse Width (2) 10 10 10 10 mS

tCESP CE Setup Time to

WE Active (3,4) 4 4 4 4 uS

tOESP 4 4 4 4 uS

Table 12

Notes:

1. The Erase operation does not need programming time.

2. These timings are for Sector Protect/Unprotect operation.

3. This timing is only for sector Unprotect.

4. Not 100% tested.

BRIGHT Preliminary BM29F040

Microelectronics

Inc.

A Winbond Company Publication Release Date: May 1999

- 21 - Revision A1

Switching Waveforms

GND

Addresses (A)

DATA (D/Q)

VCC

OE (G)

5.0 V

WE (W)

Vih

Vil

Vih

CE (E) Vih

Vil

Vih

Vil

tWCtAS t

tWPH tWHWH1

tWP

tDS

HIGH Z

5555H PA PA

A0H PD DQ7 DOUT

tGHWL

DHt

tCS

Data Polling

tRC

tCE

tOE

tDF

tOH

Figure 9. A.C.Waveforms for Program Operations (

Controlled Writes)

Notes:

1. PA is the address of the memory location to be programmed.

2. PD is the data to be programmed at the byte address.

3. DQ7 is the output of the complement of the data written tot he device.

4. DOUT is the output of the data written to the device.

5. Figure indicates the last two bus cycles of four bus cycle sequence.

BRIGHT Preliminary BM29F040

Microelectronics

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- 22 -

AC CHARACTERISTICS - for CE Controlled Write Operation

SYMBOL DESCRIPTION -75 -90 -120 -150 UNITS

JEDEC Standard

tAVAV tWC Write Cycle Time (Note 4) 70 90 120 150 nS

tWLEL tWS

Setup time 0 0 0 0 nS

tAVEL tAS Address Setup time 0 0 0 0 nS

tDVEH tDS Data Setup time 30 45 50 50 nS

tEHDX tDH Data Hold time 0 0 0 0 nS

tEHWH tWH

Hold time 0 0 0 0 nS

tWLAX tAH Address Hold time 45 45 50 50 nS

tELEH tCP CE Pulse Width 35 45 50 50 nS

tEHEL tCPH CE Pulse Width High 20 20 20 25 nS

tOES Output Enable Setup time 0 0 0 0 nS

tOEH Output Enable Read (Note 4) 0 0 0 0 nS

Hold time Toggle and Data

Polling 10 10 10 10 nS

tGHEL tGHEL Read Recover time before Write 0 0 0 0 nS

tWHWH1 tWHWH1 Programming Operation 16 16 16 16 uS

tWHWH2 tWHWH2 Erase Operation (1) typ 1.5 1.5 1.5 1.5 sec

max 30 30 30 30 sec

tVCS Vcc Setup time (Note 4) 50 50 50 50 µS

Table 13

Notes:

1. The Erase operation does not need programming time.

2. These timings are for Sector Protect/Unprotect operation.

3. This timing is only for sector Unprotect.

3. Not 100% tested.

BRIGHT Preliminary BM29F040

Microelectronics

Inc.

A Winbond Company Publication Release Date: May 1999

- 23 - Revision A1

Switching Waveforms

Addresses (A)

VCC

DATA (D/Q)

OE (G)

5.0 V

GND

WE (W)

Vih

Vil

Vih

CE (E)

Vih

Vil

Vih

Vil

tWC tAS t

tCPH tWHWH1

tCP

tDS

HIGH Z

5555H PA PA

A0H PD DQ7 DOUT

tGHEL

tWS

Data Polling

tRC

tCE

tOE

tDF

tOH

Figure 10.A.C.Waveforms for Program Operations ( CE Controlled Writes)

Notes:

1. PA is the address of the memory location to be programmed.

2. PD is the data to be programmed at the byte address.

3. DQ7 is the output of the complement of the data written to the device.

4. DOUT is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

Switching Waveforms

Addresses (A)

VCC

DATA (D/Q)

OE (G)

5.0 V

GND

WE (W)

Vih

Vil

Vih

CE (E)

Vih

Vil

Vih

Vil

tAS

tWPH

tWP

tDS

HIGH Z

5555H

AAH

tAH

tGHWL

tCS

5555H 5555H2AAAH 2AAAH SA

55H 80H AAH 55H

30H for sector erase

10H for chip erase

tVCS

Figure 11. A.C. Waveforms for Chip/Sector Erase Operations

Note: SA is the sector address for Sector erase or 5555H for Chip Erase.

BRIGHT Preliminary BM29F040

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- 24 -

Switching Waveforms

tOE

High Z

Vih

Vil

OE (G)

CE (E) Vih

Vil

Vih

Vil

Vih

tWHWH1 or 2

DATA (D/Q)

tCE

Data Out

Data OutData In

tDF

tOH

WE (W)

tCH

tOEH

Figure 12. AC Waveforms for Data Polling during Embedded Algorithm operations

Vih

Vil

OE (G)

CE (E) Vih

Vil

Vih

Vil

Vih

WE (W)

DQ6 Data In

OEH

tOH

Figure 13. AC Waveforms for Toggle Bit during Embedded Algorithm operations Operating

BRIGHT Preliminary BM29F040

Microelectronics

Inc.

A Winbond Company Publication Release Date: May 1999

- 25 - Revision A1

ORDERING INFORMATION

PART NO. ACCESS

TIME

(nS)

POWER

SUPPLY CURRENT

MAX. (mA)

PACKAGE CYCLING

(Min)

TEMPERATURE

RANGE

29F040-90NC

29F040-12NC

29F040-90AC

29F040-12AC

29F040-90TC

29F040-12TC

29F040-90NI

29F040-12NI

29F040-90AI

29F040-12AI

29F040-90TI

29F040-12TI

120

32 PDIP

32 PLCC

32 TSOP

32 PDIP

32 PLCC

32 TSOP

10,000

0°C - 70°C

-40°C - 85°C

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

3. Typical cycling is 100,000 program and erase cycles.

BRIGHT Preliminary BM29F040

Microelectronics

Inc.

- 26 -

APPENDIX A:

Compatibility to AMD's AMD29F040B

The device is fully functional compatible to the AMD29F040B except during the command addresses

subset mode. In the AMD device, Commands do not require a unique address pattern for bits A15,

A14, A13, A12 or A11 (eg.X555H or X2AAH instead of 5555H and 2AAAH). That is, the BM29F040

requires specifically A14,A13,A12 and A11 to be forced during the command sequence in addition to

A10 through A0. Note specifically that the BM29F040 does not require address A15 along with A18,

A17 and A16 to be forced during the command sequence.

AMD's reduced address requirement makes their device slightly easier to inadvertently create a

Command and cause some program error or malfunction. The advantage of reducing the address is

to simplify the hardware interface in systems where control signals are limited in number. The

29F040B reduces the interface requirement by 4 signals -- from 15 to 11 address control pins.

However if the full Command address is supplied (i.e. 2AAAH and 5555H) by the host system, there

will be no incompatibility using either device.

BRIGHT Preliminary BM29F040

Microelectronics

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A Winbond Company Publication Release Date: May 1999

- 27 - Revision A1

PACKAGE DIMENSIONS

32-pin P-DIP

1.Dimensions D Max. & S include mold flash or

tie bar burrs.

2.Dimension E1 does not include interlead flash.

3.Dimensions D & E1 include mold mismatch and

are determined at the mold parting line.

6.General appearance spec. should be based on

final visual inspection spec.

1.371.22

0.0540.048

Notes:

Symbol Min. Nom. Max. Max.Nom.Min.

Dimension in inches Dimension in mm

0.050 1.27

0.210 5.33

0.010

0.150

0.016

0.155

0.018

0.160

0.022

3.81

0.41

0.25

3.94

0.46

4.06

0.56

0.008

0.120

0.670

0.010

0.130

0.014

0.140

0.20

3.05

0.25

3.30

0.36

3.56

0.555

0.5500.545 14.1013.9713.84

17.02

15.24

14.99 15.49

0.6000.590 0.610

2.29 2.54 2.790.090 0.100 0.110

1.650 1.660 41.91 42.16

0 15

0.085 2.16

0.6500.630 16.00 16.51

protrusion/intrusion.

4.Dimension B1 does not include dambar

5.Controlling dimension: Inches

150

Seating Plane

Base Plane

116

32-pin PLCC

Notes:

DHD

Seating Plane

14 20

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches

4. General appearance spec. should be based on final

visual inspection sepc.

Symbol Min. Nom. Max. Max.Nom.Min.

Dimension in Inches Dimension in mm

3.56

0.50

2.802.67 2.93

0.71

0.66 0.81

0.41 0.46 0.56

0.20 0.25 0.35

13.89 13.97 14.05

11.35 11.43 11.51

1.27

12.45 12.9

13.46

9.91 10.41 10.92

14.86 14.99 15.11

12.32 12.45 12.57

1.91 2.29

0.004

0.095

0.090

0.075

0.495

0.49

0.485

0.595

0.590

0.585

0.430

0.410

0.390

0.530

0.51

0.490

0.050

0.453

0.450

0.447

0.553

0.550

0.547

0.014

0.010

0.008

0.022

0.018

0.016

0.0320.026 0.028

0.1150.105 0.110

0.020

0.140

1.12 1.420.044 0.056

0°10°10°

0°

0.10

2.41

BRIGHT Preliminary BM29F040

Microelectronics

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- 28 -

Package Dimensions, continued

32-pin TSOP

L1Y

0.10(0.004)

Min. Nom. Max. Min. Nom. Max.

Symbol

Note:

Controlling dimension: Millimeters

Dimension in Inches

0.047

0.006

0.041

0.039

0.037

0.007 0.008 0.009

0.005 0.006 0.007

0.720 0.724 0.728

0.311 0.315 0.319

0.780 0.787 0.795

0.020

0.016 0.020 0.024

0.031

0.000 0.004

1 3 5

0.002

1.20

0.05 0.15

1.051.00

0.95

0.17

0.12

18.30

7.90

19.80

0.40

0.00

0.20 0.23

0.15 0.17

18.40 18.50

8.00 8.10

20.00 20.20

0.50

0.50 0.60

0.80

0.10

3 5

Dimension in mm

__ __ __ __

__ __

BRIGHT Preliminary BM29F040

Microelectronics

Inc.

A Winbond Company Publication Release Date: May 1999

- 29 - Revision A1

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 May. 1999 -Initial Issued

Headquarters

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5796096

http://www.winbond.com.tw/

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,

123 Hoi Bun Rd., Kwun Tong,

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

Winbond Electronics Corporation America

2727 N. First Street, San Jose,

CA 95134, U.S.A.

TEL: 408-9436666

FAX: 408-5441798

Note: All data and specifications are subject to change without notice.