General Description
The MAX1510/MAX17510 DDR linear regulators source
and sink up to 3A peak (typ) using internal n-channel
MOSFETs. These linear regulators deliver an accurate
0.5V to 1.5V output from a low-voltage power input (VIN
= 1.1V to 3.6V). The MAX1510/MAX17510 use a sepa-
rate 3.3V bias supply to power the control circuitry and
drive the internal n-channel MOSFETs.
The MAX1510/MAX17510 provide current and thermal
limits to prevent damage to the linear regulator.
Additionally, the MAX1510/MAX17510 generate a
power-good (PGOOD) signal to indicate that the output
is in regulation. During startup, PGOOD remains low
until the output is in regulation for 2ms (typ). The internal
soft-start limits the input surge current.
The MAX1510/MAX17510 power the active-DDR termi-
nation bus that requires a tracking input reference. The
MAX1510/MAX17510 can also be used in low-power
chipsets and graphics processor cores that require
dynamically adjustable output voltages. The
MAX1510/MAX17510 are available in a 10-pin, 3mm x
3mm thin DFN package.
Applications
Notebook/Desktop Computers
DDR Memory Termination
Active Termination Buses
Graphics Processor Core Supplies
Chipset/RAM Supplies as Low as 0.5V
Features
oInternal Power MOSFETs with Current Limit (3A typ)
oFast Load-Transient Response
oExternal Reference Input with Reference
Output Buffer
o1.1V to 3.6V Power Input
o±15mV (max) Load-Regulation Error
oThermal-Fault Protection
oShutdown Input
oPower-Good Window Comparator with 2ms
(typ) Delay
oSmall, Low-Profile 10-Pin, 3mm x 3mm TDFN
Package
oCeramic or Polymer Output Capacitors
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
OUT
IN
OUTS
AGND
PGND
VOUT = VTT
VIN
(1.1V TO 3.6V)
VBIAS
(2.7V TO 3.6V)
VDDQ
(2.5V OR 1.8V) VREFOUT = VTTR
REFOUT
MAX1510
MAX17510
VCC
PGOOD
SHDN
REFIN
Typical Operating Circuit
19-3279; Rev 5; 3/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-
PACKAGE
TOP
MARK
MAX1510ETB -40°C to +85°C 10 TDFN-EP* ARD
MAX1510ETB+ -40°C to +85°C 10 TDFN-EP* ABD
MAX1510ATB/V+ -40°C to +85°C 10 TDFN-EP* AWD
MAX17510ATB+ - 40° C to + 125° C 10 TDFN-EP* AWQ
MAX17510ATB/V+ - 40° C to + 125° C 10 TDFN-EP* AWQ
SHDN
OUTSPGOOD
OUT
PGND
AGND
REFIN
VCC
TDFN
3mm x 3mm
TOP VIEW
51234
INREFOUT
MAX1510
MAX17510
A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.
+
610987
Pin Configuration
+
Denotes a lead(Pb)-free and RoHS-compliant package.
*
EP = Exposed pad.
/V denotes an automotive qualified part.
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TJ= TA= -40°C to +85°C for MAX1510ETB, TJ=
TA= -40°C to +125°C for MAX17510ATB, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN to PGND............................................................-0.3V to +4.3V
OUT to PGND ..............................................-0.3V to (VIN + 0.3V)
OUTS to AGND............................................-0.3V to (VIN + 0.3V)
VCC to AGND.........................................................-0.3V to +4.3V
REFIN, REFOUT, SHDN, PGOOD to AGND ..-0.3V to (VCC + 0.3V)
PGND to AGND .....................................................-0.3V to +0.3V
REFOUT Short Circuit to AGND .................................Continuous
OUT Continuous RMS Current: 100s ..................................±1.6A
1s......................................±2.5A
Continuous Power Dissipation (TA= +70°C)
10-Pin 3mm x 3mm Thin DFN
(derated 24.4mW/°C above +70°C)...........................1951mW
Operating Temperature Range
MAX1510ETB...................................................-40°C to +85°C
MAX17510ATB ..............................................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)
Lead(Pb)-free packages..............................................+260°C
Packages containing lead(Pb).....................................+240°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VIN Power input 1.1 3.6
Input-Voltage Range VCC Bias supply 2.7 3.6 V
Quiescent Supply Current (VCC)I
CC Load = 0, VREFIN > 0.45V 0.7 1.3 mA
SHDN = GND, VREFIN > 0.45V 350 600
Shutdown Supply Current (VCC)I
CC
(
SHDN
)
SHDN = GND, REFIN = GND 50 100 µA
Quiescent Supply Current (VIN)I
IN Load = 0 0.4 10 mA
Shutdown Supply Current (VIN)I
IN
(
SHDN
)
SHDN = GND 0.1 10 µA
TA = +25°C -4 0 +4
Feedback-Voltage Error VOUTS REFIN to OUTS
IOUT = ±200mA TA = -40°C to +125°C -6 +6 mV
Load-Regulation Error -1A ≤ IOUT ≤ +1A -15 +15 mV
Line-Regulation Error 1.4V ≤ VIN ≤ 3.3V, IOUT = ±100mA 1 mV
OUTS Input-Bias Current IOUTS -1 +1 µA
OUTPUT
Output Adjust Range 0.5 1.5 V
High-side MOSFET (source) (IOUT = 0.1A) 0.14 0.25
OUT On-Resistance Low-side MOSFET (sink) (IOUT = -0.1A) 0.14 0.25
Ω
Output Current Slew Rate COUT = 100µF, IOUT = 0.1A to 2A 3 A/µs
OUT Power-Supply Rejection
Ratio PSRR 10Hz < f < 10kHz, IOUT = 200mA,
COUT = 100µF 80 dB
OUT-to-OUTS Resistance ROUTS 12 kΩ
Discharge MOSFET
On-Resistance RDISCHARGE SHDN = GND 8 Ω
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
_______________________________________________________________________________________ 3
Note 1: Limits are 100% production tested at TA= +25°C. Limits over the operating temperature range are guaranteed through cor-
relation using statistical-quality-control (SQC) methods.
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TJ= TA= -40°C to +85°C for MAX1510ETB, TJ=
TA= -40°C to +125°C for MAX17510ATB, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFERENCE
REFIN Voltage Range VREFIN 0.5 1.5 V
REFIN Input-Bias Current IREFIN TA = +25°C -1 +1 µA
REFIN Undervoltage-Lockout
Voltage Rising edge, hysteresis = 50mV 0.35 0.45 V
REFOUT Voltage VREFOUT VCC = 3.3V, IREFOUT = 0V VREFIN
- 0.01 VREFIN VREFIN
+ 0.01 V
REFOUT Load Regulation ΔVREFOUT IREFOUT = ±5mA -20 +20 mV
FAULT DETECTION
Thermal-Shutdown Threshold TSHDN Rising edge, hysteresis = 15°C +165 °C
VCC Undervoltage-Lockout
Threshold VUVLO Rising edge, hysteresis = 100mV 2.45 2.55 2.65 V
IN Undervoltage-Lockout
Threshold Rising edge, hysteresis = 55mV 0.9 1.1 V
TA = -40°C to +85°C 1.8 3 4.2
Current-Limit Threshold ILIMIT TA = -40°C to +125°C 1.5 3 4.2 A
Soft-Start Current-Limit Time tSS 200 µs
INPUTS AND OUTPUTS
PGOOD Lower Trip Threshold With respect to feedback threshold,
hysteresis = 12mV -200 -150 -100 mV
PGOOD Upper Trip Threshold With respect to feedback threshold,
hysteresis = 12mV 100 150 200 mV
PGOOD Propagation Delay tPGOOD OUTS forced 25mV beyond PGOOD trip
threshold 51035µs
PGOOD Startup Delay Startup rising edge, OUTS within ±100mV of
the feedback threshold 1 2 3.5 ms
PGOOD Output Low Voltage ISINK = 4mA 0.3 V
PGOOD Leakage Current IPGOOD OUTS = REFIN (PGOOD high impedance),
PGOOD = VCC + 0.3V, TA = +25°C 1µA
Logic-high 2.0 V
SHDN Logic Input Threshold Logic-low 0.8 V
SHDN Logic Input Current SHDN = VCC or GND, TA = +25°C -1 +1 µA
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
4 _______________________________________________________________________________________
0.84
0.94
0.92
0.90
0.88
0.86
0.96
-3 3-2 -1 0 1 2
OUTPUT LOAD REGULATION
MAX1510/MAX17510 toc01
IOUT (A)
VOUT (V)
VREFIN = 0.9V
VIN = 1.2V
VIN = 1.5V
1.200
1.250
1.225
1.275
1.300
-3 3-2 -1 0 1 2
OUTPUT LOAD REGULATION
MAX1510/MAX17510 toc02
IOUT (A)
VOUT (V)
VREFIN = 1.25V
VIN = 1.5V
VIN = 1.8V
0
2.5
2.0
1.5
1.0
0.5
3.0
1.0 1.5 2.0 2.5 3.0
MAXIMUM OUTPUT CURRENT
vs. INPUT VOLTAGE
MAX1510/MAX17510 toc03
INPUT VOLTAGE (V)
MAXIMUM OUTPUT CURRENT (A)
DROPOUT VOLTAGE LIMITED
THERMALLY LIMITED
VOUT = 1.25V
VOUT = 0.9V
BIAS CURRENT (ICC)
vs. INPUT VOLTAGE (VIN)
MAX1510/MAX17510 toc05
VIN (V)
ICC (mA)
3.02.51.5 2.01.00.5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
03.5
VOUT = 1.25V
DROPOUT
INPUT UVLO
BIAS CURRENT (ICC)
vs. LOAD CURRENT (IOUT)
MAX1510/MAX17510 toc06
IOUT (A)
ICC (mA)
10-1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
-2 2
VIN = 1.5V
VOUT = 1.25V
VOUT = 0.90V
ENTERING
DROPOUT
POWER GROUND CURRENT (IPGND)
vs. SOURCE LOAD CURRENT (IOUT)
MAX1510/MAX17510 toc07
IOUT (A)
IPGND (mA)
1.51.00.5
0.05
0.10
0.15
0.20
0.25
0
02.0
VOUT = 1.25V
VOUT = 0.90V
VIN = 1.5V
ENTERING
DROPOUT
INPUT CURRENT (IIN)
vs. SINK LOAD CURRENT (IOUT)
MAX1510/MAX17510 toc08
IOUT (A)
IIN (mA)
-0.5-1.0-1.5
1
2
3
4
5
6
7
0
-2.0 0.0
VIN = 1.5V
VOUT = 0.90V
VOUT = 1.25V
0
0.5
0.4
0.3
0.2
0.1
0.6
03.00.5 1.0 1.5 2.0 2.5
DROPOUT VOLTAGE
vs. OUTPUT CURRENT
MAX1510/MAX17510 toc09
OUTPUT CURRENT (A)
DROPOUT VOLTAGE (V)
VOUT = 1.25V
VOUT = 0.9V
Typical Operating Characteristics
(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)
INPUT CURRENT (IIN)
vs. INPUT VOLTAGE (VIN)
MAX1510/MAX17510 toc04
VIN (V)
IIN (μA)
3.02.52.01.51.00.5
50
100
150
200
250
0
03.5
VOUT = 1.25V
VOUT = 0.90V
MAX1510/MAX17510
SHUTDOWN WAVEFORM
MAX1510/MAX17510 toc12
100μs/div
5V
0V
0V
4V
2V
1V
0V
VOUT
PGOOD
SHDN
RLOAD = 100Ω
SOURCE LOAD TRANSIENT
MAX1510/MAX17510 toc13
20.0μs/div
1A
1mV/div
0A
VOUT
AC-COUPLED
IOUT
Low-Voltage DDR Linear Regulators
_______________________________________________________________________________________
5
SOURCE/SINK LOAD TRANSIENT
MAX1510/MAX17510 toc14
4.00μs/div
+1.5A
5mV/div
-1.5A
VOUT
AC-COUPLED
IOUT
LINE TRANSIENT
MAX1510/MAX17510 toc15
40μs/div
3.3V
0.9V
1.5V
VIN (1V/div)
VOUT (10mV/div)
AC-COUPLED
IOUT = 100mA
Typical Operating Characteristics (continued)
(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)
-20
-15
-10
-5
0
5
10
15
20
-10 -5 0 5 10
REFOUT VOLTAGE ERROR
vs. REFOUT LOAD CURRENT
MAX1510/MAX17510 toc10
REFOUT LOAD CURRENT (mA)
REFOUT VOLTAGE ERROR (mV)
STARTUP WAVEFORM
MAX1510/MAX17510 toc11
500μs/div
5V
0V
0V
4V
0V
1.25V
PGOOD
VOUT
SHDN
SINK CURRENT-LIMIT DISTRIBUTION
TA = +125°C
MAX1510/MAX17510 toc20
SINK CURRENT LIMIT (A)
SAMPLE PERCENTAGE (%)
10
20
30
40
0
-4.00
-3.80
-3.60
-3.40
-3.20
-3.00
-2.80
-2.60
-2.40
-2.00
-2.20
50
SAMPLE SIZE = 200
SOURCE CURRENT-LIMIT DISTRIBUTION
TA = +125°C
MAX1510/MAX17510 toc21
SOURCE CURRENT LIMIT (A)
SAMPLE PERCENTAGE (%)
10
20
30
40
0
1.50
1.80
2.10
2.40
2.70
3.00
3.30
3.60
3.90
4.50
4.20
50
SAMPLE SIZE = 200
SINK LOAD REGULATION DISTRIBUTION
IOUT = -1A, TA = +125°C
MAX1510/MAX17510 toc22
SINK LOAD REGULATION (mV)
SAMPLE PERCENTAGE (%)
10
20
30
40
0123456
78911
10
50
SAMPLE SIZE = 200
SINK CURRENT-LIMIT DISTRIBUTION
TA = +125°C
MAX1510/MAX17510 toc20
SINK CURRENT LIMIT (A)
SAMPLE PERCENTAGE (%)
10
20
30
40
0
-4.00
-3.80
-3.60
-3.40
-3.20
-3.00
-2.80
-2.60
-2.40
-2.00
-2.20
50
SAMPLE SIZE = 200
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)
DYNAMIC OUTPUT-VOLTAGE TRANSIENT
MAX1510/MAX17510 toc17
20.0μs/div
2.5V
0.9V
0.9V
1.8V
1.2V
1.2V
VREFOUT
VDDQ
VOUT
VIN = 1.8V
SINK CURRENT-LIMIT
DISTRIBUTION
MAX1510/MAX17510 toc18
SINK CURRENT LIMIT (A)
SAMPLE PERCENTAGE (%)
-2.5-3.0-3.5
10
20
30
40
50
0
-4.0 -2.0
SAMPLE SIZE = 200 +25°C
+85°C
SOURCE CURRENT-LIMIT
DISTRIBUTION
MAX1510/MAX17510 toc19
SOURCE CURRENT LIMIT (A)
SAMPLE PERCENTAGE (%)
3.53.02.5
10
20
30
40
50
0
2.0 4.0
SAMPLE SIZE = 200 +25°C
+85°C
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
_______________________________________________________________________________________ 7
Detailed Description
The MAX1510/MAX17510 are low-voltage, low-dropout
DDR termination linear regulators with an external bias
supply input and a buffered reference output (see
Figures 1 and 2). VCC is powered by a 2.7V to 3.6V
supply that is commonly available in laptop and desk-
top computers. The 3.3V bias supply drives the gate of
the internal pass transistor, while a lower voltage input
at the drain of the transistor (IN) is regulated to provide
VOUT. By using separate bias and power inputs, the
MAX1510/MAX17510 can drive an n-channel high-side
MOSFET and use a lower input voltage to provide bet-
ter efficiency.
The MAX1510/MAX17510 regulate their output voltage
to the voltage at REFIN. When used in DDR applica-
tions as a termination supply, the MAX1510/MAX17510
deliver 1.25V or 0.9V at 3A peak (typ) from an input
voltage of 1.1V to 3.6V. The MAX1510/MAX17510 sink
up to 3A peak (typ) as required in a termination sup-
ply. The MAX1510/MAX17510 provide shoot-through
protection, ensuring that the source and sink
MOSFETs do not conduct at the same time, yet pro-
duce a fast source-to-sink load transient.
OUT
IN
AGND
PGND
VOUT = VTT = VDDQ/2
CIN2
10μF
COUT1
100μF
C1
1.0μF
R3
100kΩ
OFF
VDDQ
ON
R2
10kΩ
3.3V BIAS
SUPPLY
VIN =
1.1V TO 3.6V
POWER-GOOD
R1
10kΩVREFOUT = VTTR
CREFOUT
0.33μF
REFOUT
MAX1510
MAX17510
VCC
PGOOD
SHDN
REFIN
CREFIN
1000pF
OUTS
Figure 1. Standard Application Circuit
PIN NAME FUNCTION
1 REFOUT Buffered Reference Output. The output of the unity-gain reference input buffer sources and sinks over
5mA. Bypass REFOUT to AGND with a 0.33µF or greater ceramic capacitor.
2V
CC Analog Supply Input. Connect to the system supply voltage (+3.3V). Bypass VCC to AGND with a 1µF or
greater ceramic capacitor.
3 AGND Analog Ground. Connect the backside pad to AGND.
4 REFIN External Reference Input. REFIN sets the output regulation voltage (VOUTS = VREFIN).
5 PGOOD
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 150mV (typ) above
or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the
regulation voltage during startup, PGOOD becomes high impedance.
6 OUTS
Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the
remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12kΩ
resistor.
7SHDN Shutdown Control Input. Connect to VCC for normal operation. Connect to analog ground to shut down the
linear regulator. The reference buffer remains active in shutdown.
8 PGND Power Ground. Internally connected to the output sink MOSFET.
9 OUT Output of the Linear Regulator
10 IN Power Input. Internally connected to the output source MOSFET.
—EP
Exposed Pad. Internally connected to AGND. Connect EP to AGND PCB ground plane to maximize
thermal performance. Not intended as an electrical connection point.
Pin Description
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
8 _______________________________________________________________________________________
MAX1510
MAX17510
SOFT-
START
UVLO
IN
INPUT
1.1V TO 3.6V
OUT VTT
12kΩ
8Ω
PGND
OUTS
EN
EN
Gm
AGND
REFOUT
REFIN
VCC
3.3V BIAS
SUPPLY
OFF ON
VDDQ
VTTR
POWER-
GOOD
SHDN
PGOOD
REFIN
+150mV
REFIN
-150mV
THERMAL
SHDN
DELAY
LOGIC
Figure 2. Functional Diagram
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
_______________________________________________________________________________________ 9
The MAX1510/MAX17510 feature an open-drain
PGOOD output that transitions high 2ms after the out-
put initially reaches regulation. PGOOD goes low within
10µs of when the output goes out of regulation by
±150mV. The MAX1510/MAX17510 feature current- and
thermal-limiting circuitry to prevent damage during fault
conditions.
3.3V Bias Supply (VCC)
The VCC input powers the control circuitry and provides
the gate drive to the pass transistor. This improves effi-
ciency by allowing VIN to be powered from a lower sup-
ply voltage. Power VCC from a well-regulated 3.3V
supply. Current drawn from the VCC supply remains rel-
atively constant with variations in VIN and load current.
Bypass VCC with a 1µF or greater ceramic capacitor as
close to the device as possible.
VCC Undervoltage Lockout (UVLO)
The VCC input undervoltage-lockout (UVLO) circuitry
ensures that the regulator starts up with adequate volt-
age for the gate-drive circuitry to bias the internal pass
transistor. The UVLO threshold is 2.55V (typ). VCC must
remain above this level for proper operation.
Power-Supply Input (IN)
IN provides the source current for the linear regulator’s
output, OUT. IN connects to the drain of the internal n-
channel power MOSFET. IN can be as low as 1.1V,
minimizing power dissipation. The input UVLO prohibits
operation below 0.8V (typ). Bypass IN with a 10µF or
greater capacitor as close to the device as possible.
Reference Input (REFIN)
The MAX1510/MAX17510 regulate OUTS to the voltage
set at REFIN, making the MAX1510/MAX17510 ideal for
memory applications where the termination supply must
track the supply voltage. Typically, REFIN is set by an
external resistive voltage-divider connected to the
memory supply (VDDQ) as shown in Figure 1.
The maximum output voltage of 1.5V is limited by the
gate-drive voltage of the internal n-channel power
transistor.
Buffered Reference Output (REFOUT)
REFOUT is a unity-gain transconductance amplifier that
generates the DDR reference supply. It sources and
sinks greater than 5mA. The reference buffer is typically
connected to ceramic bypass capacitors (0.33µF to
1.0µF). REFOUT is active when VREFIN > 0.45V and
VCC is above VUVLO. REFOUT is independent of
SHDN.
Shutdown
Drive SHDN low to disable the error amplifier, gate-
drive circuitry, and pass transistor (Figure 2). In shut-
down, OUT is terminated to GND with an 8ΩMOSFET.
REFOUT is independent of SHDN. Connect SHDN to
VCC for normal operation.
Current Limit
The MAX1510/MAX17510 feature source and sink cur-
rent limits to protect the internal n-channel MOSFETs.
The source and sink MOSFETs have a typical 3A cur-
rent limit (1.8A min). This current limit prevents damage
to the internal power transistors, but the device can
enter thermal shutdown if the power dissipation
increases the die temperature above +165°C (see the
Thermal-Overload Protection
section).
Soft-Start Current Limit
Soft-start gradually increases the internal source cur-
rent limit to reduce input surge currents at startup. Full-
source current limit is available after the 200µs soft-start
timer has expired. The soft-start current limit is
given by:
where ILIMIT and tSS are from the
Electrical
Characteristics.
Thermal-Overload Protection
Thermal-overload protection prevents the linear regula-
tor from overheating. When the junction temperature
exceeds +165°C, the linear regulator and reference
buffer are disabled, allowing the device to cool. Normal
operation resumes once the junction temperature cools
by 15°C. Continuous short-circuit conditions result in a
pulsed output until the overload is removed. A continu-
ous thermal-overload condition results in a pulsed out-
put. For continuous operation, do not exceed the
absolute maximum junction-temperature rating
of +150°C.
IIt
t
LIMIT SS LIMIT
SS
()
=×
Power-Good (PGOOD)
The MAX1510/MAX17510 provide an open-drain
PGOOD output that goes high 2ms (typ) after the out-
put initially reaches regulation during startup as shown
in Figure 3. PGOOD transitions low 10µs after the out-
put goes out of regulation by ±150mV, or when the
device enters shutdown. Connect a pullup resistor from
PGOOD to VCC for a logic-level output. Use a 100kΩ
resistor to minimize current consumption.
Applications Information
Dynamic Output-Voltage Transitions
By changing the voltage at REFIN, the MAX1510/
MAX17510 can be used in applications that require
dynamic output-voltage changes between two set
points (graphics processors). Figure 4 shows a dynam-
ically adjustable resistive voltage-divider network at
REFIN. Using an external signal MOSFET, a resistor
can be switched in and out of the REFIN resistor-
divider, changing the voltage at REFIN. The two output
voltages are determined by the following equations:
VV
R
RR
VV
RR
RRR
OUT LOW REF
OUT HIGH REF
()
()
=+
⎛
⎝
⎜⎞
⎠
⎟
=+
()
++
()
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
2
12
23
123
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
10 ______________________________________________________________________________________
MAX1510
MAX17510
REFIN
R2
R1
CREFIN
R3
REFERENCE
VOLTAGE
(VREF)
VOUT(HIGH)
(R2 + R3)
R1 + (R2 + R3)
VOUT(LOW)
VOUT(HIGH) =
R2
R1 + R2
VOUT(LOW) = VREF
VREF
()
Figure 4. Dynamic Output-Voltage Change
Figure 3. MAX1510/MAX17510 PGOOD and Soft-Start Waveforms
POWER-GOOD
WINDOW
CURRENT LIMIT
OUT
PGOOD
10μs
PROPAGATION
DELAY
2ms STARTUP
DELAY
10μs
PROPAGATION
DELAY
200μs
OUTPUT OVERLOAD
CONDITION
SHDN
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
______________________________________________________________________________________ 11
For a step voltage change at REFIN, the rate of change
of the output voltage is limited by the total output
capacitance, the current limit, and the load during the
transition. Adding a capacitor across REFIN and AGND
filters noise and controls the rate of change of the
REFIN voltage during dynamic transitions. With the
additional capacitance, the REFIN voltage slews
between the two set points with a time constant given
by REQ x CREFIN, where REQ is the equivalent parallel
resistance seen by the slew capacitor.
Operating Region and Power Dissipation
The maximum power dissipation of the MAX1510/
MAX17510 depends on the thermal resistance of the 10-
pin TDFN package and the circuit board, the tempera-
ture difference between the die and ambient air, and the
rate of airflow. The power dissipated in the device is:
PSRC = ISRC x (VIN – VOUT)
PSINK = ISINK x VOUT
The resulting maximum power dissipation is:
where TJ(MAX) is the maximum junction temperature
(+150°C), TAis the ambient temperature, θJC is the ther-
mal resistance from the die junction to the package case,
and θCA is the thermal resistance from the case through
the PCB, copper traces, and other materials to the sur-
rounding air. For optimum power dissipation, use a large
ground plane with good thermal contact to the backside
pad, and use wide input and output traces.
When 1 square inch of copper is connected to the
device, the maximum allowable power dissipation of a
10-pin DFN package is 1951mW. The maximum power
dissipation is derated by 24.4mW/°C above TA= +70°C.
Extra copper on the PCB increases thermal mass and
reduces thermal resistance of the board. Refer to the
MAX1510 evaluation kit for a layout example.
The MAX1510/MAX17510 deliver up to 3A and oper-
ates with input voltages up to 3.6V, but not simultane-
ously. High output currents can only be achieved when
the input-output differential voltages are low (Figure 5).
Dropout Operation
A regulator’s minimum input-to-output voltage differen-
tial (dropout voltage) determines the lowest usable sup-
ply voltage. Because the MAX1510/MAX17510 use an
n-channel pass transistor, the dropout voltage is a func-
tion of the drain-to-source on-resistance (RDS(ON) =
0.25Ωmax) multiplied by the load current (see the
Typical Operating Characteristics
):
VDROPOUT = RDS(ON) x IOUT
For low output-voltage applications, the sink current is
limited by the output voltage and the RDS(ON) of the
MOSFET.
Input Capacitor Selection
Bypass IN to PGND with a 10µF or greater ceramic
capacitor. Bypass VCC to AGND with a 1µF ceramic
capacitor for normal operation in most applications.
Typically, the LDO is powered from the output of a
step-down controller (memory supply) that has addi-
tional bulk capacitance (polymer or tantalum) and dis-
tributed ceramic capacitors.
Output Capacitor Selection
The MAX1510/MAX17510 output stability is indepen-
dent of the output capacitance for COUT from 10µF to
220µF. Capacitor ESR between 2mΩand 50mΩis
needed to maintain stability. Within the recommended
capacitance and ESR limits, the output capacitor
should be chosen to provide good transient response:
ΔIOUT(P-P) x ESR = ΔVOUT(P-P)
where ΔIOUT(P-P) is the maximum peak-to-peak load-
current step (typically equal to the maximum source
load plus the maximum sink load), and ΔVOUT(P-P) is
the allowable peak-to-peak voltage tolerance.
Using larger output capacitance can improve efficiency
in applications where the source and sink currents
change rapidly. The capacitor acts as a reservoir for
the rapid source and sink currents, so no extra current
is supplied by the MAX1510/MAX17510 or discharged
to ground, improving efficiency.
PTT
DIS MAX J MAX A
JC CA
() ()
=+
-
θθ
0
1.0
0.5
2.0
1.5
3.0
2.5
3.5
0 1.0 1.50.5 2.0 2.5 3.0 3.5
SAFE OPERATING REGION
INPUT-OUTPUT DIFFERENTIAL VOLTAGE (V)
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM CURRENT LIMIT
100s RMS
LIMIT
1s RMS
LIMIT
TA = +100°C
TA = 0°C TO +70°C
DROPOUT VOLTAGE
LIMITED
VIN(MAX) - VOUT(MIN)
Figure 5. Power Operating Region—Maximum Output Current
vs. Input-Output Differential Voltage
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
12 ______________________________________________________________________________________
Noise, PSRR, and Transient Response
The MAX1510/MAX17510 operate with low-dropout
voltage and low quiescent current in notebook comput-
ers while maintaining good noise, transient response,
and AC rejection specifications. Improved supply-noise
rejection and transient response can be achieved by
increasing the values of the input and output capaci-
tors. Use passive filtering techniques when operating
from noisy sources.
The MAX1510/MAX17510 load-transient response
graphs (see the
Typical Operating Characteristics
) show
two components of the output response: a DC shift from
the output impedance due to the load-current change
and the transient response. A typical transient response
for a step change in the load current from -1.5A to
+1.5A is 10mV. Increasing the output capacitor’s value
and decreasing the ESR attenuate the overshoot.
PCB Layout Guidelines
The MAX1510/MAX17510 require proper layout to
achieve the intended output power level and low noise.
Proper layout involves the use of a ground plane,
appropriate component placement, and correct routing
of traces using appropriate trace widths. Refer to the
MAX1510 evaluation kit for a layout example:
• Minimize high-current ground loops. Connect the
ground of the device, the input capacitor, and the
output capacitor together at one point.
• To optimize performance, a ground plane is essen-
tial. Use all available copper layers in applications
where the device is located on a multilayer board.
• Connect the input filter capacitor less than 10mm
from IN. The connecting copper trace carries large
currents and must be at least 2mm wide, preferably
5mm wide.
• Connect the backside pad to a large ground plane.
Use as much copper as necessary to decrease the
thermal resistance of the device. In general, more
copper provides better heatsinking capabilities.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 TDFN T1033+1 21-0137 90-0003
MAX1510/MAX17510
Low-Voltage DDR Linear Regulators
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
13
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 5/04 Initial release —
1 1/05 Raised Absolute Maximum rating 1, 14
2 8/05 Added MAX1510ETB 1
3 4/09 Added automotive-qualified part MAX1510ETB/V+ 1, 2, 7, 12, 13
4 7/09 Added MAX17510 to data sheet; added temperature grades for MAX1510ATB+ and
MAX1510ATB/V+; minor edits
1, 2, 3, 6,
7, 12, 13
5 3/11 Added MAX17510 automotive qualified part 1