LTC1064-3
1
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FEATURES
APPLICATIO S
U
DESCRIPTIO
U
TYPICAL APPLICATIO
U
Antialiasing Filters
Smoothing Filters
Tracking High Frequency Lowpass Filters
8th Order Filter in a 14-Pin Package
95kHz Maximum Corner Frequency
No External Components
75:1, 150:1 and 120:1 Clock to Cutoff Frequency
Ratio
60µV
RMS
Total Wideband Noise
0.03% THD or Better
Operates from ±2.37V to ±8V Power Supplies
Low Total Output DC Offset
Low Noise, High Frequency,
8th Order Linear Phase Lowpass Filter
The LTC
®
1064-3 is a monolithic 8th order lowpass Bessel
filter, which provides a linear phase response over its
entire passband. An external TTL or CMOS clock pro-
grams the filter’s cutoff frequency. The clock to cutoff
frequency ratio is 75:1 (Pin 10 at V
+
) or 150:1 (Pin 10 at
V
) or 120:1 (Pin 10 at GND). The maximum cutoff
frequency is 95kHz. No external components are needed.
The LTC1064-3 features low wideband noise and low
harmonic distortion even for input voltages up to 3V
RMS
.
In fact the LTC1064-3 overall performance competes with
equivalent multiple op amp RC active realizations. The
LTC1064-3 is available in a 14-pin DIP or 16-pin surface
mounted SOL package. The LTC1064-3 is fabricated using
LTC’s enhanced analog CMOS Si-gate process.
The LTC1064-3 is pin compatible with the LTC1064-1,
LTC1064-2 and LTC1064-4.
8th Order Clock Sweepable Lowpass Bessel Filter Measured Frequency Response
LTC1064-3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT C
NC
V
fCLK
75/150
VOUT
NC
V+
NC
VIN
AGND
AGND
NC
INV A
1064 TA01a
NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A 0.1µF
OR LARGER CAPACITOR CLOSE TO THE PACKAGE. THE CONNECTI0N
BETWEEN PIN 7 AND PIN 14 SHOULD BE MADE UNDER THE IC PACKAGE.
CLOCK = 7MHz
V+
–8V
8V 0.1µF
0.1µF
VIN
VOUT
FREQUENCY (kHz)
10
0
–15
–30
–45
–60
–75
–90
105
1064-3 TA01b
100 1000
V
OUT
/V
IN
(dB)
V
S
= ±7.5V, f
CLK
= 7MHz, PIN 10 TO V
+
,
f
–3dB
= 95kHz, GROUP DELAY = 6µs
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTC1064-3
2
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PARAMETER CONDITIONS MIN TYP MAX UNITS
Passband Gain Referenced to 0dB, 1Hz to 1kHz 0.5 0.15 dB
Gain TempCo 0.0002 dB/°C
–3dB Frequency 50:1 (f
CLK
/f
3dB
= 75) 26.67 kHz
100:1 (f
CLK
/f
3dB
= 150) 13.34 kHz
Gain at –3dB Frequency Referenced to 0dB, f
IN
= 26.67/13.34kHz –3.8 –2.75 dB
Stopband Attenuation At 3f
3dB
–25 –29 dB
Stopband Attenuation At 5f
3dB
–56 –60 dB
Stopband Attenuation At 7f
3dB
–84 dB
Input Frequency Range 100:1 0 <f
CLK
/2 kHz
50:1 0 <f
CLK
kHz
Output Voltage Swing and V
S
= ±2.37V ±1.1 V
Operating Input Voltage Range V
S
= ±5V ±3.1 V
V
S
= ±7.5V ±5V
Total Harmonic Distortion V
S
= ±5V, Input = 1V
RMS
at 1kHz 0.015 %
V
S
= ±7.5V, Input = 3V
RMS
at 1kHz 0.03 %
Wideband Noise V
S
= ±5V, Input = GND 1Hz – 1.99MHz 55 µV
RMS
V
S
= ±7.5V, Input = GND 1Hz – 1.99MHz 60 µV
RMS
(Note 1)
The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±7.5V, 75:1, fCLK = 2MHz, R1 = 10k, TTL or CMOS clock input level
unless otherwise specified.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Total Supply Voltage (V
+
to V
) ............................ 16.5V
Power Dissipation.............................................. 400mW
Storage Temperature Range ................. 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Operating Temperature Range
LTC1064-3M (OBSOLETE) ............... 55°C to 125°C
LTC1064-3C ....................................... 40°C to 85°C
Input Voltage ........................... (V
+
+0.3V) to V
0.3V)
Burn-In Voltage ....................................................... 15V
ABSOLUTE AXI U RATI GS
WWWU
ORDER PART
NUMBER
LTC1064-3CSW
T
JMAX
= 150°C, θ
JA
= 90°C/W
LTC1064-3CN
ORDER PART
NUMBER
T
JMAX
= 110°C, θ
JA
= 70°C/W
LTC1064-3MJ
LTC1064-3CJ
1
2
3
4
5
6
7
TOP VIEW
J PACKAGE
14-LEAD CERDIP
N PACKAGE
14-LEAD PDIP
14
13
12
11
10
9
8
NC
V
IN
AGND
V
+
AGND
NC
R
IN
A
OUT C
NC
V
f
CLK
75/150
V
OUT
NC
OBSOLETE PACKAGE
Consider the N 14 Package for Alternate Source
1
2
3
4
5
6
7
8
TOP VIEW
SW PACKAGE
16-LEAD PLASTIC (WIDE) SO
16
15
14
13
12
11
10
9
NC
VIN
AGND
V+
AGND
NC
NC
RIN A
OUT C
NC
V
NC
fCLK
75/150
NC
VOUT
PACKAGE/ORDER I FOR ATIO
UU
W
ELECTRICAL CHARACTERISTICS
LTC1064-3
3
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Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±7.5V, 75:1, fCLK = 2MHz, R1 = 10k, TTL or CMOS clock input level
unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output DC Offset V
S
= ±7.5V ±30 ±150 mV
Output DC Offset TempCo V
S
= ±5V ±20 µV/°C
V
S
= ±7.5V ±50 µV/°C
Input Impedance 14 22 k
Output Impedance f
OUT
= 10kHz 2
Output Short-Circuit Current Source/Sink 3/1 mA
Clock Feedthrough 200 µV
RMS
Maximum Clock Frequency V
S
±7V, 50% Duty Cycle 5 MHz
V
S
±7V, 50% Duty Cycle, T
A
= <55°C7MHz
Power Supply Current V
S
= ±2.37V, f
CLK
= 1MHz 10 22 mA
V
S
= ±5V, f
CLK
= 1MHz 12 23 mA
26 mA
V
S
= ±7.5V, f
CLK
= 1MHz 16 28 mA
32 mA
Power Supply Voltage Range ±2.37 ±8V
Gain vs Frequency Phase vs Frequency Group Delay
FREQUENCY (Hz)
10k
GAIN (dB)
15
0
–15
–30
–45
–60
–75
–90
–105
100k 1M
1064 G01
VS = ±7.5V
TA = 25°C
fCLK = 2MHz
f–3dB = 26.67kHz
fCLK = 7MHz
f–3dB = 95kHz
fCLK = 5MHz
f–3dB = 66.67kHz
FREQUENCY (kHz)
06
PHASE (DEG)
–45
0
45
90
135
180
225
270
315
360
405
450
10 12 14 16 18 20 22
1064 G02
24 8
V
S
= ±7.5V
T
A
= 25°C
f
CLK
= 750kHz
f
–3dB
= 10kHz
FREQUENCY (kHz)
110
100
90
80
70
60
50
40
30
20
10
0
GROUP DELAY (µs)
1064 G03
VS = ±7.5V
TA = 25°C
061012 14 16 18 20 2224 8
fCLK = 750kHz, f–3dB = 10kHz
fCLK = 2MHz, f–3dB = 26.67kHz
fCLK = 5MHz, f–3dB = 66.67kHz
ELECTRICAL CHARACTERISTICS
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC1064-3
4
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Transient Response
Input 10VP-P Square Wave
VS = ±7.5V, Pin 10 to V+,
fCLK = 1.5MHz
Table 1. Wideband Noise (µVRMS)
Phase Matching Total Harmonic Distortion
Power Supply Current vs Power
Supply Voltage
V
S
= ±2.37V V
S
= ±5V V
S
= ±7.5V
Noise Noise Noise
Pin 10 to f
CLK
/f
–3dB
µV
RMS
µV
RMS
µV
RMS
V
+
75/1 50 55 60
V
150/1 52 58 62
GND 120/1 45 50 54
FREQUENCY (kHz)
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
PHASE MATCH (±DEG)
1064 G04
061012 14 16 18 20 2224 8
VS = ±7.5V
fCLK = 1.5MHz
f–3dB = 20kHz
50 UNIT SAMPLE (TA = 25°C TO 125°C)
INPUT LEVELS (V
RMS
)
0.1
0.01
DISTORTION (%)
0.1
1.0
110
1064 G05
V
S
= ±7.5V
V
S
= ±5V
V
S
= ±2.37V
f
CLK
= 1.5MHz, 75:1
f
–3dB
= 20kHz
TOTAL POWER SUPPLY VOLTAGE (V)
02 6 10 141822
POWER SUPPLY CURRENT (mA)
48
44
40
36
32
28
24
20
16
12
8
4
0481216
1064 G06
20 24
f
CLK
= 1MHz
T
A
= –55°C
T
A
= 25°C
T
A
= 125°C
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC1064-3
5
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FREQUENCY (kHz) GAIN (dB) PHASE (deg)
0.500 0.955 88.100
1.000 3.380 175.300
1.500 7.570 99.700
2.000 13.770 20.100
2.500 21.800 48.000
3.000 30.700 100.700
3.500 39.400 139.900
4.000 47.600 169.200
4.500 55.100 168.300
5.000 61.900 150.300
5.500 68.260 135.830
6.000 74.050 123.660
6.500 79.450 113.440
7.000 84.330 104.440
7.500 89.010 97.670
8.000 93.250 91.580
8.500 97.340 84.670
9.000 101.390 74.600
9.500 104.980 75.990
FREQUENCY (kHz) GAIN (dB) PHASE (deg)
0.500 0.858 90.430
1.000 2.990 179.200
1.500 6.840 89.600
2.000 12.780 3.800
2.500 20.800 71.000
3.000 29.900 129.600
3.500 38.800 173.700
4.000 47.100 152.600
4.500 54.700 126.000
5.000 61.600 103.300
5.500 68.000 85.190
6.000 73.840 69.060
6.500 79.250 54.780
7.000 84.230 42.440
7.500 88.940 30.060
8.000 93.360 21.300
8.500 97.510 10.000
9.000 100.880 1.520
9.500 105.780 7.820
FREQUENCY GAIN (dB) DELAY (ms)
0.200 0.284 0.490
0.300 0.450 0.489
0.400 0.670 0.489
0.500 0.960 0.487
0.600 1.310 0.487
0.700 1.730 0.485
0.800 2.210 0.484
0.900 2.750 0.482
1.000 3.380 0.478
1.100 4.070 0.478
1.200 4.820 0.475
1.300 5.660 0.470
1.400 6.580 0.467
1.500 7.570 0.463
1.600 8.640 0.456
1.700 9.790 0.448
1.800 11.050 0.438
1.900 12.360 0.428
2.000 13.770 0.417
Table 2. Gain/Phase, f–3dB = 1kHz, LTC1064-3 Typical Response
VS = ±5V, TA = 25°C, fCLK = 75kHz, Pin 10 at V+ (fltr 75:1)
FREQUENCY (kHz) GAIN (dB) DELAY (ms)
0.200 0.281 0.502
0.300 0.420 0.503
0.400 0.610 0.503
0.500 0.860 0.502
0.600 1.160 0.502
0.700 1.530 0.502
0.800 1.950 0.503
0.900 2.430 0.503
1.000 2.990 0.500
1.100 3.610 0.500
1.200 4.300 0.500
1.300 5.060 0.498
1.400 5.920 0.495
1.500 6.830 0.491
1.600 7.840 0.489
1.700 8.930 0.481
1.800 10.130 0.473
1.900 11.410 0.465
2.000 12.780 0.454
Table 3. Gain/Delay, f–3dB = 1kHz, LTC1064-3 Typical Response
VS = ±5V, TA = 25°C, fCLK = 75kHz, Pin 10 at V+ (fltr 75:1)
Table 4. Gain/Phase, f–3dB = 1kHz, LTC1064-3 Typical Response
VS = ±5V, TA = 25°C, fCLK = 150kHz, Pin 10 at V (fltr 150:1)
Table 5. Gain/Delay, f–3dB = 1kHz, LTC1064-3 Typical Response
VS = ±5V, TA = 25°C, fCLK = 150kHz, Pin 10 at V (fltr 150:1)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC1064-3
6
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Table 6. Gain/Phase, f–3dB = 1kHz, LTC1064-3 Typical Response
VS = ±5V, TA = 25°C, fCLK = 120kHz, Pin 10 at GND (fltr 120:1)
Table 7. Gain/Delay, f–3dB = 1kHz, LTC1064-3 Typical Response
VS = ±5V, TA = 25°C, fCLK = 120kHz, Pin 10 at GND (fltr 120:1)
FREQUENCY (kHz) GAIN (dB) DELAY (ms)
0.200 0.354 0.458
0.300 0.520 0.456
0.400 0.730 0.454
0.500 1.000 0.452
0.600 1.320 0.449
0.700 1.670 0.448
0.800 2.090 0.446
0.900 2.540 0.446
1.000 3.050 0.445
1.100 3.600 0.446
1.200 4.220 0.449
1.300 4.900 0.448
1.400 5.670 0.447
1.500 6.520 0.446
1.600 7.470 0.441
1.700 8.500 0.432
1.800 9.650 0.422
1.900 10.870 0.409
2.000 12.180 0.395
FREQUENCY (kHz) GAIN (dB) PHASE (deg)
0.500 0.994d 82.210
1.000 3.050 –162.800
1.500 6.520 116.700
2.000 12.180 40.200
2.500 19.460 –23.600
3.000 27.200 –74.000
3.500 34.700 –114.200
4.000 41.900 –146.800
4.500 48.700 –173.300
5.000 55.100 164.700
5.500 60.900 145.800
6.000 66.500 130.610
6.500 71.660 117.130
7.000 76.390 105.880
7.500 80.910 96.140
8.000 84.900 87.510
8.500 88.750 81.380
9.000 92.410 78.190
9.500 98.290 52.860
T
A
= 25°C
FREQUENCY (kHz) GAIN (dB) PHASE (deg)
10.000 0.912 –92.270
20.000 3.090 176.000
30.000 6.910 85.500
40.000 12.710 –1.200
50.000 20.500 –77.800
60.000 29.400 –138.700
70.000 38.300 174.600
80.000 46.500 138.300
90.000 54.000 109.100
100.000 61.000 84.800
110.000 67.310 64.040
120.000 73.170 46.260
130.000 78.600 31.120
140.000 83.760 18.050
150.000 88.630 7.770
T
A
= 125°C
FREQUENCY (kHz) GAIN (dB) PHASE (deg)
10.000 0.944 –92.880
20.000 3.170 175.500
30.000 6.910 85.700
40.000 12.450 –0.600
50.000 19.920 –78.000
60.000 28.500 –140.700
70.000 37.200 170.500
80.000 45.300 132.200
90.000 52.700 100.900
100.000 59.600 74.900
110.000 65.900 52.600
120.000 71.750 32.850
130.000 77.170 15.840
140.000 82.370 1.130
150.000 87.400 –11.380
Table 8. Gain/Phase, f–3dB = 20kHz, LTC1064-3 Typical
Response VS = ±7.5V, fCLK = 1.5MHz, Pin 10 at V+(fltr 75:1)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC1064-3
7
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NC (Pins 1, 6, 8 and 13): The “no connection” pins should
be preferably grounded. These pins are not internally
connected.
V
IN
, V
OUT
(Pins 2, 9): The input Pin 2 is connected to an
18k resistor tied to the inverting input of an op amp. Pin 2
is protected against static discharge. The device’s output,
Pin 9, is the output of an op amp which can typically
source/sink 3mA/1mA. Although the internal op amps are
unity gain stable, driving long coax cables is not recom-
mended.
When testing the device for noise and distortion, the
output, Pin 9, should be buffered (Figure 1).
The op amp
power supply wire (or trace) should be connected
directly to the power source. To eliminate switching
transients from filter output, buffer filter output with a
third order lowpass (see Figure 5).
AGND (Pins 3, 5): For dual supply operation these pins
should be connected to a ground plane. For single supply
operation both pins should be tied to one half supply
(Figure 3).
V
+
, V
(Pins 4, 12): Should be bypassed with a 0.1µF
capacitor to an adequate analog ground. Low noise,
nonswitching power supplies are recommended.
To avoid
latchup when the power supplies exhibit high turn-on
transients, a 1N5817 Schottky diode should be added
from the V
+
and V
pins to ground (Figure 1, 2 and 3).
R
IN
A, OUT C (Pins 7, 14): A very short connection between
Pin 7 and Pin 14 is recommended. This connection should
be preferably done under the IC package. In a breadboard,
use a one inch, or less, shielded coaxial cable: the shield
should be grounded. In a PC board, use a one inch trace or
less; surround the trace by a ground plane.
50/100 (Pin 10): Ratio Pin.The DC level at this pin deter-
mines the ratio of clock frequency to the –3dB frequency of
the filter. The ratio is 75:1 when Pin 10 is at V
+
, 120:1 when
Pin 10 is at GND and 150:1 when Pin 10 is at V
. This pin
should be bypassed with a 0.1µF capacitor to analog
ground when it’s connected to V
or V
+
(Figure 1). See
Tables 2 through 8 for typical gain and delay responses for
the three ratios.
f
CLK
(Pin 11): For ±5V supplies the logic threshold level is
1.4V. For ±8V and 0V to 5V supplies the logic threshold
levels are 2.2V and 3V respectively. The logic threshold
levels vary ±100mV over the full military temperature
range. The recommended duty cycle of the input clock is
50% although for clock frequencies below 500kHz the
clock “on” time can be as low as 200ns. The maximum
clock frequency for ±5V supplies is 4MHz. For ±7V sup-
plies and above, the maximum clock frequency is 7MHz.
Do not allow the clock levels to exceed the power supplies.
For single supply operation 6V use level shifting at Pin 11
with T
2
L levels (see Figure 4).
(Pin Numbers Refer to the 14-Pin Package)
UU
U
PI FU CTIO S
LTC1064-3
8
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Figure 3. Single Supply Operation. If Fast Power Up
or Down Transients are Expected, Use a 1N5817
Schottky Diode Between Pin 4 and Pin 5
Figure 4. Level Shifting the Input T2L Clock
for Single Supply Operation 6V
Figure 5. Adding an Output Buffer-Filter to Eliminate Any Clock
Feedthrough. Passband ±0.1dB to 50kHz, –3dB at 94kHz
LTC1064-3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+= 15V fCLK
0V TO 10V
1064-3 F03
0.1µF
0.1µF
5k
5k
V+/2
OUT C
NC
V
fCLK
75/150
VOUT
NC
NC
VIN
AGND
V+
AGND
NC
INV A
VIN
VOUT
LTC1064-3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
V+/GND/V
V
1064-3 F05
0.1µF
0.1µFVOUT
+
LT1056
200pF
430pF
10k
4.99k 4.99k
50
0.027µF
OUT C
NC
V
fCLK
75/150
VOUT
NC
NC
VIN
AGND
V+
AGND
NC
INV A
VIN
Figure 1. Buffering the Filter Output. The Buffer Op Amp
Should Not Share the LTC1064-3 Power Lines
Figure 2. Using Schottky Diodes to Protect
the IC from Power Supply Reversal
LTC1064-3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
V
OUT
+
V
V
+
POWER SOURCE
10k
10k
1064-3 F01
RECOMMENDED OP AMPS:
LT1022, LT318, LT1056
V
+
/V
NC
V
f
CLK
75/150
V
OUT
NC
NC
V
IN
AGND
V
+
AGND
NC
INV A
OUT C
V
IN
LTC1064-3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
+
V
1064-3 F02
0.1µF
0.1µF
1N5817
1N5817
OUT C
NC
V
f
CLK
75/150
V
OUT
NC
NC
V
IN
AGND
V
+
AGND
NC
INV A
V
IN
V
OUT
TYPICAL APPLICATIO S
U
LTC1064-3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
+
1064-3 F04
0.1µF
5k
2.2k
5k
5k 1µF
T
2
L
LEVEL
V
+
RATIO
OUT C
NC
V
f
CLK
75/150
V
OUT
NC
NC
V
IN
AGND
V
+
AGND
NC
INV A
V
IN
V
OUT
LTC1064-3
9
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J Package
14-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
OBSOLETE PACKAGE
J14 0801
.045 – .065
(1.143 – 1.651)
.100
(2.54)
BSC
.014 – .026
(0.360 – 0.660)
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.125
(3.175)
MIN
.300 BSC
(7.62 BSC)
.008 – .018
(0.203 – 0.457) 0° – 15°
1234567
.220 – .310
(5.588 – 7.874)
.785
(19.939)
MAX
.005
(0.127)
MIN 14 11 891013 12
.025
(0.635)
RAD TYP
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
U
PACKAGE DESCRIPTIO
LTC1064-3
10
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N Package
14-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
U
PACKAGE DESCRIPTIO
N14 1002
.020
(0.508)
MIN
.120
(3.048)
MIN
.130 ± .005
(3.302 ± 0.127)
.045 – .065
(1.143 – 1.651)
.065
(1.651)
TYP
.018 ± .003
(0.457 ± 0.076)
.005
(0.125)
MIN
.255 ± .015*
(6.477 ± 0.381)
.770*
(19.558)
MAX
31 24567
8910
11
1213
14
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
LTC1064-3
11
10643fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
S16 (WIDE) 0502
NOTE 3
.398 – .413
(10.109 – 10.490)
NOTE 4
16 15 14 13 12 11 10 9
1
N
2345678
N/2
.394 – .419
(10.007 – 10.643)
.037 – .045
(0.940 – 1.143)
.004 – .012
(0.102 – 0.305)
.093 – .104
(2.362 – 2.642)
.050
(1.270)
BSC .014 – .019
(0.356 – 0.482)
TYP
0° – 8° TYP
NOTE 3
.009 – .013
(0.229 – 0.330)
.005
(0.127)
RAD MIN
.016 – .050
(0.406 – 1.270)
.291 – .299
(7.391 – 7.595)
NOTE 4
× 45°
.010 – .029
(0.254 – 0.737)
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.420
MIN
.325 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
N
123 N/2
.050 BSC
.030 ±.005
TYP
SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
U
PACKAGE DESCRIPTIO
LTC1064-3
12
10643fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
LINEAR TECHNO LOGY CORPORATIO N 1989
LW/TP 1202 1K REV A • PRINTED IN USA
LTC1064-3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1064-3 F06
f
–3dB
=f
CLK
110
f
–3dB
=f
CLK
55
OUT C
NC
V
f
CLK
75/150
V
OUT
NC
NC
V
IN
AGND
V
+
AGND
NC
INV A
7.5V f
CLK
= 1MHz
0.1µF
0.1µF
V
IN2
V
IN1
V
OUT1
:
V
OUT2
:
–7.5V
Figure 6. Dual 4th Order Bessel Filters. VS = ±7.5V,
fCLK = 1MHz, Pin 10 to GND. f–3dB = 9kHz and 18kHz
Amplitude Response
PART NUMBER DESCRIPTION COMMENTS
LTC1069-7 8th Order Linear Phase Lowpass S0-8 Package
LTC1563 Active RC, 4th Order Bessel Lowpass Continuous Time, Resistor Programmable Cutoff
LTC1569-6 DC Accurate, 10th Order Lowpass Linear Phase, Internal Precision Clock, S0-8 Package
LTC1569-7 DC Accurate, 10th Order Lowpass Linear Phase, Internal Precision Clock, S0-8 Package
TYPICAL APPLICATIO S
U
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