LP3984 www.ti.com SNVS160F - OCTOBER 2001 - REVISED OCTOBER 2013 LP3984 Micropower 150 mA Ultra Low-Dropout CMOS Voltage Regulator in Subminiature 4-I/O DSBGA Package Check for Samples: LP3984 FEATURES DESCRIPTION * * * * * * The LP3984 is designed for portable and wireless applications with demanding performance and space requirements. 1 2 Miniature 4-I/O DSBGA or SOT-23-5 Package Logic controlled enable Stable with Tantalum Capacitors 1 F Tantalum Output Capacitor Fast Turn-On Thermal Shutdown and Short-Circuit Current Limit The LP3984's performance is optimized for battery powered systems to deliver extremely low dropout voltage and low quiescent current. Regulator ground current increases only slightly in dropout, further prolonging the battery life. Power supply rejection is better than 60 dB at low frequencies and starts to roll off at 10 kHz. High power supply rejection is maintained down to low input voltage levels common to battery operated circuits. KEY SPECIFICATIONS * * * * * * * * 2.5 to 6.0V Input Range 150 mA Output 60 dB PSRR at 1 kHz, 40 dB at 10 kHz @ 3.1VIN 1.2 A Quiescent Current when Shut Down Fast Turn-On Time: 20 s (typ.) 75 mV typ Dropout with 150 mA Load -40 to +125C Junction Temperature Range for Operation 1.5V, 1.8V, 2.9V and 3.1V The device is ideal for mobile phone and similar battery powered wireless applications. It provides up to 150 mA from a 2.5V to 6V input. The LP3984 consumes less than 1.2 A in disable mode and has fast turn-on time less than 20 s. The LP3984 is available in a 4-bump DSBGA and 5pin SOT-23 packages. Performance is specified for -40C to +125C temperature range and is available in 1.5V, 1.8V, 2.9V and 3.1V output voltages. For other output voltage options from 1.5V to 3.5V, please contact TI sales office. APPLICATIONS * * * * CDMA Cellular Handsets Wideband CDMA Cellular Handsets GSM Cellular Handsets Portable Information Appliances Typical Application Circuit 1(B2) 5(B1) VIN VOUT 1PF Tant 1PF LP3984 3(A2) VEN 4 NC 2(A1) Note: Pin Numbers in parenthesis indicate DSBGA package. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2001-2013, Texas Instruments Incorporated LP3984 SNVS160F - OCTOBER 2001 - REVISED OCTOBER 2013 www.ti.com Block Diagram Pin Descriptions Name DSBGA SOT Function VEN A2 3 Enable Input Logic, Enable High GND A1 2 Common Ground VOUT B1 5 Output Voltage of the LDO VIN B2 1 Input Voltage of the LDO 4 No Connection N.C. (1) (1) The pin numbering scheme for the DSBGA package was revised in April 2002 to conform to JEDEC standards. Only the pin numbers were revised. No changes to the physical locations of the inputs/outputs were made. For reference purposes, the obsolete numbering scheme had GND as pin 1, VOUT as pin 2, VIN as pin 3 and VEN as pin 4. Connection Diagram SOT-23-5 Package Figure 1. Top View See Package Number DBV DSBGA, 4-Bump Package Figure 2. Top View See Package Number YPB0004 2 Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LP3984 LP3984 www.ti.com SNVS160F - OCTOBER 2001 - REVISED OCTOBER 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) -0.3 to 6.5V VIN, VEN -0.3 to (VIN+0.3) 6.5V VOUT Junction Temperature 150C Storage Temperature -65C to +150C Lead Temp. 235C Pad Temp. (4) Maximum Power Dissipation 235C (5) ESD Rating (6) SOT-23-5 364 mW DSBGA 235 mW Human Body Model 2kV Machine Model (1) (2) (3) (4) (5) (6) 200V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Additional information on pad temperature can be found in the TI AN-1112 Application Report (). The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: PD = (TJ TA)/JA,where TJ is the junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance. The 364 mW rating for SOT23-5 appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150C, for TJ, 70C for TA, and 220C/W for JA. More power can be dissipated safely at ambient temperatures below 70C . Less power can be dissipated safely at ambient temperatures above 70C. The Absolute Maximum power dissipation for SOT235 can be increased by 4.5 mW for each degree below 70C, and it must be derated by 4.5mW for each degree above 70C. The human body model is 100pF discharged through 1.5k resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. OPERATING RATINGS (1) (2) VIN 2.5 to 6V VEN 0 to (VIN+0.3V) 6V -40C to +125C Junction Temperature Thermal Resistance Maximum Power Dissipation (1) (2) (3) (3) JA (SOT23-5) 220C/W JA (DSBGA) 340C/W SOT-23-5 250mW DSBGA 160mW Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 250mW rating for SOT23-5 appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125C, for TJ, 70C for TA, and 220C/W for JA using the formula: PD = (TJ - TA)/JA. More power can be dissipated at ambient temperatures below 70C . Less power can be dissipated at ambient temperatures above 70C. The maximum power dissipation for operation can be increased by 4.5 mW for each degree below 70C, and it must be derated by 4.5mW for each degree above 70C. Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LP3984 3 LP3984 SNVS160F - OCTOBER 2001 - REVISED OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise specified: VIN = 2.5V for 1.5V and 1.8V options, VIN = VOUT + 0.5 for output options higher than 2.5V, CIN = 1 F, IOUT = 1mA, COUT = 1 F, tantalum. Typical values and limits appearing in standard typeface are for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40C to +125C. (1) (2) Symbol Parameter Conditions Typ Output Voltage Tolerance Line Regulation Error VOUT Load Regulation Error (3) PSRR IQ Power Supply Rejection Ratio Quiescent Current 0.15 %/V LP3984IBP (DSBGA) 0.0009 0.002 VIN = VOUT(nom) + 0.2V, f = 1 kHz, IOUT = 50 mA, Figure 4 60 VIN = VOUT(nom) + 0.2V, f = 10 kHz, IOUT = 50 mA, Figure 4 40 VEN = 1.4V, IOUT = 0 mA 80 125 %/mA dB 110 150 VEN = 0.4V 0.005 1.2 IOUT = 1 mA 0.6 2.5 IOUT = 50 mA 25 40 IOUT = 100 mA 50 80 120 75 600 IOUT(PK) Peak Output Current VOUT VOUT(nom) - 5% 600 TON Turn-On Time (5) en Output Noise Voltage IEN Maximum Input Current at EN VIL Maximum Low Level Input Voltage VIN = 2.5 to 6.0V at EN VIH Minimum High Level Input Voltage VIN = 2.5 to 6.0V at EN COUT Output Capacitor 4 -0.15 0.005 Output Grounded (Steady State) (5) % of VOUT(nom) 0.002 IOUT = 150 mA (2) (3) (4) 1.2 2.0 IOUT = 1 mA to 150 mA LP3984IM5 (SOT-23-5) Short Circuit Current Limit (1) -1.2 -2.0 0.05 ISC TSD Units Max VIN = 2.5V to 4.5V for 1.5V and 1.8V options VIN = (VOUT + 0.5V) to 4.5V for Voltage options higher than 2.5V VEN = 1.4V, IOUT = 0 to 150 mA Dropout Voltage (4) Limit Min A mV mA 300 mA 20 s BW = 10 Hz to 100 kHz, COUT = 1F tant. 90 Vrms VEN = 0.4 and VIN = 6.0 1 nA 0.4 1.4 V V Capacitance 1 22 ESR 2 10 F Thermal Shutdown Temperature 160 C Thermal Shutdown Hysteresis 20 C Min and Max Limits are verified by design, test, or statistical analysis. Typical (Typ.) numbers are not verified, but do represent the most likely norm. The target output voltage, which is labeled VOUT(nom), is the desired voltage option. An increase in the load current results in a slight decrease in the output voltage and vice versa. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply for input voltages below 2.5V. Turn-on time is time measured between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal value. Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LP3984 LP3984 www.ti.com SNVS160F - OCTOBER 2001 - REVISED OCTOBER 2013 Figure 3. Line Transient Input Test Signal Figure 4. PSRR Input Test Signal Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LP3984 5 LP3984 SNVS160F - OCTOBER 2001 - REVISED OCTOBER 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified, CIN = COUT = 1 F Tantalum, VIN = 2.5 for 1.5V and 1.8V options, VIN = VOUT + 0.2V for output options higher than 2.5V, TA = 25C, Enable pin is tied to VIN. 6 Power Supply Rejection Ratio (VIN = 3.5V) Power Supply Rejection Ratio (VIN = 3.5V) Figure 5. Figure 6. Power Supply Rejection Ratio (VIN = 3.5V) Power Supply Rejection Ratio (LP3984-1.5, VIN = 2.5V) Figure 7. Figure 8. Line Transient Response (LP3984-3.1) Line Transient Response (LP3984-3.1) Figure 9. Figure 10. Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LP3984 LP3984 www.ti.com SNVS160F - OCTOBER 2001 - REVISED OCTOBER 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, CIN = COUT = 1 F Tantalum, VIN = 2.5 for 1.5V and 1.8V options, VIN = VOUT + 0.2V for output options higher than 2.5V, TA = 25C, Enable pin is tied to VIN. Line Transient Response (LP3984-3.1) Line Transient Response (LP3984-3.1) Figure 11. Figure 12. Line Transient Response (LP3984-3.1) Line Transient Response (LP3984-3.1) Figure 13. Figure 14. Start Up Response Start Up Response Figure 15. Figure 16. Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LP3984 7 LP3984 SNVS160F - OCTOBER 2001 - REVISED OCTOBER 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, CIN = COUT = 1 F Tantalum, VIN = 2.5 for 1.5V and 1.8V options, VIN = VOUT + 0.2V for output options higher than 2.5V, TA = 25C, Enable pin is tied to VIN. 8 Enable Response Load Transient Response (LP3984-3.1 Figure 17. Figure 18. Load Transient Response (LP3984-3.1) Load Transient Response (VIN = 4.2V) Figure 19. Figure 20. Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LP3984 LP3984 www.ti.com SNVS160F - OCTOBER 2001 - REVISED OCTOBER 2013 APPLICATION HINTS External Capacitors Like any low-dropout regulator, the LP3984 requires external capacitors for regulator stability. The LP3984 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. Input Capacitors An input capacitance of 1 F is required between the LP3984 input pin and ground (the amount of the capacitance may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be specified by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will be 1 F over the entire operating temperature range. Output Capacitor The LP3984 is designed specifically to work with tantalum output capacitors. A tantalum capacitor in 1 to 22 F range with 2 to 10 ESR range is suitable in the LP3984 application circuit. It may also be possible to use film capacitors at the output, but these are not as attractive for reasons of size and cost. The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR (Equivalent Series Resistance) value which is within a stable range (2 to 10). No-Load Stability The LP3984 will remain stable and in regulation with no external load. This is specially important in CMOS RAM keep-alive applications. On/Off Input Operation The LP3984 is turned off by pulling the VEN pin low, and turned on by pulling it high. If this feature is not used, the VEN pin should be tied to VIN to keep the regulator output on at all times. To assure proper operation, the signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. Fast On-Time The LP3984 output is turned on after Vref voltage reaches its final value (1.23V nominal). To speed up this process, the noise reduction capacitor at the bypass pin is charged with an internal 70 A current source. The current source is turned off when the bandgap voltage reaches approximately 95% of its final value. The turn-on time is determined by the time constant of the bypass capacitor. The smaller the capacitor value, the shorter the turn-on time, but less noise gets reduced. As a result, turn-on time and noise reduction need to be taken into design consideration when choosing the value of the bypass capacitor. Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LP3984 9 LP3984 SNVS160F - OCTOBER 2001 - REVISED OCTOBER 2013 www.ti.com DSBGA Mounting The DSBGA package requires specific mounting techniques which are detailed in the AN-1112 Application Report (SNVA009). Referring to the section PCB Layout ; note that the pad style which must be used with the 5pin package is NSMD (non-solder mask defined) type. For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the DSBGA device. DSBGA Light Sensitivity Exposing the DSBGA device to direct sunlight will cause mis-operation of the device. Light sources such as halogen lamps can affect electrical performance if brought near to the device. The wavelengths which have most detrimental effect are reds and infra-reds, which means that the fluorescent lighting used inside most buildings has very little effect on performance. A DSBGA test board was brought to within 1 cm of a fluorescent desk lamp and the effect on the regulated output voltage was negligible, showing a deviation of less than 0.1% from nominal. 10 Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LP3984 LP3984 www.ti.com SNVS160F - OCTOBER 2001 - REVISED OCTOBER 2013 REVISION HISTORY Changes from Revision D (May 2013) to Revision E * Page Changed layout of National Data Sheet to TI format; correct typos ................................................................................... 10 Changes from Revision E (May 2013) to Revision F Page * Deleted 2.0V option which is obsoleted ................................................................................................................................ 1 * Deleted legacy ordering table ............................................................................................................................................... 3 Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LP3984 11 PACKAGE OPTION ADDENDUM www.ti.com 2-Dec-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LP3984IMF-1.5 LIFEBUY SOT-23 DBV 5 TBD Call TI Call TI LEAB LP3984IMF-1.5/NOPB LIFEBUY SOT-23 DBV 5 TBD Call TI Call TI LEAB LP3984IMF-1.8 LIFEBUY SOT-23 DBV 5 TBD Call TI Call TI LP3984IMF-3.1/NOPB LIFEBUY SOT-23 DBV 5 TBD Call TI Call TI -40 to 125 LEBB LEDB LP3984IMFX-1.8/NOPB LIFEBUY SOT-23 DBV 5 TBD Call TI Call TI -40 to 125 LEBB LP3984ITP-2.9/NOPB LIFEBUY DSBGA YPB 4 TBD Call TI Call TI -40 to 125 LP3984ITPX-1.8/NOPB LIFEBUY DSBGA YPB 4 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 2-Dec-2017 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE OUTLINE YPB0004 DSBGA - 0.575 mm max height SCALE 12.000 DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER D 0.575 MAX C SEATING PLANE BALL TYP 0.15 0.11 0.05 C 0.5 B SYMM 0.5 A 1 4X 0.015 0.18 0.16 C A B 2 SYMM 4215097/B 07/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com EXAMPLE BOARD LAYOUT YPB0004 DSBGA - 0.575 mm max height DIE SIZE BALL GRID ARRAY (0.5) 4X ( 0.16) 2 1 A SYMM (0.5) B SYMM LAND PATTERN EXAMPLE SCALE:40X ( 0.16) METAL 0.05 MAX METAL UNDER SOLDER MASK 0.05 MIN ( 0.16) SOLDER MASK OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4215097/B 07/2016 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). www.ti.com EXAMPLE STENCIL DESIGN YPB0004 DSBGA - 0.575 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 4X ( 0.3) (R0.05) TYP 2 1 A SYMM (0.5) TYP B METAL TYP SYMM SOLDER PASTE EXAMPLE BASED ON 0.125mm THICK STENCIL SCALE:50X 4215097/B 07/2016 NOTES: (continued) 4. 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