DSP56F801FA80 - Motorola / Freescale Semiconductor

DSP56F801/D

Rev. 7.0, 1/2002

DSP56F80

Preliminary Technical Data

DSP56F801 16 -bit Digital Signal Processor

• Up to 40 MIPS operation at 80 MHz core

frequency

• DSP and MCU functionality in a unified,

C-efficient architecture

• MCU-friendly instruction set supports both

DSP and controller functions: MAC, bit

manipul at i on unit , 14 addr ess ing modes

•8K × 16-bit words Program Flash

•1K × 16-bit words Program RAM

•2K × 16-bit words Data Flash

•1K × 16-bit words Data RAM

•2K × 16-bit words Boot Flash

• Hardware DO and REP loops

• 6-channel PWM Module

• Two 4-ch annel , 12- bi t ADCs

• Serial Communications Interface (SCI)

• Serial Peripheral Interface (SPI)

• General Purpose Quad Timer

•JTAG/OnCE

TM port for debugging

• On-chip relaxation oscillator

•11 shared GPIO

• 48-pin LQFP Package

Figure 1. DSP56F801 Block Diagram

JTAG/

OnCE

Port

Digital Reg Analog Reg

Low V ol t age

Supervisor

Program Controller

and

Hardware Loopin g Unit

Data ALU

16 x 16 + 36 → 36-Bit MAC

Three 16-bit Input Registers

Two 36-bit Accumulators

Address

Generation

Unit

Bit

Manipulation

Unit

PLL

Clock Gen

or Optional

Internal

Relaxation Osc.

16-Bit

DSP56800

Core

PAB

PDB

XDB2

CGDB

XAB1

XAB2

GPIOB3/XTAL

GPIOB2/EXTA

INTERRUPT

CONTROLS IPBB

CONTROLS

IPBus Bridge

(IPBB)

MODULE CONTROLS

ADDRESS BUS [ 8:0]

DATA BUS [15:0]

COP RESET

RESETIRQA

Application-

Specific

Memory &

Peripherals

Interrupt

Controller

Program Memory

8188 x 16 Flash

1024 x 16 SRAM

Boot Flash

2048 x 16 Flash

Data Memory

2048 x 16 Flash

1024 x 16 SRAM

COP/

Watchdog

SPI

GPIO

SCI0

GPIO

Quad Timer D

or GPIO

Quad Timer C

A/D1

A/D2 ADC

6PWM Outputs

Fault Input

PWMA

16 16

VCAPC VDD VSS VDDA VSSA

624 5*

••

•

••••

VREF

*includes TCS pin which is reserved for factory use and is tied to VSS

2DSP56F801 Prel im i nary Tech nical Data MOTOROLA

Part 1 Overvie w

1.1 DSP56F801 Features

1.1.1 Digital Signal Processi ng Core

• Efficient 16-bit DSP56800 family DSP engine with dual Harvard architecture

• As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulat or (MAC)

• Two 36-bit accumulators including extension bits

• 16-bit bidirectiona l barrel shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses and one external address bus

• Four internal data bus es and one external data bus

• Instructi on set supports both DSP and controller functions

• Controller style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/OnCE debug programming interfac e

1.1.2 Memory

• Harvard architecture per mits as many as three simul ta neous accesses to program and data memory

• On-chip memory including a low-cost, high-volume flash solution

—8K × 16 bit words of Program Flash

—1K × 16-bit words of Program RAM

—2K × 16-bit words of Data Flash

—1K × 16-bit words of Data RAM

—2K × 16-bit words of Boot Flash

• Programmable Boot Flash supports customized boot code and fie ld upgrades of stored code

through a variety of interfaces (JTAG, SPI)

1.1.3 Peripheral Circuits for DSP56F801

• Pulse Width Modulator (PWM) with six PWM outputs , two Fau lt inputs, f ault-t olerant design wit h

deadtime insertion; supports both center- and edge-aligned modes

• Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions

with two 4-multiplexed inputs; ADC and PWM modules can be synchronized

• General Purpose Quad Timer: Timer D with three pins (or three additional GPIO lines)

• Serial Comm unication Interface (SCI) with two pins (or two additional GPIO lines)

DSP56F801 Description

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 3

• Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)

• Eleven multiplexed General Purpose I/O (GPIO) pins

• Computer-Operating Properly (COP) watchdog timer

• One dedicated external interrupt pin

• Ex ternal reset pin for hardware reset

• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor spee d-independent debugging

• Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core cl ock

• Oscil lator flex ibility bet ween either an external c rystal oscil lator or an on -chip rel axation oscil lator

for lower system cost and two additional GPIO lines

1.1.4 Energy Information

• Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs

• Uses a single 3.3V power supply

• On-chip reg ulato rs for d igital an d analog circuitry to lower cos t and reduc e noise

• Wait and Stop modes available

1.2 DSP56F801 Description

The DSP56F801 is a member of the DSP56800 core-based family of Digita l Signal Processors (DSPs). It

combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with

a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,

configuration flexibility, and compact program code, the DSP56F801 is well-suited for many applications.

The DSP56F801 includes many peripherals that are especially useful for applications such as motion

control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,

automotive control, engine management, noise suppression, remote utility metering, and industrial control

for power, lighting, and automation.

The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating

in parallel, allowing as many as six oper ations per instruction cycle. The microproce ssor-sty le programming

model and optimized instruction set allow straightforward generation of efficient, compact code for both

DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The DSP56F801 su pports progr am exec ution from ei ther inte rnal or ext ernal memori es. Two dat a oper ands

can be accessed from the on-chip data RAM per instruction cycle. The DSP56F801 also provides one

external dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on

peripheral configuration.

The DSP56F801 DSP controller includes 8K words (16-bit) of program Flash and 2K words of Data Fl ash

(each pr ogr ammabl e through the JTAG por t) wit h 1K wor ds of both program and da ta RAM. A t ota l of 2K

words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines

that can be used to program the main program and data flash memory areas. Both program and data flash

memories c an b e i ndependently bulk er ase d or er ased in page sizes of 256 words. The Bo ot Flas h memor y

can also be either bulk or page erased.

A key applic ation-specific feature of the DSP56F801 is the inclusion of a Pulse Width Modulator (PWM)

module. Thi s module s inco rpo rates si x comple mentary, indiv idual ly prog rammab le PWM sign al out puts to

4DSP56F801 Prel im i nary Tech nical Data MOTOROLA

enhance moto r control f unctional ity. Complementar y operation permits programmabl e dead-time insertion,

and separate top and bottom output polarity control. The up-counter value is programmable to support a

continu ously var iabl e PWM frequency. Both edg e and cente r alig ned synchr onous pul se width control (0%

to 100% modulation) are supported. The device is capable of controlling most motor types: ACIM (AC

Inducti on Motors) , both BDC an d BLDC (Brush and Brushl ess DC motor s), SRM and VRM (S witched and

Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-

cycle current limiting with sufficient output drive capability to directly drive standard opto-isolators. A

“smoke-inhibit”, write-once protection feature for key parameters is also included. The PWM is double-

buf fered and i ncludes int errupt co ntrol to perm it integral reload rat es to be progr ammable from 1 to 16 . The

PWM modules provide a reference output to synchronize the Analog-to-Digital Converters.

The DSP56F801 incorporates an 8 input, 12-bit Analog-to-Digital Converter (ADC). A full se t of standard

programmable peripherals is provided that include a Serial Communications Interface (SCI), a Serial

Peripheral Interface (SPI), and two Quad Timers. Any of these interfaces can be used as General-Purpose

Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator provides flexibility

in the choice of either on-chip or externally supplied frequency reference for chip timing operations.

Application code is used to select which source is to be used.

1.3 “Best in Class” Development Environment

The SDK (Software Development Kit) provides full y debugged peripheral drivers, libraries and interfaces

that allow programmers to create their unique C application code independent of component architecture.

The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,

compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards

support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete, scalable

tools solution for easy, fast, and efficient development.

1.4 Product Documentation

The four documents listed in Table 1 are required for a complete description and proper design with the

DSP56F801. Documentation is available from local Motorola distributors, Motorola semiconductor sales

offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/dsp.

Table 1. DSP56F8 01 Chi p Docume nta ti on

Topic Description Order Number

DSP56800

Family Manual Detailed description of the DSP56800 family architecture,

and 16-bit DSP core processor and the instruction set DSP56800FM/D

DSP56F801/803/805/807

User’s Manual Detailed description of memory, peripherals, and interfaces

of the DSP56F801, DSP56F803, DSP56F805, and

DSP56F807

DSP56F801-7UM/D

DSP56F801

Technical Data Sheet Electrical and timing specifications, pin descriptions, and

package descriptions (this document) DSP56F801/D

DSP56F801

Product Brief Summary description and block diagram of the DSP56F801

core, memory, peripherals and inter faces DSP56F801PB/D

Data Sheet Conventions
MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 5
1.5   Data Sheet Conventions
This data sheet uses the following conventions: 
Part 2  Signal/Connection Descriptions
2.1   Introduction
The input and output signals of the DSP56F801 are organized into functional groups, as shown in Table 2
and as illustrated in Figure 2. In Table 3 through Table 13, each table row describes the signal or signals
present on a pin.
OVERBAR This is  used to indicate a signal that is  active when pulled low. For example, the RESET pin is 
active when low.
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples: Signal/Symbol Logic State Signal State Voltage1
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
PIN True Asserted VIL/VOL
PIN False Deasserted VIH/VOH
PIN True Asserted VIH/VOH
PIN False Deasserted VIL/VOL
Table 2. Functional Group Pin Allocations
Functional Grou p Number of 
Pins Detailed 
Description 
Power (VDD or VDDA)5Table 3
Ground (VSS or VSSA)6Table 4
Supply Capacitors 2  Table 5
PLL and Clock 2 Table 6
Interrupt and Program Control 2 Table 7
Pulse Width Modulator (PWM) Port 7 Table 8
Serial Peripheral Interface (SPI) Port1
1. A l ternately, GPIO pins
4Table 9
Serial Communications  Interface (SCI) Port12Table 10
Analog-to-Digital Converter (ADC) Port 9 Table 11
Quad Timer Module Port 3 Table 12
JTAG/On-Chip Emulation (OnCE) 6 Table 13

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Figure 2. DSP56F801 Signals Identified by Functional Group1

1. Alternate pin functionality is shown in parenthesis.

DSP56F801

Power Port

Ground Port

Power Port

Ground Port

PLL and Clock

or GPIO

SCI0 Port

or GP IO

VDD

VSS

VDDA

VSSA

VCAPC

EXTAL (GPIOB2)

XTAL (GPIO B3)

TCK

TMS

TDI

TDO

TRST

JTAG/OnCE

Port

PWMA0-5

FAULTA0

SCLK (GPIOB4)

MOSI (GPIOB5)

MISO (G PIOB6)

SS (GPIOB7)

TXD0 (GPIOB0)

RXD0 (GPIOB1)

ANA0-7

VREF

TD0-2 (GPIOA0-2)

IRQA

RESET

Quad

Timer D

or GP IO

ADCA Port

Other

Supply

Port

Interrupt/

Program

Control

SPI Por t

or GPIO

*includes TCS pin which is reserved for factory use and is tied to VSS

Power and Gro und Signals

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 7

2.2 Power and Ground Signals

2.3 Clock and Phase Lock Loop Signals

Table 3. Power Inputs

No. of Pins Signal Name Signal Description

4VDD Power—These pin s provide power to the in ternal structure s of the chip, and should

all be attached to VDD.

1VDDA Analog Power—These pins supply an analog power source.

Table 4. Grounds

No. of Pins Signal Name Signal Description

4VSS GND—These pins provide grounding for the internal structures of the chip,

and should all be attached to VSS.

1VSSA Analog Ground—This pin supplies an analog ground.

1TCS TCS—This pin is reserved for factory use and must be tied to VSS for normal

use. In block diagrams, this pin is considered an additional VSS.

Table 5. Supply Capacitors and VPP

No. of

Pins Signal

Name Signal

Type State

During Reset Signal Description

2VCAPC Supply Supply VCAPC - Connect each pin to a 2.2 µF bypa ss capa citor i n o rder to

bypass the core logic vo ltage regulator (required for proper chip

operation). For more information, refer to Section 5.2.

Table 6. PLL and Clock

No. of

Pins Signal

Name Signal

Type State

During Reset Signal Description

1EXTAL

GPIOB2

Input

Input/

Output

Input

External Crystal Oscillator Input—This input sh ould be connec ted

to an 8 MHz external crystal or ceramic resonator. For more

information, please refer to Section 3.5.

Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO)

pin that can be programmed as a n i npu t o r ou tput pi n. This I/O can be

utilized when using the on-chip relaxation oscillator so the EXTAL pin

is not needed.

*includes TCS pin which is reserved for factory use and is tied to VSS

8DSP56F801 Prel im i nary Tech nical Data MOTOROLA

2.4 Interrupt and Program Control Signals

2.5 Pulse Width Modulator (PWM) Signals

1XTAL

GPIOB3

Output

Input/

Output

Chip-

driven

Input

Crystal Oscillator Output—This output should be connected to an 8

MHz external crystal or ceramic resonator. For more information,

please refer to Section 3.5.

This pin can also be connected to an external clock source. For more

information, please refer to Section 3.5.3.

Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO)

pin that can be prog ram me d a s an input or output pi n. This I/O ca n b e

util ized whe n usin g the on-c hip rel axati on osc illato r so the XTAL pin is

not needed.

Table 7. Interrupt and Program Control Signals

No. of

Pins Signal

Name Signal

Type State During

Reset Signal Description

1IRQA Input Input External Interrupt Request A—The IRQA input is a

synchronized external interrupt request that indica tes that an

external de vic e is re questing servic e. It c an b e p r og ram med to be

level-sensitive or negative-edge- triggered.

1RESET Input Input Reset—This input is a direct hardware reset on the processor.

When RESET is assert ed lo w, the DSP is initia lized and plac ed in

the Reset s tate. A Schm itt trigger input is use d for noise im munity.

When the RESET pin is deasserted, the initial chip operating

mode is latched from the EXTBOOT pin. The internal reset signal

will be deasserted synchronous with the internal clocks, after a

fixed number of internal clocks.

To ensure com plete hardware res et, RESET and TRST shou ld be

asserted together. The only exception occurs in a debugging

environment when a hardware DSP reset is required and it is

necessary not to reset the OnCE/JTAG module. In this case,

assert RESET, but do not assert TRST.

Table 8. Pulse Width Modulator (PWMA) Signals

No. of

Pins Signal

Name Signal

Type State During

Reset Signal Description

6PWMA0-5 Outpu t Tri- stated PWMA0-5— These are six PWMA output pins.

1FAULTA0 Input Input FAULTA0— This faul t input pin is used for disab ling se lect ed

PWMA outputs in cases where fault conditions originate off

chip.

Table 6. PLL and Clock (Continued)

No. of

Pins Signal

Name Signal

Type State

During Reset Signal Description

Serial Peripheral Interface (SPI) Signals

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 9

2.6 Serial Peripheral Interface (SPI) Signals

Table 9. Serial Peripheral Interface (SPI) Signals

No. of

Pins Signal

Name Signal

Type State During

Reset Sig nal Desc ription

1MISO

GPIOB6

Input/

Output

Input/

Output

Input

SPI Master In/Slave Out (MISO)—This serial data pin is an

input to a master device and an output from a slave device.

The MISO line of a slave device is placed in the high-

impedance state if the slave device is not selected.

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin

that can individually be programmed as input or output pin.

After reset, the default state is MISO.

1MOSI

GPIOB5

Input/

Output

Input/

Output

Input

SPI Master Out/Slave In (MOSI)—This serial data pin is an

output from a master device and an input to a slave device.

The master device places data on the MOSI line a half-cycle

before the clock edge that the slave device uses to latch the

data.

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin

that can individually be programmed as input or output pin.

After reset, the default state is MOSI.

1SCLK

GPIOB4

Input/

Output

Input/

Output

Input

SPI Serial Clock—In master mode, this pin serves as an

output, clocking slaved listeners. In slave mode, this pin

serves as the data clock input.

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin

that can individually be programmed as input or output pin.

After reset, the default state is SCLK.

1SS

GPIOB7

Input

Input/

Output

Input

SPI Slave Select—In master mode, this pin is used to

arbit rate mult iple master s. In s lave mode, this pin is used to

select the slave .

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin

that can individually be programmed as input or output pin.

After reset, the default state is SS.

10 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

2.7 Serial Communications Interface (SCI) Signals

2.8 Analog-to-Digital Converter (ADC) Signals

2.9 Quad Timer Module Signals

Table 10. Serial Communications Interface (SCI0) Signals

No. of

Pins Signal

Name Signal

Type State During

Reset Signal Description

1TXD0

GPIOB0

Output

Input/

Output

Input

Transmit Data (TXD0)—transmit data output

Port B GPIO—This pin is a Gene ral Purpos e I/O (GPIO ) pin

that can individually be programmed as input or output pin.

After reset, the default state is SCI output.

1RXD0

GPIOB1

Input

Input/

Output

Input

Receive Data (RXD0)—receive data input

Port B GPIO—This pin is a Gene ral Purpos e I/O (GPIO ) pin

that can individually be programmed as an input or output

pin.

After reset, the default state is SCI input.

Table 11. Analog to Digital Converter Signals

No. of

Pins Signal

Name Signal

Type State During

Reset Sig nal Desc ription

4ANA0-3 Input Input ANA0-3—Analog inputs to ADC channel 1

4ANA4-7 Input Input ANA4-7—Analog inputs to ADC channel 2

1VREF Input Input VREF—Analog reference voltage for ADC. Must be set to

VDDA-0.3V for optimal performance.

Table 12. Quad Timer Module Signals

No. of

Pins Signal

Name Signal

Type State During

Reset Signal Description

3TD0-2

GPIOA0-2

Input/

Output

Input/

Output

Input

TD0-2—Timer D Channel 0-2

Port A GPIO—This p in is a Gen era l Pu rpo se I/O (GPIO) pin

that can individually be programmed as input or output pin.

After reset, the default state is the quad timer input.

JTAG/OnCE

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 11

2.10 JTAG/OnCE

Table 13. JTAG/On-Chip Emulation (OnCE) Signals

No. of

Pins Signal

Name Signal

Type State During

Reset Signal Description

1TCK Input Input, pulled

low internally Test Clock Input—This input pin provide s a gat ed clock to

synchron iz e the tes t lo gic an d sh ift seri al data to the JTAG/OnCE port .

The pin is connected internally to a pull-down resistor.

1TMS Input Input, pulled

high i nte rnal ly Test Mode Select I nput —This inp ut pin is used to s equence the JTAG

TAP control ler’s state mach ine . It i s sa mpled on th e ris ing e dge of TCK

and has an on-chip pull-up resi stor.

1TDI Input Input, pulled

high i nte rnal ly Test Data Input—This input pin provides a serial input data stream to

the JTAG/OnCE port. It is sampled on the rising edge of TCK and has

an on-chip pull-up resistor.

1TDO Output Tri-stated Test Data Output—Thi s tri-st atab le outp ut pin pro vides a s erial ou tput

data stream from the JTAG/OnCE port. It is driven in the Shift-IR and

Shift-DR controller states, and changes on the falling edge of TCK.

1TRST Input Input, pulled

high i nte rnal ly Test Reset—As an input, a low signal on this pin provides a reset

signal to the JTAG TAP control ler. To ensure complete ha rdware reset,

TRST should be asserted whenever RESET is asserted. The only

exception occurs in a debugging environment when a hardware DSP

reset is required and it is necessary not to reset the OnCE/JTAG

module. In this case, assert RESET, but do not assert TRST.

1DE Output Output Debug Event—DE provides a low pulse on recognized debug events.

12 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

Part 3 Specifications

3.1 General Characteristics

The DSP56F801 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs.

The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process

technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture

of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-

compatible I/O voltage levels (a standard 3.3V I/O is desi gned to receive a maximum voltage of 3.3V ± 10%

during normal operation without causing damage). This 5V tolerant capability therefore offers the power

savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in Table 14 are stress ratings only, and functional operation at the

maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent

damage to the device.

The DSP56F801 DC and AC electrical specifications are preliminary and are from design simulations.

These specifications may not be fully tested or guaranteed at this early stage of the product life cycle.

Finalized specifications will be published after complete characterization and device qualifications have

been comple ted.

CAUTION

This device contains protective circuitry to guard against

damage due to high static voltage or electrical fields.

However, normal precautions are advised to avoid

application of any voltages higher than maximum rated

voltages to this high-impedance circuit. Reliability of

operation is enhanced if unused inputs are tied to an

appropriate voltage level.

Table 14. Absolute Maximum Ratings

Characteristic Symbol Min Max Unit

Supply voltage VDD VSS – 0.3 VSS + 4.0 V

All other input voltages, excluding Analog inputs VIN VSS – 0.3 VSS + 5.5V V

Analog inputs ANA0-7 and VREF VIN VSSA– 0.3 VDDA+ 0.3 V

Analog inputs EXTAL, XTAL VIN VSSA– 0.3 VSSA+ 3.0 V

Current drain per pin excluding VDD, VSS, & PWM ouputs I — 10 mA

Current drain per pin for PWM outputs I — 20 mA

Junction temperature TJ—150°C

Storage temperature range TSTG -55 150 °C

DC Electrical Characteristics

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 13

3.2 DC Electrical Characteristics

Table 15. Recommended Operating Conditions

Characteristic Symbol Min Max Unit

Supp ly vo ltage VDD,VDDA 3.0 3.6 V

Ambient operating temperature TA-40 85 °C

Table 16. Thermal Characteristics 1

1. See Section 5.1 for more detail.

Characteristic 48-pin LQFP

Symbol Value Unit

Thermal resistance junction-to-ambient (estimated) θJA 46.8 °C/W

I/O pin power dissipation PI/O User Determin ed W

Power dissipat ion PDPD = (IDD x VDD) + PI/O W

Maximum all owed PDPDMAX (TJ - TA) / θJA °C

Table 17. DC Electrical Characteristics

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF, fop = 80 MHz

Characteristic Symbol Min Typ Max Unit

Input high voltage (XTAL/EXTAL) VIHC 2.25 2.5 2.75 V

Input low vo ltage (XTAL/EXTAL) VILC 0—0.5 V

Input high voltage VIH 2.0 — 5.5 V

Input low voltage VIL -0.3 — 0.8 V

Input cur rent low (pul lup s/p ul ldo w ns dis ab led ) IIL -1 — 1 µA

Input current high (pullups/pulldowns disabled) IIH -1 — 1 µA

Typical Pullup or pulldown resistance RPU, RPD —30—KΩ

Input/output tri-state current low IOZL -10 — 10 µA

Input/output tri-state current low IOZH -10 — 10 µA

Output High Voltage (at IOH) VOH VDD – 0.7 — — V

Output Low Voltage (at IOL) VOL ——0.4V

Output High Current IOH ——-4mA

Output Low Current IOL ——4mA

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Input capac ita nc e CIN —8—pF

Output capacitance COUT —12—pF

PWM pin output source current1IOHP — — -10 mA

PWM pin output sink cu rrent2IOLP ——16mA

VDD supply current IDDT3

Run 4— 103 138 mA

Wait5—7298mA

Stop — 71 97 mA

Low Voltage Interrupt6VEI 2.4 2.7 2.9 V

Power on Reset7VPOR —1.72.0V

1. PWM pin output source current measured with 50% duty cycle.

2. PWM pin outp ut s ink cur r ent meas u r e d wi th 50 % duty cycle.

3. IDDT = IDD + IDDA (Total supply current for VDD + VDDA)

4. Run (operating) IDD measured using 8MH z clock sourc e. All inputs 0.2 V from rail; outputs unlo aded. All po rts

configur ed as inputs; measured with all modules enabled.

5. Wait IDD measured using external square wave clock source (f osc = 8 MHz) into XTAL; all inputs 0.2V from rail;

no DC loads; less than 50 pF on all outputs. CL = 20 pF on EXTAL; all ports configu red as inputs; EXTAL cap acitanc e

linearly affects wait IDD; measured with P LL enabled.

6. Low voltage interrupt monitors the VDD supply. When VDD drops below VEI value, an interrupt is generated.

Functionality of the device is guaranteed under transient conditions when VDDA>VEI.

7. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While

power is ramping up, this sign al remains active for as long as the internal 2 .5V is below 1. 5V typical n o matter how lon g

the ramp up rate is . The internally regulated voltage is typically 100 mV less than V DD during ramp up until 2.5V is

reached, at which time it self regulates.

Table 17. DC Electrical Characteristics (Continued)

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF, fop = 80 MHz

Characteristic Symbol Min Typ Max Unit

AC Electrical Characteristics

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 15

Figure 3. Maximum Run IDD vs. Frequency (see Note 4 above)

3.3 AC Electrical Characteristics

Timi ng wav efor ms in Section 3.3 are test ed w ith a VIL maximum of 0.8V and a VIH minimum of 2.0V f or

all pins except XTAL, which is test ed using the input lev els in Secti on 3.2. In Figure 4 the levels of VIH and

VIL for an input signal are shown.

Figure 4. Input Signal Measurement References

Figure 5 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state.

• Tri-stated, when a bus or signal is placed in a high impedance state.

• Data Valid stat e, when a signal level has reached VOL or V OH.

• Data Invalid state, when a signal level is in transition between VOL and VOH.

180

150

120

Idd (mA)

Digital (VDD=3.6V) Analog (VDDA=3.6V) Total

Freq. (MHz)

040 60 80

VIH

VIL

Fall Time

Input Signa l

Note: The mi dpoint is VIL + (VIH – VIL)/2.

Midpoint1

Low High 90%

50%

10%

Rise Time

16 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

3.4 Flash Memory Characteristics

Figure 5. Signal States

Table 18. Flash Memory Truth Table

Mode XE1

1. X address en able, all rows are disabled when XE = 0

YE2

2. Y address enable, YMUX is disabled when YE = 0

SE3

3. Sense amplifier enable

OE4

4. Output enable, tri-st ate flash data out bus when OE = 0

PROG5

5. Defines program cycle

ERASE6

6. Defines erase cycle

MAS17

7. Defines mass erase cycle, erase whole block

NVSTR8

8. Define s non-volatile sto re cycle

Standby L L L L L L L L

Read H H H H L L L L

Word Program H H L L H L L H

Page Erase H L L L L H L H

Mass Erase H L L L L H H H

Table 19. IFREN Truth Table

Mode IFREN = 1 IFREN = 0

Read Read information block Read main memory block

Word program Program information block Program main memory block

Page erase Erase information block Erase main memory block

Mass eras e Erase both block Erase main me mory block

Data Invalid State

Data1

Data2 Valid

Data

Tri-stated

Data3 Valid

Data2 Data3

Data1 Valid

Data Active Data Active

Flash Memory Characteristics
MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 17
Table 20. Timing Symbols
Characteristic Symbol See Figure(s)
PROG/ERASE to NVSTR set up time Tnvs Figure 6, Figure 7, Figure 8 
NVSTR hold time Tnvh Figure 6, Figure 7 
NVSTR hold time(mass erase) Tnvh1 Figure 8
NVSTR to program set up time Tpgs Figure 6
Program hold time Tpgh Figure 6
Address/data set up time Tads Figure 6
Address/data hol d time Tadh Figure 6
Recovery time Trcv Figure 6, Figure 7, Figure 8 
Cumulative program HV period Thv Figure 6
Program time  Tprog Figure 6
Erase time Terase Figure 7
Mass erase time Tme Figure 8
Table 21. Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF
Characteristic Symbol Min  Typ Max Unit
Program time Tprog 20 ––us
Erase time Terase 20 – – ms
Mass erase time Tme 100 – – ms
Endurance1 ECYC 10,000 20,000 – cycles
Data Retentio n1 @ 5000 cycles DRET 10 30 – years
PROG/ERASE to NVSTR set up time Tnvs –5–us
The following parameters should only be used in the Manual Word Programming Mode
NVSTR hold time Tnvh –5–us
NVSTR hold time (mass erase) Tnvh1 –100– us
NVSTR to program set up time Tpgs –10–us

18 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

Figure 6. Flash Program Cycle

Recovery time Trcv –1–us

Cumulative program HV period2Thv –3–ms

1. Program specification guaranteed from T A = 0 °C to 85 °C.

2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot

be programmed twice before next erase.

Table 21. Flash Timing Parameters (Continued)

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF

Characteristic Symbol Min Typ Max Unit

XADR

YADR

DIN

PROG

NVSTR

Tnvs

Tpgs

Tadh

Tprog

Tads

Tpgh

Tnvh Trcv

Thv

IFREN

Flash Memory Characteristics

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 19

Figure 7. Flash Erase Cycle

Figure 8. Flash Mass Erase Cycle

XADR

YE=SE=OE=MAS1=0

ERASE

NVSTR

Tnvs

Tnvh Trcv

Terase

IFREN

XADR

YE=SE=OE=0

ERASE

NVSTR

Tnvs

Tnvh1 Trcv

Tme

MAS1

IFREN

20 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

3.5 External Clock Operation

The DSP56F801 device clock is derived from either 1) an internal crystal oscillator circuit working in

conjunct io n with an externa l c rys ta l, 2) an external fre quency source, or 3) an on -chip relaxat ion osc il la tor.

To generate a reference frequency using the internal crystal oscillator circuit, a reference crystal external to

the chip must be connected between the EXTAL and XTAL pins. Paragrahs 3.5.1 and 3.5.4 describe these

methods of clocking. Whichever type of clock derivation is used provides a reference signal to a phase-

locked loop (PLL) within the DSP56F801. In turn, the PLL generates a master reference frequency that

determines the speed at which chip operations occur.

Application code can be set to change the frequency source between the relaxation oscillator and crystal

oscillator or external source, and power dow n the relaxation oscillator if desired. Selection of which clock

is use d is determi ned by se tting the PRECS bit in t he PLLCR ( phase- locked loop contro l regis ter) wor d (bi t

2). If the bit is set to 1, the external crystal oscillator circuit is selected. If the bit is set to 0, the internal

relaxation oscillator is selecte d, an d this is th e defa ult value of the b it when power is first applied.

3.5.1 Crystal Oscillator

The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in the

frequency range specified for the external crystal, which is 4-8+ MHz. Figure 9 shows a typical crystal

oscillator circuit. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal

parameters determine the component values required to provide maximum stability and reliable start-up.

The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL

pins to m inimize output distortion and start-up stabilization time.

Figure 9. External Crystal Oscillator Circuit

3.5.2 Ceramic Resonator

It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system

design can tolerate the reduced signal integrity. In Figure 10, a typical ceramic resonator circuit is shown.

Refer to supplier’s recommendations when selecting a ceramic resonator and associated components. The

resonator and components should be mounted as close as possible to the EXTAL and XTAL pins.

Figure 10. Connecting a Ceramic Resonator

Sample External Crystal Parameters:

Rz = 10 MΩ

fc = 4-8 MHz (optimized for 8 MHz)

EXTAL XTAL

Sample Ceramic Resonator Parameters

Rz = 10 MΩ

fc = 4-8 MHz (optimized for 8 MHz)

EXTAL XTAL

External Clock Operation

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 21

3.5.3 External Clock Source

The recommended method of connecting an external clock is given in Figure 11. The external clock

source is connected to XTAL and the EXTAL pin is grounded.

Figure 11. Connecting an External Clock Signal

Figure 12. External Clock Timing

Table 22. External Clock Operation Timing Requirements5

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C

Characteristic Symbol Min Typ Max Unit

Frequency of operation (external clock driver)1

1. See Figure 11 for details on using the recommended connect io n of an external clock driver.

fosc 08110MHz

Clock Pulse Width 2, 5

2. The high or low pulse width must be no smaller than 6.25 ns or the chip will not function.

tPW 6.25 ——ns

External c l ock input rise time3, 5

3. External clock input rise time is measured from 10% to 90%.

trise ——3ns

External clock input fall time4, 5

4. Ex te r na l clo c k input fall time is mea s ur e d fro m 90% to 10%.

5. Paramete rs listed are guaranteed by design.

tfall ——3ns

DSP56F801

XTAL EXTAL

External VSS

Clock

External

Clock

VIH

VIL

Note: The midpoint is VIL + (VIH – VIL)/2.

90%

50%

10%

90%

50%

10% tfall

trise

tPW

22 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

3.5.4 Use of On-Chip Relaxation Oscillator

An internal relaxation oscillator can supply the reference frequency when an external frequency source or

crystal are not used. During a DSP56F801 boot or reset sequence, the relaxation oscillator is enabled by

default, and the PRECS bit in the PLLCR word is set to 0 (Section 3.5). If an external oscillator is connected,

the rel axa tio n osci llat or ca n be de sel ecte d inst ead by sett ing the PR ECS bit in th e PLL CR t o 1. W hen th is

occurs, the PRECSS bit in the PLLSR (prescaler clock select status register) data word also sets to 1. If a

changeover between internal and external oscillators is required at startup, internal device circuits

compensat e for any asynchronous transitions betwee n the two clock signal s so that no gl it ches occur in the

resulting master clock to the chip. When changing clocks, the user m ust ensure that the clock source is not

switched until the desired clock is enabled and stable.

To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator

can be incr ementally adjusted to within ±0.25% of 8 MHz by trimmin g an internal capacito r . Bits 0-7 of the

IOSCTL (internal oscillator control) word allow the user to set in an additional offset (trim) to this preset

value to increase or decrease capacitance. The default value of this trim is 128 units, making the power-up

default capacitor size 432 units. Each unit added or deleted changes the output frequency by about 0.23%,

allowing incremental adjustment until the desired frequency accuracy is achieved.

Table 23. PLL Timing

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C

Characteristic Symbol Min Typ Max Unit

External reference crystal frequency for the PLL1

1. An externally supplied reference cl ock should be as free as possible from any phase jitter for the PLL to work

correctly . The PLL is optimized for 8 MHz input crystal.

2. ZC LK may not excee d 80 M Hz. F or additio na l in fo rmatio n on ZCLK and Fout/2, please refer to the OCCS chapter

in the User Manual.

3. This is the minimum time required after the PLL setup is changed to ensure reliable operation.

fosc 6810MHz

PLL output frequency2 (Fout/2) fop 40 —80MHz

PLL stabilization time 3 0o to +85oCtplls —10—ms

PLL stabilization time3 -40o to 0oCtplls — 100 200 ms

Table 24. Relaxation Oscillator Characteristics

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C

Characteristic Symbol Min Typ Max Unit

Frequency Accuracy1

1. Over full temperature range.

∆f—+2+5%

Frequency Drift over Temp fT789MHz

Frequency Drift over Supply ∆f/∆t—+

0.1 — %/oC

Trim Range ∆f/∆t— 0.1 —%/V

Trim Accurac y ∆fT—+0.25 — %

External Clock Operation

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 23

Figure 13. Typical Relaxation Oscillator Frequency vs. Temperature

(Tr immed to 8MHz @ 25oC)

Figure 14. Typical Relaxation Oscillator Frequency vs. Trim Value @ 25oC

8.0

7.8

8.1

8.2

7.7

7.9

7.6 7555-40 35-25 15-5 85

Tempera ture (oC)

Output Frequency

0 102030405060708090A0B0C0D0E0F0

24 DSP56F801 Prel im i nary Tech nical Data MOTOROLA
3.6   Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 25. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF
1. In the formulas, T = clock cycle. For an opera ting frequency of 80 MHz, T = 12.5 ns.
Characteristic Symbol Typical Min Typical Max Unit See 
RESET Assertion to Address, Data and Control 
Signals High Impedance tRAZ —21nsFigure 15
Minimum RESET Assertion Duration2 
OMR Bit 6 = 0
OMR Bit 6 = 1
2. Circuit stab ilization delay is required during re set when u sing an ext ernal cl ock or cryst al oscillator in two cases:
• After power-on reset
• When recovering from Stop state
tRA 275,000T
128T —
—ns
ns
Figure 15
RESET De-asserti on to First External Address 
Output tRDA 33T 34T ns Figure 15
Edge-sensitive Interrupt Request Width  tIRW 1.5T — ns Figure 16
IRQA, IRQB Assertion to External Data Memo ry 
Access Out Valid, caused by first instruction 
execution in the interrupt service routine
tIDM —15TnsFigure 17
IRQA, IRQB Assertion to General Purpose Output 
Valid, caused by first instruction execution in the 
interrupt service routine
tIG —16TnsFigure 17
IRQA Low to Fi rst Valid Interrupt Vector Address 
Out recovery from Wait State3
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Sto p state.
This is no t the minimu m required so that the IRQA interrupt i s accepted.
tIRI —13TnsFigure 18
IRQA Width Assertion to Reco ver from Stop State4
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
tIW —2TnsFigure 19
Delay from IRQA Assertion to Fetch of first 
instruction (exiting Stop) 
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
—
—275,000T
12T ns
ns
Figure 19
Duration for Level Sensitive IRQA Assertion to 
Cause the Fetch of First IRQA Interrupt Instruction 
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
—
—275,000T
12T ns
ns
Figure 20
Delay from Level Sensitive IRQA Assertion to First 
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tII
—
—275,000T
12T ns
ns
Figure 20

Reset, Stop, Wai t, Mode S e lect, and Interrupt Timing

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 25

Figure 15. Asynchronous Reset Timing

Figure 16. External Interrupt Timing (Negative-Edge-Sensitive)

Figure 17. External Level-Sensitive Interrupt Timing

First Fetch

A0–A15,

D0–D15

PS, DS,

RD, WR

RESET

First Fetch

tRAZ tRA tRDA

IRQA,

IRQB tIRW

A0–A15,

PS, DS,

RD, WR

IRQA,

IRQB

First Interrupt Instruction Execution

a) First Interrupt Instruction Execution

General

Purpose

I/O Pin

IRQA,

IRQB

b) General Purpose I/O

tIDM

tIG

26 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

Figure 18. Interrupt from Wait State Timing

Figure 19. Recovery from Stop State Using Asynchronous Interrupt Timing

Figure 20. Recovery from Stop State Using IRQA Interrupt Service

Instruction Fetch

IRQA,

IRQB

First Interrupt Vector

A0–A15,

PS, DS,

RD, WR

tIRI

Not IRQA Interrupt V ector

IRQA

A0–A15,

PS, DS,

RD, WR First Instruction Fetch

tIW

tIF

Instruction Fetch

IRQA

A0–A15

PS, DS,

RD, WR First IR Q A Interrupt

tIRQ

tII

Serial Peripheral Interface (SPI) Timing
MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 27
3.7   Serial Peripheral Interface (SPI) Timing
1. Parameters listed are guaranteed by design.
Table 26. SPI Timing1
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF, fOP = 80MHz
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
tC50
25 —
—ns
ns
Figures 21, 22, 
23, 24
Enable lead time
Master
Slave
tELD —
25 —
—ns
ns
Figure 24
Enable lag time
Master
Slave
tELG —
100 —
—ns
ns
Figure 24
Clock (SCK) high time
Master 
Slave 
tCH 17.6
12.5 —
—ns
ns
Figures 21, 22, 
23, 24
Clock (SCK) low time
Master 
Slave 
tCL 24.1
25 —
—ns
ns
Figures 21, 22, 
23, 24
Data setup time required for inputs
Master 
Slave 
tDS 20
0—
—ns
ns
Figures 21, 22, 
23, 24
Data hold time required for inputs
Master 
Slave 
tDH 0
2—
—ns
ns
Figures 21, 22, 
23, 24
Access time (time to data active from high-
impedance state)
Slave 
tA4.8 15 ns Figure 24
Disable time (hold time to high-impedance state)
Slave  tD3.7 15.2 ns Figure 24
Data Valid for outputs
Master
Slave (after enable edge)
tDV —
—4.5
20.4 ns
ns
Figures 21, 22, 
23, 24
Data invalid 
Master
Slave
tDI 0
0—
—ns
ns
Figures 21, 22, 
23, 24
Rise time
Master 
Slave 
tR—
—11.5
10.0 ns
ns
Figures 21, 22, 
23, 24
Fall time 
Master 
Slave 
tF—
—9.7
9.0 ns
ns
Figures 21, 22, 
23, 24

28 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

Figure 21. SPI Master Timing (CPHA = 0)

Figure 22. SPI Master Timing (CPHA = 1)

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

MSB in Bits 14–1 LSB in

Master MSB out Bits 14–1 Master LSB out

(Input) SS is held High on m aster

tFtR

tDI(ref)

tDV

tDI

tDS

tDH tCH

tCL

tCH tF

tCL

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

MSB in Bits 14–1 LSB in

Master MSB out Bits 14– 1 Master LSB out

(Input) SS is held High on master

tCL

tCH

tRtDS tDH

tDV

tDI

tDV(ref)

Serial Peripheral Interface (SPI) Timing

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 29

Figure 23. SPI Slave Timing (CPHA = 0)

Figure 24. SPI Slave Timing (CPHA = 1)

SCLK (CPOL = 0)

(Input)

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

Slave MSB out Bits 14–1

MSB in Bits 14–1 LSB in

(Input)

Slave LSB out

tCL

tFtELG

tDS

tELD tCH

tCL

tAtCH tRtFtD

tDI

tDV

tDH

tDI

SCLK (CPOL = 0)

(Input)

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

Slave MS B out Bits 14–1

MSB in Bits 14–1 LSB in

(Input)

Slave LSB out

tDI

tDV

tDH

tDS

tELG

tCH

tDV

tELD

tCL

tCH

30 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

3.8 Quad Timer Timing

3.9 Serial Communication Interface (SCI) Timing

Table 27. Timer Timing1, 2

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF, fOP = 80 MHz

1. In the formulas listed, T = clock cycle. For 80 MHz operation, T = 12.5 n s .

2. Parameters listed are guaranteed by design.

Characteristic Symbol Typical Min Typical Ma x Unit

Timer input period PIN 4T+6 —ns

Timer input high/low period PINHL 2T+3 — ns

Timer output period POUT 2T — ns

Timer output high/low period POUTHL 1T — ns

Figure 25. Timer Timing

Table 28. SCI Timing

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to + 8 5°C, CL ≤ 50 pF, fOP = 80 MHz

Characteristic Symbol Min Max Unit

Baud Rate1

1. fMAX is the frequency of operation of the system clock in MHz.

BR —(fMAX*2.5)/(80) Mbps

RXD2 Pulse Width

2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

RXDPW 0.965/BR 1.04/BR ns

TXD3 Pulse Widt h

3. The TXD pin i n SCI0 is named TXD0 and t he T XD pin in SCI1 is named TXD1.

4. Parameter s lis ted are guaranteed by design.

TXDPW 0.965/BR 1.04/BR ns

Timer Inputs

Timer Outputs POUTHL

POUTHL

POUT

PIN PINHL PINHL

Analog-to-Digital Converter (ADC) Characteristics

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 31

Figure 26. RXD Pulse Width

Figure 27. TXD Pulse Width

3.10 Analog-to-Digital Converter (ADC) Characteristics

Table 29. ADC Characteristics

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, VREF = VDD-0.3V , ADC D I V = 4, 9, or 14 ,

ADC clock = 4MHz, 3.0–3 .6 V, TA = –40° to +85°C, CL ≤ 50 pF, fOP = 80 MHz

Characteristic Symbol Min Typ Max Unit

Input voltages VADIN 0—VDDA1V

Resolution RES 12 — 12 Bits

Integral N on-L ine ari ty2INL — +/- 4 +/- 5 LSB3

Differential Non-Linearity DNL — +/- 0.9 +/- 1 LSB3

Monotonicity GUARANTEED

ADC internal clock fADIC 0.5 — 5 MHz

Conve rsi on range RAD VSSA —V

DDA V

Conve r si on tim e tADC —6 —

tAIC cycles4

Sample tim e tADS —1 —

tAIC cycles4

Input capacitance CADI —5 — pF4

Gain Error (transfer gain) EGAIN 1.00 1.10 1.15 —

Offset Volt age VOFFSET +10 +230 +325 mV

Total Harmonic Distortion THD 55 60 — dB

Signal-to-Noise plus Distorti on SINAD 54 56 — dB

Effective Number of Bits ENOB 8.5 9.5 — bit

Spurious Free Dynamic Range SFDR 60 65 — dB

RXD

SCI receive

data pin

(Input) RXDPW

TXD

SCI receive

data pin

(Input) TXDPW

32 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

Figure 28. Equivalent Analog Input Circuit

1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. 1.8pf

2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. 2.04pf

3. Equivalent resistance for the ESD isolation resistor and the channel select mux. 500 ohms

Sampling capacitor a t th e s am ple an d hold circuit. Capacitor 4 is no rma lly di sc on nec ted from the inpu t an d i s

only connected to it at sampling time. 1pf

Bandwidth BW —100 — KHz

ADC Quiescent Current (both ADCs) IADC — 39.3 — mA

VREF Quiescent Current (both ADCs ) IVREF — 11.85 14.5 mA

1. VDDA should be tied t o the same p otential a s VDD via separate traces. VREF must be equal to or less than VDD and

must be greater than or equal to 2.7V .

2. Measured in 10-90% range.

3. LSB = Least Significant Bit.

Table 29. ADC Characteristics (Continued)

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, VREF = VDD-0.3V , ADC D I V = 4, 9, or 14 ,

ADC clock = 4MHz, 3.0–3 .6 V, TA = –40° to +85°C, CL ≤ 50 pF, fOP = 80 MHz

Characteristic Symbol Min Typ Max Unit

ADC analog input

JTAG Timing

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 33

3.11 JTAG Timing

Table 30. JTAG Timing 1, 3

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF, fOP = 80 MHz

1. Timing i s both wait state and frequency depe ndent. Fo r the values list ed, T = cloc k cycle. For 80 MHz

operation, T = 12.5 ns.

Characteristic Symbol Min Max Unit

TCK frequency of operation2

2. TCK frequency of operation must be less than 1/8 the processor rate.

3. Paramet ers liste d ar e guarant eed by design.

fOP DC 10 MHz

TCK cycle time tCY 100 —ns

TCK cloc k puls e width tPW 50 — ns

TMS, TDI data setup time tDS 0.4 — ns

TMS, TDI data hold time tDH 1.2 — ns

TCK low to TDO data valid tDV — 26.6 ns

TCK low to TDO tri-state tTS — 23.5 ns

TRST assertion time tTRST 50 — ns

DE assertion time tDE 8T — ns

Figure 29. Test Clock Input Timing Diagram

TCK

(Input) VM

VIL

VM = VIL + (VIH – VIL)/2

VIH

tPW tPW

tCY

34 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

Figure 30. Test Access Port Timing Diagram

Figure 31. TRST Timing Diagram

Figure 32. OnCE—Debug Event

Input Data Valid

Output Data Valid

TCK

(Input)

TDI

(Input)

TDO

(Output)

TDO

(Output)

TDO

(Output)

TMS tDV

tDV

tTS

tDS tDH

TRST

(Input) tTRST

DE tDE

Package and Pin-Out Information DSP56F801

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 35

Part 4 Packaging

4.1 Package and Pin-Out Information DSP56F801

This section contains package and pin-out information for the 48-pin LQFP configuration of the

DSP56F801.

Figure 33. Top View, DSP56F801 48-pin LQFP Package

PIN 1

ORIENTATION

MARK

TDO

TD1

TD2

/SS

MISO

MOSI

SCLK

TXDO

VSS

VDD

RXD0

TCS

TCK

TMS

IREQA

TDI

VCAPC2

VSS

VDD

EXTAL

XTAL

TDO

TRST

ANA4

ANA3

VREF

ANA2

ANA1

ANA0

FAULTA0

VSS

VDD

VSSA

VDDA

RESET

PWMA5

PWMA4

PWMA3

PWMA2

PWMA1

VSS

VDD

VCAPC1

PWMA0

ANA7

ANA6

ANA5

Motorola

DSP56F801

36 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

Table 31. DSP56F801 Pin Identification by Pin Number

Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

1 TD0 13 TCS 25 RESET 37 ANA5

2TD114TCK26V

DDA 38 ANA6

3TD215TMS27V

SSA 39 ANA7

4SS

16 IREQA 28 VDD 40 PWMA0

5MISO17TDI29V

SS 41 VCAPC1

6 MOSI 18 VCAPC2 30 FAULTA0 42 VDD

7SCLK19V

SS 31 ANA0 43 VSS

8TXD020V

DD 32 ANA1 44 PWMA1

SS 21 EXTAL 33 ANA2 45 PWMA2

10 VDD 22 XTAL 34 VREF 46 PWMA3

11 RXD0 23 TDO 35 ANA3 47 PWMA4

12 DE 24 TRST 36 ANA4 48 PWMA5

Package and Pin-Out Information DSP56F801

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 37

Figure 34. 48-pin LQFP Mechanical Information

0.200 AB T-U

Z0.200 AC T-U

13 24

AE AE

T, U, Z

DETAIL Y

BASE MET AL

T-U

0.080 ZAC

SECTION AE-AE

G0.080 AC

M°

TOP & BOTTOM

L°

0.250

DETAIL AD

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE AB IS LOCATED AT BOTTOM

OF LEAD AND IS COINCIDENT WITH THE

LEAD WHER E THE LEAD EXITS THE PLASTI C

BODY AT THE BOTTOM OF THE PARTING

LINE.

4. DATUMS T , U, AND Z T O BE DETERMINED AT

DATUM PLANE AB.

5. DIMENSIONS S AND V TO BE DETERMINED

AT SEATING PLANE AC.

6. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.250 PER SIDE. DIMENSIONS

A AND B DO INCLUDE MOLD MISMA TCH AND

ARE DETERMINE D AT DATUM PLANE AB.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION

SHALL NOT CAUSE THE D DIMENSION TO

EXCEED 0.350.

8. MINIMUM SOLDER PLA TE THICKNESS

SHALL BE 0.0076.

CASE 932-03

ISSUE F

GAUGE PLANE

DIM

AMIN MAX

7.00 0 B SC

MILLIMETERS

3.50 0 B SC

7.00 0 B SC

3.50 0 B SC

1.400 1.600

0.170 0.270

1.350 1.450

0.170 0.230

0.50 0 B SC

0.050 0.150

0.090 0.200

0.500 0.700

12 REF

0.090 0.160

0.25 0 B SC

0 7

0.150 0.250

9.00 0 B SC

4.50 0 B SC

9.00 0 B SC

4.50 0 B SC

0.200 REF

1.000 REF

°°

38 DSP56F801 Prel im i nary Tech nical Data MOTOROLA

Part 5 Design Considerations

5.1 Thermal Design Considerations

An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:

Equation 1:

Where:

TA = ambient temperature °C

RθJA = package junction-to-ambient thermal resistance °C/W

PD = power dissipation in package

Histo r ic ally, th e rma l re si st anc e h as b e en e xp r esse d as the su m o f a jun ct io n-t o- c ase t h er ma l re s ist an ce and

a case-to-ambient thermal resistance:

Equation 2:

Where:

RθJA = package junction-to-ambient thermal resistance °C/W

RθJC = package junction-to-case thermal resist ance °C/W

RθCA = package case-to-ambient thermal resistance °C/W

RθJC is device-related and cannot be influenced by the user. The user controls the ther mal environment to

chang e the ca se-t o-a mbien t ther mal res ista nce, R θCA. For example, t he user can ch ange the ai r flow arou nd

the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or

otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This

model is most useful for ce ramic packa ges with heat sinks; some 90% of t he heat flow is dis sipated th rough

the case to the heat sink and out to the ambien t en vir onmen t. For ceramic pack ages , in situations wher e the

heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device

thermal performance may ne ed the additi onal modeling capability of a system level therma l simulati on tool.

The the rmal perf ormance of plast ic packa ges is more depend ent on t he temper ature o f the PCB to which the

package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the

thermal performance is adequate, a system level model m ay be appropriate.

Definitions:

A complicating factor is the existence of three common definitions for determining the junction-to-case

thermal r esistance in plasti c pack ages:

• Measure the thermal resistance from the junction to the outside surface of the package (case) closest

to the chip mounting area w hen that surface has a proper heat sink. This is done to minimize

temperature variation across the surface.

• Measure the thermal resistance from the junction to where the leads are attached to the case. This

definition is approximately equal to a junction to board thermal resistance.

TJTAPDRθJA

×()+=

RθJA RθJC RθCA

Electrical Design Considerations

MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 39

• Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package

case determined by a thermocouple.

The junction-to-case thermal resistances quoted in this data sheet are determined using the first definition

on page 45. From a practica l sta ndpoint , t hat val ue is also s uitabl e for deter mining t he junc tion t emperat ure

from a case thermocouple reading in forced convection environments. In natural convection, using the

junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the

case of th e package will est imate a juncti on temper ature slightly hotter than act ual. Hence, th e new therma l

metric, Thermal Charac terization P arameter, or ΨJT, has been defined to be (TJ – TT)/PD. This value gives

a better estimate of the junction temperature in natural convection when using the surface temperature of

the package. Remember that surface temperature readings of packages are subject to significant errors

caused by i nadequat e att achment of the sensor t o th e surface an d to erro rs caus ed by heat l oss to t he sensor.

The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the

package with thermally conductive epoxy.

5.2 Electrical Design Considerations

Use the follow ing li st of considerations to assure correct DSP op eration:

• Provide a low-imp edance pat h from the boa rd power sup ply to eac h VDD pin on the DSP, and from

the board ground to each VSS (GND) pin.

• The minimum bypass requirement is to place six 0.01–0.1 µF capacitors positioned as close as

possibl e to the package supply pins. The r ecommended bypas s configuration is to place one bypass

capacit or on each of the ten VDD/VSS pairs, inc ludin g VDDA/VSSA. The VCAP capacitor s must be

150 milliohm or less ESR capacitors.

• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and

VSS (GND) pins are less than 0.5 inch per capacitor lead.

• Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS.

• Bypass the VDD and VSS layers of the PCB with approximately 100 µF, preferably with a high-

grade capacitor such as a tantalum capacitor.

• Becaus e the DSP outp ut signals ha ve fast ri se and fal l times, PCB t race leng ths should be minimal.

• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating

capacita nce. This is especially critical in systems with higher capaci tive loads that could create

high er tran sient currents in the VDD and GND circuits.

CAUTION

This device cont ains protec ti ve circui try to guard again st

damage due to high static voltage or electrical fields.

However, normal precautions are advised to avoid

application of any voltages higher than maximum rated

voltages to this high-impedance circuit. Reliability of

operation is enhanced if unused inputs are tied to an

appropriate voltage level.

DSP56F801/D

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suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, includi ng without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including

“Typicals” must be validated for each customer appli cation by customer’s technical experts. Motorola does not convey any licens e under it s patent rights nor the

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• Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.

• Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as

development or debugging systems) should allow a means to assert TRST whenever RESET is

asserted, as well as a means to assert TRST independently of RESET. Designs that do not require

debugging functionality, such as consumer products, should tie these pins together.

• Because t he Flash memory is programmed thr ough the JTAG/OnCE port, desig ners should prov ide

an interface to this port to allow in-circuit Flash programming.

Part 6 Ordering Information

Table 32 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales

office or authorized distributor to determine availability and to order parts.

Table 32. DSP56F801 Ordering Information

Part Supply

Voltage Package Type Pin

Count Frequency

(MHz) Order Number

DSP56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack

(LQFP) 48 80 DSP56F801FA80