DSP56F801 Description
MOTOROLA DSP56F801 Prel im in ary Tech nica l Da ta 3
• Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)
• Eleven multiplexed General Purpose I/O (GPIO) pins
• Computer-Operating Properly (COP) watchdog timer
• One dedicated external interrupt pin
• Ex ternal reset pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor spee d-independent debugging
• Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core cl ock
• Oscil lator flex ibility bet ween either an external c rystal oscil lator or an on -chip rel axation oscil lator
for lower system cost and two additional GPIO lines
1.1.4 Energy Information
• Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs
• Uses a single 3.3V power supply
• On-chip reg ulato rs for d igital an d analog circuitry to lower cos t and reduc e noise
• Wait and Stop modes available
1.2 DSP56F801 Description
The DSP56F801 is a member of the DSP56800 core-based family of Digita l Signal Processors (DSPs). It
combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with
a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the DSP56F801 is well-suited for many applications.
The DSP56F801 includes many peripherals that are especially useful for applications such as motion
control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,
automotive control, engine management, noise suppression, remote utility metering, and industrial control
for power, lighting, and automation.
The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating
in parallel, allowing as many as six oper ations per instruction cycle. The microproce ssor-sty le programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The DSP56F801 su pports progr am exec ution from ei ther inte rnal or ext ernal memori es. Two dat a oper ands
can be accessed from the on-chip data RAM per instruction cycle. The DSP56F801 also provides one
external dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The DSP56F801 DSP controller includes 8K words (16-bit) of program Flash and 2K words of Data Fl ash
(each pr ogr ammabl e through the JTAG por t) wit h 1K wor ds of both program and da ta RAM. A t ota l of 2K
words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines
that can be used to program the main program and data flash memory areas. Both program and data flash
memories c an b e i ndependently bulk er ase d or er ased in page sizes of 256 words. The Bo ot Flas h memor y
can also be either bulk or page erased.
A key applic ation-specific feature of the DSP56F801 is the inclusion of a Pulse Width Modulator (PWM)
module. Thi s module s inco rpo rates si x comple mentary, indiv idual ly prog rammab le PWM sign al out puts to