UCD9090RGZT - Texas Instruments

Vmarg

Closed Loop

Margining

UCD9090

VMON

GPIO

12V

V33A

V33D

GPIO

3.3V OUT VMON

1.8V OUT

0.8V OUT

I0.8V

TEMP0.8V

VMON

I12V

TEMP12V VMON

VMON

INA196

I12V

12V OUT

3.3V OUT

12V OUT

1.8V OUT

GPIO

0.8V OUT

PWM 2MHz

INA196 I0.8V

WDI from main

processor GPIO

WDO GPIO

TEMP IC TEMP0.8V

TEMP IC TEMP12V

POWER_GOOD GPIO

WARN_OC_0.8V_

OR_12V GPIO

SYSTEM RESET GPIO

OTHER

SEQUENCER DONE

(CASCADE INPUT)

GPIO

I2C/

PMBUS

JTAG

/EN DC-DC 1

VOUT

VFB

VIN

/EN

LDO1

VOUT

VIN

/EN DC-DC 2

VOUT

VFB

VIN

3.3V

Supply

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10-Rail Power Supply Sequencer and Monitor with ACPI Support

Check for Samples: UCD9090

1FEATURES DESCRIPTION

The UCD9090 is a 10-rail PMBus/I2C addressable

2•Monitor and Sequence 10 Voltage Rails power-supply sequencer and monitor. The device

–All Rails Sampled Every 400 μsintegrates a 12-bit ADC for monitoring up to 10

–12-bit ADC With 2.5-V, 0.5% Internal VREF power-supply voltage inputs. Twenty-three GPIO pins

can be used for power supply enables, power-on

–Sequence Based on Time, Rail and Pin reset signals, external interrupts, cascading, or other

Dependencies system functions. Ten of these pins offer PWM

–Four Programmable Undervoltage and functionality. Using these pins, the UCD9090 offers

Overvoltage Thresholds per Monitor support for margining, and general-purpose PWM

•Nonvolatile Error and Peak-Value Logging per functions.

Monitor (up to 30 Fault Detail Entries) Specific power states can be achieved using the

•Closed-Loop Margining for 10 Rails Pin-Selected Rail States feature. This feature allows

with the use of up to 3 GPIs to enable and disable

–Margin Output Adjusts Rail Voltage to any rail. This is useful for implementing system

Match User-Defined Margin Thresholds low-power modes and the Advanced Configuration

•Programmable Watchdog Timer and System and Power Interface (ACPI) specification that is used

Reset for hardware devices.

•Flexible Digital I/O Configuration The TI Fusion Digital Power™designer software is

•Pin-Selected Rail States provided for device configuration. This PC-based

graphical user interface (GUI) offers an intuitive

•Multiphase PWM Clock Generator interface for configuring, storing, and monitoring all

–Clock Frequencies From 15.259 kHz to system operating parameters.

125 MHz

–Capability to Configure Independent Clock

Outputs for Synchronizing Switch-Mode

Power Supplies

•JTAG and I2C/SMBus/ PMBus™Interfaces

APPLICATIONS

•Industrial / ATE

•Telecommunications and Networking

Equipment

•Servers and Storage Systems

•Any System Requiring Sequencing and

Monitoring of Multiple Power Rails

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PMBus, Fusion Digital Power are trademarks of Texas Instruments.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Comparators

Monitor

Inputs

12-bit

200ksps,

ADC

(0.5% Int. Ref)

SEQUENCING ENGINE

BOOLEAN

Logic Builder

JTAG

GPIO

I2C/PMBus

FLASH Memory

User Data, Fault

and Peak Logging

48-pin QFN

General Purpose I/O

(GPIO)

Digital Inputs (8 max)

Digital Outputs (10 max)

Rail Enables (10 max)

Margining Outputs (10 max)

Multi-phase PWM (8 max)

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FUNCTIONAL BLOCK DIAGRAM

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see

the TI Web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1)

VALUE UNIT

Voltage applied at V33D to DVSS –0.3 to 3.8 V

Voltage applied at V33A to AVSS –0.3 to 3.8 V

Voltage applied to any other pin (2) –0.3 to (V33A + 0.3) V

Storage temperature (Tstg)–40 to 150 °C

Human-body model (HBM) 2.5 kV

ESD rating Charged-device model (CDM) 750 V

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS

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THERMAL INFORMATION UCD9090

THERMAL METRIC(1) RGZ UNITS

48 PINS

θJA Junction-to-ambient thermal resistance(2) 25

θJCtop Junction-to-case (top) thermal resistance(3) 8.9

θJB Junction-to-board thermal resistance(4) 5.5 °C/W

ψJT Junction-to-top characterization parameter(5) 0.3

ψJB Junction-to-board characterization parameter(6) 1.5

θJCbot Junction-to-case (bottom) thermal resistance(7) 1.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT

Supply voltage during operation (V33D, V33DIO, V33A) 3 3.3 3.6 V

Operating free-air temperature range, TA–40 110 °C

Junction temperature, TJ125 °C

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

SUPPLY CURRENT

IV33A VV33A = 3.3 V 8 mA

IV33DIO VV33DIO = 3.3 V 2 mA

Supply current(1)

IV33D VV33D = 3.3 V 40 mA

VV33D = 3.3 V, storing configuration parameters in

IV33D 50 mA

flash memory

ANALOG INPUTS (MON1–MON13)

VMON Input voltage range MON1–MON10 0 2.5 V

MON11 0.2 2.5 V

INL ADC integral nonlinearity –4 4 LSB

DNL ADC differential nonlinearity -2 2 LSB

Ilkg Input leakage current 3 V applied to pin 100 nA

IOFFSET Input offset current 1-kΩsource impedance –5 5 μA

MON1–MON10, ground reference 8 MΩ

RIN Input impedance MON11, ground reference 0.5 1.5 3 MΩ

CIN Input capacitance 10 pF

tCONVERT ADC sample period 12 voltages sampled, 3.89 μsec/sample 400 μsec

ADC 2.5 V, internal reference accuracy 0°C to 125°C–0.5 0.5 %

VREF –40°C to 125°C–1 1 %

ANALOG INPUT (PMBUS_ADDRx)

IBIAS Bias current for PMBus Addr pins 9 11 μA

(1) Typical supply current values are based on device programmed but not configured, and no peripherals connected to any pins.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

VADDR_OPEN Voltage –open pin PMBUS_ADDR0, PMBUS_ADDR1 open 2.26 V

VADDR_SHORT Voltage –shorted pin PMBUS_ADDR0, PMBUS_ADDR1 short to ground 0.124 V

DIGITAL INPUTS AND OUTPUTS

VOL Low-level output voltage IOL = 6 mA(2), V33DIO = 3 V Dgnd + V

0.25

VOH High-level output voltage IOH =–6 mA(3), V33DIO = 3 V V33DIO V

–0.6

VIH High-level input voltage V33DIO = 3 V 2.1 3.6 V

VIL Low-level input voltage V33DIO = 3.5 V 1.4 V

MARGINING OUTPUTS

TPWM_FREQ MARGINING-PWM frequency FPWM1-8 15.260 125000 kHz

PWM1-2 0.001 7800

DUTYPWM MARGINING-PWM duty cycle range 0 100 %

SYSTEM PERFORMANCE

VDDSlew Minimum VDD slew rate VDD slew rate between 2.3 V and 2.9 V 0.25 V/ms

Supply voltage at which device comes

VRESET For power-on reset (POR) 2.4 V

out of reset

tRESET Low-pulse duration needed at RESET pin To reset device during normal operation 2 μS

f(PCLK) Internal oscillator frequency TA= 125°C, TA= 25°C 240 250 260 MHz

tretention Retention of configuration parameters TJ= 25°C 100 Years

Write_Cycles Number of nonvolatile erase/write cycles TJ= 25°C 20 K cycles

(2) The maximum total current, IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.

(3) The maximum total current, IOHmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.

Start Stop

Clk ACK Clk ACK

PMB_Clk

PMB_Data

TLOW:SEXT

TLOW:MEXT TLOW:MEXT TLOW:MEXT

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PMBus/SMBus/I2C

The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and

PMBus is shown below.

I2C/SMBus/PMBus TIMING REQUIREMENTS

TA=–40°C to 85°C, 3 V <VDD <3.6 V; typical values at TA= 25°C and VCC = 2.5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

FSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty cycle 10 400 kHz

FI2C I2C operating frequency Slave mode, SCL 50% duty cycle 10 400 kHz

t(BUF) Bus free time between start and stop 4.7 μs

t(HD:STA) Hold time after (repeated) start 0.26 μs

t(SU:STA) Repeated-start setup time 0.26 μs

t(SU:STO) Stop setup time 0.26 μs

t(HD:DAT) Data hold time Receive mode 0 ns

t(SU:DAT) Data setup time 50 ns

t(TIMEOUT) Error signal/detect See(1) 35 ms

t(LOW) Clock low period 0.5 μs

t(HIGH) Clock high period See (2) 0.26 50 μs

t(LOW:SEXT) Cumulative clock low slave extend time See (3) 25 ms

tfClock/data fall time See (4) 120 ns

trClock/data rise time See (5) 120 ns

(1) The device times out when any clock low exceeds t(TIMEOUT).

(2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t >50 ms causes reset of any transaction that is in progress. This

specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).

(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(4) Fall time tf= 0.9 VDD to (VILMAX –0.15)

(5) Rise time tr= (VILMAX –0.15) to (VIHMIN + 0.15)

Figure 1. I2C/SMBus Timing Diagram

Figure 2. Bus Timing in Extended Mode

MON9

MON8

UCD9090

GPIO1

MON3

GPIO3

PMBUS_CLK

FPWM1/GPIO5

GPIO4

PMBUS_DATA

FPWM2/GPIO6

FPWM3/GPIO7

TCK/GPIO18

FPWM4/GPIO8

FWPM5/GPIO9

FPWM6/GPIO10

PMBUS_CNTRL

GPIO14

PMBUS_ALERT

GPIO17

DVSS

MON10

TMS/GPIO21

TDI/GPIO20

TDO/GPIO19

PWM2/GPI2

PWM1/GPI1

V33D

AVSS2

MON4

PMBUS_ADDR0

RESET

MON6

GPIO2

FPWM7/GPIO11

PMBUS_ADDR1

BPCAP

MON7

V33A

GPIO15

GPIO16

MON5

MON2

MON1

MON11

AVSS1

FPWM8/GPIO12

GPIO13

TRST

PMBUS_CLK

PMBUS_DATA

PMBUS_ALERT

PMBUS_CNTRL

PMBUS_ADDR0

PMBUS_ADDR1

DVSS

V33D

V33A

BPCAP

AVSS1

AVSS2

RESET 3

UCD9090

PWM1/GPI1

PWM2/GPI2

TRST 31

TCK/GPIO18 27

TDO/GPIO19 28

TDI/GPIO20 29

TMS/GPIO21 30

GPIO1 4

GPIO2 5

GPIO3 6

GPIO4 7

GPIO13 18

GPIO16 25

GPIO17 26

GPIO14 21

GPIO15 24

FPWM1/GPIO5 10

FPWM2/GPIO6 11

FPWM3/GPIO7 12

FPWM4/GPIO8 13

FPWM5/GPIO9 14

FPWM6/GPIO10 15

FPWM7/GPIO11 16

FPWM8/GPIO12 17

MON1

MON2

MON3

MON4

MON5

MON6

MON7

MON8

MON9

MON10

MON11

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DEVICE INFORMATION

Figure 3. UCD9090 PIN ASSIGNMENT

Table 1. PIN FUNCTIONS

PIN NAME PIN NO. I/O TYPE DESCRIPTION

ANALOG MONITOR INPUTS

MON1 1 I Analog input (0 V–2.5 V)

MON2 2 I Analog input (0 V–2.5 V)

MON3 38 I Analog input (0 V–2.5 V)

MON4 39 I Analog input (0 V–2.5 V)

MON5 40 I Analog input (0 V–2.5 V)

MON6 41 I Analog input (0 V–2.5 V)

MON7 42 I Analog input (0 V–2.5 V)

MON8 45 I Analog input (0 V–2.5 V)

MON9 46 I Analog input (0 V–2.5 V)

MON10 48 I Analog input (0 V–2.5 V)

MON11 37 I Analog input (0.2 V–2.5 V)

GPIO

GPIO1 4 I/O General-purpose discrete I/O

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Table 1. PIN FUNCTIONS (continued)

PIN NAME PIN NO. I/O TYPE DESCRIPTION

GPIO2 5 I/O General-purpose discrete I/O

GPIO3 6 I/O General-purpose discrete I/O

GPIO4 7 I/O General-purpose discrete I/O

GPIO13 18 I/O General-purpose discrete I/O

GPIO14 21 I/O General-purpose discrete I/O

GPIO15 24 I/O General-purpose discrete I/O

GPIO16 25 I/O General-purpose discrete I/O

GPIO17 26 I/O General-purpose discrete I/O

PWM OUTPUTS

FPWM1/GPIO5 10 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO

FPWM2/GPIO6 11 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO

FPWM3/GPIO7 12 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO

FPWM4/GPIO8 13 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO

FPWM5/GPIO9 14 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO

FPWM6/GPIO10 15 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO

FPWM7/GPIO11 16 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO

FPWM8/GPIO12 17 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO

PWM1/GPI1 22 I/PWM PWM (0.93 Hz to 7.8125 MHz) or GPI

PWM2/GPI2 23 I/PWM PWM (0.93 Hz to 7.8125 MHz) or GPI

PMBus COMM INTERFACE

PMBUS_CLK 8 I/O PMBus clock (must have pullup to 3.3 V)

PMBUS_DATA 9 I/O PMBus data (must have pullup to 3.3 V)

PMBUS_ALERT 19 O PMBus alert, active-low, open-drain output (must have pullup to 3.3 V)

PMBUS_CNTRL 20 I PMBus control

PMBUS_ADDR0 44 I PMBus analog address input. Least-significant address bit

PMBUS_ADDR1 43 I PMBus analog address input. Most-significant address bit

JTAG

TCK/GPIO18 27 I/O Test clock or GPIO

TDO/GPIO19 28 I/O Test data out or GPIO

TDI/GPIO20 29 I/O Test data in (tie to Vdd with 10-kΩresistor) or GPIO

TMS/GPIO21 30 I/O Test mode select (tie to Vdd with 10-kΩresistor) or GPIO

TRST 31 I Test reset –tie to ground with 10-kΩresistor

INPUT POWER AND GROUNDS

RESET 3 Active-low device reset input. Hold low for at least 2 μs to reset the device.

V33A 34 Analog 3.3-V supply. Refer to the Layout Guidelines section.

V33D 33 Digital core 3.3-V supply. Refer to the Layout Guidelines section.

BPCap 35 1.8-V bypass capacitor. Refer to the Layout Guidelines section.

AVSS1 36 Analog ground

AVSS2 47 Analog ground

DVSS 32 Digital ground

QFP ground pad NA Thermal pad –tie to ground plane.

FUNCTIONAL DESCRIPTION

TI FUSION GUI

The Texas Instruments Fusion Digital Power Designer is provided for device configuration. This PC-based

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graphical user interface (GUI) offers an intuitive I2C/PMBus interface to the device. It allows the design engineer

to configure the system operating parameters for the application without directly using PMBus commands, store

the configuration to on-chip nonvolatile memory, and observe system status (voltage, etc). Fusion Digital Power

Designer is referenced throughout the data sheet as Fusion GUI and many sections include screenshots. The

Fusion GUI can be downloaded from www.ti.com.

PMBUS INTERFACE

The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus

interface that is built on the I2C physical specification. The UCD9090 supports revision 1.1 of the PMBus

standard. Wherever possible, standard PMBus commands are used to support the function of the device. For

unique features of the UCD9090, MFR_SPECIFIC commands are defined to configure or activate those features.

These commands are defined in the UCD90xxx Sequencer and System Health Controller PMBUS Command

Reference (SLVU352). The most current UCD90xxx PMBus™Command Reference can be found within the TI

Fusion Digital Power Designer software via the Help Menu (Help, Documentation &Help Center, Sequencers

tab, Documentation section).

This document makes frequent mention of the PMBus specification. Specifically, this document is PMBus Power

System Management Protocol Specification Part II –Command Language, Revision 1.1, dated 5 February 2007.

The specification is published by the Power Management Bus Implementers Forum and is available from

www.pmbus.org.

The UCD9090 is PMBus compliant, in accordance with the Compliance section of the PMBus specification. The

firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT function.

The hardware can support either 100-kHz or 400-kHz PMBus operation.

THEORY OF OPERATION

Modern electronic systems often use numerous microcontrollers, DSPs, FPGAs, and ASICs. Each device can

have multiple supply voltages to power the core processor, analog-to-digital converter or I/O. These devices are

typically sensitive to the order and timing of how the voltages are sequenced on and off. The UCD9090 can

sequence supply voltages to prevent malfunctions, intermittent operation, or device damage caused by improper

power up or power down. Appropriate handling of under- and overvoltage faults can extend system life and

improve long term reliability. The UCD9090 stores power supply faults to on-chip nonvolatile flash memory for aid

in system failure analysis.

System reliability can be improved through four-corner testing during system verification. During four-corner

testing, the system is operated at the minimum and maximum expected ambient temperature and with each

power supply set to the minimum and maximum output voltage, commonly referred to as margining. The

UCD9090 can be used to implement accurate closed-loop margining of up to 10 power supplies.

The UCD9090 10-rail sequencer can be used in a PMBus- or pin-based control environment. The TI Fusion GUI

provides a powerful but simple interface for configuring sequencing solutions for systems with between one and

10 power supplies using 10 analog voltage-monitor inputs, two GPIs and 21 highly configurable GPIOs. A rail

includes voltage, a power-supply enable and a margining output. At least one must be included in a rail

definition. Once the user has defined how the power-supply rails should operate in a particular system, analog

input pins and GPIOs can be selected to monitor and enable each supply (Figure 4).

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Figure 4. Fusion GUI Pin-Assignment Tab

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After the pins have been configured, other key monitoring and sequencing criteria are selected for each rail from

the Vout Config tab (Figure 5):

•Nominal operating voltage (Vout)

•Undervoltage (UV) and overvoltage (OV) warning and fault limits

•Margin-low and margin-high values

•Power-good on and power-good off limits

•PMBus or pin-based sequencing control (On/Off Config)

•Rails and GPIs for Sequence On dependencies

•Rails and GPIs for Sequence Off dependencies

•Turn-on and turn-off delay timing

•Maximum time allowed for a rail to reach POWER_GOOD_ON or POWER_GOOD_OFF after being enabled

or disabled

•Other rails to turn off in case of a fault on a rail (fault-shutdown slaves)

Figure 5. Fusion GUI VOUT-Config Tab

The Synchronize margins/limits/PG to Vout checkbox is an easy way to change the nominal operating voltage

of a rail and also update all of the other limits associated with that rail according to the percentages shown to the

right of each entry.

The plot in the upper left section of Figure 5 shows a simulation of the overall sequence-on and sequence-off

configuration, including the nominal voltage, the turnon and turnoff delay times, the power-good on and

power-good off voltages and any timing dependencies between the rails.

After a rail voltage has reached its POWER_GOOD_ON voltage and is considered to be in regulation, it is

compared against two UV and two OV thresholds in order to determine if a warning or fault limit has been

exceeded. If a fault is detected, the UCD9090 responds based on a variety of flexible, user-configured options.

Faults can cause rails to restart, shut down immediately, sequence off using turnoff delay times or shut down a

group of rails and sequence them back on. Different types of faults can result in different responses.

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Fault responses, along with a number of other parameters including user-specific manufacturing information and

external scaling and offset values, are selected in the different tabs within the Configure function of the Fusion

GUI. Once the configuration satisfies the user requirements, it can be written to device SRAM if Fusion GUI is

connected to a UCD9090 using an I2C/PMBus. SRAM contents can then be stored to data flash memory so that

the configuration remains in the device after a reset or power cycle.

The Fusion GUI Monitor page has a number of options, including a device dashboard and a system dashboard,

for viewing and controlling device and system status.

Figure 6. Fusion GUI Monitor Page

The UCD9090 also has status registers for each rail and the capability to log faults to flash memory for use in

system troubleshooting. This is helpful in the event of a power-supply or system failure. The status registers

(Figure 7) and the fault log (Figure 8) are available in the Fusion GUI. See the UCD90xxx Sequencer and

System Health Controller PMBus Command Reference (SLVU352) and the PMBus Specification for detailed

descriptions of each status register and supported PMBus commands.

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Figure 7. Fusion GUI Rail-Status Register

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Figure 8. Fusion GUI Flash-Error Log (Logged Faults)

POWER-SUPPLY SEQUENCING

The UCD9090 can control the turn-on and turn-off sequencing of up to 10 voltage rails by using a GPIO to set a

power-supply enable pin high or low. In PMBus-based designs, the system PMBus master can initiate a

sequence-on event by asserting the PMBUS_CNTRL pin or by sending the OPERATION command over the I2C

serial bus. In pin-based designs, the PMBUS_CNTRL pin can also be used to sequence-on and sequence-off.

The auto-enable setting ignores the OPERATION command and the PMBUS_CNTRL pin. Sequence-on is

started at power up after any dependencies and time delays are met for each rail. A rail is considered to be on or

within regulation when the measured voltage for that rail crosses the power-good on (POWER_GOOD_ON(1))

(1) In this document, configuration parameters such as Power Good On are referred to using Fusion GUI names. The UCD90xxx

Sequencer and System Health Controller PMBus Command Reference name is shown in parentheses (POWER_GOOD_ON) the first

time the parameter appears.

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limit. The rail is still in regulation until the voltage drops below power-good off (POWER_GOOD_OFF). In the

case that there isn't voltage monitoring set for a given rail, that rail is considered ON if it is commanded on (either

by OPERATION command, PMBUS CNTRL pin, or auto-enable) and (TON_DELAY +

TON_MAX_FAULT_LIMIT) time passes. Also, a rail is considered OFF if that rail is commanded OFF and

(TOFF_DELAY + TOFF_MAX_WARN_LIMIT) time passes

PMBUS_CNTRL PIN

RAIL 1 EN

RAIL 1 VOLTAGE

RAIL 2 EN

RAIL 2 VOLTAGE

POWER_GOOD_ON[1]

TON_DELAY[2]

Rail 1 and Rail 2 are both sequenced “ON”

and “OFF” by the PMBUS_CNTRL pin

only

Rail 2 has Rail 1 as an “ON” dependency

Rail 1 has Rail 2 as an “OFF” dependency

TON_DELAY[1]

TON_MAX_FAULT_LIMIT[2]

TOFF_DELAY[1]

POWER_GOOD_OFF[1]

TOFF_DELAY[2]

TOFF_MAX_WARN_LIMIT[2]

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Turn-on Sequencing

The following sequence-on options are supported for each rail:

•Monitor only –do not sequence-on

•Fixed delay time (TON_DELAY) after an OPERATION command to turn on

•Fixed delay time after assertion of the PMBUS_CNTRL pin

•Fixed time after one or a group of parent rails achieves regulation (POWER_GOOD_ON)

•Fixed time after a designated GPI has reached a user-specified state

•Any combination of the previous options

The maximum TON_DELAY time is 3276 ms.

Turn-off Sequencing

The following sequence-off options are supported for each rail:

•Monitor only –do not sequence-off

•Fixed delay time (TOFF_DELAY) after an OPERATION command to turn off

•Fixed delay time after deassertion of the PMBUS_CNTRL pin

•Fixed time after one or a group of parent rails drop below regulation (POWER_GOOD_OFF)

•Fixed delay time in response to an undervoltage, overvoltage, or max turn-on fault on the rail

•Fixed delay time in response to a fault on a different rail when set as a fault shutdown slave to the faulted rail

•Fixed delay time in response to a GPI reaching a user-specified state

•Any combination of the previous options

The maximum TOFF_DELAY time is 3276 ms.

Figure 9. Sequence-on and Sequence-off Timing

Sequencing Configuration Options

In addition to the turn-on and turn-off sequencing options, the time between when a rail is enabled and when the

monitored rail voltage must reach its power-good-on setting can be configured using max turn-on

(TON_MAX_FAULT_LIMIT). Max turn-on can be set in 1-ms increments. A value of 0 ms means that there is no

limit and the device can try to turn on the output voltage indefinitely.

Rails can be configured to turn off immediately or to sequence-off according to rail and GPI dependencies, and

user-defined delay times. A sequenced shutdown is configured by selecting the appropriate rail and GPI

dependencies, and turn-off delay (TOFF_DELAY) times for each rail. The turn-off delay times begin when the

PMBUS_CNTRL pin is deasserted, when the PMBus OPERATION command is used to give a soft-stop

command, or when a fault occurs on a rail that has other rails set as fault-shutdown slaves.

Shutdowns on one rail can initiate shutdowns of other rails or controllers. In systems with multiple UCD9090s, it

is possible for each controller to be both a master and a slave to another controller.

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PIN SELECTED RAIL STATES

This feature allows with the use of up to 3 GPIs to enable and disable any rail. This is useful for implementing

system low-power modes and the Advanced Configuration and Power Interface (ACPI) specification that is used

for operating system directed power management in servers and PCs. In up to 8 system states, the power

system designer can define which rails are on and which rails are off. If a new state is presented on the input

pins, and a rail is required to change state, it will do so with regard to its sequence-on or sequence-off

dependencies.

The OPERATION command is modified when this function causes a rail to change its state. This means that the

ON_OFF_CONFIG for a given rail must be set to use the OPERATION command for this function to have any

effect on the rail state. The first 3 pins configured with the GPI_CONFIG command are used to select 1 of 8

system states. Whenever the device is reset, these pins are sampled and the system state, if enabled, will be

used to update each rail state. When selecting a new system state, changes to the status of the GPIs must not

take longer than 1 microsecond. See the UCD90xxx Sequencer and System Health Controller PMBus Command

Reference for complete configuration settings of PIN_SELECTED_RAIL_STATES.

Table 2. GPI Selection of System States

System

GPI 2 State GPI 1 State GPI 0 State State

NOT Asserted NOT Asserted NOT Asserted 0

NOT Asserted NOT Asserted Asserted 1

NOT Asserted Asserted NOT Asserted 2

NOT Asserted Asserted Asserted 3

Asserted NOT Asserted NOT Asserted 4

Asserted NOT Asserted Asserted 5

Asserted Asserted NOT Asserted 6

Asserted Asserted Asserted 7

MONITORING

The UCD9090 has 11 monitor input pins (MONx) that are multiplexed into a 2.5V referenced 12-bit ADC. The

monitor pins can be configured so that they can measure voltage signals to report voltage, current and

temperature type measurements. A single rail can include all three measurement types, each monitored on

separate MON pins. If a rail has both voltage and current assigned to it, then the user can calculate power for the

rail. Digital filtering applied to each MON input depends on the type of signal. Voltage inputs have no filtering.

Current and temperature inputs have a low-pass filter.

Although the monitor results can be reported with a resolution of about 15 μV, the real conversion resolution of

610 μV is fixed by the 2.5-V reference and the 12-bit ADC.

Table 3. Voltage Range and Resolution

VOLTAGE RANGE RESOLUTION

(Volts) (millivolts)

0 to 127.99609 3.90625

0 to 63.99805 1.95313

0 to 31.99902 0.97656

0 to 15.99951 0.48824

0 to 7.99976 0.24414

0 to 3.99988 0.12207

0 to 1.99994 0.06104

0 to 0.99997 0.03052

VOLTAGE MONITORING

Up to 12 voltages can be monitored using the analog input pins. The input voltage range is 0 V–2.5 V for all

MONx inputs except MON11 (pin 37) which has a range of 0.2V–2.5V. Any voltage between 0 V and 0.2 V on

these pins is read as 0.2 V. External resistors can be used to attenuate voltages higher than 2.5 V.

Analog

Inputs

(12)

Internal

2.5Vref

0.5%

Fast Digital

Comparators

MON1 – MON6

MON1

MON2

MON13

12-bit

SAR ADC

200ksps

MON1 – MON13

Glitch

Filter

UCD9090

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SLVSA30A –APRIL 2011–REVISED AUGUST 2011

The ADC operates continuously, requiring 3.89 μs to convert a single analog input and 46.7 μs to convert all 12

of the analog inputs. Each rail is sampled by the sequencing and monitoring algorithm every 400 μs. The

maximum source impedance of any sampled voltage should be less than 4 kΩ. The source impedance limit is

particularly important when a resistor-divider network is used to lower the voltage applied to the analog input

pins.

MON1 - MON6 can be configured using digital hardware comparators, which can be used to achieve faster fault

responses. Each hardware comparator has four thresholds (two UV (Fault and Warning) and two OV (Fault and

Warning)). The hardware comparators respond to UV or OV conditions in about 80 μs (faster than 400 µs for the

ADC inputs) and can be used to disable rails or assert GPOs. The only fault response available for the hardware

comparators is to shut down immediately.

An internal 2.5-V reference is used by the ADC. The ADC reference has a tolerance of ±0.5% between 0°C and

125°C and a tolerance of ±1% between –40°C and 125°C. An external voltage divider is required for monitoring

voltages higher than 2.5 V. The nominal rail voltage and the external scale factor can be entered into the Fusion

GUI and are used to report the actual voltage being monitored instead of the ADC input voltage. The nominal

voltage is used to set the range and precision of the reported voltage according to Table 3.

Figure 10. Voltage Monitoring Block Diagram

Although the monitor results can be reported with a resolution of about 15 μV, the real conversion resolution of

610 μV is fixed by the 2.5-V reference and the 12-bit ADC.

CURRENT MONITORING

Current can be monitored using the analog inputs. External circuitry, see Figure 11, must be used in order to

convert the current to a voltage within the range of the UCD9090 MONx input being used.

If a monitor input is configured as a current, the measurements are smoothed by a sliding-average digital filter.

The current for 1 rail is measured every 200μs. If the device is programmed to support 10 rails (independent of

current not being monitored at all rails), then each rail's current will get measured every 2ms. The current

calculation is done with a sliding average using the last 4 measurements. The filter reduces the probability of

false fault detections, and introduces a small delay to the current reading. If a rail is defined with a voltage

monitor and a current monitor, then monitoring for undercurrent warnings begins once the rail voltage reaches

POWER_GOOD_ON. If the rail does not have a voltage monitor, then current monitoring begins after

TON_DELAY.

The device supports multiple PMBus commands related to current, including READ_IOUT, which reads external

currents from the MON pins; IOUT_OC_FAULT_LIMIT, which sets the overcurrent fault limit;

IOUT_OC_WARN_LIMIT, which sets the overcurrent warning limit; and IOUT_UC_FAULT_LIMIT, which sets the

undercurrent fault limit. The UCD90xxx Sequencer and System Health Controller PMBus Command Reference

contains a detailed description of how current fault responses are implemented using PMBus commands.

IOUT_CAL_GAIN is a PMBus command that allows the scale factor of an external current sensor and any

amplifiers or attenuators between the current sensor and the MON pin to be entered by the user in milliohms.

IOUT_CAL_OFFSET is the current that results in 0 V at the MON pin. The combination of these PMBus

commands allows current to be reported in amperes. The example below using the INA196 would require

programming IOUT_CAL_GAIN to Rsense(mΩ)×20.

VOUT

GND

V+

Vin-

Vin+

Current Path

Rsense

INA196

3.3V

MONx

AVSS1

UCD9090

Gain = 20V/V

UCD9090

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Figure 11. Current Monitoring Circuit Example using the INA196

REMOTE TEMPERATURE MONITORING AND INTERNAL TEMPERATURE SENSOR

The UCD9090 has support for internal and remote temperature sensing. The internal temperature sensor

requires no calibration and can report the device temperature via the PMBus interface. The remote temperature

sensor can report the remote temperature by using a configurable gain and offset for the type of sensor that is

used in the application such as a linear temperature sensor (LTS) connected to the analog inputs.

External circuitry must be used in order to convert the temperature to a voltage within the range of the UCD9090

MONx input being used.

If an input is configured as a temperature, the measurements are smoothed by a sliding average digital filter. The

temperature for 1 rail is measured every 100ms. If the device is programmed to support 10 rails (independent of

temperature not being monitored at all rails), then each rail's temperature will get measured every 1s. The

temperature calculation is done with a sliding average using the last 16 measurements. The filter reduces the

probability of false fault detections, and introduces a small delay to the temperature reading. The internal device

temperature is measured using a silicon diode sensor with an accuracy of ±5°C and is also monitored using the

ADC. Temperature monitoring begins immediately after reset and initialization.

The device supports multiple PMBus commands related to temperature, including READ_TEMPERATURE_1,

which reads the internal temperature; READ_TEMPERATURE_2, which reads external temperatures; and

OT_FAULT_LIMIT and OT_WARN_LIMIT, which set the overtemperature fault and warning limit. The UCD90xxx

Sequencer and System Health Controller PMBus Command Reference contains a detailed description of how

temperature-fault responses are implemented using PMBus commands.

TEMPERATURE_CAL_GAIN is a PMBus command that allows the scale factor of an external temperature

sensor and any amplifiers or attenuators between the temperature sensor and the MON pin to be entered by the

user in °C/V. TEMPERATURE_CAL_OFFSET is the temperature that results in 0 V at the MON pin. The

combination of these PMBus commands allows temperature to be reported in degrees Celsius.

VOUT

GND

V+

TMP20

3.3V

MONx

AVSS1

UCD9090

Vout = -11.67mV/°C x T + 1.8583

at -40°C < T < 85°C

REMOTE

TEMP

SENSOR

HOST READ_TEMPERATURE_2

I2C or SPI I2C

Faults and

Warnings

Logged Peak

Temperatures

Boolean Logic

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SLVSA30A –APRIL 2011–REVISED AUGUST 2011

Figure 12. Remote Temperature Monitoring Circuit Example using the TMP20

TEPERATURE BY HOST INPUT

If the host system has the option of not using the temperature-sensing capability of the UCD9090, it can still

provide the desired temperature to the UCD9090 through PMBus. The host may have temperature

measurements available through I2C or SPI interfaced temperature sensors. The UCD9090 would use the

temperature given by the host in place of an external temperature measurement for a given rail. The temperature

provided by the host would still be used for detecting overtemperature warnings or faults, logging peak

temperatures, input to Boolean logic-builder functions, and feedback for the fan-control algorithms. To write a

temperature associated with a rail, the PMBus command used is the READ_TEMPERATURE_2 command. If the

host writes that command, the value written will be used as the temperature until another value is written. This is

true whether a monitor pin was assigned to the temperature or not. When there is a monitor pin associated with

the temperature, once READ_TEMPERATURE_2 is written, the monitor pin is not used again until the part is

reset. When there is not a monitor pin associated with the temperature, the internal temperature sensor is used

for the temperature until the READ_TEMPERATURE_2 command is written.

Figure 13. Temperature Provided by Host

PMBUS_CNTRL PIN

RAIL 1 EN

RAIL 1 VOLTAGE

RAIL 2 EN

RAIL 2 VOLTAGE

POWER_GOOD_ON[1]

TON_DELAY [2]

TOFF_DELAY [1]

TOFF_DELAY [2]

Rail 1 andRail 2 arebothsequenced “ON” and

“OFF” bythePMBUS_CNTRL pinonly

Rail 2 hasRail 1 asan “ON” dependency

Rail 1 hasRail 2 asaFaultShutdownSlave

TON_DELAY [1]

VOUT_OV_FAULT _LIMIT

VOUT_UV_FAULT _LIMIT

MAX_GLITCH_TIME

TIMEBETWEEN

RESTARTS

MAX_GLITCH_TIME +

TOFF_DELAY[1]

MAX_GLITCH_TIME

TIMEBETWEEN

RESTARTS

Rail 1 issettousetheglitchfilterforUVorOVevents

Rail 1 issettoRESTART 3 timesafteraUVorOVevent

Rail 1 issettoshutdownwithdelayforaOVevent

TIMEBETWEEN

RESTARTS

MAX_GLITCH_TIME +

TOFF_DELAY[1] MAX_GLITCH_TIME TOFF_DELAY[1]

PMBUS_CNTRL PIN

RAIL 1 EN

RAIL 1 VOLTAGE

TON_MAX_FAULT_LIMIT[1]

RAIL 2 EN

RAIL 2 VOLTAGE

POWER_GOOD_ON[1]

TON_DELAY[2]

TON_DELAY[1]

TON_MAX_FAULT_LIMIT[1]

POWER_GOOD_ON[1]

TimeBetweenRestarts

Rail1andRail2arebothsequenced

“ON” and “OFF” bythePMBUS_CNTRL

pinonly

Rail2hasRail1asan “ON” dependency

Rail1issettoshutdownimmediately

andRESTART 1timeincaseofa Time

OnMaxfault

UCD9090

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FAULT RESPONSES AND ALERT PROCESSING

Device monitors that the rail stays within a window of normal operation. There are two programmable warning

levels (under and over) and two programmable fault levels (under and over). When any monitored voltage goes

outside of the warning or fault window, the PMBALERT# pin is asserted immediately, and the appropriate bits are

set in the PMBus status registers (see Figure 7). Detailed descriptions of the status registers are provided in the

UCD90xxx Sequencer and System Health Controller PMBus Command Reference and the PMBus Specification.

A programmable glitch filter can be enabled or disabled for each MON input. A glitch filter for an input defined as

a voltage can be set between 0 and 102 ms with 400-μs resolution.

Fault-response decisions are based on results from the 12-bit ADC. The device cycles through the ADC results

and compares them against the programmed limits. The time to respond to an individual event is determined by

when the event occurs within the ADC conversion cycle and the selected fault response.

Figure 14. Sequencing and Fault-Response Timing

Figure 15. Maximum Turn-on Fault

The configurable fault limits are:

TON_MAX_FAULT –Flagged if a rail that is enabled does not reach the POWER_GOOD_ON limit within the

configured time

VOUT_UV_WARN –Flagged if a voltage rail drops below the specified UV warning limit after reaching the

POWER_GOOD_ON setting

VOUT_UV_FAULT –Flagged if a rail drops below the specified UV fault limit after reaching the

POWER_GOOD_ON setting

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VOUT_OV_WARN –Flagged if a rail exceeds the specified OV warning limit at any time during startup or

operation

VOUT_OV_FAULT –Flagged if a rail exceeds the specified OV fault limit at any time during startup or operation

MAX_TOFF_WARN –Flagged if a rail that is commanded to shut down does not reach 12.5% of the nominal rail

voltage within the configured time

Faults are more serious than warnings. The PMBALERT# pin is always asserted immediately if a warning or fault

occurs. If a warning occurs, the following takes place:

Warning Actions

—Immediately assert the PMBALERT# pin

—Status bit is flagged

—Assert a GPIO pin (optional)

—Warnings are not logged to flash

A number of fault response options can be chosen from:

Fault Responses

—Continue Without Interruption: Flag the fault and take no action

—Shut Down Immediately: Shut down the faulted rail immediately and restart according to the rail

configuration

—Shut Down using TOFF_DELAY: If a fault occurs on a rail, exhaust whatever retries are

configured. If the rail does not come back, schedule the shutdown of this rail and all

fault-shutdown slaves. All selected rails, including the faulty rail, are sequenced off according to

their sequence-off dependencies and T_OFF_DELAY times. If Do Not Restart is selected, then

sequence off all selected rails when the fault is detected.

Restart

—Do Not Restart: Do not attempt to restart a faulted rail after it has been shut down.

—Restart Up To N Times: Attempt to restart a faulted rail up to 14 times after it has been shut down.

The time between restarts is measured between when the rail enable pin is deasserted (after any

glitch filtering and turn-off delay times, if configured to observe them) and then reasserted. It can

be set between 0 and 1275 ms in 5-ms increments.

—Restart Continuously: Same as Restart Up To N Times except that the device continues to restart

until the fault goes away, it is commanded off by the specified combination of PMBus

OPERATION command and PMBUS_CNTRL pin status, the device is reset, or power is removed

from the device.

—Shut Down Rails and Sequence On (Re-sequence): Shut down selected rails immediately or after

continue-operation time is reached and then sequence-on those rails using sequence-on

dependencies and T_ON_DELAY times.

SHUT DOWN ALL RAILS AND SEQUENCE ON (RESEQUENCE)

In response to a fault, or a RESEQUENCE command, the UCD9090 can be configured to turn off a set of rails

and then sequence them back on. To sequence all rails in the system, then all rails must be selected as

fault-shutdown slaves of the faulted rail. The rails designated as fault-shutdown slaves will do soft shutdowns

regardless of whether the faulted rail is set to stop immediately or stop with delay. Shut-down-all-rails and

sequence-on are not performed until retries are exhausted for a given fault.

While waiting for the rails to turn off, an error is reported if any of the rails reaches its TOFF_MAX_WARN_LIMIT.

There is a configurable option to continue with the resequencing operation if this occurs. After the faulted rail and

UCD9090

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fault-shutdown slaves sequence-off, the UCD9090 waits for a programmable delay time between 0 and 1275 ms

in increments of 5 ms and then sequences-on the faulted rail and fault-shutdown slaves according to the start-up

sequence configuration. This is repeated until the faulted rail and fault-shutdown slaves successfully achieve

regulation or for a user-selected 1, 2, 3, 4 or unlimited times. If the resequence operation is successful, the

resequence counter is reset if all of the rails that were resequenced maintain normal operation for one second.

Once shut-down-all-rails and sequence-on begin, any faults on the fault-shutdown slave rails are ignored. If there

are two or more simultaneous faults with different fault-shutdown slaves, the more conservative action is taken.

For example, if a set of rails is already on its second resequence and the device is configured to resequence

three times, and another set of rails enters the resequence state, that second set of rails is only resequenced

once. Another example –if one set of rails is waiting for all of its rails to shut down so that it can resequence,

and another set of rails enters the resequence state, the device now waits for all rails from both sets to shut

down before resequencing.

GPIOs

The UCD9090 has 21 GPIO pins that can function as either inputs or outputs. Each GPIO has configurable

output mode options including open-drain or push-pull outputs that can be actively driven to 3.3 V or ground.

There are an additional two pins that can be used as either inputs or PWM outputs but not as GPOs. Table 4

lists possible uses for the GPIO pins and the maximum number of each type for each use. GPIO pins can be

dependents in sequencing and alarm processing. They can also be used for system-level functions such as

external interrupts, power-goods, resets, or for the cascading of multiple devices. GPOs can be sequenced up or

down by configuring a rail without a MON pin but with a GPIO set as an enable.

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Table 4. GPIO Pin Configuration Options

PIN NAME PIN RAIL EN GPI GPO PWM OUT MARGIN PWM

(10 MAX) (8 MAX) (10 MAX) (10 MAX) (10 MAX)

FPWM1/GPIO5 11 X X X X X

FPWM2/GPIO6 12 X X X X X

FPWM3/GPIO7 13 X X X X X

FPWM4/GPIO8 14 X X X X X

FPWM5/GPIO9 15 X X X X X

FPWM6/GPIO10 16 X X X X X

FPWM7/GPIO11 17 X X X X X

FPWM8/GPIO12 18 X X X X X

GPI1/PWM1 24 X X X

GPI2/PWM2 25 X X X

GPIO1 5 X X X

GPIO2 6 X X X

GPIO3 7 X X X

GPIO4 8 X X X

GPIO13 19 X X X

GPIO14 22 X X X

GPIO15 23 X X X

GPIO16 26 X X X

GPIO17 27 X X X

TCK/GPIO18 28 X X X

TDO/GPIO19 29 X X X

TDI/GPIO20 30 X X X

TMS/GPIO21 31 X X X

GPO Control

The GPIOs when configured as outputs can be controlled by PMBus commands or through logic defined in

internal Boolean function blocks. Controlling GPOs by PMBus commands (GPIO_SELECT and GPIO_CONFIG)

can be used to have control over LEDs, enable switches, etc. with the use of an I2C interface. See the

UCD90xxx Sequencer and System Health Controller PMBus Command Reference for details on controlling a

GPO using PMBus commands.

GPI(0)

GPI_POLARITY(0)

GPI_INVERSE(0)

GPI_ENABLE(0)

_GPI(0)

_STATUS(9)

STATUS_ENABLE(9)

STATUS_INVERSE(9)

STATUS(0)

STATUS(1)

STATUS(9)

STATUS_TYPE_SELECT

_GPI(1:7)

_STATUS(0:8)

Status Type 1

Status Type 31

Sub block repeated for each of GPI(1:7)

Sub block repeated for each of STATUS(0:8)

There is one STATUS_TYPE_SELECT for each of the two AND

gates in a boolean block

OR_INVERSE(x)

GPOx

_GPI(0:7)

_STATUS(0:9)

GPO(0)

GPO_INVERSE(0)

GPO_ENABLE(0)

_GPO(0)

Sub block repeated for each of GPO(1:7)

_GPO(1:7)

_GPO(0:7)

AND_INVERSE(0)

AND_INVERSE(1)

ASSERT_DELAY(x)

DE-ASSERT_DELAY(x)

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GPO Dependencies

GPIOs can be configured as outputs that are based on Boolean combinations of up to two ANDs all ORed

together (Figure 16). Inputs to the logic blocks can include the first 8 defined GPOs, GPIs and rail-status flags.

One rail status type is selectable as an input for each AND gate in a Boolean block. For a selected rail status, the

status flags of all active rails can be included as inputs to the AND gate. _LATCH rail-status types stay asserted

until cleared by a MFR PMBus command or by a specially configured GPI pin. The different rail-status types are

shown in Table 5. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for

complete definitions of rail-status types. The GPO response can be configured to have a delayed assertion or

deassertion.

Figure 16. Boolean Logic Combinations

Figure 17. Fusion Boolean Logic Builder

3ms 3ms

1ms

GPI

GPO

UCD9090

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SLVSA30A –APRIL 2011–REVISED AUGUST 2011

Table 5. Rail-Status Types for Boolean Logic

Rail-Status Types

POWER_GOOD IOUT_UC_FAULT TOFF_MAX_WARN_LATCH

MARGIN_EN TEMP_OT_FAULT SEQ_ON_TIMEOUT_LATCH

MRG_LOW_nHIGH TEMP_OT_WARN SEQ_OFF_TIMEOUT_LATCH

VOUT_OV_FAULT SEQ_ON_TIMEOUT SYSTEM_WATCHDOG_TIMEOUT_LATCH

VOUT_OV_WARN SEQ_OFF_TIMEOUT IOUT_OC_FAULT_LATCH

VOUT_UV_WARN SYSTEM_WATCHDOG_TIMEOUT IOUT_OC_WARN_LATCH

VOUT_UV_FAULT VOUT_OV_FAULT_LATCH IOUT_UC_FAULT_LATCH

TON_MAX_FAULT VOUT_OV_WARN_LATCH TEMP_OT_FAULT_LATCH

TOFF_MAX_WARN VOUT_UV_WARN_LATCH TEMP_OT_WARN_LATCH

IOUT_OC_FAULT VOUT_UV_FAULT_LATCH

IOUT_OC_WARN TON_MAX_FAULT_LATCH

GPO Delays

The GPOs can be configured so that they manifest a change in logic with a delay on assertion, deassertion, both

or none. GPO behavior using delays will have different effects depending if the logic change occurs at a faster

rate than the delay. On a normal delay configuration, if the logic for a GPO changes to a state and reverts back

to previous state within the time of a delay then the GPO will not manifest the change of state on the pin. In

Figure 18 the GPO is set so that it follows the GPI with a 3ms delay at assertion and also at de-assertion. When

the GPI first changes to high logic state, the state is maintained for a time longer than the delay allowing the

GPO to follow with appropriate logic state. The same goes for when the GPI returns to its previous low logic

state. The second time that the GPI changes to a high logic state it returns to low logic state before the delay

time expires. In this case the GPO does not change state. A delay configured in this manner serves as a glitch

filter for the GPO.

Figure 18. GPO Behavior When Not Ignoring Inputs During Delay

The Ignore Input During Delay bit allows to output a change in GPO even if it occurs for a time shorter than the

delay. This configuration setting has the GPO ignore any activity from the triggering event until the delay expires.

Figure 19 represents the two cases for when ignoring the inputs during a delay. In the case in which the logic

changes occur with more time than the delay, the GPO signal looks the same as if the input was not ignored.

Then on a GPI pulse shorter than the delay the GPO still changes state. Any pulse that occurs on the GPO when

having the Ignore Input During Delay bit set will have a width of at least the time delay.

3ms 3ms 3ms3ms

1ms

GPI

GPO

UCD9090

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Figure 19. GPO Behavior When Ignoring Inputs During Delay

State Machine Mode Enable

When this bit within the GPO_CONFIG command is set, only one of the AND path will be used at a given time.

When the GPO logic result is currently TRUE, AND path 0 will be used until the result becomes FALSE. When

the GPO logic result is currently FALSE, AND path 1 will be used until the result becomes TRUE. This provides a

very simple state machine and allows for more complex logical combinations.

GPI Special Functions

There are five special input functions for which GPIs can be used. There can be no more than one pin assigned

to each of these functions.

•Sequencing Timeout Source - If SEQ_TIMEOUT is non-zero on any rail, a fault will occur if this GPI pin

does not go active within SEQ_TIMEOUT time after the rail reaches its power good state.

•Latched Statuses Clear Source - When a GPO uses a latched status type (_LATCH), you can configure a

GPI that will clear the latched status.

•Input Source for Margin Enable - When this pin is asserted, all rails with margining enabled will be put in a

margined state (low or high).

•Input Source for Margin Low/Not-High - When this pin is asserted all margined rails will be set to Margin

Low as long as the Margin Enable is asserted. When this pin is de-asserted the rails will be set to Margin

High.

The polarity of GPI pins can be configured to be either Active Low or Active High. The first 3 GPIs that are

defined regardless of their main purpose will be used for the PIN_SELECTED_RAIL_STATES command.

Power-Supply Enables

Each GPIO can be configured as a rail-enable pin with either active-low or active-high polarity. Output mode

options include open-drain or push-pull outputs that can be actively driven to 3.3 V or ground. During reset, the

GPIO pins are high-impedance except for FPWM/GPIO pins 17–24, which are driven low. External pulldown or

pullup resistors can be tied to the enable pins to hold the power supplies off during reset. The UCD9090 can

support a maximum of 12 enable pins.

NOTE

GPIO pins that have FPWM capability (pins 10-17) should only be used as power-supply

enable signals if the signal is active high.

Cascading Multiple Devices

A GPIO pin can be used to coordinate multiple controllers by using it as a power good-output from one device

and connecting it to the PMBUS_CNTRL input pin of another. This imposes a master/slave relationship among

multiple devices. During startup, the slave controllers initiate their start sequences after the master has

completed its start sequence and all rails have reached regulation voltages. During shutdown, as soon as the

master starts to sequence-off, it sends the shut-down signal to its slaves.

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A shutdown on one or more of the master rails can initiate shutdowns of the slave devices. The master

shutdowns can be initiated intentionally or by a fault condition. This method works to coordinate multiple

controllers, but it does not enforce interdependency between rails within a single controller.

The PMBus specification implies that the power-good signal is active when ALL the rails in a controller are

regulating at their programmed voltage. The UCD9090 allows GPIOs to be configured to respond to a desired

subset of power-good signals.

PWM Outputs

FPWM1-8

Pins 10-17 can be configured as fast pulse-width modulators (FPWMs). The frequency range is 15.260 kHz to

125 MHz. FPWMs can be configured as closed-loop margining outputs, fan controllers or general-purpose

PWMs.

Any FPWM pin not used as a PWM output can be configured as a GPIO. One FPWM in a pair can be used as a

PWM output and the other pin can be used as a GPO. The FPWM pins are actively driven low from reset when

used as GPOs.

The frequency settings for the FPWMs apply to pairs of pins:

•FPWM1 and FPWM2 –same frequency

•FPWM3 and FPWM4 –same frequency

•FPWM5 and FPWM6 –same frequency

•FPWM7 and FPWM8 –same frequency

If an FPWM pin from a pair is not used while its companion is set up to function as a PWM, it is recommended to

configure the unused FPWM pin as an active-low open-drain GPO so that it does not disturb the rest of the

system. By setting an FPWM, it automatically enables the other FPWM within the pair if it was not configured for

any other functionality.

The frequency for the FPWM is derived by dividing down a 250MHz clock. To determine the actual frequency to

which an FPWM can be set, must divide 250MHz by any integer between 2 and (214-1).

The FPWM duty cycle resolution is dependent on the frequency set for a given FPWM. Once the frequency is

known the duty cycle resolution can be calculated as Equation 1.

Change per Step (%)FPWM = frequency ÷(250 ×106×16) ×100 (1)

Take for an example determining the actual frequency and the duty cycle resolution for a 75MHz target

frequency.

1. Divide 250MHz by 75MHz to obtain 3.33.

2. Round off 3.33 to obtain an integer of 3.

3. Divide 250MHz by 3 to obtain actual closest frequency of 83.333MHz.

4. Use Equation 1 to determine duty cycle resolution to obtain 2.0833% duty cycle resolution.

PWM1-2

Pins 22 and 23 can be used as GPIs or PWM outputs. These PWM outputs have an output frequency of 0.93 Hz

to 7.8125 MHz.

The frequency for PWM1 and PWM2 is derived by dividing down a 15.625MHz clock. To determine the actual

frequency to which these PWMs can be set, must divide 15.625MHz by any integer between 2 and (224-1). The

duty cycle resolution will be dependent on the set frequency for PWM1 and PWM2.

The PWM1 or PWM2 duty cycle resolution is dependent on the frequency set for the given PWM. Once the

frequency is known the duty cycle resolution can be calculated as Equation 2

Change per Step (%)PWM1/2 = frequency ÷15.625 ×106×100 (2)

To determine the closest frequency to 1MHz that PWM1 can be set to calculate as the following:

1. Divide 15.625MHz by 1MHz to obtain 15.625.

2. Round off 15.625 to obtain an integer of 16.

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3. Divide 15.625MHz by 16 to obtain actual closest frequency of 976.563kHz.

4. Use Equation 2 to determine duty cycle resolution to obtain 6.25% duty cycle resolution.

All frequencies below 238Hz will have a duty cycle resolution of 0.0015%.

Programmable Multiphase PWMs

The FPWMs can be aligned with reference to their phase. The phase for each FPWM is configurable from 0°to

360°. This provides flexibility in PWM-based applications such as power-supply controller, digital clock

generation, and others. See an example of four FPWMs programmed to have phases at 0°, 90°, 180°and 270°

(Figure 20).

Figure 20. Multiphase PWMs

MARGINING

Margining is used in product validation testing to verify that the complete system works properly over all

conditions, including minimum and maximum power-supply voltages, load range, ambient temperature range,

and other relevant parameter variations. Margining can be controlled over PMBus using the OPERATION

command or by configuring two GPIO pins as margin-EN and margin-UP/DOWN inputs. The MARGIN_CONFIG

command in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference describes

different available margining options, including ignoring faults while margining and using closed-loop margining to

trim the power-supply output voltage one time at power up.

Open-Loop Margining

Open-loop margining is done by connecting a power-supply feedback node to ground through one resistor and to

the margined power supply output (VOUT) through another resistor. The power-supply regulation loop responds to

the change in feedback node voltage by increasing or decreasing the power-supply output voltage to return the

feedback voltage to the original value. The voltage change is determined by the fixed resistor values and the

voltage at VOUT and ground. Two GPIO pins must be configured as open-drain outputs for connecting resistors

from the feedback node of each power supply to VOUT or ground.

/EN

POWER

SUPPLY Vout

VOUT

VFB

Rmrg_HI

VFB

Rmrg_LO

10k

3.3V

Open Loop Margining

MON(1:10)

GPIO(1:10)

UCD9090

GPIO

/EN

POWER

SUPPLY Vout

VOUT

VFB

Rmrg_HI

VFB

Rmrg_LO

10k

3.3V

“0” or “1 ”

VOUT

3.3V

UCD9090

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Figure 21. Open-Loop Margining

Closed-Loop Margining

Closed-loop margining uses a PWM or FPWM output for each power supply that is being margined. An external

RC network converts the FPWM pulse train into a DC margining voltage. The margining voltage is connected to

the appropriate power-supply feedback node through a resistor. The power-supply output voltage is monitored,

and the margining voltage is controlled by adjusting the PWM duty cycle until the power-supply output voltage

reaches the margin-low and margin-high voltages set by the user. The voltage setting resolutions will be the

same that applies to the voltage measurement resolution (Table 3). The closed loop margining can operate in

several modes (Table 6). Given that this closed-loop system has feed back through the ADC, the closed-loop

margining accuracy will be dominated by the ADC measurement. The relationship between duty cycle and

margined voltage is configurable so that voltage increases when duty cycle increases or decreases. For more

details on configuring the UCD9090 for margining, see the Voltage Margining Using the UCD9012x application

note (SLVA375).

Table 6. Closed Loop Margining Modes

Mode Description

DISABLE Margining is disabled.

ENABLE_TRI_STATE When not margining, the PWM pin is set to high impedance state.

When not margining, the PWM duty-cycle is continuously adjusted to keep the voltage at

ENABLE_ACTIVE_TRIM VOUT_COMMAND.

ENABLE_FIXED_DUTY_CYCLE When not margining, the PWM duty-cycle is set to a fixed duty-cycle.

MON(1:10)

GPIO

UCD9090 Vout

Vmarg

FPWM 1 VFB

10k

3.3V

Closed Loop

Margining

250 kHz – 1MHz

/EN

POWER

SUPPLY

VOUT

VFB

Delay Delay

Delay

Power Good On Power Good On

Power Good Off

POWER GOOD

SYSTEM RESET

configured without pulse Pulse Pulse

SYSTEM RESET

configured with pulse

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Figure 22. Closed-Loop Margining

SYSTEM RESET SIGNAL

The UCD9090 can generate a programmable system-reset pulse as part of sequence-on. The pulse is created

by programming a GPIO to remain deasserted until the voltage of a particular rail or combination of rails reach

their respective POWER_GOOD_ON levels plus a programmable delay time. The system-reset delay duration

can be programmed as shown in Table 7. See an example of two SYSTEM RESET signals Figure 23. The first

SYSTEM RESET signal is configured so that it de-asserts on Power Good On and it asserts on Power Good Off

after a given common delay time. The second SYSTEM RESET signal is configured so that it sends a pulse after

a delay time once Power Good On is achieved. The pulse width can be configured between 0.001s to 32.256s.

See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for pulse width

configuration details.

Figure 23. System Reset with and without Pulse Setting

The system reset can react to watchdog timing. In Figure 24 The first delay on SYSTEM RESET is for the initial

reset release that would get a CPU running once all necessary voltage rails are in regulation. The watchdog is

configured with a Start Time and a Reset Time. If these times expire without the WDI clearing them then it is

expected that the CPU providing the watchdog signal is not operating. The SYSTEM RESET is toggled either

using a Delay or GPI Tracking Release Delay to see if the CPU recovers.

Power Good On

Delay

Delay or

GPI Tracking Release Delay

POWER GOOD

WDI

SYSTEM RESET

Watchdog

Start Time

Watchdog

Reset Time

Watchdog

Start Time

Watchdog

Reset Time

UCD9090

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Figure 24. System Reset with Watchdog

Table 7. System-Reset Delay

Delay

0 ms

1 ms

2 ms

4 ms

8 ms

16 ms

32 ms

64 ms

128 ms

256 ms

512 ms

1.02 s

2.05 s

4.10 s

8.19 s

16.38 s

32.8 s

WATCH DOG TIMER

A GPI and GPO can be configured as a watchdog timer (WDT). The WDT can be independent of power-supply

sequencing or tied to a GPIO functioning as a watchdog output (WDO) that is configured to provide a

system-reset signal. The WDT can be reset by toggling a watchdog input (WDI) pin or by writing to

SYSTEM_WATCHDOG_RESET over I2C. The WDI and WDO pins are optional when using the watchdog timer.

The WDI can be replaced by SYSTEM_WATCHDOG_RESET command and the WDO can be manifested

through the Boolean Logic defined GPOs or through the System Reset function.

The WDT can be active immediately at power up or set to wait while the system initializes. Table 8 lists the

programmable wait times before the initial timeout sequence begins.

Table 8. WDT Initial Wait Time

WDT INITIAL WAIT TIME

0 ms

100 ms

200 ms

WDI

WDO

<tWDI

<tWDI <tWDI tWDI <tWDI

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Table 8. WDT Initial Wait

Time (continued)

WDT INITIAL WAIT TIME

400 ms

800 ms

1.6 s

3.2 s

6.4 s

12.8 s

25.6 s

51.2 s

102 s

205 s

410 s

819 s

1638 s

The watchdog timeout is programmable from 0.001s to 32.256s. See the UCD90xxx Sequencer and System

Health Controller PMBus Command Reference for details on configuring the watchdog timeout. If the WDT times

out, the UCD9090 can assert a GPIO pin configured as WDO that is separate from a GPIO defined as

system-reset pin, or it can generate a system-reset pulse. After a timeout, the WDT is restarted by toggling the

WDI pin or by writing to SYSTEM_WATCHDOG_RESET over I2C.

Figure 25. Timing of GPIOs Configured for Watchdog Timer Operation

DATA AND ERROR LOGGING TO FLASH MEMORY

The UCD9090 can log faults and the number of device resets to flash memory. Peak voltage measurements are

also stored for each rail. To reduce stress on the flash memory, a 30-second timer is started if a measured value

exceeds the previously logged value. Only the highest value from the 30-second interval is written from RAM to

flash.

Multiple faults can be stored in flash memory and can be accessed over PMBus to help debug power-supply

bugs or failures. Each logged fault includes:

•Rail number

•Fault type

•Fault time since previous device reset

•Last measured rail voltage

The total number of device resets is also stored to flash memory. The value can be reset using PMBus.

With the brownout function enabled, the run-time clock value, peak monitor values, and faults are only logged to

flash when a power-down is detected. The device run-time clock value is stored across resets or power cycles

unless the brownout function is disabled, in which case the run-time clock is returned to zero after each reset.

It is also possible to update and calibrate the UCD9090 internal run-time clock via a PMBus host. For example, a

host processor with a real-time clock could periodically update the UCD9090 run-time clock to a value that

corresponds to the actual date and time. The host must translate the UCD9090 timer value back into the

appropriate units, based on the usage scenario chosen. See the REAL_TIME_CLOCK command in the

UCD90xxx Sequencer and System Health Controller PMBus Command Reference for more details.

V33A

V33D

UCD9090

AVSS1

AVSS2

DVSS

3.3V

B340A

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BROWNOUT FUNCTION

The UCD9090 can be enabled to turn off all nonvolatile logging until a brownout event is detected. A brownout

event occurs if VCC drops below 2.9 V. In order to enable this feature, the user must provide enough local

capacitance to deliver up to 80 mA (consider additional load based on GPOs sourcing external circuits such as

LEDs) on for 5 ms while maintaining a minimum of 2.6 V at the device. If using the brownout circuit (Figure 26),

then a schottky diode should be placed so that it blocks the other circuits that are also powered from the 3.3V

supply.

With this feature enabled, the UCD9090 saves faults, peaks, and other log data to SRAM during normal

operation of the device. Once a brownout event is detected, all data is copied from SRAM to Flash. Use of this

feature allows the UCD9090 to keep track of a single run-time clock that spans device resets or system power

down (rather than resetting the run time clock after device reset). It can also improve the UCD9090 internal

response time to events, because Flash writes are disabled during normal system operation. This is an optional

feature and can be enabled using the MISC_CONFIG command. For more details, see the UCD90xxx

Sequencer and System Health Controller PMBus Command Reference.

Figure 26. Brownout Circuit

PMBUS ADDRESS SELECTION

Two pins are allocated to decode the PMBus address. At power up, the device applies a bias current to each

address-detect pin, and the voltage on that pin is captured by the internal 12-bit ADC. The PMBus address is

calculated as follows.

PMBus Address = 12 ×bin(VAD01) + bin(VAD00)

Where bin(VAD0x) is the address bin for one of eight addresses as shown in Table 9. The address bins are

defined by the MIN and MAX VOLTAGE RANGE (V). Each bin is a constant ratio of 1.25 from the previous bin.

This method maintains the width of each bin relative to the tolerance of standard 1% resistors.

Table 9. PMBus Address Bins

RPMBus

ADDRESS BIN PMBus RESISTANCE (kΩ)

open —

11 200

10 154

9 118

8 90.9

7 69.8

6 53.6

5 41.2

4 31.6

short —

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A low impedance (short) on either address pin that produces a voltage below the minimum voltage causes the

PMBus address to default to address 126 (0x7E). A high impedance (open) on either address pin that produces

a voltage above the maximum voltage also causes the PMBus address to default to address 126 (0x7E).

Address 0 is not used because it is the PMBus general-call address. Addresses 11 and 127 can not be used by

this device or any other device that shares the PMBus with it, because those are reserved for manufacturing

programming and test. It is recommended that address 126 not be used for any devices on the PMBus, because

this is the address that the UCD9090 defaults to if the address lines are shorted to ground or left open. Table 10

summarizes which PMBus addresses can be used. Other SMBus/PMBus addresses have been assigned for

specific devices. For a system with other types of devices connected to the same PMBus, see the SMBus device

address assignments table in Appendix C of the latest version of the System Management Bus (SMBus)

specification. The SMBus specification can be downloaded at http://smbus.org/specs/smbus20.pdf.

PMBUS_ADDR0

PMBUS_ADDR1

VDD

To 12-bit ADC

10uA

Ibias

UCD9090

On/Off Control

Resistors to set

PMBus address

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Table 10. PMBus Address Assignment Rules

Address STATUS Reason

0 Prohibited SMBus generaladdress call

11 Avoid Causes conflicts with other devices during program flash updates.

12 Prohibited PMBus alert response protocol

126 For JTAG Use Default value; may cause conflicts with other devices.

127 Prohibited Used by TI manufacturing for device tests.

Figure 27. PMBus Address-Detection Method

CAUTION

Address 126 (0x7E) is not recommended to be selected as a permanent PMBus

address for any given application design. Leaving the address in default state as 126

(0x7E) will enable the JTAG and not allow using the JTAG compatible pins (27-30) as

GPIOs. The UCD9090 runs at 10% slower frequency while the JTAG is enabled to

ensure best JTAG operation.

DEVICE RESET

The UCD9090 has an integrated power-on reset (POR) circuit which monitors the supply voltage. At power up,

the POR detects the V33D rise. When V33D is greater than VRESET, the device comes out of reset.

The device can be forced into the reset state by an external circuit connected to the RESET pin. A logic-low

voltage on this pin for longer than tRESET holds the device in reset. It comes out of reset within 1 ms after

RESETis released and can return to a logic-high level. To avoid an erroneous trigger caused by noise, connect

RESET to a 10kohm pullup resistor (from RESET to 3.3 V) and a 1000pF capacitor (from RESET to AVSS).

Any time the device comes out of reset, it begins an initialization routine that lasts about 20 ms. During the

initialization routine, the FPWM pins are held low, and all other GPIO and GPI pins are open-circuit. At the end of

initialization, the device begins normal operation as defined by the device configuration.

DEVICE CONFIGURATION AND PROGRAMMING

From the factory, the device contains the sequencing and monitoring firmware. It is also configured so that all

GPOs are high-impedance (except for FPWM/GPIO pins 10-17, which are driven low), with no sequencing or

fault-response operation. See Configuration Programming of UCD Devices, available from the Documentation &

Help Center that can be selected from the Fusion GUI Help menu, for full UCD9090 configuration details.

After the user has designed a configuration file using Fusion GUI, there are three general device-configuration

programming options:

1. Devices can be programmed in-circuit by a host microcontroller using PMBus commands over I2C (see the

UCD90xxx Sequencer and System Health Controller PMBus Command Reference).

Each parameter write replaces the data in the associated memory (RAM) location. After all the required

configuration data has been sent to the device, it is transferred to the associated nonvolatile memory (data

flash) by issuing a special command, STORE_DEFAULT_ALL. This method is how the Fusion GUI normally

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reads and writes a device configuration.

2. The Fusion GUI (Figure 28) can create a PMBus or I2C command script file that can be used by the I2C

master to configure the device.

Figure 28. Fusion GUI PMBus Configuration Script Export Tool

3. Another in-circuit programming option is for the Fusion GUI to create a data flash image from the

configuration file (Figure 29). The configuration files can be exported in Intel Hex, Serial Vector Format (SVF)

and S-record. The image file can be downloaded into the device using I2C or JTAG. The Fusion GUI tools

can be used on-board if the Fusion GUI can gain ownership of the target board I2C bus.

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Figure 29. Fusion GUI Device Configuration Export Tool

Devices can be programmed off-board using the Fusion GUI tools or a dedicated device programmer. For small

runs, a ZIF socketed board with an I2C header can be used with the standard Fusion GUI or manufacturing GUI.

The Fusion GUI can also create a data flash file that can then be loaded into the UCD9090 using a dedicated

device programmer.

To configure the device over I2C or PMBus, the UCD9090 must be powered. The PMBus clock and data pins

must be accessible and must be pulled high to the same VDD supply that powers the device, with pullup resistors

between 1 kΩand 2 kΩ. Care should be taken to not introduce additional bus capacitance (<100 pF). The user

configuration can be written to data flash using a gang programmer via JTAG or I2C before the device is installed

in circuit. To use I2C, the clock and data lines must be multiplexed or the device addresses must be assigned by

socket. The Fusion GUI tools can be used for socket addressing. Pre-programming can also be done using a

single device test fixture.

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Table 11. Configuration Options

Data Flash via JTAG Data Flash via I2C PMBus Commands via I2C

Data Flash Export (.srec or hex

Data Flash Export (.svf type file) Project file I2C/PMBus script

type file)

Off-Board Configuration Fusion tools (with exclusive bus Fusion tools (with exclusive bus

Dedicated programmer access via USB to I2C adapter) access via USB to I2C adapter)

Data flash export Fusion tools (with exclusive bus Fusion tools (with exclusive bus

On-Board Configuration access via USB to I2C adapter) access via USB to I2C adapter)

The advantages of off-board configuration include:

•Does not require access to device I2C bus on board.

•Once soldered on board, full board power is available without further configuration.

•Can be partially reconfigured once the device is mounted.

Full Configuration Update while in Normal Mode

Although performing a full configuration of the UCD9090 in a controlled test setup is recommended, there may be

times in which it is required to update the configuration while the device is in an operating system. Updating the

full configuration based on methods listed in DEVICE CONFIGURATION AND PROGRAMMING section while

the device is in an operating system can be challenging because these methods do not permit the UCD9090 to

operate as required by application during the programming. During described methods the GPIOs may not be in

the desired states which can disable rails that provide power to the UCD9090. To overcome this, the UCD9090

has the capability to allow full configuration update while still operating in normal mode.

Updating the full configuration while in normal mode will consist of disabling data flash write protection, erasing

the data flash, writing the data flash image and reset the device. It is not required to reset the device immediately

but make note that the UCD9090 will continue to operate based on previous configuration with fault logging

disabled until reset. See Configuration Programming of UCD Devices, available from the Documentation &Help

Center that can be selected from the Fusion GUI Help menu, for details.

JTAG INTERFACE

The JTAG port can be used for production programming. Four of the six JTAG pins can also be used as GPIOs

during normal operation. See the Pin Functions table at the beginning of the document and Table 4 for a list of

the JTAG signals and which can be used as GPIOs. The JTAG port is compatible with the IEEE Standard

1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is

not supported on this device. The UCD9090 runs at 10% slower frequency while the JTAG is enabled to ensure

best JTAG operation.

The JTAG interface can provide an alternate interface for programming the device. It is disabled by default in

order to enable the GPIO pins with which it is multiplexed. There are two conditions under which the JTAG

interface is enabled:

1. On power-up if the data flash is blank, allowing JTAG to be used for writing the configuration parameters to a

programmed device with no PMBus interaction

2. When address 126 (0x7E) is detected at power up. A short to ground or an open condition on either address

pin will cause an address 126 (0x7E) to be generated which enables JTAG mode.

The Fusion GUI can create SVF files (See DEVICE CONFIGURATION AND PROGRAMMING section) based on

a given data flash configuration which can be used to program the desired configuration by JTAG. For Boundary

Scan Description Language (BSDL) file that supports the UCD9090 see the product folder in www.ti.com.

INTERNAL FAULT MANAGEMENT AND MEMORY ERROR CORRECTION (ECC)

The UCD9090 verifies the firmware checksum at each power up. If it does not match, then the device waits for

I2C commands but does not execute the firmware. A device configuration checksum verification is also

performed at power up. If it does not match, the factory default configuration is loaded. The PMBALERT# pin is

asserted and a flag is set in the status register. The error-log checksum validates the contents of the error log to

make sure that section of flash is not corrupted.

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There is an internal firmware watchdog timer. If it times out, the device resets so that if the firmware program is

corrupted, the device goes back to a known state. This is a normal device reset, so all of the GPIO pins are

open-drain and the FPWM pins are driven low while the device is in reset. Checks are also done on each

parameter that is passed, to make sure it falls within the acceptable range.

Error-correcting code (ECC) is used to improve data integrity and provide high-reliability storage of Data Flash

contents. ECC uses dedicated hardware to generate extra check bits for the user data as it is written into the

Flash memory. This adds an additional six bits to each 32-bit memory word stored into the Flash array. These

extra check bits, along with the hardware ECC algorithm, allow for any single-bit error to be detected and

corrected when the Data Flash is read.

Vmarg

Closed Loop

Margining

VMON1

GPIO1

12V

V33A

V33D

GPIO2

5V OUT VMON2

3.3V OUT VMON3

2.5V OUT VMON4

1.8V OUT

0.8V OUT

I0.8V

TEMP0.8V

VMON5

VMON6

VMON7

VMON8

VMON9

VMON10

I12V

TEMP12V

INA196

I12V

12V OUT

5V OUT

/EN DC-DC 1

VOUT

VFB

VIN

3.3V OUT

/EN DC-DC 2

VOUT

VFB

VIN

GPIO3

2.5V OUT

/EN DC-DC 3

VOUT

VFB

VIN

GPIO4

12V OUT

/EN

LDO1

VOUT

VIN

1.8V OUT

GPIO5

GPIO6

0.8V OUT

/EN DC-DC 4

VOUT

VFB

VIN

FPWM5 2MHz

INA196 I0.8V

WDI from main

processor GPI1

WDO GPIO18

TEMP IC TEMP0.8V

TEMP IC TEMP12V

POWER_GOOD GPIO12

WARN_OC_0.8V_

OR_12V GPIO13

SYSTEM RESET GPIO14

OTHER

SEQUENCER DONE

(CASCADE INPUT)

GPIO17

I2C/

PMBUS

JTAG

3.3V

Supply

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APPLICATION INFORMATION

Figure 30. Typical Application Schematic

NOTE

Figure 30 is a simplified application schematic. Voltage dividers such as the ones placed

on VMON1 input have been omitted for simplifying the schematic. All VMONx pins which

are configured to measure a voltage that exceeds the 2.5V ADC reference are required to

have a voltage divider.

REF TUE

ERR ACT

ACT

V E

1 REFTOL

RPT V 1

V 4096

æ ö ´

+æ ö

= ´ + -

ç ÷ ç ÷

è ø

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Layout Guidelines

The thermal pad provides a thermal and mechanical interface between the device and the printed circuit board

(PCB). Connect the exposed thermal pad of the PCB to the device VSS pins and provide at least a 4 ×4 pattern

of PCB vias to connect the thermal pad and VSS pins to the circuit ground on other PCB layers.

For supply-voltage decoupling, provide power-supply pin bypass to the device as follows:

•0.1-μF, X7R ceramic in parallel with 0.01-μF, X7R ceramic at pin 35 (BPCAP)

•0.1-μF, X7R ceramic in parallel with 4.7-μF, X5R ceramic at pin 33 (V33D)

•0.1-μF, X7R ceramic in parallel with 4.7-μF, X5R ceramic at pin 34 (V33A)

Depending on use and application of the various GPIO signals used as digital outputs, some impedance control

may be desired to quiet fast signal edges. For example, when using the FPWM pins for fan control or voltage

margining, the pin is configured as a digital clock signal. Route these signals away from sensitive analog signals.

It is also good design practice to provide a series impedance of 20 Ωto 33 Ωat the signal source to slow fast

digital edges.

Estimating ADC Reporting Accuracy

The UCD9090 uses a 12-bit ADC and an internal 2.5-V reference (VREF) to convert MON pin inputs into digitally

reported voltages. The least significant bit (LSB) value is VLSB = VREF/2Nwhere N = 12, resulting in a VLSB = 610

μV. The error in the reported voltage is a function of the ADC linearity errors and any variations in VREF. The

total unadjusted error (ETUE) for the UCD9090 ADC is ±5 LSB, and the variation of VREF is ±0.5% between 0°C

and 125°C and ±1% between –40°C and 125°C. VTUE is calculated as VLSB ×ETUE. The total reported voltage

error is the sum of the reference-voltage error and VTUE. At lower monitored voltages, VTUE dominates reported

error, whereas at higher monitored voltages, the tolerance of VREF dominates the reported error. Reported error

can be calculated using Equation 3, where REFTOL is the tolerance of VREF, VACT is the actual voltage being

monitored at the MON pin, and VREF is the nominal voltage of the ADC reference.

(3)

From Equation 3, for temperatures between 0°C and 125°C, if VACT = 0.5 V, then RPTERR = 1.11%. If VACT = 2.2

V, then RPTERR = 0.64%. For the full operating temperature range of –40°C to 125°C, if VACT = 0.5 V, then

RPTERR = 1.62%. If VACT = 2.2 V, then RPTERR = 1.14%.

SPACER

PACKAGE OPTION ADDENDUM

www.ti.com 20-Aug-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

UCD9090RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

UCD9090RGZT ACTIVE VQFN RGZ 48 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

UCD9090RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

UCD9090RGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

UCD9090RGZR VQFN RGZ 48 2500 367.0 367.0 38.0

UCD9090RGZT VQFN RGZ 48 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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