DATASHEET
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 9FGV0241
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 1
9FGV0241 JUNE 22, 2017
Description
The 9FGV0241 is a 2-output very low power frequency
generator for PCIe Gen 1, 2, 3 and 4 applications with
integrated output terminations providing Zo=100. The
device has 2 output enables for clock management and
supports 2 different spread spectrum levels in addition to
spread off.
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
•2 – 0.7V low-power HCSL-compatible (LP-HCSL) DIF
pairs w/Zo=100
•1 – 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
•DIF cycle-to-cycle jitter <50ps
•DIF output-to-output skew <50ps
•DIF phase jitter is PCIe Gen1-2-3-4 compliant
•REF phase jitter is <1.5ps RMS
Features/Benefits
•Integrated terminations provide 100 differential Zo;
reduced component count and board space
•1.8V operation; reduced power consumption
•OE# pins; support DIF power management
•LP-HCSL differential clock outputs; reduced power and
board space
•Programmable Slew rate for each output; allows tuning
for various line lengths
•Programmable output amplitude; allows tuning for
various application environments
•DIF outputs blocked until PLL is locked; clean system
start-up
•Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
•External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
•Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
•3.3V tolerant SMBus interface works with legacy
controllers
•Space saving 24-pin 4x4 mm VFQFPN; minimal board
space
Block Diagram
XIN/CLKIN_25
X2
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
REF
vOE(1:0)#
SCLK_3.3
vSADR
DIF0
DIF1
2
IDT 603-25-150JA4C or
603-25-150JA4I 25MHz
SSC Capable
PLL
Control
Logic
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 2
9FGV0241 JUNE 22, 2017
Pin Configuration
SMBus Address Selection Table
Power Management Table
Power Connections
GNDXTAL
vSS_EN_tri
^CKPWRGD_PD#
GND
VDD1.8
vOE1#
24 23 22 21 20 19
X1_25 1 18 DIF1#
X2 2 17 DIF1
VDDXTAL1.8 3 16 VDDA1.8
vSADR/REF1.8 4 15 GNDA
GNDREF 514 DIF0#
GNDDIG 613DIF0
7 8 9 10 11 12
VDDDIG1.8
SCLK_3.3
SDATA_3.3
GND
VDD1.8
vOE0#
v prefix indicates internal 120KOhm pull down resistor
9FGV0241
connect
epad to GND
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
SADR Address
0 1101000
1 1101010
State of SADR on first application
of CKPWRGD_PD#
+ Read/Write Bit
x
x
True O/P Com p. O/P
0 X Low Low Hi-Z1
1 1 Running Running Running
1 0 Low Low Low
CKPWRGD_PD# SMBus
OE b i t DIFx
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this,
when CKPWRG_PD# is low, REF is Low.
REF
Pin Number
VDD GND
35,24
76
11,20 10,21
16 15 PLL Analog
Description
XTAL, REF
Digital Power
DIF outputs
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 3
9FGV0241 JUNE 22, 2017
Pin Descriptions
Pin# Pin Name Type Pin Description
1 X1_25 IN Crystal input, Nominally 25.00MHz.
2 X2 OUT Crystal output.
3 VDDXTAL1.8 PWR Power supply for XTAL, nominal 1.8V
4 vSADR/REF1.8 LATCHED
I/O Latch to select SMBus Address/1.8V LVCMOS copy of X1 pin.
5 GNDREF GND Ground pin for the REF outputs.
6 GNDDIG GND Ground pin for digital circuitry
7 VDDDIG1.8 PWR 1.8V digital power (dirty power)
8 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant.
9 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant.
10 GND GND Ground pin.
11 VDD1.8 PWR Power supply, nominal 1.8V
12 vOE0# IN Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
13 DIF0 OUT Differential true clock output
14 DIF0# OUT Differential Complementary clock output
15 GNDA GND Ground pin for the PLL core.
16 VDDA1.8 PWR 1.8V power for the PLL core.
17 DIF1 OUT Differential true clock output
18 DIF1# OUT Differential Complementary clock output
19 vOE1# IN Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
20 VDD1.8 PWR Power supply, nominal 1.8V
21 GND GND Ground pin.
22 ^CKPWRGD_PD# IN
Input notifies device to sample latched inputs and start up on first high assertion.
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
23 vSS_EN_tri LATCHED IN Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
24 GNDXTAL GND GND for XTAL
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 4
9FGV0241 JUNE 22, 2017
Test Loads
Alternate Terminations
Rs
Rs
Low-Power HCSL Differential Output Test Load
2pF 2pF
5 inches
Zo=100ohm
Device
REF Output
33
REF Output Test Load
5pF
Zo = 50 ohms
Driving LVDS inputs with the 9FGV0241
Receiver has
termination
Receiver does not
have termination
R7a, R7b 10K ohm 140 ohm
R8a, R8b 5.6K ohm 75 ohm
Cc 0.1 uF 0.1 uF
Vcm 1.2 volts 1.2 volts
Component
Value
Note
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 5
9FGV0241 JUNE 22, 2017
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGV0241. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–Current Consumption
Electrical Characteristics–Output Duty Cycle, Jitter, and Skew Characteristics
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
1.8V Supply Voltage VDDxx Applies to All VDD pins -0.5 2.5 V 1,2
Input Voltage V
IN
-0.5 V
DD
+0.3V V 1, 3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.6V V 1
Storage Temperature Ts -65 150 °C
1
Junction Temperature Tj 125 °C 1
Input ESD protection ESD prot Human Body Model 2000 V 1
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
IDDAOP VDDA, PLL Mode, All outputs active @100MHz 7 8 mA 1
IDDOP VDD, All outputs active @100MHz 15 18 mA 1
Suspend Supply Current IDDSUSP VDDxxx, PD# = 0, Wake-On-LAN enabled 6 8 mA 1
Powerdown Current IDDPD PD#=0 0.6 1 mA 1, 2
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Assumin
g
REF is not runnin
g
in power down state
Operating Supply Current
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle t
D
C
Measured differentially, PLL Mode 45 50 55 % 1
Skew, Output to Output t
sk3
V
T
= 50% 34 50 ps 1
Jitter, Cycle to cycle tjcyc-cyc PLL mode 14 50 ps 1,2
1Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 6
9FGV0241 JUNE 22, 2017
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
1.8V Supply Voltage VDD Supply voltage for core, analog and single-ended
LVCMOS outputs
1.7 1.8 1.9 V 1
T
COM
Commercial range 0 25 70 °C 1
T
IND
Industrial range -40 25 85 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus 0.75 V
DD
V
DD
+ 0.3 V 1
Input Mid Voltage V
IM
Single-ended tri-level inputs ('_tri' suffix, if present) 0.4 V
DD
0.6 V
DD
V1
Input Low Voltage V
IL
Single-ended inputs, except SMBus -0.3 0.25 V
DD
V1
Schmitt Trigger Positive
Going Threshold Voltage VT+ Single-ended inputs, where indicated 0.4 VDD 0.7 VDD V1
Schmitt Trigger Negative
Goin
g
Threshold Volta
g
e
VT- Single-ended inputs, where indicated 0.1 VDD 0.4 VDD V1
Hysteresis Voltage V
H
V
T+
- V
T-
0.1 V
DD
0.4 V
DD
V1
Output High Voltage V
IH
Single-ended outputs, except SMBus. I
OH
= -2mA V
DD
-0.45 V 1
Output Low Voltage V
IL
Single-ended outputs, except SMBus. I
OL
= -2mA 0.45 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
IINP
Single-ended inputs
VIN
= 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200 200 uA 1
Input Frequency F
in XTAL, or X1 input 23 25 27 MHz
1
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock 0.4 1.8 ms 1,2
SS Modulation Frequency fMOD
Allowable Frequency
(Triangular Modulation) 31 31.6 32 kHz 1
OE# Latency tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
234clocks1,3
Tdrive_PD# tDRVPD
DIF output enable after
PD# de-assertion
4 300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 1,2
Trise t
R
Rise time of single-ended control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V, see note 4 for V
DDSMB
< 3.3V 0.8 V 1,4
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V, see note 5 for V
DDSMB
< 3.3V 2.1 3.6 V 1,5
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
1.7 3.6 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency fMAXSMB Maximum SMBus operating frequency 400 kHz 1
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
Capacitance
3
Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB
5 For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB
Input Current
Ambient Operating
Temperature
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 7
9FGV0241 JUNE 22, 2017
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common
Clocked (CC) Architectures
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Scope avera
g
in
g
on 3.0V/ns settin
g
23.14.3
V/ns
1, 2, 3
Scope avera
g
in
g
on 2.0V/ns settin
g
1.5 2.3 3.5
V/ns
1, 2, 3
Slew rate matching
Δ
Trf Slew rate matching, Scope averaging on 320 %1,2,4
Voltage High VHI GH 660 794 850 1,7
Voltage Low VLOW -150 21 150 1
Max Voltage Vmax 816 1150 1
Min Voltage Vmin -300 -15 1
Vswing Vswing Scope averaging off 300 1551 mV 1,2
Crossin
g
Volta
g
e (abs) Vcross_abs Scope avera
g
in
g
off 300
397
550 mV 1,5
Crossing Voltage (var) Δ-Vcross Scope averaging off 15 140 mV 1,6
2
Measured from differential waveform
7 At default SMBus settings.
Measurement on single ended signal using
absolute value. (Scope averaging off) mV
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
Slew rate Trf
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting ∆-Vcross to be smaller than Vcross absolute.
1Guaranteed by design and characterization, not 100% tested in production.
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
SYMBOL PARAMETER CONDITIONS MIN TYP MAX Specification
Limit
UNITS NOTES
tjphPCIeG1-CC PCIe Gen 1 212535 86ps (p-p)1, 2, 3
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
0.9 0.9 1.1 3 ps
(rms) 1, 2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
1.5 1.6 1.9 3.1 ps
(rms) 1, 2
tjphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
0.3 0.37 0.44 1 ps
(rms)
1, 2
tjphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz) 0.3 0.37 0.44 0.5 ps
(rms) 1, 2
Notes on PCIe Filtered Phase Jitter Tables
1
Applies to all differential outputs,
g
uaranteed by desi
g
n and characterization.
Phase Jitter,
PLL Mode
tjphPCIeG2-CC
2 Calculated from Intel-supplied Clock Jitter Tool, with spread on and off.
3
Sample size of at least 100K cycles. This fi
g
ure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1
-12
.
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 8
9FGV0241 JUNE 22, 2017
Electrical Characteristics–REF
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Clock Periods–Differential Outputs with -0.5% Spread Spectrum Enabled
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values ppm 1,2
Clock period T
p
eriod
25 MHz output nominal 40 ns 1,2
Rise/Fall Slew Rate t
rf1
Byte 3 = 1F, V
OH
= VDD-0.45V, V
OL
= 0.45V 0.5 1 2.5 V/ns 1,3
Rise/Fall Slew Rate t
rf1
Byte 3 = 5F, V
OH
= VDD-0.45V, V
OL
= 0.45V 0.5 1.6 2.5 V/ns 1,3
Rise/Fall Slew Rate t
rf1
Byte 3 = 9F, V
OH
= VDD-0.45V, V
OL
= 0.45V 0.5 2 2.5 V/ns 1,3
Rise/Fall Slew Rate t
rf1
Byte 3 = DF, V
OH
= VDD-0.45V, V
OL
= 0.45V 0.5 2.1 2.5 V/ns 1,3
Duty Cycle d
t1
V
T
= VDD/2 V 45 53.1 55 % 1,4
Duty Cycle Distortion d
tcd
V
T
= VDD/2 V 0 2 4 % 1,5
Jitter, cycle to cycle t
j
c
y
c-c
y
c
V
T
= VDD/2 V 19 250 ps 1,4
Noise floor t
j
dBc1k
1kHz offset -130 -105 dBc 1,4
Noise floor t
j
dBc10k
10kHz offset to Nyquist -140 -120 dBc 1,4
Jitter, phase tjphREF 12kHz to 5MHz 0.63 1.5 ps
(rms) 1,4
1Guaranteed by design and characterization, not 100% tested in production.
3 Typical value occurs when REF slew rate is set to default value
4
When driven by a crystal.
5
When driven by an external oscillator via the X1 pin. X2 should be floatin
g
in this case.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
0
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2
Notes
Measurement Window
UnitsSSC OFF
Center
Freq.
MHz
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
Notes
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 9
9FGV0241 JUNE 22, 2017
General SMBus Serial Interface Information
How to Write
•Controller (host) sends a start bit
•Controller (host) sends the write address
•IDT clock will acknowledge
•Controller (host) sends the beginning byte location = N
•IDT clock will acknowledge
•Controller (host) sends the byte count = X
•IDT clock will acknowledge
•Controller (host) starts sending Byte N through Byte
N+X-1
•IDT clock will acknowledge each byte one at a time
•Controller (host) sends a Stop bit
Note: Read/Write address is determined by SADR latch.
How to Read
•Controller (host) will send a start bit
•Controller (host) sends the write address
•IDT clock will acknowledge
•Controller (host) sends the beginning byte location = N
•IDT clock will acknowledge
•Controller (host) will send a separate start bit
•Controller (host) sends the read address
•IDT clock will acknowledge
•IDT clock will send the data byte count = X
•IDT clock sends Byte N+X-1
•IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
•Controller (host) will need to acknowledge each byte
•Controller (host) will send a not acknowledge bit
•Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
OO
OO
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
N Not acknowledge
PstoP bit
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 10
9FGV0241 JUNE 22, 2017
SM Bus Tabl e: Output Enabl e Regi ste r
Byte 0 Nam e Control Function Type 0 1 De fa ul t
Bit 7 1
Bit 6 1
Bit 5 1
Bit 4 1
Bit 3 1
Bit 2 DIF OE1 Output Enable RW Low/Low Enabled 1
Bit 1 DIF OE0 Output Enable RW Low/Low Enabled 1
Bit 0 1
SM Bus Tabl e: SS Readback and V hi gh Control Re gi ster
Byte 1 Nam e Control Function Type 0 1 De fa ul t
Bit 7 SSENRB1 SS Enable Readback Bit1 RLatch
Bit 6 SSENRB1 SS Enable Readback Bit0 RLatch
Bit 5 SSEN_SWCNTRL Enable SW control of SS RW SS control locked Values in B1[4:3]
control SS amount. 0
Bit 4 SSENSW1 SS Enable Software Ctl Bit1 RW10
Bit 3 SSENSW0 SS Enable Software Ctl Bit0 RW10
Bit 2 1
Bit 1 AMPLITUDE 1 RW 00 = 0.6V 01 = 0.7V 1
Bit 0 AMPLITUDE 0 RW 10= 0.8V 11 = 0.9V 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SM Bus Tabl e: DIF S l ew Rate Control Re gi ste r
Byte 2 Nam e Control Function Type 0 1 De fa ul t
Bit 7 1
Bit 6 1
Bit 5 1
Bit 4 1
Bit 3 1
Bit 2 SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 RW 2.0V/ns 3.0V/ns 1
Bit 1 SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 RW 2.0V/ns 3.0V/ns 1
Bit 0 1
SM Bus Tabl e: REF Control Re giste r
Byte 3 Nam e Control Function Type 0 1 De fa ul t
Bit 7 RW 00 = Slowest 01 = Slow 0
Bit 6 RW 10 = Fast 11 = Faster 1
Bit 5 REF Power Down Function Wake-on-Lan Enable for REF RW
REF does not run in
Power Down
REF runs in Power
Down 0
Bit 4 REF OE REF Output Enable RW Low Enabled 1
Bit 3 1
Bit 2 1
Bit 1 1
Bit 0 1
Byte 4 is re serve d and reads back 'hFF'.
Reserved
Reserved
Slew Rate Control
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
00' for SS_EN_tri = 0, '01' for SS_EN_tri
= 'M', '11 for SS_EN_tri = '1'
REF
Reserved
Controls Output Amplitude
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 11
9FGV0241 JUNE 22, 2017
Recommended Crystal Characteristics (3225 package)
SM Bus Tabl e: Re visi on and Vendor I D Re gi ste r
Byte 5 Nam e Control Function Type 0 1 De fa ul t
Bit 7 RID3 R0
Bit 6 RID2 R0
Bit 5 RID1 R0
Bit 4 RID0 R0
Bit 3 VID3 R0
Bit 2 VID2 R0
Bit 1 VID1 R0
Bit 0 VID0 R1
SM Bus Tabl e: Device Type / De vice I D
Byte 6 Nam e Control Function Type 0 1 De fa ul t
Bit 7 Device Type1 R0
Bit 6 Device Type0 R0
Bit 5 Device ID5 R0
Bit 4 Device ID4 R0
Bit 3 Device ID3 R0
Bit 2 Device ID2 R0
Bit 1 Device ID1 R1
Bit 0 Device ID0 R0
SM Bus Tabl e: Byte Count Regi ster
Byte 7 Nam e Control Function Type 0 1 De fa ul t
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 BC4 RW 0
Bit 3 BC3 RW 1
Bit 2 BC2 RW 0
Bit 1 BC1 RW 0
Bit 0 BC0 RW 0
A rev = 0000
Byte Count Programming
Writing to this register will configure how
many bytes will be read back, default is
= 8 bytes.
Device Type
Revision ID
Reserved
0001 = IDT
00010 binary or 02 hex
00 = FGV, 01 = DBV,
10 = DMV, 11= Reserved
Device ID
Reserved
VENDOR ID
Reserved
PARAMETER VALUE UNITS NOTES
Frequency 25 MHz 1
Resonance Mode Fundamental
-
1
Frequency Tolerance @ 25°C
±
20 PPM Max 1
Frequency Stability, ref @ 25°C Over
Operating Temperature Range ±20 PPM Max 1
Temperature Range (commercial) 0~70 °
C
1
Temperature Range (industrial) -40~85 °C2
Equivalent Series Resistance (ESR) 50
Ω
Max 1
Shunt Capacitance (C
O
)7pF Max1
Load Capacitance (C
L
)8pF Max1
Drive Level 0.3 mW Max 1
Aging per year ±5 PPM Max 1
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 12
9FGV0241 JUNE 22, 2017
Thermal Characteristics
Marking Diagrams
Notes:
1. ‘LOT’ is the lot number.
2. ‘YYWW’ is the last two digits of the year and week that the part was assembled.
3. ‘L’ denotes RoHS compliant package.
4. ‘I’ denotes industrial temperature grade.
PARAMETER SYMBOL CONDITIONS PKG TYP
VALUE UNITS NOTES
θ
JC
Junction to Case 62 °C/W 1
θ
Jb
Junction to Base 5.4 °C/W 1
θ
JA0
Junction to Air, still air 50 °C/W 1
θ
JA1
Junction to Air, 1 m/s air flow 43 °C/W 1
θ
JA3
Junction to Air, 3 m/s air flow 39 °C/W 1
θJA5 Junction to Air, 5 m/s air flow 38 °C/W 1
1ePad soldered to board
Thermal Resistance NLG20
NLG24
LOT
241AL
YYWW
LOT
241AIL
YYWW
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 13
9FGV0241 JUNE 22, 2017
Package Outline and Dimensions (NLG24)
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 14
9FGV0241 JUNE 22, 2017
Package Outline and Dimensions (NLG24), cont.
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 15
9FGV0241 JUNE 22, 2017
Ordering Information
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Part / Orde r Num ber Shi ppi ng P acka gi ng Packa ge Te m pera ture
9FGV0241AKLF Tubes 24-pin VFQFPN 0 to +70° C
9FGV0241AKLFT Tape and Reel 24-pin VFQFPN 0 to +70° C
9FGV0241AKILF Tubes 24-pin VFQFPN -40 to +85° C
9FGV0241AKILFT Tape and Reel 24-pin VFQFPN -40 to +85° C
Rev. Issue Date Initiator Description Page #
E 2/3/2015 RDW Updated IDDAOP and IDDOP typ and max specs per latest
characterization review. 5
F 11/30/2015 RDW
Updated block diagram 1
G 1/4/2016 RDW Corrected typo in ordering information; changed rev "B" to rev "A" 13
H 10/18/2016 RDW
Removed IDT crystal part number
J 6/19/2017 RG
Updated front page Gendes to reflect the PCIe Gen4 updates.
Updated Electrical Characteristics - Filtered Phase Jitter Parameters -
PCIe Common Clocked (CC) Architectures and added PCIe Gen4 Data
1,7
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9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR SYNTHESIZERS