19-0895; Rev 1; 3/91 MAKIM Complete High-Speed CMOS 12-Bit ADC General Description The MAX162 and MX7572 are complete 12-Bit analog- to-digital converters (ADC's) that combine high speed, low power consumption, and an on-chip voltage reference. The conversion times are 3us (MAX162) and 5 and 12us (MX7572). The buried zener reference provides low drift and low noise performance. External component requirements are limited to only decoupling capacitors for the power supply and reference voltages. On-chip clock circuitry is also included which can either be driven from an external source, or in stand-alone applications, can be used with a crystal. The MAX162/MX7572uses a standard microprocessor interface architecture. Three-state data outputs are controlled by Read (RD) and Chip Select (CS) inputs. Data access and bus release times of 90 and 75ns respectively ensure compatibility with most popular microprocessors without resorting to wait states. Applications Digital Signal Processing (DSP) High Accuracy Process Control High Speed Data Acquisition Electro-Mechanical Systems Functional Diagram sono Weer aN | |2 1 12-BIT ONG a Yoo AEFERENCE , sai 2 Lm APPROXIMATI MUAX 162 REGISTER MX7572 12-BIT LATCH 1 ie a 8 contrat [42 ag wei [Tao , W = MULTIPLEXER 18 BEN THREE- s outer THAEE-STATE cock FT GLX OUT DRIVERS Pedal osciaTor EY ook iN i | T afr ee ye | is a a a Deno Features 12-Bit Resolution and Linearity 3us (MAX162), 5.8 and 12us (.MX7572) Conversion Times No missing Codes On-Chip Voltage Reference 90ns Access Time eee 215mW Max Power Consumption 24-Lead Narrow DIP Package Ordering Information . ERROR _ PART TEMP.RANGE PACKAGE" (1 cp) 3ys CONVERSION TIME . MAXi62ACNG 0 to +70C_ Plastic DIP +1/2 MAX162BCNG _OC to +70C_Plastic DIP +1 MAX162CCNG _OC to +70C_Plastic DIP +1 MAX162ACWG _0C to +70C__ Wide SO 1/2 MAX162BCWG 0C ta +70C__ Wide SO +1 MAX162CCWG 0C to +70C__ Wide SO +1 MAX162CC/D OC to +70C _Dice* +4 MAX162AING -40C to +85C__Plastic DIP 12 MAX162BING -40C to +85C __ Plastic DIP +1 MAX162CING -40C to +85C__ Plastic DIP +1 MAX162AMRG -55C to +125C CERDIP +1/2 MAX162BMRG _-55C to +125C__ CERDIP +1 MAX162CMRG _-55C to +125C CERDIP +1 Ordering information continued at end of data sheet. *All devices24 lead packages ** Consult factory for dice specifications. Pin Configuration AND - 2) Voo Vecr 23] Ves aGnD zz) BUSY on fm) CS p10 [J reo] AD 09 fe MAXIMA a] HBEN oe MAN 162 F] CLK OUT 7 7] CLOCK IN 06 re) 00/8 05 Le re) 04 ft ia] 02/10 DEND [2 rs) 03/11 MAXIMA Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. ZLSLXW/Z9OLXVWMAX162/MX7572 Complete High-Speed CMOS 12-Bit ADC ABSOLUTE MAXIMUM RATINGS Vop tODGND ..... eee cee es -0.3V to +7V Vgg to OGND ..... cece cence +0.3V to -17V AGND to DGND ...................... -0.3V, Vop + 0.3V AIN to AGND 2... elec eee cece e ees -15V to +15V Digital Input Voltage to OGND ........ -0.3V, Vop + 0.3V (Pins 17, 19-21) Digital Output Voltage to DGND ...... -0.3V, Vop + 0.3V (pins 4-11, 13-16, 18, 22) Operating Temperature Ranges MAX162XC, MX7572JN, KN, LN, JCWG, KCWG, LCWG .................. 0C to +70C MAX162XI, MX7572AQ, BQ, CQ ...... -25C to +85C MAX162XM, MX7572SQ, TQ, UQ .... -55C to +125C Storage Temperature Range ........... -65C to +160C Power Dissipation (any Package) to +75C ...,. 1000mWw Derates Above +75C by ............ cece cess 10mW/C Lead Temperature (Soldering 10 seconds) ....... +300C Stresses above those listed under Absolute Maximum Ratin S" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +5V 5%, Vsg = -15V 45%: Slow Memory Mode: Ta = TmIN to TMAx unless otherwise noted. fcLk = 4MHz for MAX162, 2.5MHz for MX7572XX05 and 1MH7z for MX7572KX12) PARAMETER [SYMBOL | CONDITIONS MIN TYP MAX | UNITS ACCURACY Resolution 12 Bits MAX162A, MX7572L/C/U TA = 25C +1/2 Integral Non-Linearity INL MAX162AC, Al, MX7572L/C +1/2 | LSB MAX162AM, MX7572U +3/4 MAX162B/C, MX7572K/B/T/J/A/S +1 Differential Non-Linearity DNL Guaranteed Monotonic Over Temp. +1 LSB MAX162C, Ta = 25C +4 MX7572J/A/S Ta = TMIN to Tmax +6 MAX162B, Ta = 25C +3 Offset Error (Note 1) MX7572K/B/T Ta = TMIN to TMAX +5 LSB MAX162A, Ta = 25C +3 MX7572L/C/U Ta = TmIN to Tmax +4 MAX162C, _ 96 MX7572J/A/8 Ta= 25C +15 Full Scale Error (Note 2) NOB a a/T Ta = 25C #10 | LSB MAX162A, one MX7572L/C/U Ta= 25C +10 MAX162C, MX7572u/A/S +45 Full Scale Tempco (Notes 3, 4) MAX162B/A, MX7572K/B/T, MX7572L/C/U +25 | Ppmrc ANALOG INPUT Input Voltage Range For Bipolar Input see Figures 19-21 0 5 Vv Input Current AIN = OV to +5V 3.5 mA INTERNAL REFERENCE VREF Output Voltage Ta = 25C -5.2 -5.25 -5.3 V MAX162C, MX7572U/A/S 40 . VreF Output Tempco (Note 5) MAX 162B/A, MX7572K/B/T, MX7572L/C/U 20 ppm/'C Output Current Sink Capability (Note 6} 500 HA MAXIMAComplete High-Speed CMOS 12-Bit ADC ELECTRICAL CHARACTERISTICS (Continued) (VoD = +5V +5%, Vsg = -15V +5%; Slow Memory Mode; Ta = TMIN to TMAX unless otherwise noted. feLK = 4MHz for MAX162, 2.5MHz for MX7572XX05 and 1MHz for MX7572XX 12) PARAMETER SYMBOL CONDITIONS MIN TYP MAX | UNITS POWER SUPPLY REJECTION Vpp Only FS Change, Vss = -15V, Vop = 4.75 to 5.25V +1/2 LSB FS Change, Vop = 5V Vss Only MAX162/MX7572 Vss = -14.25V to -15.75V +1/8 LSB MAX 162 Vss = -11.4V to -12.6V +1/8 LSB LOGIC INPUTS Input Low Voltage VIL CS, RD, HBEN, CLKIN 0.8 V Input High Voltage Vin | CS, RD, HBEN, CLKIN 2.4 Vv Input Capacitance (Note 7) Cin | CS, RD, HBEN, CLKIN 10 pF Input Current IN GB RD HBEN, VIN = 0 to Vpb oO pA LOGIC OUTPUTS Output Low Voltage VOL D11-D0/8, BUSY, CLKOUT Isink = 1.6mA 0.4 Vv Output High Voltage VOH D11-D0/8, BUSY, CLKOUT IsouRCE = 200HA 4 V Floating State Leakage Current ILKG B11-D0/8, VouT = OV to VpD 410 pA Floating State Output Capacitance (Note 7) Court 15 pF CONVERSION TIME Synchronous 3.25 _ . (13 clock cycles) MAX162 tconv | fCLk = 4MHz Asynchronous 3 3.25 | HS (12 to 13 clock cycles) Synchronous les) 5 _ (12.5 clock cycles MX7572XX05 tconv | fcLk = 2.5MHz Asynchronous 48 52 us (12 to 13 clock cycles) Synchronous 12.5 _ {12.5 clock cycles MX7572XX12 tconv | fCLk = MHz Asynchronous 12 13 us (12 to 13 clock cycles) POWER REQUIREMENTS Vop +5% for Specified Performance 4.75 5 .25 Vv IDD CS = RD = Vpo, AIN = 5V 5 7 mA Iss CS = RD = Vop, AIN = 5V 8 12 | mA Power Dissipation Vop = +5V, Vss = -15V 145 215 mw Note 1: Typical change over temp is t1L5B Note 2: Vop = +5V, Vs = -15V, FS = +5.000V, Ideal last code transition = FS -3/2LSB Note 3: Full Scale TC = AFS/AT, where AFS is full scale change from Ta = 25C to TMiN or TMAX. Note 4: Includes internal reference drift. Note 5: VacF TC = AVREF/AT, where AVReF is reference voltage change from Ta = 25C to TMIN OF TMAX. Note 6: Output current should not change during conversion. Note 7: Guaranteed by design, not subject to test. Note 8: Vss = -12V 5% for the MAX162 only. Functional operation is guaranteed by testing offset error and full scale error. MAXAIMWI Z2LSZXW/C9OILXVNMAX162/MX7572 Complete High-Speed CMOS 12-Bit ADC TIMING CHARACTERISTICS (Note 9) (Voo = +5V, Veg = -15V; Ty = Tray tO Twax unless otherwise noted.) T, = 25C MXTS7OUIKIL Moron PARAMETER SYMBOL | CONDITIONS MX7572A/B/C 572S/T/U luNits MIN TYP MAX! MIN MAX | MIN MAX CS to RD Setup Time t, 0 0 0 ns RD to BUSY Delay tp C, = S0pF 90 190 230 270 | ns Data Access Time (Note 10} ty ct OOpF se os iso 0 ns RD Pulse Width ty t, ty t, CS to RD Hold Time ts 0 0 0 ns Nata iO Time After BUSY ts 70 90 100 ns Bus Relinquish Time (Note 11) ty 20 75 | 20 85 20 90 | ns HBEN to RD Setup Time ty 0 ) ns HBEN to RD Hold Time ty 0 0 0 ns Delay Between Read Operations tio 200 200 200 ns Note 9: Timing specifications are sample tested at 25C to ensure compliance. All input control signals are specified with t, = t= Sns (10% to 90% of +5V) and timed from a voltage level of +1.6V. Note 10: +, and t, are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. Note 11: t, is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. 5V 3kQ OBN DBN 3ka C. CL I GND I a. High-Z to Von (t3) and Vox to Vou (te) b. High-Z to Voz (t3) and Vou to Vor (t) Figure 1. Load Circuits for Access Time SV 3k OBN DBN 3ko 109 10pF = neo I Ti a Vow to High-Z b. Vor to High-Z Figure 2. Load Circuits for Output Float Delay 4 MAXIMComplete High-Speed CMOS 12-Bit ADC Pin Description PIN NAME FUNCTION PIN NAME FUNCTION 1 AIN Analog Input, 0 to +5V unipolar input 19 HBEN High Byte Enable Input. This pin is used to multiplex the internal 12-bit 2 Vaer -5.25V Reference Output conversion result into the lower bit outputs (D7-D0/8). HBEN also disables 3 AGND Analog Ground conversion starts when HIGH. 11 011-D4 | Three-State Data Outputs 20 RD READ Input. This active low signal starts a conversion when CS and 12 DGND Digital Ground HBEN are low. RD also enables the output drivers when CS is low. 13-16 |D3/11-B0/8| Three-State Data Outputs _ 21 cs The CHIP SELECT Input must be low 17 | CLKIN | Clock Input. An external TTL/CMOS for the ADC to recognize RD and compatible clock may be applied to HBEN inputs. this pin or a crystal can be connected _ . between CLKIN and CLKOUT. 22 BUSY The BUSY Output is low when a conversion is in progress. 18 | CLKOUT | Clock Output. An inverted CLKIN . signal appears at this pin. 23 Vss Negative Supply, -15V for Mx7572 and -15V or -12V for MAX162. 24 Vop Positive Supply, +5V. Data Bus Output, CS & RD = LOW Pin 4 | PinS | Pin6 | Pin7 | Pin8 | Ping | Pin 10 | Pin 11 | Pin 13 | Pin 14 | Pin 15 | Pin 16 MNEMONIC* p11 D10 DS D8 D7 D6 DS D4 D3/11_ | D210 D1/9 D0/8 HBEN = LOW | DB11 DB10 DBS DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO HBEN = HIGH; 0B11 DB10 DBS DB8 LOW LOW LOW LOW DB11 DB10 DBS Obs Note: * 011... DO/8 are the ADC data output pins. DB11... DBO are the 12-bit conversion results, DB11 is the MSB. Converter Operation MAAXIAA MAX162 MX7572 OTO +SV ANALOG INPUT -5.25! Vaer OUTPUT BUTPUT Pd CONTROL > } INPUTS CLK DUT t ste CLK IN Fe Tes 00/8 of 02/10 03/11 NOTES: MAX 162 - 4MHZ CRYSTAL/CERAMIC RESONATOR. MX7572XX05 - 2.5MHz CRYSTAL/CERAMIC RESONATOR. MX7572XX12 - 1.0MHz CRYSTAL/CERAMIC RESONATOR. C1 AND C2 CAPACITANCE VALUES DEPEND ON CRYSTAL/CERAMIC RESONATOR MANUFACTURER. TYPICAL VALUES ARE FROM 0 TO 100pF. Figure 3. MAX162/MX7572 Operational Diagram MAXIM The MAX162 and MX7572 use a successive approxi- mation technique to convert an unknown analog input to a 12 bit digital output code. The control logic provides easy interface to most microprocessors. Most applications require only a few external passive components to perform the analog-to-digital function. Figure 3 shows the MAX162/MX7572 in its simplest operational configuration. Figure 4 shows the MAX162/MX7572analog equivalent circuit. The internal voltage output DAC is controlled by a successive approximation register (SAR) and has an oUtput impedance of 2.5k. The analog input is connected to the DAC output with a 2.5kQ resistor. The comparator is essentially a zero crossing detector and its output is fed back to the SAR input. Conversion start is controlled by the CS, RD and HBEN digital inputs. A conversion starts at the falling edge of CS and RD while HBEN is low. Once started, conversion cannot be stopped. The BUSY output goes low as soon as the conversion starts. BUSY may be used to control an external sample-and-hold when wide bandwidth input signals are being measured. 2LSLZXW/C9OLXVINMAX162/MX7572 Complete High-Speed CMOS 12-Bit ADC 1 JAIN 25K oe 25k COMPARATOR = l + -? | - LL | = SAR MAXIMA J | MAX 162 MX7572 IZBIT LATCH Figure 4. MAX162/MX7572 Analog Equivaient Circuit The SAR is set to half scale as soon as the CS and RD inputs go low. This reset is asynchronous with the clock input. The analog input is then compared to one half of the full scale voltage. About 30ns after the second falling edge of CLKIN (or rising edge of CLKOUT), the output of the comparator is latched into the SAR MSB bit (see Figure 5). The bit is kept if the analog input is greater than half scale, or dropped if it is smaller. The next bit (bit 11) is then set with the DAC output either at 1/4 scale (if the MSB was dropped) or 3/4 scale (if the MSB was kept). The conversion continues in this manner until the LSB is tried. Following a falling CLKIN signal, the BUSY output goes high and the SAR result is latched into the three-state output buffers. Clock Operation Ciock Oscillator Figure 6 shows the MAX162/MX7572clock circuitry. The capacitive load on the CLKOUT pin must be minimized for low power dissipation and to avoid digital coupling of the CLKOUT buffer currents to the comparator. If an external clock source is being used to drive CLKIN, CLKOUT should be left open. The external clock source must have a 50% duty cycle. If the internal oscillator is being used, a crystal/ceramic resonator should be connected between CLKOUT and CLKIN as shown in Figure 6. Cl, 18] CLK OUT MAX 162 ro MX7572 2 {o_o Dor Clock +4 Flere NOTES: MAX162 - 4MHZ CRYSTAL/CERAMIC RESONATOR. MX7572XX05 - 2.5MHz CRYSTAL/CERAMIC RESONATOR. MX7572XX12 - 1.0MHz CRYSTAL/CERAMIC RESONATOR. 1 AND C2 CAPACITANCE VALUES DEPEND ON CRYSTAL/CERAMIC RESONATOR MANUFACTURER. TYPICAL VALUES ARE FROM 0 TO 100pF. Figure 6. MAX162/MX7572 Internal Clock Circuit ae \ 7 CLK IN CLK OUT O81 (MSB) t 30ns TYP S\S\S\I\ MY NAA MS wr wy ff [ wa ~~ wr OBIO DBI 080 (LSB) Figure 5. Operating Waveforms Using an External Clock Source for CLKIN. 6 MAXIComplete High-Speed CMOS 12-Bit ADC Control input Synchronization In applications where the RD control input is not synchronized with the ADC clock, the conversion time can vary from 12 to 13 clock cycles. The SAR changes state on the falling edge of the CLKIN input (or rising edge on the CLKOUT pin). To ensure a fixed conversion time use the following guidelines for synchronization: MAX 162 For the MAX162 the RD input should go low at the falling edge of CLKIN. In this case the conversion tasts 13 clock cycles and the conversign time is 3.25ys when fox = 4MHz. If the CLKIN and RD falling edges are skewed, the skew must not be more than 50ns to ensure the 13 period conversion time (See Figure 7). The MSB is tried at the second clock falling edge, leaving two clock cycles for the external sample-and- hold to settle from hold transients. MX7572 The MX7572 RD input can go low at the rising edge of CLKIN. In this case the conversion lasts 12.5 clock cycles and the conversion time is 5us when fo. = 2.5MHz and 12.546 when fo, , = 1MHz. The delay {rom the falling edge of RD to the falling edge of CLKIN must not be less than 180ns to ensure the 12.5 clock cycle conversion time (See Figure 8). This leaves the external sample-and-hold 1.5 clock cycles to settle from hold transients. An additional half clock cycle of settling can be allowed for driving the sample-and- hold by having RD go low at the falling edge of CLKIN, similar to the MAX162. This results in a 13 cycle conversion time (5.2us when fo_, = 2.5MHz, 13us when fei = 1MHz). a_i & sem 0611 (SB) , ff f ff Sf aad be ton ~ us x 4 CLKIN BL NS NA NN {LSB} Figure 7 MAX162 RD and CLKIN For Synchronous Operation Bam | / ane ha ae L __ {cony BUSY CLKIN tf | OBII (MSB) 0B10 DBI 080 (LSB) Figure 8. MX7572 RD and CLKIN For Synchronous Operation MAXAI/VI ZLSLXW/COLXVWNMAX162/MX7572 Complete High-Speed CMOS 12-Bit ADC MAX 162 +5 MX7572 T 0 acs >J > FLIP _ "LF FLOP CONVERSION START (RISING EDGE TRIGGER] Ls = CLEAR on! ACTIVE HIGH EWABLE THREE-STATE OUTPUTS DI... 00/8 = Dell... DBO EWABLE THREE-STATE OUTPUTS OW... BB = OBI... OBB 07... 04 = LOW 03/11... 00/8 = 0811... OBS ACTIVE HIGH WOTE: OF)... 00/8 ARE THE ADC OATA OUTPUT PINS. O81]... DBO ARE THE 12-BIT CONVERSION RESULTS. Figure 9. Logic Equivalent for RD, CS and HBEN inputs Digital Interface Output Data Format The 12 output data bits can either be presented fuil parallel or in two 8 bit words. To obtain parallel output for 16 bit processors, HBEN should be kept low and the output data D11-D0 will be right justified. For a two byte data read, outputs D7-D0/8 are used. Byte selection is controlled by HBEN which multiplexes the data outputs. When HBEN is low, the lower 8 bits are presented at the data outputs. When HBEN is high, the upper 4 bits are presented with the leading 4 bits being low for D7-D0/8. Note that the 4 MSBs always appear at digital outputs D11-D8 whenever the digital drivers are enabled, re- gardless of the state of HBEN. Timing and Controi Conversion start and data read operations are con- tralled by three digital inputs; HBEN, CS and RD. Figure 9 shows the logic equivalent for the conversion and data output control circuitry. A logic low is re- quired on all three inputs to start a conversion. Once a conversion is in progress, it cannot be re-started. The BUSY output is low during the entire conversion cycle. There are two modes of operation as outlined in the timing diagrams of Figures 10-13. Slow memory mode is intended for processors that can be forced into a WAIT state for periods as long as the MAX162/MX7572 conversion time. ROM mode is for processors that cannot be forced into a wait state. In both operational modes, a processor READ operation to the ADC address starts the conversion. in the ROM mode, a second READ operation is required to access the conversion result. ts r! ts yy <= OLD DATA X NEW DATA mark 4 DB11-080 0611-080 }{ Figure 10. Slow Memory Mode, Parallel Read Timing Diagram Table 1. Slow Memory Mode, Parallel Read Data Bus Status MAX162/MX7572 Data Outputs D11 | D10 D9 D8 D7 D6 D5 D4 | 03/11 | 02/10 | D1/9 | DO/8 Read DB11 DB10 | DB9 | OBS | DB? | DB6 | DBS5 | DB4 | DB3 | DB2 | DB1 | DBO 8 MAXIMComplete High-Speed CMOS 12-Bit ADC ~ \ {im _,.& AL ] ts ae t p* ty | ts fi f 0 N } ) te tcony t hig > BUSY at ty pe 6p el ty s et ty OLD DATA NEW DATA F NEW DATA 7 MIA 087-080 Pera )\{ fies )- oLSLXW/C9LXVN Figure 11. Slow Memory Mode, Two Byte Read Timing Diagram Table 2. Slow Memory Mode, Two Byte Read Data Bus Status MAX162/ MX7572 Data Outputs D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 First Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Second Read LOW LOW LOW LOW DB11 DB10 DB9 DB8& P tz rtcony r]| te t tcony BUSY tpl pe t? rligee = el t7 se DLO DATA NEW DATA DATA ] 051-80 ee ee Figure 12. ROM Mode, Parallel Read Timing Diagram Table 3. ROM Mode, Parallel Read Data Bus Status MAX162/MX7572 Data Outputs Di | D10 DS Ds D7 D6 DS D4 | D3/11 |O2/10 | 01/9 | DO/S First Read (Old Data) DB11 | DB10 | DBS | DBS | DB7 | OBE | OBS | DB4 | DBS | DB2 | DB1 | DBO Second Read DB11 | 0610 | DBS ; OBS | DB7 | OBG | OBS | 0B4 | DBS | DB2 | DB | DBO MAXI 9MAX162/MX7572 Complete High-Speed CMOS 12-Bit ADC tg| > 5 t f CSN a, 4 BUSY ny elope eh Pi 3 e | ty [a b } ty |< DATA _+{ OLO DATA hy. 4 WEWDATA 4. NEW DATA k__ 087-080 F__DB11-DB8_ fF + 067-080 Figure 13. ROM Mode, Two Byte Read Timing Diagram Tabie 4. ROM Mode, Two Byte Read Data Bus Status MAX 162/MX7572 Data Outputs D7 D6 D5 D4 D3/11 D210 D1/9 DO/8 First Read (Old Data) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Second Read LOW LOW LOW LOW DB11 DB10 DBS DBS Third Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Slow Memory Mode, Parallel Read (HBEN = LOW) Figure 10 and Table 1 show the timing diagram and data bus status for Slow Memory Mode, Parallel Read. CS and RD going low starts the conversion and BUSY goes low indicating that the conversion is in progress. Data from the previous conversion appears at_the digital outputs. At the end of the conversion, BUSY returns high and the output latches are updated to place the digital conversion result on data outputs D11-D0/8. Slow Memory Mode, Two Byte Read For a two byte read, only outputs D7-D0/8 are used. Starting the conversion and reading the 8 LSB's is identical to the Slow Memory Mode, Paralle] Read. See Figure 11 and Table 2. A second READ operation with HBEN high places the 4 MSBs with 4 leading zeros on the data outputs D7-D0/8. The high byte read does not start another conversion since HBEN is igh. 10 ROM Mode, Parallel Read (HBEN = LOW) The ROM mode avoids placing the processor into a wait state. A conversion is started with a READ oper- ation and the 12-bits of data from the previous con- version appears at the data outputs D11-D0/8 (see Figure 12 and Table 3). This data may be disregarded if not needed. A second READ operation will access the results of the first operation and also start a new conversion. The delay between successive READ operations must be longer than the conversion time for the MAX162/MX7572. ROM Mode, Two Byte Read As in the Slow Memory Mode, only data outputs D7- DO/8 should be used for two byte reads. Figure 13 and Table 4 show the operation in this mode. A conversion is started with a READ operation with HBEN low. The data outputs present the 8 LSBs from the previous conversion and this data can be dis- regarded if not required. Two more READ operations are needed to access the conversion result. The first READ must be with HBEN high, where the 4 MSB's with 4 leading zeros are accessed. The second READ is with HBEN low, which reads in the 8 LSBs and starts a new conversion. MMAXAIS/VIComplete High-Speed CMOS 12-Bit ADC interface Application Hints Digital Bus Noise If the data bus connected to the ADC is active during a conversion, LSBs of error can be caused due to coupling from the data pins to the ADC comparator. Using the Slow Memory Mode avoids this problem by placing the processor in a wait state during the con- version. In the ROM mode, if the data bus is going to be active during the conversion, the bus should be isolated from the ADC using three-state drivers. ROM Mode Considerable_digital noise is generated in the ADC when RD or CS go high and the output data drivers are disabled after a conversion is started. This noise will feed into the ADC comparator and cause large errors if it coincides with the time the SAR is latching a decision to keep or drop a bit. To avoid this problem, RD and CS should be active for less than one clock cycle. In other words, the RD and CS low pulse should be shorter than 250ns for the MAX162, 400ns for the MX7572XX05 and 1ys for the MX7572XX12. If this cannot be done, the RD or CS signal must go high at a rising edge of CLKIN, since the comparator output is always latched at falling edges of CLKIN. Analog Considerations Application Hints Physical Layout For best system performance printed circuit boards should be used for the MAX162/MX7572. Wire wrap boards are not recommended. The layout of the board should ensure that digital and analog signal lines are kept separated from each other as much as possible. Care should be taken not to run analog and digital lines parallel to each other or digital lines underneath the MAX162/MX7572 package. ANALOG DIGITAL SUPPLY SUPPLY +15 GMO -15 +5 COMMON 4 +, + te ty + + Ly HHH | HHH H HH OHH +15 GND -15V ANALOG CIRCUITRY +15V. GND -15V SAMPLE ANO HOLD +5 (GND DIGITAL CIRCUITRY MAX162* MX7572 AGND -15V +5V | Figure 14. Power Supply Grounding Practice MAXIM Grounding Figure 14 shows the recommended system ground connections. A single point analog STAR ground should be established at pin 3 (AGND) of the MAX162/MX7572 separate from the lagic ground. All other analog grounds and pin 12 (OGND) of the MAX162/MX7572 should be connected to this STAR ground and no other digital grounds should be con- nected to this STAR point. The ground return to the power supply from this STAR ground should be low impedance for noise free operation of the ADC. Power Supply Bypassing The high speed comparator in the ADC is sensitive to high frequency noise in the Vop and Vsg power supplies. These supplies should be by-passed to the analog STAR ground with O.1uF and 10uF by-pass capacitors with minimum lead length for supply noise rejection. If the +5V power supply is very noisy, a small (10-20 ohms) resistor can be connected as shown in Figure 14 to filter external noise. internal Reference The MAX162/MX7572 has an internal buried zener reference which provides the DAC reference voltage. The reference voltage is -5.25V +1% and has a low temperature coefficient. The reference output is available at pin 2, and should be bypassed to analog ground (pin 3) with a 47uF tantalum capacitor in parallel with O.juF capacitor to minimize noise and provide low impedance at high frequencies. This by-pass capacitor must not be less than 4.7yF. The internal reference output buffer can sink upto SOQuA. Driving The Analog Input The input signal leads to AGND and AIN should be as short as possible to minimize noise pick-up. If the leads must be long use shielded cables to minimize noise pick-up. The input impedance at the AIN pin is typically 2.5kQ. The amplifier driving AIN must have low enough DC output impedance for low gain error. Furthermore, low AC output impedance is also required since the analog input current is modulated at the clock rate during a conversion (4MHz for MAX162 and 2.5 or 1MHz for the MX7572). The output impedance of the driving amplifier is equal to its open loop output impedance divided by the loop gain at the frequency of interest. MX7572 The MX7572 maximum clock rate of 2.5MHz makes it possible to drive it with amplifiers like the OP-42, AD711 or OP-27. At 1MHz clock rate a MAX400 or OP-07 can also be used. MAX162 The MAX162 with a maximum 4MHz clock rate might cause settling problems with the above amplifiers. An LF356, LF400 or LT1056 can be used to drive the input. Alternatively, an emitter follower buffer inside the feedback loop of a OP-42, AD711 or OP-27 can be used to improve high frequency output impedance. 11 ZLSZLXW/COLXVINMAX162/MX7572 Complete High-Speed CMOS 12-Bit ADC MAX162/MX7572 to Sample-and-Hold interface The analog input to the ADC must be stable to within 1/2 LSB during the entire conversion for specified 12 bit accuracy. This limits the input signal bandwidth to less than 6Hz for sinusoidal inputs, even when using the faster MAX162. For higher bandwidth signals a sample-and-hold should be used. The BUSY output from the MAX162/MX7572 may be used to provide the TRACK/HOLD signal to the sample-and-hold amplifier. However, since the ADC's DAC is switched at approximately the same time as the BUSY signal goes low, the switching transients at the output of the sample-and-hold caused by the DAC switching may result in code dependent errors due to the aperture delay of the sample-and-hold. A NAND gate may be used to ensure that the sample- and-hold switches to the hold mode BEFORE any disturbances as shown in Figures 15 & 16. The NAND gate solution works only_if the width of the RD pulse is wider than the RD to BUSY delay in the MAX162/ MX7572. If this is not the case, use a flip flop which ts set by the falling edge of RD and reset by the rising edge of BUSY. For synchronous RD and CLKIN as described above, the hold settling time allowed for the sample-and- hold is 500ns, 600ns and 1.5us for the MAX162, MX7572XX05 and MX7572XX12 respectively. To achieve the maximum sampling rate, the MAX162/ MX7572 data must be read within the time allowed for the sample-and-hold to acquire a new input voltage. MX7572 Figure 15 shows an AD585 sample-and-hold to MX7572 interface. The MX7572 RD input and BUSY output are used to put the AD585 in hold mode when a conversion is in progress. In this example the analog input range is +2.5V but other voltage ranges can be configured differently as explained later. The maximum sampling rate is 125kHz with a 2.5MHz clock and 64.5kHz with a 1MHz clock allowing for a 3us sampile-and-hold acquisition time. Although this circuit works quite well for the 1MHz clock rate, at the 2.5MHz clock rate a faster sample- and-hold amplifier such as the HA-5320 is recom- mended. 0} CE] Olaf Ou n 24 % T =a +5 Ol uF I +Vs Von 10sF a! = Hou iz -< J _ BUSY _ I o\ = | nye HOLO RD CONTROL 14 20 INPUTS -15V > -Vs Vout AIN HBEN oO 4 8 1 ore uF 9 19 * Rl Os Apses* SNF = Vin i . 2 Vaer _ 12 R3 , MAXIM 39k \ 41 pF = OlpF MAX162 + IW + ANALOG MX7572 INPUT = -2.5V TO +2.5V - 3 AGND R4 eNO Vs = 82k r 33 -15 1OuF Out +| ] *ADOTIONAL PINS OMITTED FOR CLARITY Figure 15. MX7572AD585 Sample-and-Hold Interface 12 MAXAL/VIComplete High-Speed CMOS 12-Bit ADC 1 _ . A uF =~ l0uF 9 24 [_ t T at + oY | oo aL 2 | ow la cs o\'e 14 S/H = 120 CONTROL Ao oP inputs 7 1 1 -I5V 1 -Vs Vout AIN HBEN a oO Ol uF [uF 3 MAXIM + HA5320 sen 2 A MAX162 82k MX7572 = -Vin AA Vi = i REF pcno 12 RS ct Vin * Olaf ANALOG INPUT = 3 -2.5V TO +2.5V v0 AGND RA enn Vss = 82k a 3 -15V ant 1OuF Ol pF + | *ADOTIONAL PINS OMITTED FOR CLARITY Figure 16. MAX 162/MX7572HA5320 Sampie-and-Hold Interface MAX162 Figure 16 shows the MAX162 to HA5320 interface. The maximum sampling rate is 210kHz with a 4MHz clock which allows for a 1.5us acquisition time. The HA5320 can also be replaced by a HA5330 for higher throughput. Unipolar input Operation Figure 17 shows the nominal input/output transfer function of the MAX162/MX7572 Code transitions occur half way between successive integer LSB values. The output coding is binary with 1LSB = 1.22mvV (5V/4096). Offset and Full Scale Adjustment In applications where the offset and full scale range have to be adjusted for the ADC, use the circuit shown in Figure 18. Note that the amplifier shown MAXLWVI could also have been a sample-and-hold. The offset should be adjusted first. Apply 1/2 LSB (0.61 mV) at the analog input and adjust the offset of the amplifier until the digital output code changes between 0000 0000 0000 and 0000 0000 0001. To adjust the full scale range, apply FS-3/2LSB (4.99817V) at the analog input and adjust R1 until the output code changes between 1111 1111 1110 and 4141 1111 1111. Bipolar input Operation Bipolar operation can be achieved in two modes: non-inverting and inverting. For both cases the am- plifier shown in the circuits can be replaced by the AD585 or HA5320 sample-and-hold amplifiers. Several different input ranges are possible by se- lecting the values for the scaling resistors as shown in Tables 5 and 6. 8 ZZSZXW/C9OLXVWNMAX162/MX7572 Complete High-Speed CMOS 12-Bit ADC OUTPUT FULL SCALE CODE TRANSITION W... UH Wn... 110 W... 101 7 FS = 5V y iLSB = _FS 096 . On .. 010 1 2 3 FS LSB LSBS LSBS FS - 1LSB AIN, INPUT VOLTAGE (IN TERMS OF LSBS) Figure 17. MAX162/MX7572 Transfer Function AMPLIFIER 0-5V OR S/H R3 ANALOG . INPUT Vin } Al ADDITIONAL PINS OMITTED FOR CLARITY Figure 18. Full-Scale Adjustment Figure 19 shows the bipolar operation in the non- inverting mode, where the output coding is offset binary. Figure 20 shows the ideal transfer function for this mode. Figure 21 shows the bipolar operation in the inverting mode, where the output coding is complementary offset binary. Figure 20 shows the ideal transfer func- tion for the circuit in Figure 21. The resistors used in bipolar applications should be of the same type and from the same manufacturer to obtain low temperature drifts. 0.1% resistors are recommended for applications where offset and full scale adjustments must be made in bipolar circuits. If high tolerances are used, larger value potentiometers must be used and this results in poor sensitivity and higher temperature drifts. 4 ANALOG INPUT Vy AMPLIFIER OR S/H Rg" ) U ain a hiKo MAXIM Aa Ol MAX162 7 a nae MX 7572* sens 2 01% 5.26V 2) veer Ol uf cAI 3 *ADDITIONAL PINS OMITTED FOR CLARITY **OMIT IF ERROR ADJUST IS NOT REQUIRED Figure 19. MAX162/MX7572 Non-inverting Bipolar Operation Table 5. Resistor and Potentiometer Values Required for Oftset and Gain Adjustment of Figure 19 V,, Range | R3" | R4* | R, | Rg |1/2LSB |FS/2-3/2LSBs (Volts) | (kQ) | (kQ) | (2) | (O) | (mv) (Volts) +25 3.83 | 8.25 | 500 | 500 | 0.61 2.49817 +5.0 33.2 | 16.9 | 500 | 1000] 1.22 4.99634 +10.0 475 | 9.53 | 500 | 500 | 2.44 | 9.99268 Notes: * R3 and R4 have a 0.1% tolerance. All resistors are standard EIA/MIL decade values. 5- INVERTING NONINVERTING FIGURE ZI FIGURE 19 V1. TD by 11... 110 Li T ks, ; 100... 010+ Lo 100... 001 4 6 L, 100...000 -- yp - =~ + - On... 1+ LE se On... 10+ LS ont... 101 Lo t | 7 000... 001 ++ L. 000 . . . 000 Ly $$ ov Vin INPUT VOLTAGE Figure 20. Ideal Input/Output Transfer Characteristic for the Bipolar circuits in Figures 19 and 21. MAXI/ViFor Non-inverting (Figure 19) Complete High-Speed CMOS 12-Bit ADC Offset and Full Scale Adjustment Offset should always be adjusted before full scale. For both circuits apply +1/2LSB to the analog input (see tables 5 and 6) and adjust Rz until the output code flickers between the following codes: For inverting (Figure 21) the following codes: For Non-inverting (Figure 19) For inverting (Figure 21) 1000 0000 0000 1000 0000 0001 O11t 1117 1911 0171 1111 1110 Apply FS-3/2LSB (see tables 5 and 6) to the input and adjust Rg until the ADC output code flickers between 1171 11711 1110 149711117 1711 0000 0000 0001 0000 0000 0000 anauog PoP INPUT yy R3 3 Rz 3 + Ti AIN MAAXIM | AGND MAX 162 MX7572* -5.25V ADDITIONAL PINS OMITTED FOR CLARITY Var Figure 21. MAX162/MX7572 Inverting Bipolar Operation Table 6. Resistor and Potentiometer Values Required tor Offset and Gain Adjustment of Figure 21 Vy Range] R1* | R2* | R3* | R, | Rg |1/2LSB Fs/2-3/2LSBs (Volts) [(&) | (KA) }(KQ)| (2) | (2) | (mvp | (Volts) +25 20 |20.5|42.2|2000/1000/ 0.61 | 2.49817 +5.0 20 110.2] 21 |1000|1000] 1.22 | 4.99634 +10.0 | 20 15.11|10.5|500 [1000] 2.44 | 9.99268 Notes: * Ri, R2, and R3 have a 0.1% tolerance. All resistors are standard EIA/MIL decade values. MAXAI/VI AGNO Veer 0.128" (3.25mm) AIN oo Chip Topography Vss BUSY 15 oLSZXW/COLXVNComplete High-Speed CMOS 12-Bit ADC __Ordering Information (continued) MAX162/MX7572 ERROR PART TEMP.RANGE PACKAGE* (LSB) Sus CONVERSION TIME MX7572JN05 OC to+70C _Plastic DIP +1 MX7572KNO05 OC to+70C Plastic DIP +1 MX7572LNO05 OC to +70C _~Plastic DIP 21/2 MX7572JCWGOS OC to +70C Wide SO +1 MX7572KCWG05 OC to +70C =~ Wide SO +1 MX7572LCWGOS OC to +70C Wide SO 41/2 MX7572AQ05 -40C to +85C = CERDIP +1 MX7572BQ05 -40C to +85C = CERDIP +1 MX7572CQ05 -40C to +85C = CERDIP +1/2 MX7572SQ05 -65C to +125C =CERDIP +1 MX7572TQ05 -66C to +125C CERDIP +1 MX7572UQ05 -58C to+125C + CERDIP +1/2 12us CONVERSION TIME MX7572JN12 OC to +70C _Plastic DIP +1 MX7572KN12 OC ta +70C __~Plastic DIP +1 MX7572LN12 0OC to +70C ~Plastic DIP +2 MX7572JCWG12 0Cta+70C WideSO +1 MX7572KCWG1i2 0C to +70C ~=3=Wide SO +1 MxX7572LCWG12 0C ta +70C ~3 Wide SO +1/2 MX7572AQ12 -40C to +B86C = CERDIP +1 MX7572BQ12 -40C to +85C =CERDIP +1 MX7572CQ12 -40C to +85C = CERDIP +1/2 MX75725012 -66C to+1265C = CERDIP +1 MX7572TQ12 65C to+125C | CERDIP +1 MX7572UQ12 -56C to+125C CERDIP t1/2 *All devices24 lead packages Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 Printed USA MAAXIAA is a registered trademark of Maxim Integrated Products. 1991 Maxim Integrated Products