PIC12C5XX In-Circuit Serial Programming for PIC12C5XX OTP MCUs This document includes the programming specifications for the following devices: 1.0 * PIC12C508A * PIC12C509A * PIC12CE518 * PIC12CE519 PROGRAMMING THE PIC12C5XX PDIP, SOIC, JW VDD 1 GP5/OSC1/CLKIN 2 GP4/OSC2/CLKOUT 3 GP3/MCLR/Vpp 4 PIC12C5XX PIC12C5XXA PIC12CE5XXA * PIC12C508 * PIC12C509 Pin Diagram 8 VSS 7 GP0 6 GP1 5 GP2/T0CKI The PIC12C5XX can be programmed using a serial method. Due to this serial programming, the PIC12C5XX can be programmed while in the user's system increasing design flexibility. This programming specification applies to PIC12C5XX devices in all packages. 1.1 Hardware Requirements The PIC12C5XX requires two programmable power supplies, one for VDD (2.0V to 6.5V recommended) and one for VPP (12V to 14V). Both supplies should have a minimum resolution of 0.25V. 1.2 Programming Mode The programming mode for the PIC12C5XX allows programming of user program memory, special locations used for ID, and the configuration word for the PIC12C5XX. 2000 Microchip Technology Inc. DS30557E-page 1 PIC12C5XX 2.0 PROGRAM MODE ENTRY The program/verify test mode is entered by holding pins DB0 and DB1 low while raising MCLR pin from VIL to VIHH. Once in this test mode the user program memory and the test program memory can be accessed and programmed in a serial fashion. The first selected memory location is the fuses. GP0 and GP1 are Schmitt trigger inputs in this mode. Incrementing the PC once (using the increment address command) selects location 0x000 of the regular program memory. Afterwards all other memory locations from 0x001-01FF (PIC12C508/CE518), 0x00103FF (PIC12C509/CE519) can be addressed by incrementing the PC. If the program counter has reached the last user program location and is incremented again, the on-chip special EPROM area will be addressed. (See Figure 2-2 to determine where the special EPROM area is located for the various PIC12C5XX devices). 2.1 Programming Method The programming technique is described in the following section. It is designed to guarantee good programming margins. It does, however, require a variable power supply for VCC. 2.1.1 PROGRAMMING METHOD DETAILS Essentially, this technique includes the following steps: 1. 2. a) Perform blank check at VDD = VDDmin. Report failure. The device may not be properly erased. Program location with pulses and verify after each pulse at VDD = VDDP: where VDDP = VDD range required during programming (4.5V - 5.5V). Programming condition: VPP = 13.0V to 13.25V VDD = VDDP = 4.5V to 5.5V VPP must be VDD + 7.25V to keep "programming mode" active. b) 5. 6. VDDmin is the minimum operating voltage spec. for the part. VDDmax is the maximum operating voltage spec. for the part. 2.1.2 VPP: VPP can be a fixed 13.0V to 13.25V supply. It must not exceed 14.0V to avoid damage to the pin and should be current limited to approximately 100mA. VDD: 2.0V to 6.5V with 0.25V granularity. Since this method calls for verification at different VDD values, a programmable VDD power supply is needed. Current Requirement: 40mA maximum Microchip may release devices in the future with different VDD ranges which make it necessary to have a programmable VDD. It is important to verify an EPROM at the voltages specified in this method to remain consistent with M i c r o c h i p ' s t e s t s c r e e n i n g . Fo r ex a m p l e , a PIC12C5XX specified for 4.5V to 5.5V should be tested for proper programming from 4.5V to 5.5V. Note: Any programmer not meeting the programmable VDD requirement and the verify at VDDmax and VDDmin requirement may only be classified as "prototype" or "development" programmer but not a production programmer. 2.1.3 SOFTWARE REQUIREMENTS Certain parameters should be programmable (and therefore easily modified) for easy upgrade. a) b) c) Verify condition: Pulse width Maximum number of pulses, present limit 8. Number of over-programming pulses: should be = (A * N) + B, where N = number of pulses required in regular programming. In our current algorithm A = 11, B = 0. VPP VDD + 7.5V but not to exceed 13.25V 2.2 If location fails to program after "N" pulses, (suggested maximum program pulses of 8) then report error as a programming failure. Program Memory Cells: When programming one word of EPROM, a programming pulse width (TPW) of 100s is recommended. Note: 4. SYSTEM REQUIREMENTS Clearly, to implement this technique, the most stringent requirements will be that of the power supplies: VDD = VDDP 3. Verify all locations (using speed verify mode) at VDD = VDDmin Verify all locations at VDD = VDDmax Device must be verified at minimum and maximum specified operating voltages as specified in the data sheet. Once location passes "Step 2", apply 11X over programming, i.e., apply 11 times the number of pulses that were required to program the location. This will guarantee a solid programming margin. The over programming should be made "software programmable" for easy updates. Program all locations. DS30557E-page 2 Programming Pulse Width The maximum number of programming attempts should be limited to 8 per word. After the first successful verify, the same location should be over-programmed with 11X over-programming. Configuration Word: The configuration word for oscillator selection, WDT (watchdog timer) disable and code protection, and MCLR enable, requires a programming pulse width (TPWF) of 10ms. A series of 100s pulses is preferred over a single 10ms pulse. 2000 Microchip Technology Inc. PIC12C5XX FIGURE 2-1: PROGRAMMING METHOD FLOWCHART Start Blank Check @ VDD = VDDmin Report Possible Erase Failure Continue Programming at user's option No Pass? Report Programming Failure Yes Yes Program 1 Location @ VPP = 13.0V to 13.25V VDD = VDDP No Pass? No N > 8? N=N+1 (N = # of program pulses) Yes Increment PC to point to next location, N = 0 Apply 11N additional program pulses No All locations done? Yes Verify all locations @ VDD = VDDmin No Pass? Report verify failure @ VDDmin Yes Verify all locations DD VV DD max. @VV DD= = DD max No Pass? Report verify failure @ VDDmax Yes Now program Configuration Word Verify Configuration Word @ VDDmax & VDDmin Done 2000 Microchip Technology Inc. DS30557E-page 3 PIC12C5XX FIGURE 2-2: PIC12C5XX SERIES PROGRAM MEMORY MAP IN PROGRAM/VERIFY MODE Address 11 (Hex) 000 NNN Bit Number 0 User Program Memory (NNN + 1) x 12 bit TTT 0 0 ID0 TTT + 1 0 0 0 0 ID1 ID2 0 0 ID3 TTT + 2 TTT + 3 For Customer Use (4 x 4 bit usable) For Factory Use TTT + 3F (FFF) Configuration Word 5 bits NNN Highest normal EPROM memory address. NNN = 0x1FF for PIC12C508/CE518. NNN = 0x3FF for PIC12C509/CE519. Note that some versions will have an oscillator calibration value programmed at NNN TTT Start address of special EPROM area and ID locations. DS30557E-page 4 2000 Microchip Technology Inc. PIC12C5XX 2.3 Special Memory Locations The highest address of program memory space is reserved for the internal RC oscillator calibration value. This location should not be overwritten except when this location is blank, and it should be verified, when programmed, that it is a MOVLW XX instruction. The ID Locations area is only enabled if the device is in programming/verify mode. Thus, in normal operation mode only the memory location 0x000 to 0xNNN will be accessed and the Program Counter will just roll over from address 0xNNN to 0x000 when incremented. The configuration word can only be accessed immediately after MCLR going from VIL to VHH. The Program Counter will be set to all '1's upon MCLR = VIL. Thus, it has the value "0xFFF" when accessing the configuration EPROM. Incrementing the Program Counter once causes the Program Counter to roll over to all '0's. Incrementing the Program Counter 4K times after reset (MCLR = VIL) does not allow access to the configuration EPROM. 2.3.1 2.4 Program/Verify Mode The program/verify mode is entered by holding pins GP1 and GP0 low while raising MCLR pin from VIL to VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial. GP0 and GP1 are Schmitt Trigger inputs in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). Note: The MCLR pin should be raised from VIL to VIHH within 9 ms of VDD rise. This is to ensure that the device does not have the PC incremented while in valid operation range. CUSTOMER ID CODE LOCATIONS Per definition, the first four words (address TTT to TTT + 3) are reserved for customer use. It is recommended that the customer use only the four lower order bits (bits 0 through 3) of each word and filling the eight higher order bits with '0's. A user may want to store an identification code (ID) in the ID locations and still be able to read this code after the code protection bit was programmed. EXAMPLE 2-1: CUSTOMER CODE 0xD1E2 The Customer ID code "0xD1E2" should be stored in the ID locations 0x200-0x203 like this (PIC12C508/ 508A/CE518): 200: 201: 202: 203: 0000 0000 0000 0000 0000 0000 0000 0000 1101 0001 1110 0010 Reading these four memory locations, even with the code protection bit programmed would still output on GP0 the bit sequence "1101", "0001", "1110", "0010" which is "0xD1E2". Note: All other locations in PICmicro(R) MCU configuration memory are reserved and should not be programmed. 2000 Microchip Technology Inc. DS30557E-page 5 PIC12C5XX 2.4.1 PROGRAM/VERIFY OPERATION All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1 s is required between a command and a data word (or another command). The GP1 pin is used as a clock input pin, and the GP0 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (GP1) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin GP0 is required to have a minimum setup and hold time (see AC/DC specs) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to have a minimum delay of 1 s between the command and the data. After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. Therefore, during a read operation the LSB will be transmitted onto pin GP0 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1 s delay is also specified between consecutive commands. TABLE 2-1: The commands that are available are listed in Table . COMMAND MAPPING Command Mapping (MSB ... LSB) Data Load Data 0 0 0 0 1 0 0, data(14), 0 Read Data 0 0 0 1 0 0 0, data(14), 0 Increment Address 0 0 0 1 1 0 Begin programming 0 0 1 0 0 0 End Programming 0 0 1 1 1 0 Note: The clock must be disabled during in-circuit programming. DS30557E-page 6 2000 Microchip Technology Inc. PIC12C5XX 2.4.1.1 LOAD DATA After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. Because this is a 12 bit core, the two msb's of the data word are ignored. A timing diagram for the load data command is shown in Figure 5-1. 2.4.1.2 READ DATA After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The GP0 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. Because this is a 12bit core, the two MSB's of the data are unused and read as '0'. A timing diagram of this command is shown in Figure 5-2. 2.4.1.3 INCREMENT ADDRESS The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.4.1.4 2.5 Programming Algorithm Requires Variable VDD The PIC12C5XX uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VCC range required during programming. VDD min. = minimum operating VDD spec for the part. VDDmax = maximum operating VDD spec for the part. Programmers must verify the PIC12C5XX at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC12C5XX with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. BEGIN PROGRAMMING A load data command must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100s programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 2.4.1.5 END PROGRAMMING After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time. 2000 Microchip Technology Inc. DS30557E-page 7 PIC12C5XX 3.0 CONFIGURATION WORD The PIC12C5XX family members have several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to select various device configurations. Figure 3-1 provides an overview of configuration bits. FIGURE 3-1: Bit Number: PIC12C5XX CONFIGURATION WORD BIT MAP 11 10 9 8 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- MCLRE CP WDTE FOSC1 FOSC0 bit 11-5:Reserved, '-' write as '0' for PIC12C5XX bit 4: MCLRE, Master Clear pin Enable Bit 0 = MCLR internally connected to Vdd 1 = MCLR pin enabled bit 3: CP, Code Protect Enable Bit 1 = Code Memory Unprotected 0 = Code Memory Protected bit 2: WDTE, WDT Enable Bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC<1:0>, Oscillator Selection Bit 11: ExtRC oscillator 10: IntRC oscillator 01: XT oscillator 00: LP oscillator DS30557E-page 8 2000 Microchip Technology Inc. PIC12C5XX 4.0 CODE PROTECTION The program code written into the EPROM can be protected by writing to the CP bit of the configuration word. In PIC12C5XX, it is still possible to program and read locations 0x000 through 0x03F, after code protection. Once code protection is enabled, all protected segments read '0's (or "garbage values") and are prevented from further programming. All unprotected 4.1 segments, including ID locations and configuration word, read normally. These locations can be programmed. Once code protection is enabled, all code protected locations read 0's. All unprotected segments, including the internal oscillator calibration value, ID, and configuration word read as normal. Embedding Configuration Word and ID Information in the Hex File To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. TABLE 4-1: CODE PROTECTION PIC12C508 To code protect: * (CP enable pattern: XXXXXXXX0XXX) Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0xFFF) Read Enabled, Write Enabled Read Enabled, Write Enabled [0x00:0x3F] Read Enabled, Write Enabled Read Enabled, Write Enabled [0x40:0x1FF] Read Disabled (all 0's), Write Disabled Read Enabled, Write Enabled ID Locations (0x200 : 0x203) Read Enabled, Write Enabled Read Enabled, Write Enabled PIC12C508A To code protect: * (CP enable pattern: XXXXXXXX0XXX) Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled [0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled [0x40:0x1FE] Read disabled (all 0's), Write Disabled Read enabled, Write Enabled 0x1FF Oscillator Calibration Value Read enabled, Write Enabled Read enabled, Write Enabled ID Locations (0x200 : 0x203) Read enabled, Write Enabled Read enabled, Write Enabled PIC12C509 To code protect: * (CP enable pattern: XXXXXXXX0XXX)) Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled [0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled [0x40:0x3FF] Read disabled (all 0's), Write Disabled Read enabled, Write Enabled ID Locations (0x400 : 0x403) Read enabled, Write Enabled Read enabled, Write Enabled 2000 Microchip Technology Inc. DS30557E-page 9 PIC12C5XX PIC12C509A To code protect: * (CP enable pattern: XXXXXXXX0XXX)) Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled [0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled [0x40:0x3FE] Read disabled (all 0's), Write Disabled Read enabled, Write Enabled 0x3FF Oscillator Calibration Value Read enabled, Write Enabled Read enabled, Write Enabled ID Locations (0x400 : 0x403) Read enabled, Write Enabled Read enabled, Write Enabled PIC12CE518 To code protect: * (CP enable pattern: XXXXXXXX0XXX) Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled [0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled [0x40:0x1FE] Read disabled (all 0's), Write Disabled Read enabled, Write Enabled 0x1FF Oscillator Calibration Value Read enabled, Write Enabled Read enabled, Write Enabled ID Locations (0x200 : 0x203) Read enabled, Write Enabled Read enabled, Write Enabled PIC12CE519 To code protect: * (CP enable pattern: XXXXXXXX0XXX)) Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled [0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled [0x40:0x3FF] Read disabled (all 0's), Write Disabled Read enabled, Write Enabled ID Locations (0x400 : 0x403) Read enabled, Write Enabled Read enabled, Write Enabled DS30557E-page 10 2000 Microchip Technology Inc. PIC12C5XX 4.2 Checksum 4.2.1 CHECKSUM CALCULATIONS Checksum is calculated by reading the contents of the PIC12C5XX memory locations and adding up the opcodes up to the maximum user addressable location, (not including the last location which is reserved for the oscillator calibration value) e.g., 0x1FE for the PIC12C508/CE518. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC12C5XX family is shown in Table 4-2. The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. The oscillator calibration value location is not used in the above checksums. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The least significant 16 bits of this sum is the checksum. TABLE 4-2: CHECKSUM COMPUTATION Code Protect Checksum* Blank Value 0x723 at 0 and max address PIC12C508 OFF ON SUM[0x000:0x1FE] + CFGW & 0x01F SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EE20 EDF7 DC68 D363 PIC12C508A OFF ON SUM[0x000:0x1FE] + CFGW & 0x01F SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EE20 EDF7 DC68 D363 PIC12C509 OFF ON SUM[0x000:0x3FE] + CFGW & 0x01F SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EC20 EBF7 DA68 D163 PIC12C509A OFF ON SUM[0x000:0x3FE] + CFGW & 0x01F SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EC20 EBF7 DA68 D163 PIC12CE518 OFF ON SUM[0x000:0x1FE] + CFGW & 0x01F SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EE20 EDF7 DC68 D363 PIC12CE519 OFF ON SUM[0x000:0x3FE] + CFGW & 0x01F SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EC20 EBF7 DA68 D163 Device Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND 2000 Microchip Technology Inc. DS30557E-page 11 PIC12C5XX 5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS TABLE 5-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (20C recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. Sym. Characteristic PD1 VDDP Supply voltage during programming PD2 IDDP Supply current (from VDD) during programming Min. Typ. Max. Units 4.75 5.0 5.25 V 20 mA Conditions General PD3 VDDV Supply voltage during verify VDDmin VDDmax V Note 1 PD4 VIHH1 Voltage on MCLR/VPP during programming 12.75 13.25 V Note 2 PD5 VIHH2 PD6 IPP Programming supply current (from VPP) PD9 VIH1 (GP1, GP0) input high level 0.8 VDD V Schmitt Trigger input PD8 VIL1 (GP1, GP0) input low level 0.2 VDD V Schmitt Trigger input Voltage on MCLR/VPP during verify VDD + 4.0 13.5 50 mA Serial Program Verify P1 TR MCLR/VPP rise time (VSS to VHH) 8.0 s P2 Tf MCLR Fall time 8.0 s P3 Tset1 Data in setup time before clock 100 ns P4 Thld1 Data in hold time after clock 100 ns P5 Tdly1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 s P6 Tdly2 Delay between clock to clock of next command or data 1.0 s P7 Tdly3 Clock to date out valid (during read data) 200 ns P8 Thld0 Hold time after MCLR 2 s Note 1: Program must be verified at the minimum and maximum VDD limits for the part. 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode. DS30557E-page 12 2000 Microchip Technology Inc. PIC12C5XX FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 100ns 0 0 0 GP1 (CLOCK) GP0 (DATA) 0 1 2 1ms min. 1 6 4 5 15 0 0 0 P5 P3 P3 1ms min. P4 P4 } } } } 100ns min. 100ns min. Program/Verify Mode Reset FIGURE 5-2: 3 READ DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 100ns 1 0 0 GP1 (CLOCK) GP0 (DATA) 0 0 2 1ms min. 1 6 3 4 5 15 P7 0 P5 P4 1ms min. P3 } } 100ns min. GP0 input GP0 = output Program/Verify Mode Reset FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP P6 1 2 0 1 3 4 5 6 0 0 0 1ms min. Next Command 1 2 GP1 (CLOCK) GP0 (DATA) 1 0 0 P5 P3 P4 1ms min. } } 100ns min Program/Verify Mode Reset 2000 Microchip Technology Inc. DS30557E-page 13 PIC12C5XX NOTES: DS30557E-page 14 2000 Microchip Technology Inc. PIC12C5XX NOTES: 2000 Microchip Technology Inc. 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Printed in the USA. 5/00 Italy United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5858 Fax: 44-118 921-5835 05/16/00 Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS30557E-page 16 2000 Microchip Technology Inc.