Quad-Channel Digital Isolators
Data Sheet ADuM2400/ADuM2401/ADuM2402
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Low power operation
5 V operation
1.0 mA per channel maximum @ 0 Mbps to 2 Mbps
3.5 mA per channel maximum @ 10 Mbps
31 mA per channel maximum @ 90 Mbps
3 V operation
0.7 mA per channel maximum @ 0 Mbps to 2 Mbps
2.1 mA per channel maximum @ 10 Mbps
20 mA per channel maximum @ 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package version (RW-16)
16-lead SOIC wide body enhanced creepage version (RI-16)
Safety and regulatory approvals (RI-16 package)
UL recognition: 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
IEC 60601-1: 250 V rms (reinforced)
IEC 60950-1: 400 V rms (reinforced)
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 846 V peak
APPLICATIONS
General-purpose, high voltage, multichannel isolation
Medical equipment
Motor drives
Power supplies
GENERAL DESCRIPTION
The ADuM240x1 are 4-channel digital isolators based on Analog
Devices, Inc., iCoupler® technology. Combining high speed CMOS
and monolithic air core transformer technology, these isolation
components provide outstanding performance characteristics that
are superior to alternatives, such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with opto-
couplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, nonlinear transfer functions, and tempera-
ture and lifetime effects are eliminated with the simple
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
V
IA
V
IB
V
IC
V
ID
NC
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
V
OD
V
E2
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
05007-001
ADuM2400
Figure 1. ADuM2400
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
V
IA
V
IB
V
IC
V
OD
V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
V
ID
V
E2
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
05007-002
ADuM2401
Figure 2. ADuM2401
DECODE ENCODE
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
V
IA
V
IB
V
OC
V
OD
V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
IC
V
ID
V
E2
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
05007-003
ADuM2402
Figure 3. ADuM2402
iCoupler digital interfaces and stable performance characteristics.
Furthermore, iCoupler devices run at one-tenth to one-sixth
the power of optocouplers at comparable signal data rates.
The ADuM240x isolators provide four independent isolation
channels in a variety of channel configurations and data rates (see
the Ordering Guide). The ADuM240x models operate with the
supply voltage of either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In
addition, the ADuM240x provide low pulse width distortion (<2 ns
for CRWZ grade) and tight channel-to-channel matching (<2 ns
for CRWZ grade). The ADuM240x isolators have a patented
refresh feature that ensures dc correctness in the absence of input
logic transitions and during power-up/power-down conditions.
ADuM2400/ADuM2401/ADuM2402 Data Sheet
Rev. E | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 5
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 7
Package Characteristics ............................................................. 10
Regulatory Information............................................................. 10
Insulation and Safety-Related Specifications.......................... 10
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 11
Recommended Operating Conditions .................................... 11
Absolute Maximum Ratings ......................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions......................... 13
Typical Performance Characteristics ........................................... 16
Application Information................................................................ 18
PC Board Layout ........................................................................ 18
Propagation Delay-Related Parameters................................... 18
DC Correctness and Magnetic Field Immunity.......................... 18
Power Consumption .................................................................. 19
Insulation Lifetime..................................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
2/12—Rev. D to Rev. E
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Change to PC Board Layout Section............................................ 18
8/11—Rev. C to Rev D
Added 16-Lead SOIC_IC ..................................................Universal
Changes to Features Section and General Description
Section................................................................................................ 1
Changes to Table 5 and Table 6..................................................... 10
Changes to Table 8 Endnote.......................................................... 11
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 21
7/08—Rev. B to Rev. C
Changes to Layout ............................................................................ 1
Changes to Table 6.......................................................................... 10
6/07—Rev. A to Rev. B
Updated VDE Certification Throughout.......................................1
Changes to Features and Note 1 ......................................................1
Changes to Figure 1, Figure 2, and Figure 3 ..................................1
Changes to Regulatory Information ............................................ 10
Changes to Table 7.......................................................................... 11
Changes to Insulation Lifetime Section ...................................... 20
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide.......................................................... 21
1/06—Rev. 0 to Rev. A
Changes to Regulatory Information section............................... 13
Updated Outline Dimensions....................................................... 23
Changes to Ordering Guide.......................................................... 23
9/05—Revision 0: Initial Version
Data Sheet ADuM2400/ADuM2401/ADuM2402
Rev. E | Page 3 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.53 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.21 mA
ADuM2400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 2.2 2.8 mA DC to 1 MHz logic signal frequency
VDD2 Supply Current IDD2 (Q) 0.9 1.4 mA DC to 1 MHz logic signal frequency
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current IDD1 (10) 8.6 10.6 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10) 2.6 3.5 mA 5 MHz logic signal frequency
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current IDD1 (90) 70 100 mA 45 MHz logic signal frequency
VDD2 Supply Current IDD2 (90) 18 25 mA 45 MHz logic signal frequency
ADuM2401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.8 2.4 mA DC to 1 MHz logic signal frequency
VDD2 Supply Current IDD2 (Q) 1.2 1.8 mA DC to 1 MHz logic signal frequency
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current IDD1 (10) 7.1 9.0 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10) 4.1 5.0 mA 5 MHz logic signal frequency
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current IDD1 (90) 57 82 mA 45 MHz logic signal frequency
VDD2 Supply Current IDD2 (90) 31 43 mA 45 MHz logic signal frequency
ADuM2402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal frequency
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 or VDD2 Supply Current IDD1 (10), IDD2 (10) 5.6 7.0 mA 5 MHz logic signal frequency
90 Mbps (CRWZ Grade Only)
VDD1 or VDD2 Supply Current IDD1 (90), IDD2 (90) 44 62 mA 45 MHz logic signal frequency
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 2.0 V
Logic Low Input Threshold VIL, VEL 0.8 V
Logic High Output Voltages (VDD1 or VDD2) − 0.1 5.0 V IOx = −20 μA, VIx = VIxH
VOAH, VOBH,
VOCH, VODH (VDD1 or VDD2) − 0.4 4.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
VOAL, VOBL,
VOCL, VODL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM240xARWZ
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
PHL, tPLH 50 65 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 t
PSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM2400/ADuM2401/ADuM2402 Data Sheet
Rev. E | Page 4 of 24
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM240xBRWZ
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 32 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 15 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels7
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM240xCRWZ
Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 18 27 32 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 10 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels7
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic High Output8
|CMH| 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at
Logic Low Output8
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel9 I
DDI (D) 0.19 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D) 0.05 mA/Mbps
1 All voltages are relative to their respective ground.
2 Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See
through for information on per channel supply current as a function of data rate for unloaded and loaded conditions. See through Fig for
total VDD1 and VDD2 supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.
Power Consumption
Power Consumption
Figure 8
Figure 8
Figure 10
Figure 10
Figure 11 ure 15
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information
on per channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per channel supply current for a
given data rate.
Data Sheet ADuM2400/ADuM2401/ADuM2402
Rev. E | Page 5 of 24
ELECTRICAL CHARACTERISTICS—3 V OPERATION1
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.31 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.11 0.14 mA
ADuM2400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.2 1.9 mA DC to 1 MHz logic signal frequency
VDD2 Supply Current IDD2 (Q) 0.5 0.9 mA DC to 1 MHz logic signal frequency
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current IDD1 (10) 4.5 6.5 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10) 1.4 2.0 mA 5 MHz logic signal frequency
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current IDD1 (90) 37 65 mA 45 MHz logic signal frequency
VDD2 Supply Current IDD2 (90) 11 15 mA 45 MHz logic signal frequency
ADuM2401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.0 1.6 mA DC to 1 MHz logic signal frequency
VDD2 Supply Current IDD2 (Q) 0.7 1.2 mA DC to 1 MHz logic signal frequency
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current IDD1 (10) 3.7 5.4 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10) 2.2 3.0 mA 5 MHz logic signal frequency
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current IDD1 (90) 30 52 mA 45 MHz logic signal frequency
VDD2 Supply Current IDD2 (90) 18 27 mA 45 MHz logic signal frequency
ADuM2402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 0.9 1.5 mA DC to 1 MHz logic signal frequency
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 or VDD2 Supply Current IDD1 (10), IDD2 (10) 3.0 4.2 mA 5 MHz logic signal frequency
90 Mbps (CRWZ Grade Only)
VDD1 or VDD2 Supply Current IDD1 (90), IDD2 (90) 24 39 mA 45 MHz logic signal frequency
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 1.6 V
Logic Low Input Threshold VIL, VEL 0.4 V
Logic High Output Voltages (VDD1 or VDD2) − 0.1 3.0 V IOx = −20 μA, VIx = VIxH
VOAH, VOBH,
VOCH, VODH (VDD1 or VDD2) − 0.4 2.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
VOAL, VOBL,
VOCL, VODL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM240xARWZ
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
PHL, tPLH 50 75 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 t
PSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM2400/ADuM2401/ADuM2402 Data Sheet
Rev. E | Page 6 of 24
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM240xBRWZ
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 38 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels7
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM240xCRWZ
Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 34 45 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 16 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels7
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic High Output8
|CMH| 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at
Logic Low Output8
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel9 I
DDI (D) 0.10 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D) 0.03 mA/Mbps
1 All voltages are relative to their respective ground.
2 Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See
through for information on per channel supply current as a function of data rate for unloaded and loaded conditions. See through Fig for
total VDD1 and VDD2 supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.
Power Consumption
Power Consumption
Figure 8
Figure 8
Figure 10
Figure 10
Figure 11 ure 15
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information
on per channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per channel supply current for a
given data rate.
Data Sheet ADuM2400/ADuM2401/ADuM2402
Rev. E | Page 7 of 24
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications
are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q)
5 V/3 V Operation 0.50 0.53 mA
3 V/5 V Operation 0.26 0.31 mA
Output Supply Current per Channel, Quiescent IDDO (Q)
5 V/3 V Operation 0.11 0.14 mA
3 V/5 V Operation 0.19 0.21 mA
ADuM2400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal frequency
3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal frequency
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal frequency
3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal frequency
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal frequency
3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal frequency
3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal frequency
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 70 100 mA 45 MHz logic signal frequency
3 V/5 V Operation 37 65 mA 45 MHz logic signal frequency
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 11 15 mA 45 MHz logic signal frequency
3 V/5 V Operation 18 25 mA 45 MHz logic signal frequency
ADuM2401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal frequency
3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal frequency
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal frequency
3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal frequency
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal frequency
3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal frequency
3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal frequency
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 57 82 mA 45 MHz logic signal frequency
3 V/5 V Operation 30 52 mA 45 MHz logic signal frequency
ADuM2400/ADuM2401/ADuM2402 Data Sheet
Rev. E | Page 8 of 24
Parameter Symbol Min Typ Max Unit Test Conditions
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 18 27 mA 45 MHz logic signal frequency
3 V/5 V Operation 31 43 mA 45 MHz logic signal frequency
ADuM2402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal frequency
3 V/5 V Operation 0.9 1.5 mA DC to 1 MHz logic signal frequency
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal frequency
3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal frequency
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 5.6 7.0 mA 5 MHz logic signal frequency
3 V/5 V Operation 3.0 4.2 mA 5 MHz logic signal frequency
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal frequency
3 V/5 V Operation 5.6 7.0 mA 5 MHz logic signal frequency
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 44 62 mA 45 MHz logic signal frequency
3 V/5 V Operation 24 39 mA 45 MHz logic signal frequency
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 24 39 mA 45 MHz logic signal frequency
3 V/5 V Operation 44 62 mA 45 MHz logic signal frequency
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH
5 V/3 V Operation 2.0 V
3 V/5 V Operation 1.6 V
Logic Low Input Threshold VIL, VEL
5 V/3 V Operation 0.8 V
3 V/5 V Operation 0.4 V
Logic High Output Voltages (VDD1 or VDD2) −
0.1
(VDD1 or VDD2) V IOx = −20 μA, VIx = VIxH
VOAH, VOBH,
VOCH, VODH
(VDD1 or VDD2) −
0.4
(VDD1 or VDD2) −
0.2
V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
VOAL, VOBL,
VOCL, VODL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM240xARWZ
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 t
PHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels
Pulse-Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 t
PSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM240xBRWZ
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 15 35 50 ns CL = 15 pF, CMOS signal levels
Data Sheet ADuM2400/ADuM2401/ADuM2402
Rev. E | Page 9 of 24
Parameter Symbol Min Typ Max Unit Test Conditions
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels7
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM240xCRWZ
Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 14 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels7
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF C
L = 15 pF, CMOS signal levels
5 V/3 V Operation 3.0 ns
3 V/5 V Operation 2.5 ns
Common-Mode Transient Immunity at
Logic High Output8
|CMH| 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at
Logic Low Output8
|CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr
5 V/3 V Operation 1.2 Mbps
3 V/5 V Operation 1.1 Mbps
Input Dynamic Supply Current per Channel9 I
DDI (D)
5 V/3 V Operation 0.19 mA/Mbps
3 V/5 V Operation 0.10 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D)
5 V/3 V Operation 0.03 mA/Mbps
3 V/5 V Operation 0.05 mA/Mbps
1 All voltages are relative to their respective ground.
2 Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8
through Figure 10 for information on per channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for
total VDD1 and VDD2 supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per channel supply current for a
given data rate.
ADuM2400/ADuM2401/ADuM2402 Data Sheet
Rev. E | Page 10 of 24
PACKAGE CHARACTERISTICS
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input to Output)1 R
I-O 1012 Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance2 C
I 4.0 pF
IC Junction-to-Case Thermal Resistance, Side 1 θJCI 33 °C/W
IC Junction-to-Case Thermal Resistance, Side 2 θJCO 28 °C/W
Thermocouple located at center
of package underside
1 Device considered a two-terminal device: Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15,
and Pin 16 shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM240x are approved by the organizations listed in Ta bl e 5. Refer to Table 10 and the Insulation Lifetime section for details
regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 5.
UL CSA VDE
Recognized under 1577 Component
Recognition Program1
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10 (VDE V
0884-10): 2006-122
Single Protection
5000 V rms Isolation Voltage
Basic insulation per CSA 60950-1-07 and
IEC 60950-1, 600 V rms (848 V peak)
maximum working voltage
Reinforced insulation, 846 V peak
RW-16 package:
Reinforced insulation per CSA 60950-1-07
and IEC 60950-1, 380 V rms (537 V peak)
maximum working voltage; reinforced
insulation per IEC 60601-1 125 V rms
(176 V peak) maximum working voltage
RI-16 package:
Reinforced insulation per CSA 60950-1-07
and IEC 60950-1, 400 V rms (565 V peak)
maximum working voltage; reinforced
insulation per IEC 60601-1 250 V rms
(353 V peak) maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL1577, each ADuM240x is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA).
2 In accordance with DIN V VDE V 0884-10, each ADuM240x is proof tested by applying an insulation test voltage ≥1590 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 5000 V rms 1-minute duration
Minimum External Air Gap L(I01) 8.0 min mm Distance measured from input terminals to output
terminals, shortest distance through air along the PCB
mounting plane, as an aid to PC board layout
Minimum External Tracking (Creepage) RW-16 Package L(I02) 7.7 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum External Tracking (Creepage) RI-16 Package L(I02) 8.3 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Data Sheet ADuM2400/ADuM2401/ADuM2402
Rev. E | Page 11 of 24
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Note that the * marking on packages denotes DIN V VDE V 0884-10 approval for 846 V peak working voltage.
Table 7.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 450 V rms I to II
For Rated Mains Voltage ≤ 600 V rms I to II
Climatic Classification 40/105/21
Pollution Degree (DIN VDE 0110, Table 1) 2
Maximum Working Insulation Voltage VIORM 846 V peak
Input-to-Output Test Voltage, Method b1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VPR 1590 V peak
Input-to-Output Test Voltage, Method a VPR
After Environmental Tests Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC 1375 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 1018 V peak
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 6000 V peak
Safety-Limiting Values Maximum value allowed in the event of a failure;
see Figure 4
Case Temperature TS 150 °C
Side 1 Current IS1 265 mA
Side 2 Current IS2 335 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω
CASE T E M P E RATURE (° C)
SAFE TY-LIM IT ING CURRENT (mA)
0
0
350
300
250
200
150
100
50
50 100 150 200
SIDE #1
SIDE #2
05007-004
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting
Values with Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter Rating
Operating Temperature (TA) −40°C to +105°C
Supply Voltages1 (VDD1, VDD2) 2.7 V to 5.5 V
Input Signal Rise and Fall Times 1.0 ms
1 All voltages are relative to their respective ground.
ADuM2400/ADuM2401/ADuM2402 Data Sheet
Rev. E | Page 12 of 24
ABSOLUTE MAXIMUM RATINGS
Table 9.
Parameter Rating
Storage Temperature Range (TST) −65°C to +150°C
Ambient Operating Temperature
Range (TA)
−40°C to +105°C
Supply Voltage Range (VDD1, VDD2)1 −0.5 V to +7.0 V
Input Voltage Range
(VIA, VIB, VIC, VID, VE1, VE2)1, 2
−0.5 V to VDDI + 0.5 V
Output Voltage Range
(VOA, VOB, VOC, VOD)1, 2
−0.5 V to VDDO + 0.5 V
Average Output Current Per Pin3
Side 1 (IO1) −18 mA to +18 mA
Side 2 (IO2) −22 mA to +22 mA
Common-Mode Transients4 −100 kV/μs to +100 kV/μs
1 All voltages are relative to their respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the section. PC Board Layout
3 See for maximum rated current values for various temperatures. Figure 4
4 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the Absolute Maximum Rating can cause latch-
up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Table 10. Maximum Continuous Working Voltage1
Parameter Max Unit Constraint
AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime
AC Voltage, Unipolar Waveform
Reinforced Insulation 846 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Reinforced Insulation 846 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the section for more details. Insulation Lifetime
Table 11. Truth Table (Positive Logic)
VIx Input1 V
Ex Input VDDI State1 V
DDO State1 V
Ox Output1 Notes
H H or NC Powered Powered H
L H or NC Powered Powered L
X L Powered Powered Z
X H or NC Unpowered Powered H Outputs return to input state within 1 μs of VDDI power restoration.
X L Unpowered Powered Z
X X Powered Unpowered Indeterminate Outputs return to input state within 1 μs of VDDO power restoration if
VEx state is H or NC. Outputs return to high impedance state within
8 ns of VDDO power restoration if VEx state is L.
1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and
VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
Data Sheet ADuM2400/ADuM2401/ADuM2402
Rev. E | Page 13 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
05007-005
V
DD1 1
*GND
12
V
IA 3
V
IB 4
V
DD2
16
GND
2
*
15
V
OA
14
V
OB
13
V
IC 5
V
OC
12
V
ID 6
V
OD
11
NC
7
V
E2
10
*GND
18
GND
2
*
9
NC = NO CONNECT
ADuM2400
TO P VIEW
(Not to Scale)
* PIN 2 AND PIN 8 ARE INTE RNALLY CONNECT E D, AND CONNE CTING
BOT H TO GND
1
IS RE COMME NDE D. P IN 9 AND PI N 15 ARE INTE RNALLY
CONNECT E D, AND CONNE CT ING BOT H TO GND
2
IS RECOMM E NDE D.
Figure 5. ADuM2400 Pin Configuration
Table 12. ADuM2400 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
2 GND1 Ground 1. Ground reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VID Logic Input D.
7 NC No Connect.
8 GND1 Ground 1. Ground reference for Isolator Side 1.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.
VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic
high or low is recommended.
11 VOD Logic Output D.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2.
16 VDD2 Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
ADuM2400/ADuM2401/ADuM2402 Data Sheet
Rev. E | Page 14 of 24
05007-006
V
DD1 1
*GND
12
V
IA 3
V
IB 4
V
DD2
16
GND
2
*
15
V
OA
14
V
OB
13
V
IC 5
V
OC
12
V
OD 6
V
ID
11
V
E1 7
V
E2
10
*GND
18
GND
2
*
9
ADuM2401
TOP VIEW
(No t t o S cale)
* PIN 2 AND P IN 8 ARE INTE RNAL LY CONNECT E D, AND CONNECTIN G
BOT H T O GND
1
IS RECOM MENDED. PIN 9 AND P IN 15 ARE I NTERNAL LY
CONNECTED, AND CONNECT ING BOTH TO GND
2
IS RE COMME NDE D.
Figure 6. ADuM2401 Pin Configuration
Table 13. ADuM2401 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
2 GND1 Ground 1. Ground reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VOD Logic Output D.
7 VE1 Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled
when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.
8 GND1 Ground 1. Ground reference for Isolator Side 1.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA,
VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or
low is recommended.
11 VID Logic Input D.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2.
16 VDD2 Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Data Sheet ADuM2400/ADuM2401/ADuM2402
Rev. E | Page 15 of 24
05007-007
V
DD1 1
*GND
12
V
IA 3
V
IB 4
V
DD2
16
GND
2
*
15
V
OA
14
V
OB
13
V
OC 5
V
IC
12
V
OD 6
V
ID
11
V
E1 7
V
E2
10
*GND
18
GND
2
*
9
ADuM2402
TOP VIEW
(No t t o S cale)
*
PIN 2 AND PIN 8 ARE INTE RNALLY CONNECT E D, AND CONNECTI NG
BOT H T O GND
1
IS RECOM MENDED. PIN 9 AND PIN 15 ARE INTE RNALLY
CONNECTED, AND CONNECT ING BOTH TO GND
2
IS RECOMM E NDE D.
Figure 7. ADuM2402 Pin Configuration
Table 14. ADuM2402 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
2 GND1 Ground 1. Ground reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 VE1 Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected.
VOC and VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or
low is recommended.
8 GND1 Ground 1. Ground reference for Isolator Side 1.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected.
VOA and VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or
low is recommended.
11 VID Logic Input D.
12 VIC Logic Input C.
13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2.
16 VDD2 Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
ADuM2400/ADuM2401/ADuM2402 Data Sheet
Rev. E | Page 16 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
05007-008
DATA RATE (Mbps)
CURRENT/CHANNEL (mA)
0
0
10
5
15
20
20 60 8040 100
5V
3V
Figure 8. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
05007-009
DATA RATE (Mbps)
CURRENT/CHANNEL (mA)
0
0
3
2
1
4
5
6
20 60 8040 100
5V
3V
Figure 9. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
05007-010
DATA RATE (Mbps)
CURRENT/CHANNEL (mA)
0
0
6
4
2
8
10
20 60 8040 100
5V
3V
Figure 10. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
05007-011
DATA RATE (Mbps)
CURRENT (mA)
0
0
40
50
20
10
30
60
70
80
20 60 8040 100
5V
3V
Figure 11. Typical ADuM2400 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
05007-012
DATA RAT E ( Mbp s)
CURRENT (mA)
0
0
15
10
5
20
25
20 60 8040 100
5V
3V
Figure 12. Typical ADuM2400 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
05007-013
DATA RATE ( M bp s)
CURRENT ( mA)
0
0
25
20
15
10
5
30
35
20 60 8040 100
5V
3V
Figure 13. Typical ADuM2401 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Data Sheet ADuM2400/ADuM2401/ADuM2402
Rev. E | Page 17 of 24
05007-014
DATA RATE (Mbps)
CURRENT (mA)
0
0
20
15
10
5
30
25
35
40
20 60 8040 100
5V
3V
Figure 14. Typical ADuM2401 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
05007-015
DATA RATE (Mbps)
CURRENT (mA)
0
0
25
20
15
10
5
45
40
35
30
50
20 60 8040 100
5V
3V
Figure 15. Typical ADuM2402 VDD1 or VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
–50 –25
25
30
35
40
0507525 100
05007-016
3V
5V
Figure 16. Propagation Delay vs. Temperature, C Grade
ADuM2400/ADuM2401/ADuM2402 Data Sheet
Rev. E | Page 18 of 24
APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM240x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 17). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16
for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF.
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm. Bypassing
between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should
be considered unless the ground pair on each package side are
connected close to the package.
V
DD1
GND
1
V
IA
V
IB
V
IC/
V
OC
V
ID/
V
OD
V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC/
V
IC
V
OD/
V
ID
V
E2
GND
2
05007-017
Figure 17. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, the board layout should be designed such that
any coupling that does occur equally affects all pins on a given
component side. Failure to ensure this could cause voltage
differentials between pins exceeding the device’s Absolute
Maximum Ratings, thereby leading to latch-up or permanent
damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the length of time
it takes for a logic signal to propagate through a component.
The propagation delay to a logic low output can differ from the
propagation delay to logic high.
INPUT (
V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
05007-018
Figure 18. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs among channels within a single
ADuM240x component.
Propagation delay skew refers to the maximum amount the
propagation delay differs among multiple ADuM240x components
operated under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent via the transformer to the decoder.
The decoder is bistable and is therefore either set or reset by the
pulses, indicating input logic transitions. In the absence of logic
transitions at the input for more than ~1 μs, a periodic set of
refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses for more than approximately 5 μs, the input side
is assumed to be without power or nonfunctional; in which
case, the isolator output is forced to a default state (see Table 1 1 )
by the watchdog timer circuit.
The limitation on the ADuM240x’s magnetic field immunity is
set by the condition in which induced voltage in the transformer’s
receiving coil is large enough to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this can occur. The 3 V operating condition of the
ADuM240x is examined because it represents the most
susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt)Σ∏rn2; n = 1, 2,…, N
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM240x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 19.
MAGNETI C FIEL D F REQ UE NCY (Hz )
100
MAXIMUM ALLOWABLE MAG NETIC FLUX
DENSITY (kgauss)
0.001 1M
10
0.01
1k 10k 10M
0.1
1
100M100k
05007-019
Figure 19. Maximum Allowable External Magnetic Flux Density
Data Sheet ADuM2400/ADuM2401/ADuM2402
Rev. E | Page 19 of 24
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM240x transformers. Figure 20 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As can be seen, the ADuM240x is immune and can
be affected only by extremely large currents operated at high
frequency and very close to the component. For the 1 MHz
example noted, place a 0.5 kA current 5 mm away from the
ADuM240x to affect the component’s operation.
MAGNETI C F I ELD FREQ UENCY (Hz)
MAXI M UM ALLOWABLE CURRENT (kA)
1000
100
10
1
0.1
0.011k 10k 100M100k 1M 10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
05007-020
Figure 20. Maximum Allowable Current for
Various Current-to-ADuM240x Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce sufficiently large error voltages to trigger the
thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM240x isolator is
a function of the supply voltage, the data rate of the channel,
and the output load of the channel.
For each input channel, the supply current is given by:
IDDI = IDDI (Q) f ≤ 0.5fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5fr
For each output channel, the supply current is given by:
IDDO = IDDO (Q) f ≤ 0.5fr
IDDO = (IDDO (D) + (0.5 × 10-3 × CLVDDO) × (2f − fr) + IDDO (Q)
f > 0.5fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total IDD1 and IDD2, the supply currents for each
input and output channel corresponding to IDD1 and IDD2 are
calculated and totaled. Figure 8 and Figure 9 provide per channel
supply currents as a function of data rate for an unloaded output
condition. Figure 10 provides per channel supply current as a
function of data rate for a 15 pF output condition. Figure 11
through Figure 15 provide the total IDD1 and IDD2 as a function of
data rate for the ADuM2400/ADuM2401/ADuM2402 channel
configurations.
ADuM2400/ADuM2401/ADuM2402 Data Sheet
Rev. E | Page 20 of 24
INSULATION LIFETIME In the case of unipolar ac or dc voltage, the stress on the
insulation is significantly lower. This allows operation at higher
working voltages while still achieving a 50-year service life.
The working voltages listed in Table 10 can be applied while
maintaining the 50-year minimum lifetime, provided the voltage
conforms to either the unipolar ac or dc voltage cases. Any
cross-insulation voltage waveform that does not conform to
Figure 22 or Figure 23 should be treated as a bipolar ac waveform
and its peak voltage should be limited to the 50-year lifetime
voltage value listed in Table 10.
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM240x.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. The values shown in Table 1 0
summarize the peak voltage for 50 years of service life for a
bipolar ac operating condition and the maximum CSA/VDE
approved working voltages. In many cases, the approved
working voltage is higher than the 50-year service life voltage.
Operation at these high working voltages can lead to shortened
insulation life in some cases.
Note that the voltage presented in Figure 22 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
0V
RATED P E AK V OLTAGE
05007-021
Figure 21. Bipolar AC Waveform
The insulation lifetime of the ADuM240x depends on the voltage
waveform type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates, depending on
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 21,
Figure 22, and Figure 23 illustrate these different isolation
voltage waveforms.
0V
RATED P E AK V OLTAGE
05007-022
Figure 22. Unipolar AC Waveform
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines Analog Devices recommended maximum working
voltage.
0V
RATED P E AK V OLTAGE
05007-023
Figure 23. DC Waveform
Data Sheet ADuM2400/ADuM2401/ADuM2402
Rev. E | Page 21 of 24
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AC
10-12-2010-A
13.00 (0.5118)
12.60 (0.4961)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
8°
0°
16 9
8
1
1.27
(0.0500)
BSC
SEATING
PLANE
Figure 25. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body (RI-16-1)
Dimensions shown in millimeters and (inches)
ADuM2400/ADuM2401/ADuM2402 Data Sheet
Rev. E | Page 22 of 24
ORDERING GUIDE
Model1, 2
Number
of Inputs,
VDD1 Side
Number
of Inputs,
VDD2 Side
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse Width
Distortion (ns)
Temperature
Range Package Description
Package
Option
ADuM2400ARWZ 4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2400BRWZ 4 0 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2400CRWZ 4 0 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2400ARIZ 4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM2400BRIZ 4 0 10 50 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM2400CRIZ 4 0 90 32 2 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM2401ARWZ 3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2401BRWZ 3 1 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2401CRWZ 3 1 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2401ARIZ 3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM2401BRIZ 3 1 10 50 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM2401CRIZ 3 1 90 32 2 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM2402ARWZ 2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2402BRWZ 2 2 10 50 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2402CRWZ 2 2 90 32 2 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM2402ARIZ 2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM2402BRIZ 2 2 10 50 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM2402CRIZ 2 2 90 32 2 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
1 Tape and reel is available. The addition of an -RL suffix designates a 13” (1,000 units) tape and reel option.
2 Z = RoHS Compliant Part.
Data Sheet ADuM2400/ADuM2401/ADuM2402
Rev. E | Page 23 of 24
NOTES
