1. General description
The 74LVC2G02 is a high-performance, low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
The 74LVC2G02 provides the 2-input NOR gate function.
2. Features
nWide supply voltage range from 1.65 V to 5.5 V
n5 V tolerant outputs for interfacing with 5 V logic
nHigh noise immunity
n±24 mA output drive (VCC = 3.0 V)
nCMOS low power consumption
nComplies with JEDEC standard:
uJESD8-7 (1.65 V to 1.95 V)
uJESD8-5 (2.3 V to 2.7 V)
uJESD8-B/JESD36 (2.7 V to 3.6 V)
nLatch-up performance exceeds 250 mA
nDirect interface with TTL levels
nInputs accept voltages up to 5 V
nESD protection:
uHBM EIA/JESD22-A114-C exceeds 2000 V
uMM EIA/JESD22-A115-A exceeds 200 V
nMultiple package options
nSpecified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC2G02
Dual 2-input NOR gate
Rev. 04 — 15 May 2006 Product data sheet
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 2 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
3. Ordering information
4. Marking
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC2G02DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm SOT505-2
74LVC2G02DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm SOT765-1
74LVC2G02GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 ×1.95 ×0.5 mm SOT833-1
74LVC2G02GM −40 °C to +125 °C XQFN8 plastic extremely thin quad flat package; no leads;
8 terminals; body 1.6 ×1.6 ×0.5 mm SOT902-1
Table 2. Marking
Type number Marking code
74LVC2G02DP V02
74LVC2G02DC V02
74LVC2G02GT V02
74LVC2G02GM V02
Fig 1. Logic symbol Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
mna716
1A
1B 1Y
2
17
2A
2B 2Y
6
53
mna717
7
≥ 1
≥ 1
2
1
3
6
5
mna105
B
A
Y
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 3 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 4. Pin configuration TSSOP8 and
VSSOP8 Fig 5. Pin configuration XSON8
Fig 6. Pin configuration XQFN8
74LVC2G02
1A VCC
1B 1Y
2Y 2B
GND 2A
001aab642
1
2
3
4
6
5
8
7
74LVC2G02
2B
1Y
VCC
2A
2Y
1B
1A
GND
001aab643
36
27
18
45
Transparent top view
001aae971
1B2B
1A
VCC
2Y
1Y
GND
2A
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
74LVC2G02
Table 3. Pin description
Symbol Pin Description
TSSOP8,
VSSOP8 XSON8 XQFN8
1A 1 1 7 data input 1A
1B 2 2 6 data input 1B
2Y 3 3 5 data output 2Y
GND444ground (0 V)
2A 5 5 3 data input 2A
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 4 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
7. Functional description
7.1 Function table
[1] H = HIGH voltage level;
L = LOW voltage level.
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal condition.
[3] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8 and XQFN packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
2B 6 6 2 data input 2B
1Y 7 7 1 data output 1Y
VCC 8 8 8 supply voltage
Table 3. Pin description
…continued
Symbol Pin Description
TSSOP8,
VSSOP8 XSON8 XQFN8
Table 4. Function table[1]
Input Output
nA nB nY
LLH
LHL
HLL
HHL
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground=0V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +6.5 V
VIinput voltage [1] −0.5 +6.5 V
VOoutput voltage Active mode [1] −0.5 VCC + 0.5 V
Power-down mode [1][2] −0.5 +6.5 V
IIK input clamping current VI<0V - −50 mA
IOK output clamping current VO< 0 V or VO>V
CC -±50 mA
IOoutput current VO=0VtoV
CC -±50 mA
ICC quiescent supply current - 100 mA
IGND ground current - −100 mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb =−40 °C to +125 °C[3] - 300 mW
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 5 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
9. Recommended operating conditions
10. Static characteristics
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage Active mode 0 - VCC V
Power-down mode 0 - 5.5 V
Tamb ambient temperature −40 - +125 °C
∆t/∆V input transition rise and
fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 5.5 V 0 - 10 ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb =−40 °C to +85 °C[1]
VIH HIGH-state input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 × VCC -- V
VIL LOW-state input voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 × VCC V
VOH HIGH-state output voltage VI=V
IH or VIL
IO=−100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V
IO=−4 mA; VCC = 1.65 V 1.2 1.53 - V
IO=−8 mA; VCC = 2.3 V 1.9 2.13 - V
IO=−12 mA; VCC = 2.7 V 2.2 2.50 - V
IO=−24 mA; VCC = 3.0 V 2.3 2.60 - V
IO=−32 mA; VCC = 4.5 V 3.8 4.10 - V
VOL LOW-state output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V - - 0.1 V
IO = 4 mA; VCC = 1.65 V - 0.08 0.45 V
IO = 8 mA; VCC = 2.3 V - 0.14 0.3 V
IO = 12 mA; VCC = 2.7 V - 0.19 0.4 V
IO = 24 mA; VCC = 3.0 V - 0.37 0.55 V
IO = 32 mA; VCC = 4.5 V - 0.43 0.55 V
ILI input leakage current VI = 5.5 V or GND; VCC = 5.5 V - ±0.1 ±5µA
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±10 µA
ICC quiescent supply current VI=V
CC or GND; IO= 0 A; VCC = 5.5 V - 0.1 10 µA
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 6 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
[1] All typical values are measured at Tamb = 25 °C.
∆ICC additional quiescent
supply current per pin; VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V - 5 500 µA
Ciinput capacitance - 2.5 - pF
Tamb =−40 °C to +125 °C
VIH HIGH-state input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 × VCC -- V
VIL LOW-state input voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 × VCC V
VOH HIGH-state output voltage VI=V
IH or VIL
IO=−100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V
IO=−4 mA; VCC = 1.65 V 0.95 - - V
IO=−8 mA; VCC = 2.3 V 1.7 - - V
IO=−12 mA; VCC = 2.7 V 1.9 - - V
IO=−24 mA; VCC = 3.0 V 2.0 - - V
IO=−32 mA; VCC = 4.5 V 3.4 - - V
VOL LOW-state output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V - - 0.1 V
IO = 4 mA; VCC = 1.65 V - - 0.70 V
IO = 8 mA; VCC = 2.3 V - - 0.45 V
IO = 12 mA; VCC = 2.7 V - - 0.60 V
IO = 24 mA; VCC = 3.0 V - - 0.80 V
IO = 32 mA; VCC = 4.5 V - - 0.80 V
ILI input leakage current VI = 5.5 V or GND; VCC = 5.5 V - - ±20 µA
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - ±20 µA
ICC quiescent supply current VI=V
CC or GND; IO= 0 A; VCC = 5.5 V - - 40 µA
∆ICC additional quiescent
supply current per pin; VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V - - 5000 µA
Table 7. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 7 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
11. Dynamic characteristics
[1] All typical values are measured at nominal VCC and Tamb = 25 °C.
[2] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL×VCC2×fo) = sum of the outputs.
12. Waveforms
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions Min Typ Max Unit
Tamb = −40 °C to +85 °C[1]
tPHL, tPLH propagation delay input
nA, nB to output nY see Figure 7
VCC = 1.65 V to 1.95 V 1.2 3.8 8.9 ns
VCC = 2.3 V to 2.7 V 0.8 2.4 5.4 ns
VCC = 2.7 V 0.8 3.2 6.0 ns
VCC = 3.0 V to 3.6 V 0.6 2.4 4.9 ns
VCC = 4.5 V to 5.5 V 0.6 1.8 4.3 ns
CPD power dissipation
capacitance per gate; VI= GND to VCC [2] -14-pF
Tamb = −40 °C to +125 °C
tPHL, tPLH propagation delay input
nA, nB to output nY see Figure 7
VCC = 1.65 V to 1.95 V 1.2 - 11.2 ns
VCC = 2.3 V to 2.7 V 0.8 - 6.8 ns
VCC = 2.7 V 0.8 - 7.5 ns
VCC = 3.0 V to 3.6 V 0.6 - 6.2 ns
VCC = 4.5 V to 5.5 V 0.6 - 5.5 ns
Measurement points are given in Table 9.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 7. Input (nA, nB) to output (nY) propagation delays
001aae972
nA, nB input
nY output
tPLH
tPHL
GND
VI
VM
VM
VOH
VOL
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 8 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
Table 9. Measurement points
Supply voltage Input Output
VCC VMVM
1.65 V to 1.95 V 0.5VCC 0.5VCC
2.3 V to 2.7 V 0.5VCC 0.5VCC
2.7 V 1.5 V 1.5 V
3.0 V to 3.6 V 1.5 V 1.5 V
4.5 V to 5.5 V 0.5VCC 0.5VCC
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistor
CL = Load capacitance including jig and probe capacitance
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
VEXT = Test voltage for switching times
Fig 8. Load circuitry for switching times
Table 10. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPLH, tPHL
1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩopen
2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ωopen
2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ωopen
3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ωopen
4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ωopen
VEXT
VCC
VIVO
001aae235
DUT
CL
RT
RL
RL
PULSE
GENERATOR
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 9 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
13. Package outline
Fig 9. Package outline SOT505-2 (TSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(1) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00 0.95
0.75 0.38
0.22 0.18
0.08 3.1
2.9 3.1
2.9 0.65 4.1
3.9 0.70
0.35 8°
0°
0.13 0.10.20.5
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.47
0.33
SOT505-2 - - - 02-01-16
wM
bp
D
Z
e
0.25
14
85
θ
A2A1
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
1.1
pin 1 index
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 10 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
Fig 10. Package outline SOT765-1 (VSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(2) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00 0.85
0.60 0.27
0.17 0.23
0.08 2.1
1.9 2.4
2.2 0.5 3.2
3.0 0.4
0.1 8°
0°
0.13 0.10.20.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1 MO-187 02-06-07
wM
bp
D
Z
e
0.12
14
85
θ
A2A1
Q
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1
1
pin 1 index
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 11 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
Fig 11. Package outline SOT833-1 (XSON8)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT833-1 - - -
MO-252
- - -
SOT833-1
04-07-22
04-11-09
DIMENSIONS (mm are the original dimensions)
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17 2.0
1.9 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
8
2
7
3
6
4
5
8×
(2)
4×
(2)
A
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 12 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
Fig 12. Package outline SOT902-1 (XQFN8)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT902-1 MO-255- - - - - -
SOT902-1
05-11-16
05-11-25
UNIT A
max
mm 0.5
A1
0.25
0.15
0.05
0.00 1.65
1.55 0.35
0.25 0.15
0.05
DIMENSIONS (mm are the original dimensions)
XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm
bDLe1
1.65
1.55
eE L1v
0.10.55 0.5
w
0.05
y
0.05 0.05
y1
0 1 2 mm
scale
X
C
y
C
y1
terminal 1
index area
terminal 1
index area
B A
D
E
detail X
A
A1
b
8
7
6
5
e1
e1
e
e
AC B
∅ vMC∅ wM
4
1
2
3
L
L1
metal area
not for soldering
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 13 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
14. Abbreviations
15. Revision history
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC2G02_4 20060515 Product data sheet - 74LVC2G02_3
Modifications: •The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
•Added: type number 74LVC2G02GM (XQFN8 package)
74LVC2G02_3
(9397 750 14532) 20050201 Product specification - 74LVC2G02_2
74LVC2G02_2
(9397 750 13772) 20040915 Product specification - 74LVC2G02_1
74LVC2G02_1
(9397 750 11932) 20031015 Product specification - -
74LVC2G02_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 15 May 2006 14 of 15
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.semiconductors.philips.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Philips Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Philips Semiconductors
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, Philips Semiconductors does not give any representations
or warranties, expressed or implied, as to the accuracy or completeness of
such information and shall have no liability for the consequences of use of
such information.
Right to make changes — Philips Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — Philips Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a Philips Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Philips Semiconductors accepts no liability for inclusion and/or use
of Philips Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is for the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Philips Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — Philips Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.semiconductors.philips.com/profile/terms, including those
pertaining to warranty, intellectual property rights infringement and limitation
of liability, unless explicitly otherwise agreed to in writing by Philips
Semiconductors. In case of any inconsistency or conflict between information
in this document and such terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
Philips Semiconductors 74LVC2G02
Dual 2-input NOR gate
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
For more information, please visit: http://www.semiconductors.philips.com.
For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com.
Date of release: 15 May 2006
Document identifier: 74LVC2G02_4
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 4
7.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 5
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
17 Contact information. . . . . . . . . . . . . . . . . . . . . 14
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
