ADuM2280/ADuM2281/ADuM2285/ADuM2286 Data Sheet
Rev. 0 | Page 14 of 20
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM228x digital isolators requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 12). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 3 for VDD1 and between Pin 14 and
Pin 16 for VDD2. The capacitor value should be between 0.01 µF
and 0.1 µF. The total lead length between both ends of the
capacitor and the input power supply pin should not exceed
20 mm. Bypassing between Pin 3 and Pin 7 and between Pin 9
and Pin 14 should be considered unless the ground pair on each
package side are connected close to the package.
GND
1
NC
V
DD1
V
IA
/V
OA
GND
2
NC
V
DD2
V
OA
/V
IA
V
IB
V
OB
NC NC
GND
1
NC
NC GND
2
10446-012
Figure 12. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients,
care should be taken to ensure that board coupling across the
isolation barrier is minimized. Furthermore, the board layout
should be designed such that any coupling that does occur
equally affects all pins on a given component side. Failure
to ensure this could cause voltage differentials between pins
exceeding the device’s absolute maximum ratings, thereby
leading to latch-up or permanent damage.
The ADuM228x can readily meet CISPR 22 Class A (and
FCC Class A) emissions standards, as well as the more strin-
gent CISPR 22 Class B (and FCC Class B) standards in an
unshielded environment, with proper PCB design choices.
Refer to the AN-1109 Application Note for PCB-related
EMI mitigation techniques, including board layout and stack-
up issues.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high-to-low transition may
differ from the propagation delay time of a low-to-high
transition.
INP UT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
10446-013
Figure 13. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM228x component.
Propagation delay skew refers to the maximum amount
the propagation delay differs between multiple ADuM228x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent via the transformer to
the decoder. The decoder is bistable and is, therefore, either set
or reset by the pulses indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 µs,
a periodic set of refresh pulses indicative of the correct input
state are sent to ensure dc correctness at the output.
If the decoder receives no pulses for more than about 5 µs, the
input side is assumed to be unpowered or nonfunctional, in which
case, the isolator output is forced to a default low state by the
watchdog timer circuit.
The limitation on the device’s magnetic field immunity is set
by the condition in which induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines such conditions. The
ADuM2280 is examined in a 3 V operating condition because it
represents the most susceptible mode of operation of this product.
The pulses at the transformer output have an amplitude greater
than 1.5 V. The decoder has a sensing threshold of about 1.0 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt)∑πrn2; n = 1, 2, …, N
where:
β is the magnetic flux density.
rn is the radius of the nth turn in the receiving coil.
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM2280 and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 14.