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FEATURES
DB, DBQ, DW, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
VCCB
NC
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
NC - No internal connection
DESCRIPTION/ORDERING INFORMATION
SN74LVCC3245A
OCTAL BUS TRANSCEIVERWITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
•Bidirectional Voltage Translator•2.3 V to 3.6 V on A Port and 3 V to 5.5 V on BPort
•Control Inputs V
IH
/V
IL
Levels Are Referencedto V
CCA
Voltage•Latch-Up Performance Exceeds 250 mA PerJESD 17•ESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A)– 1000-V Charged-Device Model (C101)
This 8-bit (octal) noninverting bus transceiver contains two separate supply rails. The B port is designed to trackV
CCB
, which accepts voltages from 3 V to 5.5 V, and the A port is designed to track V
CCA
, which operates at 2.3V to 3.6 V. This allows for translation from a 3.3-V to a 5-V system environment and vice versa, from a 2.5-V to a3.3-V system environment and vice versa.
The SN74LVCC3245A is designed for asynchronous communication between data buses. The device transmitsdata from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at thedirection-control (DIR) input. The output-enable ( OE) input can be used to disable the device so the buses areeffectively isolated. The control circuitry (DIR, OE) is powered by V
CCA
.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube of 25 SN74LVCC3245ADWSOIC – DW LVCC3245AReel of 2000 SN74LVCC3245ADWRSOP – NS Reel of 2000 SN74LVCC3245ANSR LVCC3245ASSOP – DB Reel of 2000 SN74LVCC3245ADBR LH245A–40 °C to 85 °C
SSOP (QSOP) – DBQ Reel of 2500 SN74LVCC3245ADBQR LVCC3245ATube of 60 SN74LVCC3245APWTSSOP – PW Reel of 2000 SN74LVCC3245APWR LH245AReel of 250 SN74LVCC3245APWT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
FUNCTION TABLE(EACH TRANSCEIVER)
INPUTS
OPERATIONOE DIR
L L B data to A busL H A data to B busH X Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1996–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DIR
OE
A1
B1
To Seven Other Channels
2
3
22
21
Absolute Maximum Ratings
(1)
SN74LVCC3245A
OCTAL BUS TRANSCEIVERWITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CCA
Supply voltage range –0.5 6 VV
CCB
All A ports
(2)
–0.5 V
CCA
+ 0.5V
I
Input voltage range All B ports
(3)
–0.5 V
CCB
+ 0.5 VExcept I/O ports
(2)
–0.5 V
CCA
+ 0.5All A ports –0.5 V
CCA
+ 0.5V
O
Output voltage range
(3)
VAll B ports –0.5 V
CCB
+ 0.5I
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through V
CCA
, V
CCB
, or GND ±100 mADB package 63DBQ package 61θ
JA
Package thermal impedance
(4)
DW package 46 °C/WNS package 65PW package 88T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) This value is limited to 4.6 V maximum.(3) This value is limited to 6 V maximum.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Recommended Operating Conditions
(1)
SN74LVCC3245A
OCTAL BUS TRANSCEIVERWITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
V
CCA
V
CCB
MIN NOM MAX UNIT
V
CCA
Supply voltage 2.3 3.3 3.6 VV
CCB
Supply voltage 3 5 5.5 V2.3 V 3 V 1.72.7 V 3 V 2V
IHA
High-level input voltage V3 V 3.6 V 23.6 V 5.5 V 22.3 V 3 V 22.7 V 3 V 2V
IHB
High-level input voltage V3 V 3.6 V 23.6 V 5.5 V 3.852.3 V 3 V 0.72.7 V 3 V 0.8V
ILA
Low-level input voltage V3 V 3.6 V 0.83.6 V 5.5 V 0.82.3 V 3 V 0.82.7 V 3 V 0.8V
ILB
Low-level input voltage V3 V 3.6 V 0.83.6 V 5.5 V 1.652.3 V 3 V 1.72.7 V 3 V 2High-level input voltage (control pins)V
IH
V(referenced to V
CCA
)
3 V 3.6 V 23.6 V 5.5 V 22.3 V 3 V 0.72.7 V 3 V 0.8Low-level input voltage (control pins)V
IL
V(referenced to V
CCA
)
3 V 3.6 V 0.83.6 V 5.5 V 0.8V
IA
Input voltage 0 V
CCA
VV
IB
Input voltage 0 V
CCB
VV
OA
Output voltage 0 V
CCA
VV
OB
Output voltage 0 V
CCB
V2.3 V 3 V –82.7 V 3 V –12I
OHA
High-level output current mA3 V 3 V –242.7 V 4.5 V –242.3 V 3 V –122.7 V 3 V –12I
OHB
High-level output current mA3 V 3 V –242.7 V 4.5 V –242.3 V 3 V 82.7 V 3 V 12I
OLA
Low-level output current mA3 V 3 V 242.7 V 4.5 V 24
(1) All unused inputs of the device must be held at the associated V
CC
or GND to ensure proper device operation. Refer to the TIapplication report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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SN74LVCC3245A
OCTAL BUS TRANSCEIVERWITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
Recommended Operating Conditions (continued)
V
CCA
V
CCB
MIN NOM MAX UNIT
2.3 V 3 V 122.7 V 3 V 12I
OLB
Low-level output current mA3 V 3 V 242.7 V 4.5 V 24∆t/ ∆v Input transition rise or fall rate 10 ns/VT
A
Operating free-air temperature –40 85 °C
4
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Electrical Characteristics
SN74LVCC3245A
OCTAL BUS TRANSCEIVERWITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CCA
V
CCB
MIN TYP MAX UNIT
I
OH
= –100 µA 3 V 3 V 2.9 3I
OH
= –8 mA 2.3 V 3 V 22.7 V 3 V 2.2 2.5V
OHA
I
OH
= –12 mA V3 V 3 V 2.4 2.83 V 3 V 2.2 2.6I
OH
= –24 mA
2.7 V 4.5 V 2 2.3I
OH
= –100 µA 3 V 3 V 2.9 32.3 V 3 V 2.4I
OH
= –12 mAV
OHB
2.7 V 3 V 2.4 2.8 V3 V 3 V 2.2 2.6I
OH
= –24 mA
2.7 V 4.5 V 3.2 4.2I
OL
= 100 µA 3 V 3 V 0.1I
OL
= 8 mA 2.3 V 3 V 0.6V
OLA
I
OL
= 12 mA 2.7 V 3 V 0.1 0.5 V3 V 3 V 0.2 0.5I
OL
= 24 mA
2.7 V 4.5 V 0.2 0.5I
OL
= 100 µA 3 V 3 V 0.1I
OL
= 12 mA 2.3 V 3 V 0.4V
OLB
V3 V 3 V 0.2 0.5I
OL
= 24 mA
2.7 V 4.5 V 0.2 0.53.6 V ±0.1 ±1I
I
Control inputs V
I
= V
CCA
or GND 3.6 V µA5.5 V ±0.1 ±1I
OZ
(1)
A or B ports V
O
= V
CCA/B
or GND, V
I
= V
IL
or V
IH
3.6 V 3.6 V ±0.5 ±5µAA port = V
CCA
or GND, I
O
= 0 3.6 V Open 5 50I
CCA
B to A 3.6 V 5 50 µAB port = V
CCB
or GND, I
O
= 0 3.6 V
5.5 V 5 503.6 V 5 50I
CCB
A to B A port = V
CCA
or GND, I
O
= 0 3.6 V µA5.5 V 8 80V
I
= V
CCA
– 0.6 V, Other inputs at V
CCA
or GND,A port 3.6 V 3.6 V 0.35 0.5OE at GND and DIR at V
CCA
V
I
= V
CCA
– 0.6 V, Other inputs at V
CCA
or GND,∆I
CCA
(2)
OE 3.6 V 3.6 V 0.35 0.5 mADIR at V
CCA
V
I
= V
CCA
– 0.6 V, Other inputs at V
CCA
or GND,DIR 3.6 V 3.6 V 0.35 0.5OE at GNDV
I
= V
CCB
– 2.1 V, Other inputs at V
CCB
or GND,∆I
CCB
(2)
B port 3.6 V 5.5 V 1 1.5 mAOE at GND and DIR at GNDC
i
Control inputs V
I
= V
CCA
or GND Open Open 4 pFC
io
A or B ports V
O
= V
CCA/B
or GND 3.3 V 5 V 18.5 pF
(1) For I/O ports, the parameter I
OZ
includes the input leakage current.(2) This is the increase in supply current for each input that is at one of the specified voltage levels, rather than 0 V or the associated V
CC
.
5
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Switching Characteristics
Operating Characteristics
Power-Up Considerations
(1)
SN74LVCC3245A
OCTAL BUS TRANSCEIVERWITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 4 )
V
CCA
= 2.5 V V
CCA
= 2.7 V TO V
CCA
= 2.7 V TO±0.2 V, 3.6 V, 3.6 V,FROM TO
V
CCB
= 3.3 V V
CCB
= 5 V V
CCB
= 3.3 VPARAMETER UNIT(INPUT) (OUTPUT)
±0.3 V ±0.5 V ±0.3 V
MIN MAX MIN MAX MIN MAX
t
PHL
1 9.4 1 6 1 7.1A B nst
PLH
1 9.1 1 5.3 1 7.2t
PHL
1 11.2 1 5.8 1 6.4B A nst
PLH
1 9.9 1 7 1 7.6t
PZL
1 14.5 1 9.2 1 9.7OE A nst
PZH
1 12.9 1 9.5 1 9.5t
PZL
1 13 1 8.1 1 9.2OE B nst
PZH
1 12.8 1 8.4 1 9.9t
PLZ
1 7.1 1 7 1 6.6OE A nst
PHZ
1 6.9 1 7.8 1 6.9t
PLZ
1 8.8 1 7.3 1 7.5OE B nst
PHZ
1 8.9 1 7 1 7.9
V
CCA
= 3.3 V, V
CCB
= 5 V, T
A
= 25 °C
PARAMETER TEST CONDITIONS TYP UNIT
Outputs enabled 38C
pd
Power dissipation capacitance per transceiver C
L
= 50, f = 10 MHz pFOutputs disabled 4.5
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-upsequence always should be followed to avoid excessive supply current, bus contention, oscillations, or otheranomalies caused by improperly biased device pins. To guard against such power-up problems, take theseprecautions:
1. Connect ground before any supply voltage is applied.2. Power up the control side of the device (V
CCA
for all four of these devices).3. Tie OE to V
CCA
with a pullup resistor so that it ramps with V
CCA
.4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),ramp it with V
CCA
. Otherwise, keep DIR low.
(1) Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.
6
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PARAMETER MEASUREMENT INFORMATION FOR A PORT
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH - 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
SN74LVCC3245A
OCTAL BUS TRANSCEIVERWITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
V
CCA
= 2.5 V ±0.2 V AND V
CCB
= 3.3 V ±0.3 V
Figure 1. Load Circuit and Voltage Waveforms
7
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PARAMETER MEASUREMENT INFORMATION FOR B PORT
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH - 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PULSE DURATION
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
SN74LVCC3245A
OCTAL BUS TRANSCEIVERWITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
V
CCA
= 2.5 V ±0.2 V AND V
CCB
= 3.3 V ±0.3 V
Figure 2. Load Circuit and Voltage Waveforms
8
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PARAMETER MEASUREMENT INFORMATION FOR B PORT
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 2 × VCC
Open
GND
500 Ω
500 Ω
VCC
0 V
tw
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
VOLTAGE WA VEFORMS
PULSE DURATION
tPLH tPHL
VOH
VOL
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + 0.3 V
VOH - 0.3 V
≈0 V
2.7 V
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
B-Port
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
50% VCC
50% VCC
B-Port
Input
VCC
0 V
Input
50% VCC
50% VCC
50% VCC
50% VCC
1.5 V 1.5 V
1.5 V 1.5 V
SN74LVCC3245A
OCTAL BUS TRANSCEIVERWITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
V
CCA
= 3.6 V and v
CCB
= 5.5 V
Figure 3. Load Circuit and Voltage Waveforms
9
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PARAMETER MEASUREMENT INFORMATION FOR A AND B PORT
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 7 V
Open
GND
500 Ω
500 Ω
2.7 V
0 V
tw
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
VOLTAGE WA VEFORMS
PULSE DURATION
tPLH tPHL
VOH
VOL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3.5 V
0 V
VOL + 0.3 V
VOH - 0.3 V
≈0 V
2.7 V
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Input
2.7 V
0 V
Input
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
SN74LVCC3245A
OCTAL BUS TRANSCEIVERWITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS585O – NOVEMBER 1996 – REVISED MARCH 2005
V
CCA
AND V
CCB
= 3.6 V
Figure 4. Load Circuit and Voltage Waveforms
10
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
74LVCC3245ADBQRE4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
74LVCC3245ADBQRG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LVCC3245ADBLE OBSOLETE SSOP DB 24 TBD Call TI Call TI
SN74LVCC3245ADBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LVCC3245ADBR ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245ADBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245ADW ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245ADWE4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245ADWR ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245ADWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245ADWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245ANSR ACTIVE SO NS 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245ANSRE4 ACTIVE SO NS 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245ANSRG4 ACTIVE SO NS 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245APW ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LVCC3245APWE4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245APWG4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245APWLE OBSOLETE TSSOP PW 24 TBD Call TI Call TI
SN74LVCC3245APWR ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245APWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245APWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245APWT ACTIVE TSSOP PW 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245APWTE4 ACTIVE TSSOP PW 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCC3245APWTG4 ACTIVE TSSOP PW 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVCC3245A :
•Enhanced Product: SN74LVCC3245A-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVCC3245ADBQR SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVCC3245ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
SN74LVCC3245ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74LVCC3245ANSR SO NS 24 2000 330.0 24.4 8.2 15.4 2.5 12.0 24.0 Q1
SN74LVCC3245APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
SN74LVCC3245APWT TSSOP PW 24 250 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVCC3245ADBQR SSOP DBQ 24 2500 367.0 367.0 38.0
SN74LVCC3245ADBR SSOP DB 24 2000 367.0 367.0 38.0
SN74LVCC3245ADWR SOIC DW 24 2000 367.0 367.0 45.0
SN74LVCC3245ANSR SO NS 24 2000 367.0 367.0 45.0
SN74LVCC3245APWR TSSOP PW 24 2000 367.0 367.0 38.0
SN74LVCC3245APWT TSSOP PW 24 250 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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