Features
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
V61182is2waymultiplexwith2rowsand38columns
V61184is4waymultiplexwith4rowsand36columns
V61188is8waymultiplexwith8rowsand32columns
Lowdynamiccurrent,150Amax.
Lowstandbycurrent,1Amax.at25C
Voltagebiasandmuxsignalgenerationonchip
Displayrefreshonchip,40x8RAMfordisplaystorage
DisplayRAMaddressableas8,40bitwords
Columndriveronlymodetohave40columnoutputs
SeparatelogicandLCDsupplyvoltagepins
Widepowersupplyrange,V:2to6V,V:2to8V
BLANKfunctionforLCDblankingonpowerupetc.
Voltagebiasinputsforapplicationswithlargepixelsizes
Bitmapped
Serialinput/output
Verylowexternalcomponentcount
-40Cto+85Ctemperaturerange
Nobusystates
LCDupdatingsynchronizedtotheLCDrefreshsignal
QFP52andTABpackages
µ
µo
oo
nCrossfreecascadableforlargeLCDapplications
DDLCD
Description
TheV6118isauniversallowmultiplexLCDdriver.TheVer-
sionV61182drivestwowaysmultiplex(twoblackplanes)
LCD,theversionV61184,fourwaymultiplexLCD,andthe
V61188,eightwaymultiplexLCD.Thedisplayrefreshis
handledonchipviaa40x8bitRAMwhichholdstheLCD
contentdrivenbythedriver.LCDpixels(orsegments)are
addressedonaonetoonebasiswiththe40x8bitRAM(a
setbitcorrespondstoanactivatedLCDpixel).TheV6118
hasverylowdynamiccurrentconsumption,150Amax.,
makingitparticularlyattractiveforportableandbattery
poweredapplications.Thewideoperatingrangeonboth
thelogic(V)andtheLCD(V)supplyvoltagesoffers
muchapplicationflexibility.TheLCDbiasgenerationis
internal.Thevoltagebiaslevelscanalsobeprovidedextern-
nallyforapplicationshavinglargepixelssizes.TheV6118
canbeusedasacolumnonlydriverforcascadinginlarge
displayapplications.Inthecolumnonlymode,40column
Outputsavailabletoaddressthedisplay.ABLANKfunc-
tionisprovidedtoblanktheLCD,usefulatpoweruptohold
thedisplayblankuntilthemicroprocessorhasupdatedthe
displayRAM.
µ
DDLCD
Applications
n
n
n
n
n
n
n
Balancesandscales
Automotivedisplays
Utilitymeters
Largedisplays(publicinformationpanelsetc.)
Pagers
Portable,batteryoperatedproducts
Telephones
2,4and8MultiplexLCDDriver
1
TypicalOperatingConfiguration
V6118
QFP52
V61188
EMMICROELECTRONIC-MARINSA V6118
2
Stressesabovetheselistedmaximumratingsmaycause
permanentdamagetothedevice.Exposurebeyondspecified
operatingconditionsmayaffectdevicereliabilityorcause
malfunction.
AbsoluteMaximumRatings
V
V
V
V
T
P
V
T
DD
LCD
LOGIC
DISP
STO
MAX
SMAX
S
-0.3Vto+8V
-0.3Vto+9V
-0.3VtoV+0.3V
DD
-0.3VtoV+0.3V
LCD
-65to+150C
o
100mW
1000V
250Cx10s
o
HandlingProcedures
Thisdevicehasbuilt-inprotectionagainsthighstaticvoltages
orelectricfields;however,anti-staticprecautionsmustbetaken
asforanyotherCMOScomponent.Unlessotherwisespecified,
properoperationcanonlyoccurwhenallterminalvoltagesare
keptwithinthesupplyvoltagerange.Unusedinputsmust
alwaysbetiedtoadefinedlogicvoltagelevel.
OperatingConditions
ElectricalCharacteristics
ILCD
IDD
IDD
IDD
ISS
IIN
CIN
VIL
VIH
VIH
VOH
VOL
ROUT
ROUT
ROUT
RBIAS
RBIAS
RBIAS
±VDC
Seenote 1)
SeenoteatT=+25C
1) o
A
Seenote 1)
Seenote 2)
SeenoteatT=+25C
3) o
A
0<V<V
INDD
atT=+25C
Ao
I=4mA
H
I=4mA
L
I=10A,V=7V
OUTLCD
µ
I=10A,V=3V
OUTLCD
µ
I=10A,V=2V
OUTLCD
µ
I=10A,V=7V
OUTLCD
µ
I=10A,V=3V
OUTLCD
µ
I=10A,V=2V
OUTLCD
µ
Seetables4aand4b,
V=5V
LCD
0
2.0
3.0
2.4
100
0.1
3
200
0.1
1
8
0.5
1.2
9
16
18
30
30
150
1
12
250
1
100
0.8
VDD
VDD
0.4
1.5
2.5
20
25
50
µA
µA
µA
µA
µA
nA
pF
V
V
V
V
V
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
mV
1)
2)
3)
4)
5)
Alloutputsopen,STRatV,FR=400Hz,allotherinputsatV.Table3
Alloutputsopen,STRatV,FR=400Hz,f=1MHz,allotherinputsatV.
Alloutputsopen,allinputsatV.
Thisistheimpedancebetweenthevoltagebiaslevelpins(V1,V2,orV3)andtheoutputpinsS1toS40
whenagivenvoltagebiaslevelisdrivingtheoutputs(S1toS40).
Thisistheimpedanceseenatthesegmentpin.Outputsmeasuredoneatatime.
SSDD
SSCLKDD
DD
V61182/4/8
3
ColumnDrivers
S1toS40logic1logic0logic1|Sx*-V|
S1toS40logic0logic0logic1|V-Sx*|
|V-Sx*|=|Sx*-V|±25mV
S1toS40logic1logic0logic0|V-Sx*|
S1toS40logic0logic0logic0|Sx*-V|
|V-Sx*|=|Sx*-V|±25mV
SS
LCD
LCDSS
LCD
SS
LCDSS
RowDrivers
TimingCharacteristics
V=5.0V±10%,V=2to8V,andT=-40to+85C
DDLCDA
o
Clockhighpulsewidth
Clocklowpulsewidth
ClockandFRrisetime
ClockandFRfalltime
Datainputsetuptime
Datainputholdtime
Dataoutputpropagation
STRpulsewidth
CLKfallingtoSTRrising
STRfallingtoCLKfalling
FRfrequency(Vers.2/4/8)
tCH
tCL
tCR
tCF
tDS
tDH
tPD
tSTR
tP
tD
FFR 2)
C=50pF
LOAD
120
120
201)
301)
100
10
200
128/256/512
200
200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
Clockhighpulsewidth
Clocklowpulsewidth
ClockandFRrisetime
ClockandFRfalltime
Datainputsetuptime
Datainputholdtime
Dataoutputpropagation
STRpulsewidth
CLKfallingtoSTRrising
STRfallingtoCLKfalling
FRfrequency(Vers.2/4/8)
tCH
tCL
tCR
tCF
tDS
tDH
tPD
tSTR
tP
tD
FFR 2)
C=50pF
LOAD
500
500
1001)
1501)
500
10
1128/256/512
200
200
400
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Hz
V61182/4/8
4
DI
Col39
1)AsetaddressbitcorrespondstoawriteenabledRAM
address,thesamedatacanbewrittentomorethanone
RAMaddressbysettingtherequiredaddressbits.
CLK
STR
V6118asarowandcolumndriver(inactive)
40bitloadcycle,RAMaddressprovidedbyaddressbit1to(n*)
COL
1)AsetaddressbitcorrespondstoawriteenabledRAM
Address,thesamedatacanbewrittentomorethanone
RAMaddressbysettingtherequiredaddressbits.
*n=theV6118versionnumber(i.e.2,4,or8)
DI
CLK
STR
V61182/4/8
5
40bitdisplaylatch
40displaydriveroutputs
X
V61182/4/8
1)
2)
TheV6118hasinternalvoltagebiaslevelgeneration.When
drivinglargepixels,anexternalresistordividerchaincanbe
connectedtothevoltagebiaslevelinputstoobtain
enhanceddisplaycontrast(seeFig.12,13and14).The
externalresistordividerratioshouldbeinaccordancewith
theinternalresistorratio(seetable8).
V3isconnectedinternallyontheV61184.
Name
S1...S40
V3
V2
V1
VLCD
FR
DI
DO
CLK
STR
COL
VSS
Function
LCDoutputs,seetable7
LCDvoltagebiaslevel3
1)2)
LCDvoltagebiaslevel1
1)
PowersupplyfortheLCD
ACinputsignalforLCDdriveroutputs
Serialdatainput
Serialdataoutput
Dataclockinput
Datastrobe,blank,synchronizeinput
Powersupplyforlogic
Columnonlydrivermode
SupplyGND
LCDvoltagebiaslevel2
1)
6
LCDVoltageBiasLevels
1+
1+
==
VOFF VOFF
VON
(rms)
(*) (rms)VOP
V61182/4/8
RowandColumnMultiplexingWaveformV61182
VSS,VLCD
VOP == -VSTATE V-V
COLROW
VDD
VSS
VSS
VSS
VSS
VSS
VLCD
VLCD
VLCD
VLCD
V1
V1
V1
V1
V2
V3
V2
V3
V3
V3
V2
V2
2.43V/2.86
V/2.86
0.43V/2.86
0
-0.43V/2.86
-V/2.86
-2.43V/.86
OP
OP
OP
OP
OP
OP
FR
Row1
Row2
Col1
Col2
State1
State2*
State2
T=2/(FRfrequency)
FRAME
*SeeTable8 Fig.7
2.43V/2.86
OP
V/2.86
OP
0.43V/2.86
OP 0
-0.43V/2.86
OP
-V/2.86
OP
-2.43V/2.86
OP
State1*
7
V61182/4/8
8
RowandColumnMultiplexingWaveformV61184
V,
SS
VLCD
VOP =
-VSTATE V-V
COLROW
=
V61182/4/8
9
V61182/4/8
10
FunctionalDescription
SupplyVoltageV,V,V
LCDDDSS
ThevoltagebetweenVandVisthesupplyvoltageforthe
logicandtheinterface.ThevoltagebetweenVandVisthe
supplyvoltagefortheLCDandisusedforthegenerationofthe
internalLCDbiaslevels.TheinternalLCDbiaslevelshavea
maximumimpedanceof25kforaVvoltagefrom3to8V.
WithoutexternalconnectionstotheV1,V2,andV3biaslevel
inputs,theV6118candrivemostmediumsizedLCD(pixelarea
upto4'000mm).
Fordisplayswithawidevariationinpixelsizestheconfiguration
showninFig.13cangiveenhancedcontrastbygivingfaster
pixelswitchingtimes.Onchangingtherowpolarity(seeFig.7,
8and9)theparallelcapacitorslowertheimpedanceofthebias
levelgenerationtothepeakcurrent,givingfasterpixelcharge
timesandthusahigherRMS"on"value.AhigherRMS"on"
valuecangivebettercontrast.IfforagivenLCDsizeand
operatingvoltage,the"off"pixelsappear"on",orthereispoor
contrast,thenanexternalbiaslevelgenerationcircuitcanbe
usedwiththeV6118.Anexternalbiaslevelgenerationcircuit
canlowerthebiaslevelimpedanceandhenceimprovetheLCD
contrast(seeFig.12).TheoptimumvaluesofR,Rx,andC,vary
accordingtotheLCDsizeusedandV.Theyarebest
determinedthroughactualexperimentationwiththeLCD.
ForLCDwitheverylargeaveragepixelsizeupto10'000mm,
thebiaslevelconfigurationshowninFig.14shouldbeused.
WhenV6118sarecascadedconnecttheV1,V2,andV3bias
inputsareshowninFig.10.Thepixelloadisaveragedacrossall
thecascadeddrivers.Thiswillgiveenhanceddisplaycontrast
astheeffectivebiaslevelsourceimpedanceistheparallel
combinationofthetotalnumberofdrivers.Forexample,iftwo
V6118arecascadedasshowninFig.10,thenthemaximum
biaslevelimpedancebecomes12.5KforaVvoltagefrom
3to8V.Table8showstherelationshipbetweenV1,V2,andV3
formultiplexrates2,4and8.NotethatV>V1>V2>V3for
theV61182andV61188,andfortheV61184,
V>V1>V2.
Thedatainputpin,DI,isusedtoloadserialdataintotheV6118.
Theserialdatawordlengthis40bitswhenisinactive,and
48bitswhenitisactive.Dataisloadedininversenumerical
order,thedataforbit40(bit48whenisactive)isloaded
firstwiththedataforbit1last.Thecolumndatabitsareloaded
firstandthentheaddressbits(seeFig.4and5).
Thedataoutputpin,DO,isusedincascadedapplications(see
Fig.10).DOtransfersthedatatothenextcascadedchip.The
dataatDOisequaltothedataatDIdelayedby40clockperiods,
whenisinactiveand48clockperiodswhenisactive.
InordertocascadeV6118s,DOofonechipmustbeconnected
toDIofthefollowingchip(seeFig.10).Incascaded
applicationsthedataofthelastV6118(theonethatdoesnot
haveDOconnected)mustbeloadedfirstandthedataforthe
firstV6118(itsDIisconnectedtotheprocessor)loadedlast
(seeFig.10).
DDSS
LCDSS
Ω
Ω
LCD
LCD
LCD
LCD
LCD
2
2
DataInput/Output
COL
COL
COLCOL
ThedisplayRAMwordlengthis40bits(seeFig.6).EachLCD
rowhasacorrespondingdisplayRAMaddresswhichprovides
thecolumndata(onoroff)whentherowisselected(on).When
downloadingdatatotheV6118anydisplayRAMaddresscan
bechosen,thereisnodisplayRAMaddressingsequence(see
Fig.4and5).
ThesamedatacanbewrittentomorethanonedisplayRAM
address.Ifmorethanoneaddressbitisset,thenmorethanone
displayRAMaddressiswriteenabled,andsothesamedatais
writtentomorethanoneaddress.Thisfeaturecanbeusefulto
flashtheLCDonandoffundersoftwarecontrol.Iftheaddress
bitsareallzerothennodisplayRAMiswriteenabledandno
dataiswrittentothedisplayRAMonthefallingedgeofSTR.
Useaddress0tosynchronizecascadedV6118swithout
updatingthedisplayRAM.
LCD,andsynchronizecascadedV6118s.TheSTRinputwrites
thedataloadedintotheshiftregister,ontheDIinput,tothe
displayRAMonthefallingedgeoftheSTRsignal.Thedisplay
RAMaddressisgivenbytheaddressbits(seeFig.4and5).
TheSTRinputwhenhighblankstheLCDbydisconnectingthe
internalvoltagebiasgenerationfromtheVpotential.
SegmentoutputsS1toS40(rows andcolumns)arepulledup
toV.ThedelaytodrivingtheLCDwithVonS1toS40,is
dependentonthecapacitiveloadoftheLCDandistypically1
µs.AnLCDpixelrespondstoRMSvoltageandtakes
approximately100mstoturnonoroff.Thedelayfromputting
STRhightotheLCDbeingblankisdependentontheLCDoff
timeandistypically100ms.Inapplications,whichhavealong
STRpulsewidth(10µs),theLCDisdrivenbyVonboththe
rowsandcolumnsduringthistime.Asthetimeisshort(1µA),it
willhavezeromeasurableeffectontheRMS"on"value(over
100ms)ofanLCDpixelandalsozeromeasurableeffectonthe
pixelDCcomponent.SuchSTRpulseswillnotbevisibletothe
humaneyeonanLCD.
WhenSTRishightheLCDwillbe
drivenbytheparallelcombinationoftheexternalvoltagebias
generationcircuitandpartoftheinternalvoltagebias
generationcircuit.
TheSTRinput,whenhigh,synchronizescascadedV6118sby
forcinganewtimeframetobeginatthenextfallingedgeofthe
FRinputsignal(seeFig.6).Atimeframebeginswithrow1
andsotheLCDpictureisrebuiltfromrow1eachtime
CLKInput
STRInput
TheCLKisusedtoclocktheDIserialdataintotheshiftregister
andtoclocktheDOserialdataout.Loadingandshiftingofdata
occursatthefallingedgeofthisclock,outputtingofthedataat
therisingedge(seeFig.3).Whencascadingdevices,allCLK
linesshouldbetiedtogether(seeFig.10).
TheSTRinputisusedtowritetothedisplayRAM,blankthe
SS
LCDLCD
LCD
Noteifanexternalvoltagebiasgenerationcircuitisusedas
showninFig.12and14,theLCDblankfunction(STRhigh)
willnotblanktheLCD.
V61182/4/8
11
cascadedV6118saresynchronized.Whencascadingdevices,
allSTRlinesmustbetiedtogether(seeFig.10).
TheFRsignalcontrolsthesegmentoutputfrequency
generation(seeFig.7,8and9).ToavoidhavingDConthe
display,theFRsignalmusthavea50%dutycycle.The
frequencyoftheFRsignalmustbentimesthedesireddisplay
refreshrate,wherenistheV6118versionno.(2,4or8).For
example,ifthedesiredrefreshrateis40Hz,theFRsignal
frequencymustbe320HzfortheV61188.Aselectedrow(on)
isinphasewiththeFRsignal(seeFig.7,8and9).
Itisrecommendedthatdatatransferto theV6118shouldbe
synchronizedtotheFRsignaltoavoidafallingorrisingedgeon
theFRsignalwhilewritingdatatotheV6118.TheLCDpixels
changepolaritywiththeFRsignal.OntheedgesoftheFR
signalcurrentspikeswillappearontheVandVsupply
lines.Ifthesupplylineshavehighimpedancethenvoltage
spikeswillappear.Thesevoltagespikescouldinterferewith
dataloadingontheDIandCLKpins.
Thereare40LCDdriveroutputsontheV6118.Whenis
inactivetheoutputsS1toSnfunctionasrowdriversandthe
outputsS(n+1)toS40functionascolumndrivers,wherenis
theV6118versionno.(2,4or8).Whenisactive,all40
outputsfunctionascolumndrivers(seetable6).Thereisaone
FRinput
DriveroutputS1toS40
SSLCD
COL
COL
toonerelationshipbetweenthedisplayRAMandtheLCD
driveroutputs.Eachpixel(segment)drivenbytheV6118on
theLCDhasadisplayRAMbitwhichcorrespondstoit.Setting
thebitturnsthesegment"on"andclearingitturnsit"off".
TheV6118functionsasarowandcolumndriverwhilethe
isinactive.WhenactivetheinputconfigurestheV6118to
functionasacolumndriveronly.Theformerrowoutputs
functionascolumnoutputs.Incascadedapplicationsone
V6118shouldbeusedintherowcolumnconfiguration(
inactive)andtherestaspurecolumndrivers(active)(see
Fig.10).Notewhen cascadingV6118snevercascadesone
versionwithanother.IfaV61188isusedtodrivetherowsthen
onlyV61188scanbecascadedwithit.Whenisactivethe
V6118needs48bitsofdatainaloadcycle.40bitsareusedfor
thecolumndataand8bitstoaddressthedisplayRAM
regardlessofV6118version(2,4or8)(seeFig.4,5and10).
Onpowerupthedataisshiftregisters,thedisplayRAMandthe
40-bitdisplaylatchareundefined.TheSTRinputshouldbe
takenhighonpoweruptoblankthedisplay,andthenthe
displaydatawrittentothedisplayRAM(seeFig.11).When
finishedtheinitialwritetothedisplayRAM,taketheSTRinput
lowtodisplaythedisplayRAMcontents(seealsosection“STR
Input").
COL Input
COL
COL
COL
COL
COL
PowerUp
V61182/4/8
1)Whenthemicroprocessorisreset,theportpinwillbe
configuredasaninputandsotheSTRlinewould
float.ThepullupresistorwillensurethattheLCDis
blankwhilethesystemresetlineisactiveandafter
untiltheportpinissetupbysoftware.
12
V61188
ByconnectingtheV1,V2andV3biasinputsasshown,thepixelloadisaveragedacrossallthedrivers.The
sffectivebiaslevelsourceimpedanceistheparallelcombinationofthetotalnumberofdrivers.Forexample,
iftwoV6118arecascadedasabove,thenthemaximumbiaslevelimpedancebecomes12.5k.
V61182/4/8
13
V61188
V61182/4/8
14
OrderingInformation
TheV6118isavailableinthefollowingpackages:
QFP52,pinplasticpackageV6118252FChipformV61182Chip*
V6118452FV61184Chip*
V6118852FV61188Chip'
TAB,tapeautomatedbondingV61182TAB*onrequest
V61184TABWhenordering,pleasespecifythecompletepartnum-
V61188TABberandpackage.
PackageandOrderingInformatiion
V61182/4/8
EMMicroelectronic-MarinSAcannotassumeresponsibilityforuseofanycircuitrydescribedotherthancircuitryentirelyembodiedin
anEMMicroelectronic-Marinproduct.EMMicroelectronic-Marinreservestherighttochangecircuitryandspecificationswithout
noticeatanytime.Youarestronglyurgedtoensurethattheinformationgivenhasnotbeensupersededbyamoreup-to-dateversion.
1997EMMicroelectronic-MarinSA,09/97,Rev.J/158
