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FEATURES DESCRIPTION
APPLICATIONS
CONTENTS
TYPICAL APPLICATION DIAGRAM
+– Bridge
Rectifier
LINE
INPUT
VOUT
EMI Filter
UCC28019
Rload
GND
ICOMP
ISENSE
GATE
VCC
VSENSE
VCOMP
VINS
1
2
3
4
8
7
6
5
Auxilary
Supply
UCC28019
SLUS755 – APRIL 2007
8-Pin Continuous Conduction Mode (CCM) PFC Controller
•8-pin Solution Without Sensing Line Voltage
The UCC28019 8-pin active Power Factor CorrectionReduces External Components
(PFC) controller uses the boost topology operating inContinuous Conduction Mode (CCM). The controller•Wide-Range Universal AC Input Voltage
is suitable for systems in the 100 W to >2 kW range•Fixed 65-kHz Operating Frequency
over a wide-range universal AC line input. Startup•Maximum Duty Cycle of 97%
current during under-voltage lockout is less than 200µA. The user can control low power standby mode•Output Over/Under-Voltage Protection
by pulling the VSENSE pin below 0.77 V.•Input Brown-Out Protection
Low-distortion wave-shaping of the input current•Cycle-by-Cycle Peak Current Limiting
using average current mode control is achieved•Open Loop Detection
without input line sensing, reducing the Bill of•Low-Power User Controlled Standby Mode
Materials component count. Simple externalnetworks allow for flexible compensation of thecurrent and voltage control loops. The switchingfrequency is internally fixed and trimmed to better•CCM Boost Power Factor Correction Power
than ±5% accuracy at 25°C. Fast 1.5-A gate peakConverters in the 100 W to >2 kW Range
current drives the external switch.•Server and Desktop Power Supplies
Numerous system-level protection features include•Telecom Rectifiers
peak current limit, soft over-current, open-loop•Industrial Electronics
detection, input brown-out, output•Home Electronics
over/under-voltage, a no-power discharge path onVCOMP, and overload protection on ICOMP.Soft-Start limits boost current during start-up. A•Electrical Characteristics 3
trimmed internal reference provides accurateprotection thresholds and regulation set-point. An•Device Information 10
internal clamp limits the gate drive voltage to 12.5 V.•Application Information 12•Design Example 23•Additional References 43
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
UCC28019
SLUS755 – APRIL 2007
ORDERING INFORMATION
OPERATING TEMPERATUREPART NUMBER PACKAGE
(1)
RANGE, T
A
UCC28019D SOIC 8-Pin (D) ead (Pb)-Free/Green
–40 °C to 125 °CPlastic DIP 8 Pin (P) LeadUCC28019P
(Pb)-Free/Green
(1) SOIC (D) package is available taped and reeled by adding "R" suffix the the above part number, reeled quantities are 2500 devices perreel.
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
VCC –0.3 to 22GATE –0.3 to 16Input voltage range VVINS, VSENSE, VCOMP, ICOMP –0.3 to 7ISENSE –24 to 7Input current range VSENSE, ISENSE –1 to 1 mAOperating –55 to 150Junction temperature, T
J
Storage –65 to 150 °CLead temperature, T
SOL
Soldering, 10s 300°
(1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other condition beyond those included under “Recommended OperatingConditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
PACKAGE THERMAL IMPEDANCE T
A
= 25 °C POWER RATING (W) T
A
= 85 °C POWER RATING (W)JUNCTION TO AMBIENT
(°C/W)
SOIC-8 (D) 160 0.65 0.25PDIP-8 (P) 110 1 0.36
(1) Tested per JEDEC EIA/JESD 51-1. Thermal resistance is a strong function of board construction and layout. Air flow reduces thermalresistance. This number is only a general guide. See TI document SPRA953 Thermal Metrics.
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
VCC input voltage from a low-impedance source VCC
OFF(max)
+ 1 V 21 VT
J
Operating junction temperature –40 125 °C
over operating free-air temperature range (unless otherwise noted)
PARAMETER RATING UNIT
Human Body Model (HBM) 2 kVCharged Device Model (CDM) 500 V
2
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ELECTRICAL CHARACTERISTICS
UCC28019
SLUS755 – APRIL 2007
Unless otherwise noted, VCC = 15 V
DC
, 0.1 µF from VCC to GND, -40°C ≤T
J
= T
A
≤125°C. All voltages are with respect toGND. Currents are positive into and negative out of the specified terminal.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC Bias Supply
I
VCC(start)
Pre-start current VCC = VCC
ON
– 0.1 V 25 100 200 µAI
VCC(stby)
Standby current VSENSE = 0.5 V 1.0 2.1 2.9
mAI
VCC(on_load)
Operating current VSENSE = 4.5 V, C
GATE
= 4.7 nF 4 7 10
Under Voltage Lockout (UVLO)
VCC
ON
Turn on threshold 10.0 10.5 11.0VCC
OFF
Turn off threshold 9 9.5 10 VUVLO Hysteresis 0.8 1.0 1.2
Oscillator
T
A
= 25°C 61.7 65.0 68.3f
SW
Switching frequency, kHz– 40°C ≤T
A
≤125°C 59 65 71
PWM
VCOMP = 0 V, VSENSE = 5 V,D
MIN
Minimum duty cycle 0%ICOMP = 6.4 VD
MAX
Maximum duty cycle VSENSE = 4.95 V 94% 97% 99.3%t
OFF(min)
Minimum off time VSENSE = 3 V, ICOMP = 1 V 100 250 600 ns
System Protection
ISENSE threshold, soft over currentV
SOC
-0.66 -0.73 -0.79(SOC) ,ISENSE threshold, peak current LimitV
PCL
-1.00 -1.08 -1.15 V(PCL) ,VSENSE threshold, open loop ICOMP = 1 V, ISENSE = 0 V,V
OLP
0.77 0.82 0.86protection (OLP), VCOMP = 1 VOpen loop protection (OLP) internal
VSENSE = 0.5 V 100 250 nApull-down currentVSENSE threshold, outputV
UVD
4.63 4.75 4.87under-voltage detection (UVD),VSENSE threshold, outputV
OVP
ISENSE = -0.2 V 5.12 5.25 5.38over-voltage protection (OVP),
VInput brown-out detection (IBOP)VINS
BROWNOUT_th
0.76 0.82 0.88high-to-low thresholdInput brown-out Detection (IBOP)VINS
ENABLE_th
1.4 1.5 1.6low-to-high thresholdI
VINS_0 V
VINS bias current VINS = 0 V 0 ±0.1 µAICOMP threshold, external overload
0.6 Vprotection
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UCC28019
SLUS755 – APRIL 2007
ELECTRICAL CHARACTERISTICS (continued)Unless otherwise noted, VCC = 15 V
DC
, 0.1 µF from VCC to GND, -40°C ≤T
J
= T
A
≤125°C. All voltages are with respect toGND. Currents are positive into and negative out of the specified terminal.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Loop
gmi Transconductance gain T
A
= 25°C 0.75 0.95 1.15 mSOutput linear range ±50 µAICOMP voltage during OLP VSENSE = 0.5 V 3.7 4.0 4.3 V
Voltage Loop
V
REF
Reference voltage -40°C ≤T
A
≤125°C 4.90 5.00 5.10 Vgmv Transconductance gain 31.5 42 52.5 µSMaximum sink current under normal
VSENSE = 6 V, VCOMP = 4 V 21 30 38operation
Source current under soft start VSENSE = 4 V, VCOMP = 0 V –21 -30 -38
µAVSENSE = 4 V, VCOMP = 0 V –100 –170 –250Maximum source current under EDRoperation
VSENSE = 4 V, VCOMP = 4 V –60 –100 –140Enhanced dynamic response, V
SENSE
4.63 4.75 4.87 Vlow threshold, fallingV
SENSE
input bias current 1 V ≤VSENSE ≤5 V 100 250 nAV
COMP
voltage during OLP VSENSE = 0.5 V, I
VCOMP
= 0.5 mA 0 0.2 0.4 V
GATE Driver
GATE current, peak, sinking
(1)
C
GATE
= 4.7 nF 2.0
AGATE current, peak, sourcing
(1)
C
GATE
= 4.7 nF –1.5GATE rise time C
GATE
= 4.7 nF, GATE = 2 V to 8 V 40 60
nsGATE fall time C
GATE
= 4.7 nF, GATE = 8 V to 2 V 25 40GATE low voltage, no load GATE = 0 A 0 0.05GATE low voltage, sinking GATE = 20 mA 0.3 0.8GATE low voltage, sourcing GATE = -20 mA –0.3 –0.8GATE low voltage, sinking VCC = 5 V, GATE = 5 mA 0.2 0.75 1.2
VGATE low voltage, sinking VCC = 5 V, GATE = 20 mA 0.2 0.9 1.5GATE high voltage VCC = 20 V, C
GATE
= 4.7 nF 11 12.5 14GATE high voltage VCC = 11 V, C
GATE
= 4.7 nF 9.5 10.5 11.0VCC = VCC
OFF
+ 0.2 V,GATE high voltage 8.0 9.0 10.2C
GATE
= 4.7 nF
(1) Not tested. Characterized by design.
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TYPICAL CHARACTERISTICS
0 5 15
VCC - Bias Supply Voltage - V
0
0.5
1.5
2.5
3.0
4.0
10 20
1.0
2.0
3.5
SUPPLY CURRENT
vs
BIAS SUPPLY VOLTAGE
IVCC Turn ONIVCC Turn OFF
VSENSE = VINS = 3V
No Gate Load
IVCC - Supply Current - mA
-60 -35 -10 65 115 140
TJ- Temperature - °C
8.0
9.0
11.0
12.0
15 40 90
10.0
VCCON/VCCOFF - UVLO Threshold - V
UVLO THRESHOLDS
vs
TEMPERATURE
VCC Turn OFF (VCCOFF)
VCC Turn ON (VCCON)
TJ- Temperature - °C
0
2
4
6
8
10
1
3
5
7
9
IVCC - Supply Current - mA
SUPPLY CURRENT
vs
TEMPERATURE
Operating, GATE Load = 4.7 nF
IVCC(on_load)
Standby
IVCC(stby)
-60 -35 -10 65 115 14015 40 90
TJ- Temperature - °C
0
0.1
0.2
0.3
0.4
0.5
IVCC(start) - Supply Current - mA
SUPPLY CURRENT
vs
TEMPERATURE
Pre-Start
(IVCC(start))
VCC = VCCON - 0.1 V
-60 -35 -10 65 115 14015 40 90
UCC28019
SLUS755 – APRIL 2007
Unless otherwise noted, VCC = 15 V
DC
, 0.1 µF from VCC to GND, T
J
= T
A
= 25 °C. All voltages are with respectto GND. Currents are positive into and negative out of the specified terminal.
Figure 1. Figure 2.
Figure 3. Figure 4.
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TJ- Temperature - °C
55
59
63
67
71
75
fSW - Switching Frequency - kHz
OSCILLATOR FREQUENCY
vs
TEMPERATURE
Switching Frequency
57
61
65
69
73
-60 -35 -10 65 115 14015 40 90
10 16
VCC - Bias Supply Voltage - V
55
59
63
67
71
75
fSW - Switching Frequency - kHz
OSCILLATOR FREQUENCY
vs
BIAS SUPPLY VOLTAGE
57
61
65
69
73
Switching Frequency
20181412
TJ- Temperature - °C
0
0.4
0.8
1.2
1.6
2.0
gmi - Gain - mA/V
CURRENT AVERAGING
AMPLIFIER TRANSCONDUCTANCE
vs
TEMPERATURE
Gain
0.2
0.6
1.0
1.4
1.8
-60 -35 -10 65 115 14015 40 90
TJ- Temperature - °C
30
34
38
42
46
50
gmv - Gain - µA/V
VOLTAGE ERROR AMPLIFIER
TRANSCONDUCTANCE
vs
TEMPERATURE
32
36
40
44
48
Gain
-60 -35 -10 65 115 14015 40 90
UCC28019
SLUS755 – APRIL 2007
TYPICAL CHARACTERISTICS (continued)
Figure 5. Figure 6.
Figure 7. Figure 8.
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TJ- Temperature - °C
4.50
5.25
5.50
VOVP / VUVD- VSENSE Threshold - V
VSENSE THRESHOLD
vs
TEMPERATURE
4.75
5.00
Under-Voltage Protection (VUVD)
Over-Voltage Protection (VOVP)
-60 -35 -10 65 115 14015 40 90
TJ- Temperature - °C
0
0.4
0.8
1.2
1.6
2.0
VOLP – VSENSE Threshold - V
VSENSE THRESHOLD
vs
TEMPERATURE
0.2
0.6
1.0
1.4
1.8
-60 -35 -10 65 115 14015 40 90
Open Loop Protection (VOLP)
TJ- Temperature - °C
VSOC - ISENSE Threshold - V
ISENSE THRESHOLD
vs
TEMPERATURE
Soft Over-Current Protection (SOC)
-60 -35 -10 65 115 14015 40 90
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.1
-0.3
-0.5
-0.7
-0.9
TJ- Temperature - °C
0
0.4
0.8
1.2
1.6
2.0
VINSENABLE_TH / VINSBROUWNOUT_TH – VINS Threshold - V
VINS THRESHOLD
vs
TEMPERATURE
0.2
0.6
1.0
1.4
1.8
-60 -35 -10 65 115 14015 40 90
VINS Enable (VINSENABLE_TH)
Input Brown-Out Protection (VINSBROWNOUT_TH)
UCC28019
SLUS755 – APRIL 2007
TYPICAL CHARACTERISTICS (continued)
Figure 9. Figure 10.
Figure 11. Figure 12.
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TJ- Temperature - °C
100
200
300
400
500
600
t - Time - ns
MINIMUM OFF TIME
vs
TEMPERATURE
tOFF(min)
VSENSE = 3 V
ICOMP = 1 V
105
250
350
450
550
-60 -35 -10 65 115 14015 40 90
TJ- Temperature - °C
0
10
20
30
40
50
t - Time - ns
GATE DRIVE SWITCHING
vs
TEMPERATURE
Fall Time
CGATE = 4.7 nF
VGATE = 2 V - 8 V
Rise Time
5
15
25
35
45
-60 -35 -10 65 115 14015 40 90
10 12 16 20
VCC - Bias Supply Voltage - V
0
10
20
30
40
50
18
t - Time - ns
GATE DRIVE SWITCHING
vs
BIAS SUPPLY VOLTAGE
Fall Time
CGATE = 4.7 nF
VGATE = 2 V - 8 V
Rise Time
5
15
25
35
45
14
TJ- Temperature - °C
0
0.4
0.8
1.2
1.6
2.0
VGATE – Gate Low Voltage - V
GATE LOW VOLTAGE
WITH DEVICE OFF
vs
TEMPERATURE
0.2
0.6
1.0
1.4
1.8
-60 -35 -10 65 115 14015 40 90
VGATE
VCC = 5 V
IVCC = 20 mA
UCC28019
SLUS755 – APRIL 2007
TYPICAL CHARACTERISTICS (continued)
Figure 13. Figure 14.
Figure 15. Figure 16.
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TJ- Temperature - °C
4.50
4.75
5.00
5.25
5.50
VREF - Reference Voltage - V
REFERENCE VOLTAGE
vs
TEMPERATURE
Reference Voltage
VCC = 15V
-60 -35 -10 65 115 14015 40 90
UCC28019
SLUS755 – APRIL 2007
TYPICAL CHARACTERISTICS (continued)
Figure 17.
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DEVICE INFORMATION
Connection Diagram
GND
ICOMP
ISENSE
GATE
VCC
VSENSE
VCOMP
VINS
1
2
3
4
8
7
6
5
Pin Descriptions
UCC28019
SLUS755 – APRIL 2007
UCC28019 Top View (SOIC-8, PDIP-8)
Terminal Functions
TERMINAL
I/O FUNCTIONNAME #
Gate drive: Integrated push-pull gate driver for one or more external power MOSFETs. 2.0-A sink and 1.5-AGATE 8 O
source capability. Output voltage is clamped at 12.5 V.GND 1 Ground: Device ground reference.
Current loop compensation: Transconductance current amplifier output. A capacitor connected to GNDICOMP 2 O provides compensation and averaging of the current sense signal in the current control loop. The controller isdisabled if the voltage on ICOMP is less than 0.6 V.
Inductor current sense: An input for the voltage across the external current sense resistor, whichrepresents the instantaneous current through the PFC boost inductor. This voltage is averaged to eliminateISENSE 3 I the effects of noise and ripple. Soft Over Current (SOC) limits the average inductor current. Cycle-by-cyclepeak current limit (PCL) immediately shuts off the GATE drive if the peak-limit voltage is exceeded. Use a220- Ωresistor between this pin and the current sense resistor to limit inrush-surge currents into this pin.
Device supply: External bias supply input. Under Voltage Lock Out (UVLO) disables the controller until VCCexceeds a turn-on threshold of 10.5 V. Operation continues until VCC falls below the turn-off (UVLO)VCC 7
threshold of 9.5 V. A ceramic by-pass capacitor of 0.1 µF minimum value should be connected from VCC toGND as close to the device as possible for high frequency filtering of the VCC voltage.
Voltage loop compensation: Transconductance voltage error amplifier output. A resistor-capacitor networkconnected from this pin to GND provides compensation. VCOMP is held at GND until VCC, VINS, andVSENSE all exceed their threshold voltages. Once these conditions are satisfied, VCOMP is charged untilVCOMP 5 O
the VSENSE voltage reaches 95% of its nominal regulation level. When the Enhanced Dynamic Response(EDR) is engaged, additional current is applied to VCOMP to reduce the charge time. EDR additional currentis inhibited during soft-start. Soft-start is programmed by the capacitance on this pin.
Input ac voltage sense: Input Brown Out Protection (IBOP) detects when the system ac-input voltage isabove a user-defined normal operating level, or below a user-defined “brown-out” level. A filteredresistor-divider network connects from this pin to the rectified-mains node. At startup the controller is disabledVINS 4 I
until the VINS voltage exceeds a threshold of 1.5 V, initiating a soft-start. The controller is also disabled ifVINS drops below the brown-out threshold of 0.8 V. Operation will not resume until both VINS and VSENSEvoltages exceed their enable thresholds, initiating another soft-start.
Output voltage sense: An external resistor-divider network connected from this pin to the PFC outputvoltage provides feedback sensing for output voltage regulation. A small capacitor from this pin to GND filtershigh-frequency noise. Standby disables the controller and discharges VCOMP when the voltage at VSENSEdrops below the enable threshold of 0.8V. An internal 100nA current source pulls VSENSE to GND forVSENSE 6 I
Open-Loop Protection (OLP), including pin disconnection. Output over-voltage protection (OVP) disables theGATE output when VSENSE exceeds 105% of the reference voltage. Enhanced Dynamic Response (EDR)rapidly returns the output voltage to its normal regulation level when a system line or load step causesVSENSE to fall below 95% of the reference voltage.
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UCC28019
SLUS755 – APRIL 2007
Figure 18. Block Diagram
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APPLICATION INFORMATION
UCC28019 Operation
UCC28019
SLUS755 – APRIL 2007
The UCC28019 is a switch-mode controller used in boost converters for power factor correction operating at afixed frequency in continuous conduction mode. The UCC28019 requires few external components to operate asan active PFC pre-regulator. Its trimmed oscillator provides a nominal fixed switching frequency of 65 kHz,ensuring that both the fundamental and second harmonic components of the conducted-EMI noise spectrum arebelow the EN55022 conducted-band 150-kHz measurement limit.
Its tightly-trimmed internal 5-V reference voltage provides for accurate output voltage regulation over the typicalworld-wide 85 V
AC
to 265 V
AC
mains input range from zero to full output load. The usable system load rangesfrom 100 W to 2 kW and may be extended in special situations.
Regulation is accomplished in two loops. The inner current loop shapes the average input current to match thesinusoidal input voltage under continuous inductor current conditions. Under extremely light load conditions,depending on the boost inductor value, the inductor current may go discontinuous but still meet Class-Drequirements of IEC 1000-3-2 despite the higher harmonics. The outer voltage loop regulates the output voltageon VCOMP (dependent upon the line and load conditions) which determines the internal gain parameters formaintaining a low-distortion steady-state input current waveshape.
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Power Supply
VCC
VCCON 10.5V
VCCOFF 9.5V
IVCC
IVCC(start) <200µA
IVCC(stby) <2.9mA
IVCC(ON)
UVLO Soft-Start UVLORun RunFault/Standby
Controller
State
PWM
State OFF Ramp Regulated OFF Regulated OFF
Soft-
Start
Ramp
UCC28019
SLUS755 – APRIL 2007
APPLICATION INFORMATION (continued)
The UCC28019 operates from an external bias supply. It is recommended that the device be powered from aregulated auxiliary supply. This device is not intended to be used from a bootstrap bias supply. A bootstrap biassupply is fed from the input high voltage through a resistor with sufficient capacitance on VCC to hold up thevoltage on VCC until current can be supplied from a bias winding on the boost inductor. The minimal hysteresison VCC would require an unreasonable value of hold-up capacitance.
During normal operation, when the output is regulated, current drawn by the device includes the nominal runcurrent plus the current supplied to the gate of the external boost switch. Decoupling of the bias supply musttake switching current into account in order to keep ripple voltage on VCC to a minimum. A ceramic capacitorwith a minimum value of 0.1 µF is recommended from VCC to GND with short, wide traces.
Figure 19. Device Supply States
The device bias operates in several states. During startup, VCC Under-Voltage LockOut (UVLO) sets theminimum operational dc input voltage of the PFC controller. There are two UVLO thresholds. When the UVLOturn-on threshold is exceeded, the controller turns ON. If VCC falls below the UVLO lower turn-off threshold, thecontroller turns OFF. During UVLO, current drawn by the device is minimal. After the device turns on, Soft Start(SS) is initiated and the output is ramped up in a controlled manner to reduce the stress on the externalcomponents and prevents output voltage overshoot. During soft start and after the output is in regulation, thedevice draws its normal run current. If any of several fault conditions is encountered or if the device is put inStandby with an external signal, the device draws a reduced standby current.
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Soft Start
5V
VCOMP
VCOMP
FAULT
gmv
ISS = -30uA
for VSENSE < 4.75V
during Soft-Start
+
VSENSE
System Protection
Feedback
Voltage
OVP 105% VREF
OLP Soft-Start
(No EDR) OLP
OVP
(No Gate Output) Run UVD
(EDR on)
Protection
State
100% VREF
OLP/SS 16% VREF
Run
EDR 95% VREF
UCC28019
SLUS755 – APRIL 2007
APPLICATION INFORMATION (continued)
VCOMP, the output of the voltage loop transconductance amplifier, is pulled low during UVLO, IBOP, andOLP(Open-Loop Protection)/STANDBY. After the fault condition is released, soft start controls the rate of rise ofVCOMP in order to obtain a linear control of the increasing duty cycle as a function of time. During soft start aconstant 30 µA of current is sourced into the compensation components causing the voltage on this pin to ramplinearly until the output voltage reaches 85% of its final value. At this point, the sourcing current begins todecrease until the output voltage reaches 95% of its final rated voltage. The soft-start time is controlled by thevoltage error amplifier compensation components selected, and is user-programmable based on desired loopcrossover frequency. Once V
OUT
exceeds 95% of rate voltage, EDR is no longer inhibited.
Figure 20. Soft Start
System level protection features keep the system in safe operating limits:
Figure 21. Output Protection States
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VCC Under-Voltage Lockout (UVLO)
+
+
VCCON 10.5V S Q
QR
CDECOUPLE
VCC
Auxilary Supply
GND
VCCOFF 9.5V
UVLO
Input Brown-Out Protection (IBOP)
Input Brown-Out Protection (IBOP)
+
+
VINENABLE_th
1.5 V
S Q
QR
VINBROWNOUT_th
0.82 V
CVINS
Rectified AC Line
RVINS1
RVINS2
VINS
5V
20k
IBOP
CIN
UCC28019
SLUS755 – APRIL 2007
APPLICATION INFORMATION (continued)
During startup, UVLO keeps the device in the off state until VCC rises above the 10.5-V enable threshold,VCC
ON
. With a typical 1 V of hysteresis on UVLO to eliminate noise, the device turns off when VCC drops to the9.5-V disable threshold, VCC
OFF
.
Figure 22. UVLO
The VINS, (sensed input line voltage), input provides a means for the designer to set the desired mains RMSvoltage level at which the PFC pre-regulator should start-up, V
AC(turnon)
, as well as the desired mains RMS levelat which it should shut down, V
AC(turnoff)
. This prevents unwanted sustained system operation at or below a“brown-out” voltage, where excessive line current could overheat components. In addition, because VCC bias isnot derived directly from the line voltage, IBOP protects the circuit from low line conditions that may not triggerthe VCC UVLO turn-off.
Figure 23. Input Brown-Out Protection (IBOP)
Input line voltage is sensed directly from the rectified ac mains voltage through a resistor divider filter networkproviding a scaled and filtered value at the VINS input. IBOP puts the device in standby mode when VINS falls(high-to-low) below 0.8 V, VINS
BROWNOUT_th
. The device comes out of standby when VINS rises (low-to-high)above 1.5 V, VINS
ENABLE_th
. I
VINS_0 V
, bias current sourced from VINS, is less than 0.1 µA. With a bias currentthis low, there is little concern for any set-point error caused by this current flowing through the sensing network.The highest reasonable value resistance for this network should be chosen to minimize power dissipation,especially in applications requiring low standby power. Be aware that higher resistance values are moresusceptible to noise pickup, but low noise PCB layout techniques can help mitigate this. Also, depending on theresistor type used and its voltage rating, R
VINS1
should be implemented with multiple resistors in series to reducevoltage stresses.
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2 1 2
ENABLE _ th(max)
VINS VINS
AC( on ) ENABLE _ th(max) F _ BRIDGE
VINS
R R V VINS V
=- -
2
1 2
IN _ RMS
VINS
VINS VINS
V
PR R
=+
2
2
1 2
0 9
CVIN _ dschg
VINS
BROWNOUT _ th(min)
VINS
VINS
IN _ RMS(min)
VINS VINS
t
C
VINS
R n R
. V ( )
R R
-
=é ù
ê ú
ê ú
ê ú
ê ú
+
ë û
l
2
half _ cycles
CVINS _ dschrg
LINE(min)
N
tf
=
UCC28019
SLUS755 – APRIL 2007
APPLICATION INFORMATION (continued)First, select R
VINS1
based on the the highest reasonable resistance value available for typical applications.
Then select R
VINS2
based on this value:
Where V
F_Bridge
is the forward voltage drop across the ac rectifier bridge.
Power dissipated in the resistor network is:
The filter capacitor, C
VINS
, has two functions. First, to attenuate the voltage ripple to levels between the enableand brown-out thresholds which will prevent the ripple on VINS from falsely triggering IBOP when the converteris operating at low line. Second, C
VINS
delays the brown-out protection operation for a desired number of linehalf-cycle periods while still having a good response to an actual brown-out event.
The capacitor is chosen so that it will discharge to the VINS
BROWNOUT_th
level after N number of half line cyclesof delay to accommodate line dropouts.
Where:
and V
IN_RMS(min)
is the lowest normal operating RMS input voltage.
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Output Over-Voltage Protection (OVP)
Open Loop Protection/Standby (OLP/Standby)
Output Under-Voltage Detection (UVD) / Enhanced Dynamic Response (EDR)
+
OPEN LOOP
PROTECTION/
STANDBY
RFB1
Output Voltage
Standby
OLP/STANDBY
RFB2
+
OVERVOLTAGE
OVP
VSENSE
Optional
+
UNDERVOLTAGE UVD
4.75V
5.25V
0.82V
UCC28019
SLUS755 – APRIL 2007
APPLICATION INFORMATION (continued)
V
OUT(OVP)
is the output voltage exceeding 5% of the rated value, causing VSENSE to exceed a 5.25-V threshold(5-V reference voltage + 5%), V
OVP
. The normal voltage control loop is bypassed and the GATE output isdisabled until VSENSE falls below 5.25 V. For example, V
OUT(OVP)
is 420 V in a system with a 400-V ratedoutput.
If the output voltage feedback components were to fail and disconnect (open loop) the signal from the VSENSEinput, then it is likely that the voltage error amp would increase the GATE output to maximum duty cycle. Toprevent this, an internal pull-down forces VSENSE low. If the output voltage falls below 16% of its rated voltage,causing VSENSE to fall below 0.8 V, the device is put in Standby, a state where the PWM switching is haltedand the device is still on but draws standby current below 3 mA. This shutdown feature also gives the designerthe option of pulling VSENSE low with an external switch.
During large changes in load, Enhanced Dynamic Response (EDR) acts to speed up the slow response of thelow-bandwidth voltage loop.
Figure 24. Over Voltage Protection, Open Loop Protection/Standby
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Overcurrent Protection
PCL
+
VPCL
1.08V
ISENSE
Soft Over Current (SOC)
RSENSE
RISENSE
+–
CISENSE
(Optional)
LINE
INPUT VOUT
VSOC 0.73V
Peak Current Limit (PCL)
SOC
+
-1x
300ns
Leading Edge
Blanking
+
Soft Over-Current (SOC)
Peak Current Limit (PCL)
UCC28019
SLUS755 – APRIL 2007
APPLICATION INFORMATION (continued)
Inductor current is sensed by R
SENSE
, a low value resistor in the return path of input rectifier. The other side ofthe resistor is tied to the system ground. The voltage is sensed on the rectifier side of the sense resistor and isalways negative. There are two over-current protection features; Peak Current Limit (PCL) protects againstinductor saturation and Soft Over Current (SOC) protects against an overload on the output.
Figure 25. Soft Over Current (SOC) / Peak Current Limit (PCL)
SOC limits the input current. SOC is activated when the current sense voltage on ISENSE reaches -0.73 V,affecting the internal VCOMP level, and the control loop is adjusted to reduce the PWM duty cycle.
Peak current limit operates on a cycle-by-cycle basis. When the current sense voltage on ISENSE reaches -1.08V, PCL is activated terminating the active switch cycle. The voltage at ISENSE is amplified by a fixed gain of-1.0 and then leading-edge blanked to improve noise immunity against false triggering.
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Current Sense Resistor, R
SENSE
1 25
SOC(min)
SENSE
L _ PEAK (max)
V
R. I
£
2
RSENSE IN _ RMS (max) SEN SE
P ( I ) R=
PCL
PCL
SENSE
V
IR
=
Gate Driver
VCC
VCC
GATE
COUT
LBST DBST VOUT
Rectified
AC
GND
RGATE
UVLO
IBOP
OLP
From
PWM
Latch
10k
S Q
QR
PCL
OVP
Clock Pre-Drive and
Clamp Circuit
QBST
Fault
Logic
UCC28019
SLUS755 – APRIL 2007
APPLICATION INFORMATION (continued)
The current sense resistor, R
SENSE
, is sized using the minimum threshold value of Soft Over Current (SOC),V
SOC(min)
= 0.66 V. To avoid triggering this threshold during normal operation, taking into account the gain of theinternal non-linear power limit, resulting in a decreased duty cycle, the resistor is typically sized for an overloadcurrent of 25% more than the peak inductor peak current.
Since R
SENSE
sees the average input current, worst-case power dissipation occurs at input low line when inputline current is at its maximum. Power dissipated by the sense resistor is:
Peak Current Limit (PCL) protection turns off the output driver when the voltage across the sense resistorreaches the PCL threshold, V
PCL
. The absolute maximum peak current, I
PCL
, is given as:
The GATE output is designed with a current-optimized structure to directly drive large values of total MOSFETgate capacitance at high turn-on and turn-off speeds. An internal clamp limits voltage on the MOSFET gate to12.5 V. An external gate drive resistor, R
GATE
, limits the rise time and dampens ringing caused by parasiticinductances and capacitances of the gate drive circuit thus reducing EMI. The final value of the resistor dependsupon the parasitic elements associated with the layout and other considerations. A 10-k Ωresistor close to thegate of the MOSFET, between the gate and ground, discharges stray gate capacitance and protects againstinadvertent dv/dt-triggered turn-on.
Figure 26. Gate Driver
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Current Loop
ISENSE and ICOMP Functions
Pulse Width Modulator
Control Logic
Voltage Loop
Output Sensing
UCC28019
SLUS755 – APRIL 2007
APPLICATION INFORMATION (continued)
The overall system current loop consists of the current averaging amplifier stage, the pulse width modulator(PWM) stage, the external boost inductor stage, and the external current sensing resistor.
The negative polarity signal from the current sense resistor is buffered and inverted at the ISENSE input. Theinternal positive signal is then averaged by the current amplifier (gmi), whose output is the ICOMP pin. Thevoltage on ICOMP is proportional to the average inductor current. An external capacitor to GND is applied to theICOMP pin for current loop compensation and current ripple filtering. The gain of the averaging amplifier isdetermined by the internal VCOMP voltage. This gain is non-linear to accommodate the world-wide ac-linevoltage range. ICOMP is connected to 4 V internally whenever the device is in a Fault or Standby condition.
The PWM stage compares the ICOMP signal with a periodic ramp to generate a leading-edge-modulated outputsignal which is high whenever the ramp voltage exceeds the ICOMP voltage. The slope of the ramp is definedby a non-linear function of the internal VCOMP voltage.
The PWM output signal always starts low at the beginning of the cycle, triggered by the internal clock. Theoutput stays low for a minimum off-time, t
OFF(min)
, after which the ramp rises linearly to intersect the ICOMPvoltage. The ramp-I
COMP
intersection determines t
OFF
, and hence D
OFF
. Since D
OFF
= V
IN
/V
OUT
by theboost-topology equation, and since V
IN
is sinusoidal in wave-shape, and since ICOMP is proportional to theinductor current, it follows that the control loop forces the inductor current to follow the input voltage wave-shapeto maintain boost regulation. Therefore, the average input current is also sinusoidal in wave-shape.
The output of the PWM comparator stage is conveyed to the GATE drive stage, subject to control by variousprotection functions incorporated into the IC. The GATE output duty-cycle may be as high as 99%, but willalways have a minimum off-time t
OFF(min)
. Normal duty-cycle operation can be interrupted directly by OVP andPCL on a cycle-by-cycle basis. UVLO, IBOP and OLP/Standby also terminate the GATE output pulse, andfurther inhibit output until the SS operation can begin.
The outer control loop of the PFC controller is the voltage loop. This loop consists of the PFC output sensingstage, the voltage error amplifier stage, and the non-linear gain generation.
A resistor-divider network from the PFC output voltage to GND forms the sensing block for the voltage controlloop. The resistor ratio is determined by the desired output voltage and the internal 5-V regulation referencevoltage.
Like the VINS input, the very low bias current at the VSENSE input allows the choice of the highest practicableresistor values for lowest power dissipation and standby current. A small capacitor from VSENSE to GND servesto filter the signal in a high-noise environment. This filter time constant should generally be less than 100 µs.
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Voltage Error Amplifier
Non-linear Gain Generation
UCC28019
SLUS755 – APRIL 2007
APPLICATION INFORMATION (continued)
The transconductance error amplifier (gmv) generates an output current proportional to the difference betweenthe voltage feedback signal at VSENSE and the internal 5-V reference. This output current charges ordischarges the compensation network capacitors on the VCOMP pin to establish the proper VCOMP voltage forthe system operating conditions. Proper selection of the compensation network components leads to a stablePFC pre-regulator over the entire ac-line range and 0-100% load range. The total capacitance also determinesthe rate-of-rise of the VCOMP voltage at soft start, as discussed earlier.
The amplifier output VCOMP is pulled to GND during any Fault or Standby condition to discharge thecompensation capacitors to an initial zero state. Usually, the large capacitor has a series resistor which delayscomplete discharge by their respective time constant (which may be several hundred milliseconds). If VCC biasvoltage is quickly removed after UVLO, the normal discharge transistor on VCOMP loses drive and the largecapacitor could be left with substantial voltage on it, negating the benefit of a subsequent Soft-Start. TheUCC28019 incorporates a parallel discharge path which operates without VCC bias, to further discharge thecompensation network after VCC is removed.
When output voltage perturbations greater than ±5% appear at the VSENSE input, the amplifier moves out oflinear operation. On an over-voltage, the OVP function acts directly to shut off the GATE output until VSENSEreturns within ±5% of regulation. On an under-voltage, the UVD function invokes EDR which immediatelyincreases the internal VCOMP voltage by 2 V and increases the external VCOMP charging current typically to100 µA to 170 µA. This higher current facilitates faster charging of the compensation capacitors to the newoperating level, improving transient response time.
The voltage at VCOMP is used to set the current amplifier gain and the PWM ramp slope. This voltage isbuffered internally and is then subject to modification by the EDR function and the SOC function, as discussedearlier.
Together the current gain and the PWM slope adjust to the different system operating conditions (set by theac-line voltage and output load level) as VCOMP changes, to provide a low-distortion, high-power-factor inputcurrent wave-shape following that of the input voltage.
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Layout Guidelines
Cut out in
ground plane
Signal
GND
Power
GND
GND
ICOMP
ISENSE
VINS VCOMP
VSENSE
VCC
GATE
UCC28019
SLUS755 – APRIL 2007
APPLICATION INFORMATION (continued)
As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon theintegrity of the ground return. The pinout of the UCC28019 is ideally suited for separating the high di/dt inducednoise on the power ground from the low current quiet signal ground required for adequate noise immunity. A starpoint ground connection at the GND pin of the device can be achieved with a simple cut out in the ground planeof the printed circuit board. As shown in Figure 27 , the capacitors on ISENSE, VINS, VCOMP, and VSENSE(C11, C12, C15, C17, and C16, respectively) must all be returned directly to the quiet portion of the groundplane, indicated by Signal GND, and not the high current return path of the converter, shown as the Power GND.Because the example circuit in Figure 27 uses surface mount components, the ICOMP capacitor, C10, has itsown dedicated return to the GND pin.
Figure 27. Recommended Layout for the UCC28019
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DESIGN EXAMPLE
350-W, Universal Input, 390-V
DC
Output, PFC Converter
Design Goals
UCC28019
SLUS755 – APRIL 2007
This example illustrates the design process and component selection for a continuous conduction mode powerfactor correction boost converter utilizing the UCC28019. The target design is a universal input, 350W PFCdesigned for an ATX supply application. This design process is directly tied to the UCC28019 Design Calculatorspreadsheet that can be found in the Tools section of the UCC28019 product folder on the Texas Instrumentswebsite.
Table 1. Design Goal Parameters
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Input characteristics
Input voltage V
IN
85 115 265 VACInput frequency f
LINE
47 63 HzV
AC(on)
75I
OUT
= 0.9 ABrown out voltage VACV
AC(off)
65I
OUT
= 0.9 A
Output characteristics
V
OUT
85 VAC ≤V
IN
≤265 VACOutput voltage 370 390 410 VDC47 Hz ≤f
LINE
≤63 Hz0 A ≤I
OUT
≤0.9 A85 VAC ≤V
IN
≤65VACLine regulation 5%I
OUT
= 0.440 AV
IN
= 115 VAC, f
LINE
= 60 Hz
5%0 A ≤I
OUT
≤0.9 ALoad regulation
V
IN
= 230 VAC, f
LINE
= 50 Hz
5%0 A ≤I
OUT
≤0.9 AV
RIPPLE(SW)
V
IN
= 115 VAC, f
LINE
= 60 Hz 3.9I
OUT
= 0.9 AHigh frequency output voltageripple
V
RIPPLE(SW)
V
IN
= 230 VAC , f
LINE
= 50 Hz 3.9I
OUT
= 0.9 A
VppV
RIPPLE(f_LINE)
V
IN
= 115 VAC, f
LINE
= 60 Hz, 19.5I
OUT
= 0.9 ALine frequency output voltageripple
V
RIPPLE(f_LINE)
V
IN
= 230 VAC, f
LINE
= 50 Hz 19.5I
OUT
= 0.9 AI
OUTOutput load current 85 VAC ≤V
IN
≤265 VAC 0.9 A47 Hz ≤f
LINE
≤63 HzOutput power P
OUT
350 WOutput over voltage protection V
OUT(OVP)
410
VOutput under voltage protection V
OUT(UVP)
370
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UCC28019
SLUS755 – APRIL 2007
DESIGN EXAMPLE (continued)Table 1. Design Goal Parameters (continued)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Control loop characteristics
Switching frequency f
SW
, T
J
= 25 °C 61.7 65 68.3 kHzf
(CO)Control loop bandwidth 10 HzV
IN
= 162 VDC, I
OUT
= 0.45 APhase margin V
IN
= 162 VDC, I
OUT
= 0.45 A 70 degreesPFPower factor 0.99V
IN
= 115 VAC, I
OUT
= 0.9 ATHD
V
IN
= 115 VAC, f
LINE
= 60 Hz 4.13% 10%I
OUT
= 0.9 ATotal harmonic distortion
THD
V
IN
= 230 VAC, f
LINE
= 50 Hz 6.67% 10%I
OUT
= 0.9 AηFull load efficiency V
IN
= 115 VAC, f
LINE
= 60 Hz, 0.92I
OUT
= 0.9 AAmbient temperature T
AMB
50 °C
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+
+
UCC28019
SLUS755 – APRIL 2007
The following procedure refers to the schematic shown in Figure 28 .
Figure 28. Design Example Schematic
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Current Calculations
OUT (max)
OUT (max)
OUT
P
IV
=
350 0 9
390
OUT (max)
W
I . A
V
= @
OUT (max)
IN _ RMS(max)
IN (min)
P
IV PFh
=
350 4 52
0 92 85 0 99
IN _ RMS(max)
W
I . A
. V .
= =
´ ´
2
IN _ PEAK(max) IN _ RMS (max)
I I=
2 4 52 6 39
IN _ PEAK (max)
I . A . A= ´ =
2IN _ PEAK (max)
IN _ AVG(max)
I
Ip
=
2 6 39 4 07
IN _ AVG(max)
. A
I . A
p
´
= =
Bridge Rectifier
2
BRIDGE F _ BRIDGE IN _ AVG(max)
P V I=
2 0 95 4 07 7 73
BRIDGE
P . V . A . W= ´ ´ =
UCC28019
SLUS755 – APRIL 2007
First, determine the maximum average output current, I
OUT(max)
:
The maximum input RMS line current, I
IN_RMS(max)
, is calculated using the parameters from Table 1 and theefficiency and power factor initial assumptions:
Based upon the calculated RMS value, the maximum peak input current, I
IN_PEAK(max)
, and the maximum averageinput current, I
IN_AVG(max)
, assuming the waveform is sinusoidal, can be determined.
Assuming a forward voltage drop, V
F_BRIDGE
, of 0.95 V across the rectifier diodes, BR1, the power loss in theinput bridge, P
BRIDGE
, can be calculated:
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Input Capacitor
RIPPLE RIPPLE IN _ PEAK (max)
I I I= D
0 2
RIPPLE
I .D =
0 2 6 39 1 28
RIPPLE
I . . A . A= ´ =
IN _ RIPPLE(max) RIPPLE _ IN IN _ RECTIFIED(max)
V V V= D
0 06
RIPPLE _ IN
V .D =
2
IN _ RECTIFIED IN
V V=
2 265 375
IN _ RECTIFIED(max)
V V V= ´ =
0 06 375 7 21
IN _ RIPPLE(max)
V . V . V= ´ =
8
RIPPLE
IN
SW IN _ RIPPLE(max)
I
Cf V
=
1 28 0 341
8 65 7 21
IN
. A
C . F
kHz . V m= =
´ ´
UCC28019
SLUS755 – APRIL 2007
Note that the UCC28019 is a continuous conduction mode controller and as such the inductor ripple currentshould be sized accordingly. Allowing an inductor ripple current, I
RIPPLE
, of 20% and a high frequency voltageripple factor, V
RIPPLE_IN
, of 6%, the maximum input capacitor value, C
IN
, is calculated by first determining theinput ripple current, I
RIPPLE
, and the input voltage ripple, V
IN_RIPPLE(max)
:
The value for the input x-capacitor can now be calculated:
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Boost Inductor
2
RIPPLE
L _ PEAK(max) IN _ PEAK (max)
I
I I= +
1 28
6 39 7 03
2
L _ PEAK (max)
. A
I . A . A= + =
1
OUT
BST (min)
SW ( typ ) RIPPLE
V D( D )
Lf I
-
³
390 0 5 1 0 5 1 17
65 1 28
BST (min)
V . ( . )
L . mH
kHz . A
´ -
³ ³
´
OUT IN _ RECTIFIED(min)
(max)
OUT
V V
DUTY V
-
=
2 85 120
IN _ RECTIFIED(min)
V V V= ´ =
390 120 0 692
390
(max)
V V
DUTY .
V
-
= =
Boost Diode
125 0 5
DIODE F _ C OUT (max) SW ( typ ) OUT RR
P V I . f V Q= +
125 1 5
F _ C
V . V=
0
RR
Q nC=
1 5 0 897 0 5 65 390 0 1 35
DIODE
P . V . A . kHz V nC . W= ´ + ´ ´ ´ =
UCC28019
SLUS755 – APRIL 2007
The boost inductor, L
BST
, is selected after determining the maximum inductor peak current, I
L_PEAK(max)
:
The minimum value of the boost inductor is calculated based upon a worst case duty cycle of 0.5:
The actual value of the boost inductor that will be used is 1.25 mH.
The maximum duty cycle, DUTY
(max)
, can be calculated and will occur at the minimum input voltage:
The diode losses are estimated based upon the forward voltage drop, V
F
, at 125 °C and the reverse recoverycharge, Q
RR
, of the diode. Using a silicone carbide diode, although more expensive, will essentially eliminate thereverse recovery losses:
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Switching Element
2
125COND DS _ RMS DSon( C )
P I R=
125 0 35
DSon( C )
R .= W
16
23
OUT (max) IN _ RECTIFIED(min)
DS _ RMS
IN _ RECTIFIED(min) OUT
P V
IV Vp
= -
350 16 120
2 3 54
120 3 390
DS _ RMS
W V
I . A
V Vp
´
= - =
´
2
3 54 0 35 4 38
COND
P . A . . W= ´ W =
4 5
r
t . ns=
780
OSS
C pF=
2
0 5
SW SW ( typ ) r OUT IN _ PEAK (max) OSS OUT
P f ( t V I . C V )= +
2
65 4 5 390 6 39 0 5 780 390 4 59
SW
P kHz( . ns V . A . pF V ) . W= ´ ´ + ´ ´ =
4 38 4 59 8 97
COND SW
P P . W . W . W+ = + =
UCC28019
SLUS755 – APRIL 2007
The conduction losses of the switch are estimated using the R
DS(on)
of the FET at 125 °C , found in the FET datasheet, and the calculated drain to source RMS current, I
DS_RMS
:
The switching losses are estimated using the rise time of the gate, t
r
, and the output capacitance losses.
For the selected device:
Total FET losses:
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Sense Resistor
1 25
SOC
SENSE
L _ PEAK (max)
V
RI .
=´
0 66 0 075
7 03 1 25
SENSE
. V
R .
. A .
= = W
´
0 067
SENSE
R .= W
SENSERMSINRsense RIP 2
(max)_
=
2
4 52 0 067 1 36
Rsense
P . A . . W= ´ W =
PCL
PCL
SENSE
V
IR
=
1 15 17 25
0 067
PCL
. V
I . A
.
= =
W
UCC28019
SLUS755 – APRIL 2007
To accommodate the gain of the internal non-linear power limit, R
SENSE
, is sized such that it will trigger the softover-current at 25% higher than the maximum peak inductor current using the minimum SOC threshold, V
SOC
, ofISENSE.
Using a parallel combination of available standard value resistors, the sense resistor is chosen.
The power dissipated across the sense resistor, P
Rsense
, must be calculated:
The peak current limit, PCL, protection feature will be triggered when current through the sense resistor resultsin the voltage across R
SENSE
to be equal to the V
PCL
threshold. For a worst case analysis, the maximum V
PCLthreshold is used:
To protect the device from inrush current, a standard 220-m Ωresistor, R
ISENSE
, is placed in series with theISENSE pin. A 1000-pF capacitor is placed close to the device to improve noise immunity on the ISENSE pin.
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Output Capacitor
2 2
2OUT HOLDUP
OUT (min)
OUT OUT _ HOLDUP(min)
P t
CV V
³-
2 2
2 350 21 28 240
390 300
OUT (min)
W . ms
C F
V V m
´ ´
³ ³
-
0 05
OUT _ RIPPLE( pp ) OUT
V . V<
0 05 390 19 5
OUT _ RIPPLE( pp ) PP
V . V . V< ´ <
2
OUT
OUT _ RIPPLE( pp )
LINE(min) OUT
I
V( f )Cp
=
0 9 11 26
2 47 270
OUT _ RIPPLE( pp )
. A
V . V
( Hz ) Fp m
= =
´ ´
22
OUT (max)
Cout _ fline
I
I=
2
0 9 0 635
2
Cout _ fline
. A
I . A= =
16 1 5
3
OUT
Cout _ HF OUT (max)
IN _ RECTIFIED(min)
V
I I .
Vp
= -
16 390
0 9 1 5 1 8
3 120
Cout _ HF
V
I . A . . A
Vp
´
= - =
´
2 2
2Cout _ RMS( total ) Cout _ fline Cout _ HF
I I I= +
2 2
0 635 1 8 1 9
Cout _ RMS( total )
I . A . A . A= + =
UCC28019
SLUS755 – APRIL 2007
The output capacitor, C
OUT
, is sized to meet holdup requirements of the converter. Assuming the downstreamconverters require the output of the PFC stage to never fall below 300 V, V
OUT_HOLDUP(min)
, during one line cycle,t
HOLDUP
= 1/f
LINE(min)
, the minimum calculated value for the capacitor is:
It is advisable to de-rate this capacitor value by 20%; the actual capacitor used is 270 µF.
Setting the maximum peak-to-peak output ripple voltage to be less than 5% of the output voltage will ensure thatthe ripple voltage will not trigger the output over-voltage or output under-voltage protection features of thecontroller. The maximum peak-to-peak ripple voltage, occurring at twice the line frequency, and the ripplecurrent of the output capacitor are calculated:
The required ripple current rating at twice the line frequency is equal to:
There will also be a high frequency ripple current through the output capacitor:
The total ripple current in the output capacitor is the combination of both and the output capacitor must beselected accordingly:
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Output Voltage Set Point
1
2
REF FB
FB
OUT REF
V R
RV V
=-
2
5 1 13 04
390 5
FB
V M
R . k
V V
´ W
= = W
-
1 2
2
FB FB
OUT ( OVP ) OVP
FB
R R
V VSENSE R
æ ö
+
=ç ÷
è ø
1 13
5 25 410 7
13
OUT ( OVP )
M k
V . V . V
k
W + W
æ ö
= ´ =
ç ÷
W
è ø
1 2
2
FB FB
OUT ( UVD ) UVD
FB
R R
V VSENSE R
æ ö
+
=ç ÷
è ø
1 13
4 75 371 6
13
OUT ( UVD )
M k
V . V . V
k
W + W
æ ö
= ´ =
ç ÷
W
è ø
UCC28019
SLUS755 – APRIL 2007
For low power dissipation and minimal contribution to the voltage set point error, it is recommended to use 1 M Ωfor the top voltage feedback divider resistor, R
FB1
. Multiple resistors in series are used due to the maximumallowable voltage across each. Using the internal 5-V reference, V
REF
, select the bottom divider resistor, R
FB2
, tomeet the output voltage design goals.
Using 13 k Ωfor R
FB2
results in a nominal output voltage set point of 391 V.
The over-voltage protection, OVD, will be triggered when the output voltage exceeds 5% of its nominal set-point:
The under-voltage detection, UVD, will be triggered when the output voltage falls below 5% of its nominalset-point:
A small capacitor on VSENSE must be added to filter out noise that would trigger the enhanced dynamicresponse in a no-load high-line configuration. Limit the value of the filter capacitor such that the RC timeconstant is less than 0.1ms so as not to significantly reduce the control response time to output voltagedeviations.
32
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Loop Compensation
2
1
1 2 2 2
OUT (max) OUT SENSE
IN _ RMS FQ
I V R K
M M V Kh
=
1
FQ
SW ( typ )
Kf
=
115 385
65
FQ
K . s
kHz m= =
17K=
2
1 2 2 2
0 9 390 0 067 7 0 372
0 92 115 15 385
. A V . V
M M .
. V . s sm m
´ ´ W´
= =
´ ´
VCOMP - V
0
0.4
0.8
1.2
1.6
2.0
M1M2
M1M2
vs
VCOMP
0.2
0.6
1.0
1.4
1.8
0 1 2 5 73 4 6
UCC28019
SLUS755 – APRIL 2007
The selection of compensation components, for both the current loop and the voltage loop, is made easier byusing the UCC28019 Design Calculator spreadsheet that can be found in the Tools section of the UCC28019product folder on the Texas Instruments website. The current loop is compensated first by determining theproduct of the internal loop variables, M
1
M
2
, using the internal controller constants K
1
and K
FQ
:
The VCOMP operating point is found on Figure 29 . The Design Calculator spreadsheet enables the user toiteratively select the appropriate VCOMP value.
Figure 29. M
1
M
2
vs. VCOMP
For the given M
1
M
2
of 0.372 V/ µs, the VCOMP, approximately equal to 4, as shown in Figure 29 .
33Submit Documentation Feedback
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1
0 2
0 064
if : VCOMP
then : M .
< <
=
1
2 3
0 139 0 214
if : VCOMP
then : M . VCOMP .
£ <
= ´ -
1
3 5 5
0 279 0 632
if : VCOMP .
then : M . VCOMP .
£ <
= ´ -
1
5 5 7
0 903
if : . VCOMP
then : M .
£ <
=
1
4
0 279 4 0 632 0 484
VCOMP
M . . .
=
= ´ - =
2
0 1 5
0
if : VCOMP .
V
then : M sm
< <
=
2
2
1 5 5 6
0 1223 1 5
if : . VCOMP .
V
then : M . (VCOMP . ) sm
£ <
= ´ -
2
5 6 7
2 056
if : . VCOMP
V
then : M . sm
£ <
=
2
2
4
0 1223 4 1 5 0 764
VCOMP
V V
M . ( . ) .
s sm m
=
= ´ - =
UCC28019
SLUS755 – APRIL 2007
The individual loop factors, M
1
which is the current loop gain factor, and M
2
which is the voltage loop PWM rampslope, are calculated using the following conditions:
The M
1
current loop gain factor:
The M
2
PWM ramp slope:
34
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1 2 0 484 0 764 0 37
V V
M M . . .
s sm m
´ = ´ =
1 2
0 37 0 372
V V
. M M .
s sm m
@ =
2
3
0 3
0 0510 0 1543 0 1167
if : VCOMP
then : M . VCOMP . VCOMP .
< <
= ´ - ´ -
2
3
3 7
0 1026 0 3596 0 3085
if : VCOMP
then : M . VCOMP . VCOMP .
£ <
= ´ - ´ +
2
3
4
0 1026 4 0 3596 4 0 3085 0 512
VCOMP
M . . . .
=
= ´ - ´ + =
1
12
ICOMP
IAVG
gmiM
CK fp
=
0 95 0 484 1100
7 2 9 5
ICOMP
. mS .
C pF
. kHzp
´
= =
´ ´ ´
UCC28019
SLUS755 – APRIL 2007
Verify that the product of the individual gain factors is approximately equal to the M
1
M
2
factor determined above,if not, reselect VCOMP and recalculate M
1
M
2
.
The non-linear gain variable, M
3
, can now be calculated:
The frequency of the current averaging pole, f
IAVG
, is chosen to be at 9.5 kHz. The required capacitor onICOMP, C
ICOMP
, for this is determined using the transconductance gain, gmi, of the internal current amplifier:
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1
2
1
1 2
1
1
SENSE OUT
CL
ICOMP
FQ BST
K R V
G ( f ) s( f ) K C
K M M L s( f ) gmiM
= ´
+
( )
20
CLdB CL
G ( f ) log G ( f )=
1*104
qGCL(f)
f - Hz
-100
-60
-20
20
60
100
GCLdB(f)
CURRENT AVERAGING CIRCUIT
-80
-40
0
40
80
10 100 1*1031*106
1*105
-180
-160
-140
-120
-100
-80
Gain
Phase
UCC28019
SLUS755 – APRIL 2007
The transfer function of the current loop can be plotted:
Figure 30. Bode Plot of the Current Averaging Circuit.
36
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2
1 2
FB
FB
FB FB
R
GR R
=+
13 0 013
1 13
FB
k
G .
M k
W
= =
W + W
3
1
2
1 2
1
2
PWM _ PS
SENSE OUT OUT
FQ IN ( typ )
fK R V C
K M M V
p
=
3
2
11 589
7 0 067 390 270
2
15 385 0 484 0 764 115
PWM _ PS
f . Hz
. V F
V
. s . . V
s
m
p
mm
= =
´ W´ ´
´ ´ ´
3
1 2 1
12
OUT
PWM _ PS
PWM _ PS
M V
M M s
G ( f ) s( f )
f
m
p
´
=
+
VL FB PWM _ PS
G ( f ) G G ( f )=
( )
20
VLdB VL
G ( f ) log G ( f )=
UCC28019
SLUS755 – APRIL 2007
The open loop of the voltage transfer function, G
VL
(f) contains the product of the voltage feedback gain, G
FB
,and the gain from the pulse width modulator to the power stage, G
PWM_PS
, which includes the pulse widthmodulator to power stage pole, f
PWM_PS
. The plotted result is shown in Figure 31 .
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1*104
qGVL(f)
f - Hz
-60
20
GVLdB(f)
OPEN LOOP VOLTAGE TRANSFER
FUNCTION
-40
-20
0
10 100 1*103
-100
-80
-60
-40
-20
0
10.10.01
Gain
Phase
UCC28019
SLUS755 – APRIL 2007
Figure 31. Bode Plot of the Open Loop Voltage Transfer Function
38
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1
2
ZERO
VCOMP VCOMP
fR Cp
=
1
2
POLE
VCOMP VCOMP VCOMP _ P
VCOMP VCOMP _ P
fR C C
C C
p
=
+
( )
1
1
VCOMP VCOMP
EA
VCOMP VCOMP VCOMP _ P
VCOMP VCOMP _ P
VCOMP VCOMP _ P
s( f )R C
G ( f ) gmv
R C C
C C s( f ) s( f ) C C
é ù
ê ú
ê ú
+
=ê ú
é ù
æ ö
ê ú
+ +
ê ú
ç ÷
ê ú
ç ÷
+
ê ú
è ø
ë û
ë û
10
V
f Hz=
20
10 2
G ( f )
VLdB
V
PWM _ PS
VCOMP
V
f
gmv f
C
fp
=´
0 709
20
10
42 1 589 3 88
10 2 10
. dB
VCOMP
Hz
S. Hz
C . F
Hz
m
m
p
´
= =
´ ´ ´
1
2
VCOMP
ZERO VCOMP
Rf Cp
=
130 36
2 1 589 3 3
VCOMP
R . k
. Hz . Fp m
= = W
´ ´ ´
2 1
VCOMP
VCOMP _ P
POLE VCOMP VCOMP
C
Cf R Cp
=-
3 3 0 258
2 20 33 3 3 1
VCOMP _ P
. F
C . F
Hz k . F
mm
p m
= =
´ ´ ´ W´ -
UCC28019
SLUS755 – APRIL 2007
The voltage error amplifier is compensated with a zero, f
ZERO
, at the f
PWM_PS
pole and a pole, f
POLE
, placed at 20Hz to reject high frequency noise and roll off the gain amplitude. The overall voltage loop crossover, f
V
, isdesired to be at 10 Hz. The compensation components of the voltage error amplifier are selected accordingly.
From Figure 31 , and the Design Calculator spreadsheet, the open loop gain of the voltage transfer function at 10Hz is approximately 0.709 dB. Estimating that the parallel capacitor, C
VCOMP_P
, is much smaller than the seriescapacitor, C
VCOMP
, the unity gain will be at f
V
, and the zero will be at f
PWM_PS
, the series compensation capacitoris determined:
A 3.3- µF capacitor is used for C
VCOMP
.
A 33-k Ωresistor is used for R
VCOMP
.
A 0.22- µF capacitor is used for C
VCOMP_P
.
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VL _ total FB PWM _ PS EA
G ( f ) G ( f )G ( f )G ( f )=
( )
20
VL _ totaldB VL _ total
G ( f ) log G ( f )=
1*104
f - Hz
-150
100
GVL_totaldB(f)
CLOSED LOOP VOLTAGE TRANSFER
FUNCTION
-50
0
50
10 100 1*103
0
20
40
60
80
100
10.10.01
-100
qGVL_total(f)
Gain
Phase
UCC28019
SLUS755 – APRIL 2007
The total closed loop transfer function, G
VL_total
, contains the combined stages and is plotted in Figure 32 .
Figure 32. Closed Loop Voltage Bode Plot
40
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Brown Out Protection
0
150
VINS VINS _ V
I I= ´
150 0 1 150
VINS
I . A Am m= ´ =
75
AC( on )
V V=
65
AC ( off )
V V=
1
2AC( on ) F _ BRIDGE ENABLE _ th(max)
VINS
VINS
V V VINS
RI
´ - -
=
1
2 75 0 95 1 6 6 9
150
VINS
V . V . V
R . M
Am
´ - -
= = W
1
22
ENABLE _ th(max) VINS
VINS
AC( on ) ENABLE _ th(max) F _ BRIDGE
VINS R
RV VINS V
´
=´ - -
2
1 6 6 5 100
2 75 1 6 0 95
VINS
. V . M
R k
V . V . V
´ W
= = W
´ - -
UCC28019
SLUS755 – APRIL 2007
Select the top divider resistor into the VINS pin so as not to contribute excessive power loss. The extremely lowbias current into VINS means the value of R
VINS1
could be hundreds of megaohms. For practical purposes, avalue less than 10 M Ωis usually chosen. Assuming approximately 150 times the input bias current through theresistor dividers will result in an R
VINS1
that is less than 10 M Ω, so as to not contribute excessive noise, and stillmaintain minimal power loss. The brown out protection will turn off the gate drive when the input falls below theuser programmable minimum voltage, V
AC(off)
, and turn on when the input rises above V
AC(on)
.
A 6.5-M resistance is chosen.
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2
HALF _ CYCLES
CVINS _ dischrg
LINE (min)
N
tf
=´
2 5 25 6
2 47
CVINS _ dischrg
.
t . ms
Hz
= =
´
2
2
1 2
0 9
CVINS _ dischrg
VINS
BROWNOUT _ th(min)
VINS
VINS
IN _ RMS(min)
VINS VINS
t
C
VINS
R ln R
. V R R
-
=é ù
ê ú
ê ú
´ê ú
æ ö
´ ´
ê ú
ç ÷
+
ê ú
è ø
ë û
25 6 0 63
0 76
100 100
0 9 85 6 5 100
VINS
. ms
C . F
. V
k ln k
. V . M k
m
-
= =
é ù
ê ú
ê ú
W´ W
æ ö
ê ú
´ ´ç ÷
ê ú
W + W
è ø
ë û
UCC28019
SLUS755 – APRIL 2007
The capacitor on VINS, C
VINS
, is selected so that it's discharge time is greater than the output capacitor hold uptime. C
OUT
was chosen to meet one-cycle hold-up time so C
VINS
will be chosen to meet 2.5 half-line cycles.
42
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REFERENCES
RELATED PRODUCTS
UCC28019
SLUS755 – APRIL 2007
These references, additional design tools, and links to additional references, including design software andmodels may be found on the web at http://www.power.ti.com under Technical Documents.
Evaluation Module, 350-W Universal Input, 390-V
DC
Output PFC Converter, Texas Instruments Literature No.SLUA272
Design Spreadsheet, UCC28019 Design Calculator, Texas Instruments
The following parts have characteristics similar to the UCC28019 and may be of interest.
Related Products
DEVICE DESCRIPTION
UCC3817/18 Full-Feature PFC ControllerUC2853A 8-Pin CCM PFC Controller
43Submit Documentation Feedback
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
www.ti.com 17-May-2007
Pack Materials-Page 1
Device Package Pins Site Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC28019DR D 8 FMX 330 0 6.4 5.2 2.1 8 12 PKGORN
T1TR-MS
P
TAPE AND REEL BOX INFORMATION
Device Package Pins Site Length (mm) Width (mm) Height (mm)
UCC28019DR D 8 FMX 342.9 336.6 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 17-May-2007
Pack Materials-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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