IO3
GND VCC
IO4
1
2
6
3
5
4
DBV/DCK PACKAGE
(TOP VIEW)
IO1
IO2
IO3
GND
VCC
IO4
1
2
6
3
5
4
DRL PACKAGE
(TOP VIEW)
IO2
IO1
QFN PACKAGE
(TOP VIEW)
IO1
IO2
GND
VCC
IO4
IO3
GND
1
2
34
5
6
DPK PACKAGE
(TOP VIEW)
IO1
IO2
GND
VCC
IO4
IO3
1
2
34
5
6
TPD4E001
www.ti.com
SLLS682H –JULY 2006–REVISED JULY 2012
4-CHANNEL ESD PROTECTION ARRAY WITH 1.5-pF IO CAPACITANCE
Check for Samples: TPD4E001
1FEATURES
2• 4-Channel ESD Clamp Array to Enhance • Alternate 2-, 3-, 6-Channel Options Available:
System-Level ESD Protection TPD2E001, TPD3E001, and TPD6E001
APPLICATIONS
• Exceeds IEC61000-4-2 (Level 4) ESD
Protection Requirements • USB 2.0
– ±8-kV IEC 61000-4-2 Contact Discharge • Ethernet
– ±15-kV IEC 61000-4-2 Air-Gap Discharge • FireWire™
• ±15-kV Human-Body Model (HBM) • Precision Analog Interface
• 5.5-A Peak Pulse Current (8/20-us Pulse) • SVGA Connections
• Low 1.5-pF Input Capacitance
• Low 1-nA (Max) Leakage Current
• 0.9-V to 5.5-V Supply-Voltage Range
• Space-Saving DRL, DBV, DCK, and DRS
Package Options
DESCRIPTION/ORDERING INFORMATION
The TPD4E001 is a low-capacitance ±15-kV ESD-protection diode array designed to protect sensitive electronics
attached to communication lines. Each channel consists of a pair of diodes that steer ESD current pulses to VCC
or GND. The TPD4E001 protects against ESD pulses up to ±15-kV Human-Body Model (HBM), ±8-kV Contact
Discharge, and ±15-kV Air-Gap Discharge, as specified in IEC 61000-4-2. This device has a 1.5-pF IO
capacitance per channel, making it ideal for use in high-speed data IO interfaces. The ultra low leakage current
(<1 nA max) is suitable for precision analog measurements in applications like glucose meters, heart rate
monitors, etc.
The TPD4E001 is available in DRL, DBV (SOT-23), DCK (SC-70), DRS (QFN), and DPK (PUSON) packages
and is specified for –40°C to 85°C operation.
ORDERING INFORMATION
TAPACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING
1.6 × 1.6 DRL Reel of 4000 TPD4E001DRLR 2CR, 2C7
2.9 × 2.8 DBV (SOT-23) Reel of 3000 TPD4E001DBVR NFY5
–40°C to 85°C 2.1 × 2.0 DCK (SC-70) Reel of 3000 TPD4E001DCKR 2CF, 2CR
3 × 3 DRS (QFN) Reel of 1000 TPD4E001DRSR ZWM
1.6 × 1.6 DPK (PUSON) Reel of 5000 TPD4E001DPKR 2C7
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2FireWire is a trademark of Apple Computer, Inc.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
IO3 IO4
GND
IO2IO1
VCC
TPD4E001
SLLS682H –JULY 2006–REVISED JULY 2012
www.ti.com
Figure 1. FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
DRS/DRL/DPK NO. DBV/DCK NO. NAME FUNCTION
1, 2, 4, 5 1, 3, 4, 6 IOx ESD-protected channel
3 2 GND Ground
6 5 VCC Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor.
Exposed Thermal
Pad (DRS package N/A Exposed thermal pad. Connect to GND or leave floating.
only)
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC –0.3 7 V
VI/O IO voltage tolerance –0.3 VCC + 0.3 V
Tstg Storage temperature range –65 150 °C
TJJunction temperature 150 °C
Infrared (15 s) 220
Bump temperature (soldering) °C
Vapor phase (60 s) 215
Lead temperature (soldering, 10 s) 300 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2Submit Documentation Feedback Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): TPD4E001
TPD4E001
www.ti.com
SLLS682H –JULY 2006–REVISED JULY 2012
Electrical Characteristics
VCC = 5 V ± 10%, TA= -40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VCC Supply voltage 0.9 5.5 V
ICC Supply current 1 100 nA
VFDiode forward voltage IF= 10 mA 0.65 0.95 V
VBR Breakdown Voltage IBR = 10mA 11 V
Positive transients VCC + 25
TA= 25°C, ±15-kV HBM,
IF= 10 A Negative transients –25
TA= 25°C, Positive transients VCC + 60
±8-kV Contact Discharge
VCChannel clamp voltage(2) V
Negative transients –60
(IEC 61000-4-2), IF= 24 A
TA= 25°C, Positive transients VCC + 100
±15-kV Air-Gap Discharge Negative transients –100
(IEC 61000-4-2), IF= 45 A
Ii/o Channel leakage current Vi/o = GND to VCC ±1 nA
Ci/o Channel input capacitance VCC = 5 V, Bias of VCC/2 1.5 pF
(1) Typical values are at VCC = 5 V and TA= 25°C.
(2) Channel clamp voltage is not production tested
ESD Protection PARAMETER TYP UNIT
HBM ±15 kV
IEC 61000-4-2 Contact Discharge ±8 kV
IEC 61000-4-2 Air-Gap Discharge ±15 kV
Peak Pulse Current, IPK (Tp = 8/20 µs) 5.5 Amps
Peak Pulse Power, PPK (Tp = 8/20 µs) 100 Watts
Copyright © 2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPD4E001
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0 5 10 15 20 25 30 35 40 45 50
Time ( s)μ
0
10
20
30
40
50
60
70
80
90
100
I (A)
PK
P (W)
PK
Power (W)
Current (A)
1
10
100
1000
–40 25 45 65 85
Temperature(°C)
IOLeakageCurrent(pA)
0.00 1.00 2.00 2.50 3.00 4.00 5.00
IO Voltage (V)
1.00
1.20
1.40
1.60
1.80
2.00
2.20
IO Capacitance (pF)
TPD4E001
SLLS682H –JULY 2006–REVISED JULY 2012
www.ti.com
TYPICAL OPERATING CHARACTERISTICS
IO CAPACITANCE
vs
IO VOLTAGE
(VCC = 5.0 V)
IO LEAKAGE CURRENT
vs
TEMPERATURE
(VCC = 5.5 V)
PEAK PULSE WAVEFORM, VCC = 5.5 V
4Submit Documentation Feedback Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): TPD4E001
IO3
IO4
GND
IO2
IO1
0.1µF
VCC
USB
Controller
RT
VBUS
D+
D–
GND
VBUS
D+
D–
GND
D1
TPD4E001
www.ti.com
SLLS682H –JULY 2006–REVISED JULY 2012
APPLICATION INFORMATION
Detailed Description
When placed near the connector, the TPD4E001 ESD solution offers little or no signal distortion during normal
operation due to low IO capacitance and ultra-low leakage current specifications. The TPD4E001 ensures that
the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper
operation, the following layout/ design guidelines should be followed:
1. Place the TPD4E001 solution close to the connector. This allows the TPD4E001 to take away the energy
associated with ESD strike before it reaches the internal circuitry of the system board.
2. Place a 0.1-μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin
during the ESD strike event.
3. Ensure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD4E001
consumes nA leakage current. But during the ESD event, VCC and GND may see 15 A to
30 A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy
associated with the ESD strike.
4. Leave the unused IO pins floating .
5. The VCC pin can be connected in two different ways:
(a) If the VCC pin is connected to the system power supply, the TPD4E001 works as a transient suppressor
for any signal swing above VCC + VF. A 0.1-μF capacitor on the device VCC pin is recommended for ESD
bypass.
(b) If the VCC pin is not connected to the system power supply, the TPD4E001 can tolerate higher signal
swing in the range up to 10V. Please note that a 0.1μF capacitor is still recommended at the VCC pin for
ESD bypass.
Copyright © 2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPD4E001
TPD4E001
SLLS682H –JULY 2006–REVISED JULY 2012
www.ti.com
REVISION HISTORY
Changes from Revision C (April 2007) to Revision D Page
• Added DVB (SOT-23) package and package information. ................................................................................................... 1
Changes from Revision D (December 2010) to Revision E Page
• Added DCK (SC-70) Package to Ordering Information table. .............................................................................................. 1
Changes from Revision E (April 2011) to Revision F Page
• Added Peak Pulse current and power values to ESD Protection Table. .............................................................................. 3
• Added Peak Pulse Waveform Graph to Typical Operating Characteristics. ........................................................................ 4
Changes from Revision F (May 2011) to Revision G Page
• Added DPK (PUSON) package and package information. ................................................................................................... 1
Changes from Revision G (December 2011) to Revision H Page
• Updated TOP-SIDE MARKING column in ORDERING INFORMATION table. ................................................................... 1
6Submit Documentation Feedback Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): TPD4E001
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jun-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPD4E001DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPD4E001DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPD4E001DPKR ACTIVE USON DPK 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPD4E001DPKT ACTIVE USON DPK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPD4E001DRLR ACTIVE SOT DRL 6 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPD4E001DRLRG4 ACTIVE SOT DRL 6 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPD4E001DRSR ACTIVE SON DRS 6 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jun-2012
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPD4E001DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.2 1.55 4.0 8.0 Q3
TPD4E001DPKR USON DPK 6 5000 180.0 9.5 1.75 1.75 0.7 4.0 8.0 Q2
TPD4E001DPKT USON DPK 6 250 180.0 9.5 1.75 1.75 0.7 4.0 8.0 Q2
TPD4E001DRLR SOT DRL 6 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3
TPD4E001DRLR SOT DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
TPD4E001DRSR SON DRS 6 1000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPD4E001DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
TPD4E001DPKR USON DPK 6 5000 180.0 180.0 30.0
TPD4E001DPKT USON DPK 6 250 180.0 180.0 30.0
TPD4E001DRLR SOT DRL 6 4000 180.0 180.0 30.0
TPD4E001DRLR SOT DRL 6 4000 202.0 201.0 28.0
TPD4E001DRSR SON DRS 6 1000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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