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April 1st, 2010

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32182 Group

User’s Manual

Rev.1.00 2003.06

RENESAS 32-BIT RISC SINGLE-CHIP

MICROCOMPUTER

M32R FAMILY / M32R/ECU SERIES

All information contained in these materials, including products and product speciﬁcations,

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REVISION HISTORY

Rev. Date Description

Page Summary

(1/1)

32182 Group User’s Manual

1.00 Jun 4, 2003 First edition issued –

(1)

Table of contents

CHAPTER 1 OVERVIEW

1.1 Outline of the 32182 Group ---------------------------------------------------------------------------------------------1-2

1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU) ---------------------------------------------1-2

1.1.2 Built-in Multiplier/Accumulator-------------------------------------------------------------------------------1-3

1.1.3 Built-in Single-precision FPU --------------------------------------------------------------------------------1-3

1.1.4 Built-in Flash Memory and RAM ----------------------------------------------------------------------------1-3

1.1.5 Built-in Clock Frequency Multiplier-------------------------------------------------------------------------1-4

1.1.6 Powerful Peripheral Functions Built-in --------------------------------------------------------------------1-4

1.2 Block Diagram--------------------------------------------------------------------------------------------------------------1-5

1.3 Pin Functions ---------------------------------------------------------------------------------------------------------------1-8

1.4 Pin Assignments -----------------------------------------------------------------------------------------------------------1-14

CHAPTER 2 CPU

2.1 CPU Registers -------------------------------------------------------------------------------------------------------------2-2

2.2 General-purpose Registers ---------------------------------------------------------------------------------------------2-2

2.3 Control Registers ----------------------------------------------------------------------------------------------------------2-2

2.3.1 Processor Status Word Register: PSW (CR0) ----------------------------------------------------------2-3

2.3.2 Condition Bit Register: CBR (CR1) ------------------------------------------------------------------------2-4

2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3)-------------------------2-4

2.3.4 Backup PC: BPC (CR6) --------------------------------------------------------------------------------------2-4

2.3.5 Floating-point Status Register: FPSR (CR7) ------------------------------------------------------------2-5

2.4 Accumulator-----------------------------------------------------------------------------------------------------------------2-7

2.5 Program Counter ----------------------------------------------------------------------------------------------------------2-7

2.6 Data Formats ---------------------------------------------------------------------------------------------------------------2-8

2.6.1 Data Types-------------------------------------------------------------------------------------------------------2-8

2.6.2 Data Formats ----------------------------------------------------------------------------------------------------2-9

2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution -----------------2-14

CHAPTER 3 ADDRESS SPACE

3.1 Outline of the Address Space ------------------------------------------------------------------------------------------3-2

3.2 Operation Modes ----------------------------------------------------------------------------------------------------------3-5

3.3 Internal ROM and Extended External Areas------------------------------------------------------------------------3-9

3.3.1 Internal ROM Area ---------------------------------------------------------------------------------------------3-9

3.3.2 Extended External Area --------------------------------------------------------------------------------------3-9

3.4 Internal RAM and SFR Areas ------------------------------------------------------------------------------------------3-10

3.4.1 Internal RAM Area ---------------------------------------------------------------------------------------------3-10

3.4.2 SFR (Special Function Register) Area --------------------------------------------------------------------3-10

3.5 EIT Vector Entry -----------------------------------------------------------------------------------------------------------3-33

3.6 ICU Vector Table ----------------------------------------------------------------------------------------------------------3-34

3.7 Notes about Address Space --------------------------------------------------------------------------------------------3-36

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CHAPTER 4 EIT

4.1 Outline of EIT---------------------------------------------------------------------------------------------------------------4-2

4.2 EIT Events ------------------------------------------------------------------------------------------------------------------4-3

4.2.1 Exception ---------------------------------------------------------------------------------------------------------4-3

4.2.2 Interrupt -----------------------------------------------------------------------------------------------------------4-5

4.2.3 Trap ----------------------------------------------------------------------------------------------------------------4-6

4.3 EIT Processing Procedure ----------------------------------------------------------------------------------------------4-6

4.4 EIT Processing Mechanism---------------------------------------------------------------------------------------------4-7

4.5 Acceptance of EIT Events-----------------------------------------------------------------------------------------------4-8

4.6 Saving and Restoring the PC and PSW -----------------------------------------------------------------------------4-8

4.7 EIT Vector Entry -----------------------------------------------------------------------------------------------------------4-10

4.8 Exception Processing ----------------------------------------------------------------------------------------------------4-11

4.8.1 Reserved Instruction Exception (RIE)---------------------------------------------------------------------4-11

4.8.2 Address Exception (AE) --------------------------------------------------------------------------------------4-12

4.8.3 Floating-Point Exception (FPE) -----------------------------------------------------------------------------4-13

4.9 Interrupt Processing ------------------------------------------------------------------------------------------------------4-15

4.9.1 Reset Interrupt (RI) --------------------------------------------------------------------------------------------4-15

4.9.2 System Break Interrupt (SBI)--------------------------------------------------------------------------------4-15

4.9.3 External Interrupt (EI) -----------------------------------------------------------------------------------------4-17

4.10 Trap Processing----------------------------------------------------------------------------------------------------------4-18

4.10.1 Trap ----------------------------------------------------------------------------------------------------------------4-18

4.11 EIT Priority Levels -------------------------------------------------------------------------------------------------------4-19

4.12 Example of EIT Processing -------------------------------------------------------------------------------------------4-20

4.13 Precautions on EIT ------------------------------------------------------------------------------------------------------4-22

CHAPTER 5 INTERRUPT CONTROLLER (ICU)

5.1 Outline of the Interrupt Controller--------------------------------------------------------------------------------------5-2

5.2 ICU Related Registers ---------------------------------------------------------------------------------------------------5-4

5.2.1 Interrupt Vector Register -------------------------------------------------------------------------------------5-5

5.2.2 Interrupt Request Mask Register ---------------------------------------------------------------------------5-6

5.2.3 SBI (System Break Interrupt) Control Register ---------------------------------------------------------5-7

5.2.4 Interrupt Control Registers -----------------------------------------------------------------------------------5-8

5.3 Interrupt Request Sources in Internal Peripheral I/O -------------------------------------------------------------5-11

5.4 ICU Vector Table ----------------------------------------------------------------------------------------------------------5-12

5.5 Description of Interrupt Operation -------------------------------------------------------------------------------------5-13

5.5.1 Acceptance of Internal Peripheral I/O Interrupts -------------------------------------------------------5-13

5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers --------------------------------------------5-15

5.6 Description of System Break Interrupt (SBI) Operation----------------------------------------------------------5-18

5.6.1 Acceptance of SBI ---------------------------------------------------------------------------------------------5-18

5.6.2 SBI Processing by Handler ----------------------------------------------------------------------------------5-18

CHAPTER 6 INTERNAL MEMORY

6.1 Outline of the Internal Memory -----------------------------------------------------------------------------------------6-2

6.2 Internal RAM----------------------------------------------------------------------------------------------------------------6-2

6.3 Internal Flash Memory ---------------------------------------------------------------------------------------------------6-2

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6.4 Registers Associated with the Internal Flash Memory -----------------------------------------------------------6-5

6.4.1 Flash Mode Register ------------------------------------------------------------------------------------------6-5

6.4.2 Flash Status Registers ----------------------------------------------------------------------------------------6-6

6.4.3 Flash Status Register 2 (FSTAT2)-------------------------------------------------------------------------6-6

6.4.4 Flash Control Registers---------------------------------------------------------------------------------------6-8

6.4.5 Virtual Flash S Bank Registers -----------------------------------------------------------------------------6-12

6.5 Programming the Internal Flash Memory----------------------------------------------------------------------------6-13

6.5.1 Outline of Internal Flash Memory Programming--------------------------------------------------------6-13

6.5.2 Controlling Operation Modes during Flash Programming--------------------------------------------6-18

6.5.3 Procedure for Programming/Erasing the Internal Flash Memory ----------------------------------6-21

6.5.4 Flash Programming Time (Reference)--------------------------------------------------------------------6-30

6.6 Virtual Flash Emulation Function --------------------------------------------------------------------------------------6-31

6.6.1 Virtual Flash Emulation Area --------------------------------------------------------------------------------6-32

6.6.2 Entering Virtual Flash Emulation Mode -------------------------------------------------------------------6-35

6.6.3 Application Example of Virtual Flash Emulation Mode------------------------------------------------6-36

6.7 Connecting to A Serial Programmer ----------------------------------------------------------------------------------6-38

6.8 Internal Flash Memory Protect Function-----------------------------------------------------------------------------6-40

6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory --------------------------------------6-41

CHAPTER 7 RESET

7.1 Outline of Reset------------------------------------------------------------------------------------------------------------7-2

7.2 Reset Operation -----------------------------------------------------------------------------------------------------------7-2

7.2.1 Reset at Power-on ---------------------------------------------------------------------------------------------7-3

7.2.2 Reset during Operation ---------------------------------------------------------------------------------------7-3

7.2.3 Reset at Entering RAM Backup Mode --------------------------------------------------------------------7-3

7.2.4 Reset Vector Relocation during Flash Programming--------------------------------------------------7-3

7.3 Internal State Immediately after Reset -------------------------------------------------------------------------------7-4

7.4 Things to Be Considered after Reset---------------------------------------------------------------------------------7-4

CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8.1 Outline of Input/Output Ports -------------------------------------------------------------------------------------------8-2

8.2 Selecting Pin Functions --------------------------------------------------------------------------------------------------8-3

8.3 Input/Output Port Related Registers----------------------------------------------------------------------------------8-5

8.3.1 Port Data Registers --------------------------------------------------------------------------------------------8-7

8.3.2 Port Direction Registers --------------------------------------------------------------------------------------8-8

8.3.3 Port Operation Mode Registers-----------------------------------------------------------------------------8-9

8.3.4 Port Peripheral Output Select Registers------------------------------------------------------------------8-20

8.3.5 Port Input Special Function Control Register------------------------------------------------------------8-21

8.4 Port Input Level Switching Function ----------------------------------------------------------------------------------8-24

8.5 Port Peripheral Circuits --------------------------------------------------------------------------------------------------8-27

8.6 Precautions on Input/Output Ports ------------------------------------------------------------------------------------8-31

(4)

CHAPTER 9 DMAC

9.1 Outline of the DMAC------------------------------------------------------------------------------------------------------9-2

9.2 DMAC Related Registers------------------------------------------------------------------------------------------------9-4

9.2.1 DMA Channel Control Registers ---------------------------------------------------------------------------9-6

9.2.2 DMA Software Request Generation Registers----------------------------------------------------------9-18

9.2.3 DMA Source Address Registers----------------------------------------------------------------------------9-19

9.2.4 DMA Destination Address Registers ----------------------------------------------------------------------9-20

9.2.5 DMA Transfer Count Registers -----------------------------------------------------------------------------9-21

9.2.6 DMA Interrupt Related Registers---------------------------------------------------------------------------9-22

9.3 Functional Description of the DMAC----------------------------------------------------------------------------------9-27

9.3.1 DMA Transfer Request Sources----------------------------------------------------------------------------9-27

9.3.2 DMA Transfer Processing Procedure ---------------------------------------------------------------------9-33

9.3.3 Starting DMA ----------------------------------------------------------------------------------------------------9-34

9.3.4 DMA Channel Priority -----------------------------------------------------------------------------------------9-34

9.3.5 Gaining and Releasing Control of the Internal Bus ----------------------------------------------------9-34

9.3.6 Transfer Units ---------------------------------------------------------------------------------------------------9-35

9.3.7 Transfer Counts-------------------------------------------------------------------------------------------------9-35

9.3.8 Address Space--------------------------------------------------------------------------------------------------9-35

9.3.9 Transfer Operation ---------------------------------------------------------------------------------------------9-35

9.3.10 End of DMA and Interrupt ------------------------------------------------------------------------------------9-37

9.3.11 Each Register Status after Completion of DMA Transfer --------------------------------------------9-37

9.4 Precautions about the DMAC ------------------------------------------------------------------------------------------9-38

CHAPTER 10 MULTIJUNCTION TIMERS

10.1 Outline of Multijunction Timers ---------------------------------------------------------------------------------------10-2

10.2 Common Units of Multijunction Timers -----------------------------------------------------------------------------10-8

10.2.1 MJT Common Unit Register Map--------------------------------------------------------------------------10-9

10.2.2 Prescaler Unit --------------------------------------------------------------------------------------------------10-10

10.2.3 Clock Bus and Input/Output Event Bus Control Unit -------------------------------------------------10-11

10.2.4 Input Processing Control Unit ------------------------------------------------------------------------------10-15

10.2.5 Output Flip-flop Control Unit --------------------------------------------------------------------------------10-21

10.2.6 Interrupt Control Unit -----------------------------------------------------------------------------------------10-26

10.3 TOP (Output-Related 16-Bit Timer) ---------------------------------------------------------------------------------10-43

10.3.1 Outline of TOP --------------------------------------------------------------------------------------------------10-43

10.3.2 Outline of Each Mode of TOP -------------------------------------------------------------------------------10-45

10.3.3 TOP Related Register Map ----------------------------------------------------------------------------------10-47

10.3.4 TOP Control Registers ----------------------------------------------------------------------------------------10-49

10.3.5 TOP Counters (TOP0CT–TOP10CT) ---------------------------------------------------------------------10-54

10.3.6 TOP Reload Registers (TOP0RL–TOP10RL)-----------------------------------------------------------10-55

10.3.7 TOP Correction Registers (TOP0CC–TOP10CC) -----------------------------------------------------10-56

10.3.8 TOP Enable Control Registers------------------------------------------------------------------------------10-57

10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function)--------------------------10-59

10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) --------------10-65

10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) ---------------------10-70

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10.4 TIO (Input/Output-Related 16-Bit Timer)---------------------------------------------------------------------------10-73

10.4.1 Outline of TIO ---------------------------------------------------------------------------------------------------10-73

10.4.2 Outline of Each Mode of TIO --------------------------------------------------------------------------------10-75

10.4.3 TIO Related Register Map -----------------------------------------------------------------------------------10-78

10.4.4 TIO Control Registers -----------------------------------------------------------------------------------------10-80

10.4.5 TIO Counters (TIO0CT–TIO9CT) --------------------------------------------------------------------------10-88

10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0)---------------------------------------------10-89

10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1) ----------------------------------------------------------10-90

10.4.8 TIO Enable Control Registers -------------------------------------------------------------------------------10-91

10.4.9 Operation in TIO Measure Free-Run/ Clear Input Modes--------------------------------------------10-93

10.4.10 Operation in TIO Noise Processing Input Mode --------------------------------------------------------10-95

10.4.11 Operation in TIO PWM Output Mode----------------------------------------------------------------------10-96

10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function)-----------------------10-99

10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) -----------10-101

10.4.14 Operation in TIO Continuous Output Mode (without Correction Function)-----------------------10-103

10.5 TMS (Input-Related 16-Bit Timer) -----------------------------------------------------------------------------------10-105

10.5.1 Outline of TMS --------------------------------------------------------------------------------------------------10-105

10.5.2 Outline of TMS Operation ------------------------------------------------------------------------------------10-105

10.5.3 TMS Related Register Map ----------------------------------------------------------------------------------10-107

10.5.4 TMS Control Registers----------------------------------------------------------------------------------------10-108

10.5.5 TMS Counters (TMS0CT, TMS1CT) ----------------------------------------------------------------------10-109

10.5.6 TMS Measure Registers (TMS0MR3–0, TMS1MR3–0) ----------------------------------------------10-109

10.5.7 Operation of TMS Measure Input --------------------------------------------------------------------------10-110

10.6 TML (Input-Related 32-Bit Timer)------------------------------------------------------------------------------------10-111

10.6.1 Outline of TML --------------------------------------------------------------------------------------------------10-111

10.6.2 Outline of TML Operation ------------------------------------------------------------------------------------10-112

10.6.3 TML Related Register Map ----------------------------------------------------------------------------------10-112

10.6.4 TML Control Registers ----------------------------------------------------------------------------------------10-113

10.6.5 TML Counters ---------------------------------------------------------------------------------------------------10-114

10.6.6 TML Measure Registers --------------------------------------------------------------------------------------10-114

10.6.7 Operation of TML Measure Input---------------------------------------------------------------------------10-115

CHAPTER 11 A-D CONVERTER

11.1 Outline of A-D Converter-----------------------------------------------------------------------------------------------11-2

11.1.1 Conversion Modes ---------------------------------------------------------------------------------------------11-5

11.1.2 Operation Modes -----------------------------------------------------------------------------------------------11-5

11.1.3 Special Operation Modes ------------------------------------------------------------------------------------11-8

11.1.4 A-D Converter Interrupt and DMA Transfer Requests ------------------------------------------------11-11

11.1.5 Sample-and-Hold Function-----------------------------------------------------------------------------------11-11

11.2 A-D Converter Related Registers------------------------------------------------------------------------------------11-12

11.2.1 A-D Single Mode Register 0 ---------------------------------------------------------------------------------11-14

11.2.2 A-D Single Mode Register 1 ---------------------------------------------------------------------------------11-16

11.2.3 A-D Scan Mode Register 0 ----------------------------------------------------------------------------------11-18

11.2.4 A-D Scan Mode Register 1 ----------------------------------------------------------------------------------11-20

11.2.5 A-D Conversion Speed Control Register -----------------------------------------------------------------11-22

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11.2.6 A-D Disconnection Detection Assist Function Control Register ------------------------------------11-23

11.2.7 A-D Disconnection Detection Assist Method Select Register ---------------------------------------11-24

11.2.8 A-D Successive Approximation Register -----------------------------------------------------------------11-27

11.2.9 A-D Comparate Data Register ------------------------------------------------------------------------------11-28

11.2.10 10-bit A-D Data Registers ------------------------------------------------------------------------------------11-29

11.2.11 8-bit A-D Data Registers--------------------------------------------------------------------------------------11-30

11.3 Functional Description of A-D Converter---------------------------------------------------------------------------11-31

11.3.1 How to Find Analog Input Voltages ------------------------------------------------------------------------11-31

11.3.2 A-D Conversion by Successive Approximation Method ----------------------------------------------11-32

11.3.3 Comparator Operation ----------------------------------------------------------------------------------------11-33

11.3.4 Calculating the A-D Conversion Time---------------------------------------------------------------------11-34

11.3.5 Accuracy of A-D Conversion --------------------------------------------------------------------------------11-37

11.4 Inflow Current Bypass Circuit-----------------------------------------------------------------------------------------11-39

11.5 Precautions on Using A-D Converter -------------------------------------------------------------------------------11-41

CHAPTER 12 SERIAL I/O

12.1 Outline of Serial I/O -----------------------------------------------------------------------------------------------------12-2

12.2 Serial I/O Related Registers ------------------------------------------------------------------------------------------12-5

12.2.1 SIO Interrupt Related Registers ----------------------------------------------------------------------------12-6

12.2.2 SIO Transmit Control Registers ----------------------------------------------------------------------------12-13

12.2.3 SIO Transmit/Receive Mode Registers -------------------------------------------------------------------12-14

12.2.4 SIO Transmit Buffer Registers ------------------------------------------------------------------------------12-17

12.2.5 SIO Receive Buffer Registers -------------------------------------------------------------------------------12-18

12.2.6 SIO Receive Control Registers -----------------------------------------------------------------------------12-19

12.2.7 SIO Baud Rate Registers ------------------------------------------------------------------------------------12-22

12.3 Transmit Operation in CSIO Mode ----------------------------------------------------------------------------------12-23

12.3.1 Setting the CSIO Baud Rate---------------------------------------------------------------------------------12-23

12.3.2 Initializing CSIO Transmission ------------------------------------------------------------------------------12-24

12.3.3 Starting CSIO Transmission ---------------------------------------------------------------------------------12-26

12.3.4 Successive CSIO Transmission ----------------------------------------------------------------------------12-26

12.3.5 Processing at End of CSIO Transmission----------------------------------------------------------------12-27

12.3.6 Transmit Interrupts ---------------------------------------------------------------------------------------------12-27

12.3.7 Transmit DMA Transfer Request ---------------------------------------------------------------------------12-27

12.3.8 Example of CSIO Transmit Operation --------------------------------------------------------------------12-29

12.4 Receive Operation in CSIO Mode -----------------------------------------------------------------------------------12-31

12.4.1 Initialization for CSIO Reception----------------------------------------------------------------------------12-31

12.4.2 Starting CSIO Reception -------------------------------------------------------------------------------------12-33

12.4.3 Processing at End of CSIO Reception --------------------------------------------------------------------12-33

12.4.4 About Successive Reception --------------------------------------------------------------------------------12-34

12.4.5 Flags Showing the Status of CSIO Receive Operation -----------------------------------------------12-35

12.4.6 Example of CSIO Receive Operation ---------------------------------------------------------------------12-36

12.5 Precautions on Using CSIO Mode-----------------------------------------------------------------------------------12-38

12.6 Transmit Operation in UART Mode ---------------------------------------------------------------------------------12-39

12.6.1 Setting the UART Baud Rate --------------------------------------------------------------------------------12-39

12.6.2 UART Transmit/Receive Data Formats-------------------------------------------------------------------12-39

12.6.3 Initializing UART Transmission -----------------------------------------------------------------------------12-41

12.6.4 Starting UART Transmission --------------------------------------------------------------------------------12-43

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12.6.5 Successive UART Transmission ---------------------------------------------------------------------------12-43

12.6.6 Processing at End of UART Transmission---------------------------------------------------------------12-43

12.6.7 Transmit Interrupts---------------------------------------------------------------------------------------------12-43

12.6.8 Transmit DMA Transfer Request ---------------------------------------------------------------------------12-44

12.6.9 Example of UART Transmit Operation--------------------------------------------------------------------12-45

12.7 Receive Operation in UART Mode ----------------------------------------------------------------------------------12-47

12.7.1 Initialization for UART Reception---------------------------------------------------------------------------12-47

12.7.2 Starting UART Reception ------------------------------------------------------------------------------------12-49

12.7.3 Processing at End of UART Reception -------------------------------------------------------------------12-49

12.7.4 Example of UART Receive Operation --------------------------------------------------------------------12-51

12.7.5 Start Bit Detection during UART Reception--------------------------------------------------------------12-53

12.8 Fixed Period Clock Output Function --------------------------------------------------------------------------------12-54

12.9 Precautions on Using UART Mode----------------------------------------------------------------------------------12-55

CHAPTER 13 CAN MODULE

13.1 Outline of the CAN Module --------------------------------------------------------------------------------------------13-2

13.2 CAN Module Related Registers --------------------------------------------------------------------------------------13-4

13.2.1 CAN Control Registers----------------------------------------------------------------------------------------13-15

13.2.2 CAN Status Registers -----------------------------------------------------------------------------------------13-18

13.2.3 CAN Frame Format Select Registers ---------------------------------------------------------------------13-21

13.2.4 CAN Configuration Registers--------------------------------------------------------------------------------13-22

13.2.5 CAN Timestamp Count Registers--------------------------------------------------------------------------13-24

13.2.6 CAN Error Count Registers ----------------------------------------------------------------------------------13-25

13.2.7 CAN Baud Rate Prescalers----------------------------------------------------------------------------------13-26

13.2.8 CAN Interrupt Related Registers ---------------------------------------------------------------------------13-27

13.2.9 CAN Cause of Error Registers ------------------------------------------------------------------------------13-45

13.2.10 CAN Mode Registers ------------------------------------------------------------------------------------------13-46

13.2.11 CAN DMA Transfer Request Select Register -----------------------------------------------------------13-47

13.2.12 CAN Mask Registers ------------------------------------------------------------------------------------------13-48

13.2.13 CAN Single-Shot Mode Control Registers ---------------------------------------------------------------13-52

13.2.14 CAN Message Slot Control Registers---------------------------------------------------------------------13-53

13.2.15 CAN Message Slots -------------------------------------------------------------------------------------------13-57

13.3 CAN Protocol -------------------------------------------------------------------------------------------------------------13-72

13.3.1 CAN Protocol Frames -----------------------------------------------------------------------------------------13-72

13.3.2 Data Formats during CAN Transmission/Reception---------------------------------------------------13-73

13.3.3 CAN Controller Error States ---------------------------------------------------------------------------------13-74

13.4 Initializing the CAN Module--------------------------------------------------------------------------------------------13-75

13.4.1 Initializing the CAN Module ----------------------------------------------------------------------------------13-75

13.5 Transmitting Data Frames ---------------------------------------------------------------------------------------------13-78

13.5.1 Data Frame Transmit Procedure ---------------------------------------------------------------------------13-78

13.5.2 Data Frame Transmit Operation----------------------------------------------------------------------------13-79

13.5.3 Transmit Abort Function --------------------------------------------------------------------------------------13-80

13.6 Receiving Data Frames ------------------------------------------------------------------------------------------------13-81

13.6.1 Data Frame Receive Procedure ----------------------------------------------------------------------------13-81

13.6.2 Data Frame Receive Operation-----------------------------------------------------------------------------13-82

13.6.3 Reading Out Received Data Frames----------------------------------------------------------------------13-84

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13.7 Transmitting Remote Frames ----------------------------------------------------------------------------------------13-86

13.7.1 Remote Frame Transmit Procedure -----------------------------------------------------------------------13-86

13.7.2 Remote Frame Transmit Operation------------------------------------------------------------------------13-87

13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission-------------13-89

13.8 Receiving Remote Frames --------------------------------------------------------------------------------------------13-91

13.8.1 Remote Frame Receive Procedure------------------------------------------------------------------------13-91

13.8.2 Remote Frame Receive Operation ------------------------------------------------------------------------13-92

13.9 Precautions about CAN Module--------------------------------------------------------------------------------------13-95

CHAPTER 14 REAL TIME DEBUGGER (RTD)

14.1 Outline of the Real-Time Debugger (RTD) ------------------------------------------------------------------------14-2

14.2 Pin Functions of the RTD ----------------------------------------------------------------------------------------------14-3

14.3 Functional Description of the RTD-----------------------------------------------------------------------------------14-4

14.3.1 Outline of the RTD Operation ------------------------------------------------------------------------------14-4

14.3.2 Operation of RDR (Real-time RAM Content Output) -------------------------------------------------14-4

14.3.3 Operation of the WRR (RAM Content Forcible Rewrite)---------------------------------------------14-6

14.3.4 Operation of VER (Continuous Monitor) -----------------------------------------------------------------14-7

14.3.5 Operation of VEI (Interrupt Request) ---------------------------------------------------------------------14-7

14.3.6 Operation of RCV (Recover from Runaway) -----------------------------------------------------------14-8

14.3.7 Method for Setting a Specified Address when Using the RTD -------------------------------------14-9

14.3.8 Resetting the RTD---------------------------------------------------------------------------------------------14-10

14.4 Typical Connection with the Host ------------------------------------------------------------------------------------14-11

CHAPTER 15 EXTERNAL BUS INTERFACE

15.1 Outline of the External Bus Interface -------------------------------------------------------------------------------15-2

15.1.1 External Bus Interface Related Signals ------------------------------------------------------------------15-2

15.2 External Bus Interface Related Registers -------------------------------------------------------------------------15-4

15.2.1 Port Operation Mode Registers ----------------------------------------------------------------------------15-4

15.2.2 Port Peripheral Output Select Register ------------------------------------------------------------------15-8

15.2.3 Bus Mode Control Register ---------------------------------------------------------------------------------15-9

15.3 Read/Write Operations -------------------------------------------------------------------------------------------------15-10

15.4 Bus Arbitration ------------------------------------------------------------------------------------------------------------15-16

15.5 Typical Connection of External Extension Memory -------------------------------------------------------------15-18

15.6 Example of Bus Voltage Settings Using VCC-BUS -------------------------------------------------------------15-21

CHAPTER 16 WAIT CONTROLLER

16.1 Outline of the Wait Controller -----------------------------------------------------------------------------------------16-2

16.2 Wait Controller Related Registers -----------------------------------------------------------------------------------16-4

16.2.1 CS Area Wait Control Registers ----------------------------------------------------------------------------16-4

16.3 Typical Operation of the Wait Controller ---------------------------------------------------------------------------16-6

CHAPTER 17 RAM BACKUP MODE

17.1 Outline of RAM Backup Mode ----------------------------------------------------------------------------------------17-2

17.2 Example of RAM Backup when Power is Off --------------------------------------------------------------------------17-3

17.2.1 Normal Operating State---------------------------------------------------------------------------------------17-3

17.2.2 RAM Backup State---------------------------------------------------------------------------------------------17-4

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17.3 Example of RAM Backup for Saving Power Consumption ----------------------------------------------------17-5

17.3.1 Normal Operating State---------------------------------------------------------------------------------------17-5

17.3.2 RAM Backup State---------------------------------------------------------------------------------------------17-6

17.3.3 Precautions to Be Observed at Power-On ---------------------------------------------------------------17-7

17.4 Exiting RAM Backup Mode (Wakeup) ------------------------------------------------------------------------------17-8

CHAPTER 18 OSCILLATOR CIRCUIT

18.1 Oscillator Circuit----------------------------------------------------------------------------------------------------------18-2

18.1.1 Example of an Oscillator Circuit ----------------------------------------------------------------------------18-2

18.1.2 XIN Oscillation Stoppage Detection Circuit --------------------------------------------------------------18-3

18.1.3 Oscillation Drive Capability Select Function -------------------------------------------------------------18-5

18.1.4 System Clock Output Function------------------------------------------------------------------------------18-7

18.1.5 Oscillation Stabilization Time at Power-On --------------------------------------------------------------18-7

18.2 Clock Generator Circuit ------------------------------------------------------------------------------------------------18-8

CHAPTER 19 JTAG

19.1 Outline of JTAG ----------------------------------------------------------------------------------------------------------19-2

19.2 Configuration of the JTAG Circuit------------------------------------------------------------------------------------19-3

19.3 JTAG Registers ----------------------------------------------------------------------------------------------------------19-4

19.3.1 Instruction Register (JTAGIR)-------------------------------------------------------------------------------19-4

19.3.2 Data Register----------------------------------------------------------------------------------------------------19-5

19.4 Basic Operation of JTAG ----------------------------------------------------------------------------------------------19-6

19.4.1 Outline of JTAG Operation-----------------------------------------------------------------------------------19-6

19.4.2 IR Path Sequence----------------------------------------------------------------------------------------------19-8

19.4.3 DR Path Sequence --------------------------------------------------------------------------------------------19-9

19.4.4 Inspecting and Setting Data Registers--------------------------------------------------------------------19-10

19.5 Boundary Scan Description Language -----------------------------------------------------------------------------19-11

19.6 Notes on Board Design when Connecting JTAG----------------------------------------------------------------------19-12

19.7 Processing Pins when Not Using JTAG----------------------------------------------------------------------------19-13

CHAPTER 20 POWER SUPPLY CIRCUIT

20.1 Configuration of the Power Supply Circuit-------------------------------------------------------------------------20-2

20.2 Power-On Sequence----------------------------------------------------------------------------------------------------20-3

20.2.1 Power-On Sequence when Not Using RAM Backup --------------------------------------------------20-3

20.2.2 Power-On Sequence when Using RAM Backup--------------------------------------------------------20-4

20.3 Power-Off Sequence----------------------------------------------------------------------------------------------------20-5

20.3.1 Power-Off Sequence when Not Using RAM Backup --------------------------------------------------20-5

20.3.2 Power-Off Sequence when Using RAM Backup -------------------------------------------------------20-6

CHAPTER 21 ELECTRICAL CHARACTERISTICS

21.1 Absolute Maximum Ratings -------------------------------------------------------------------------------------------21-2

21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz ----------------------------------------------21-3

21.2.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 10 MHz)-------------------21-3

21.2.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) -----------------------------------------21-5

21.2.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) --------------------------21-6

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21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz ------------------------------------------------21-7

21.3.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 8 MHz) --------------------21-7

21.3.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz)-------------------------------------------21-9

21.3.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz)----------------------------21-10

21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz --------------------------------------------21-11

21.4.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz)------21-11

21.4.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ----------------------------21-13

21.4.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) -------------21-14

21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz----------------------------------------------21-15

21.5.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V f(XIN) = 8 MHz) --------21-15

21.5.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) ------------------------------21-17

21.5.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz)---------------21-18

21.6 Flash Memory Related Characteristics-----------------------------------------------------------------------------21-19

21.7 A.C. Characteristics (when VCCE = 5 V) --------------------------------------------------------------------------21-20

21.7.1 Timing Requirements------------------------------------------------------------------------------------------21-20

21.7.2 Switching Characteristics-------------------------------------------------------------------------------------21-24

21.7.3 A.C. Characteristics--------------------------------------------------------------------------------------------21-27

21.8 A.C. Characteristics (when VCCE = 3.3 V) -----------------------------------------------------------------------21-36

21.8.1 Timing Requirements------------------------------------------------------------------------------------------21-36

21.8.2 Switching Characteristics-------------------------------------------------------------------------------------21-40

21.8.3 A.C. Characteristics--------------------------------------------------------------------------------------------21-43

CHAPTER 22 TYPICAL CHARACTERISTICS

To be written at a later time---------------------------------------------------------------------------------------------------22-2

APPENDIX 1 MECHANICAL SPECIFICAITONS

Appendix 1.1 Dimensional Outline Drawing ------------------------------------------------------------------- Appendix 1-2

APPENDIX 2 INSTRUCTION PROCESSING TIME

Appendix 2.1 32182 Instruction Processing Time------------------------------------------------------------ Appendix 2-2

APPENDIX 3 PROCESSING OF UNUSED PINS

Appendix 3.1 Example Processing of Unused Pins --------------------------------------------------------- Appendix 3-2

APPENDIX 4 SUMMARY OF PRECAUTIONS

Appendix 4.1 Precautions about the CPU--------------------------------------------------------------------- Appendix 4-2

Appendix 4.1.1 Precautions Regarding Data Transfer ------------------------------------------------ Appendix 4-2

Appendix 4.2 Precautions about the Address Space------------------------------------------------------- Appendix 4-3

Appendix 4.2.1 Virtual Flash Emulation Function ------------------------------------------------------- Appendix 4-3

Appendix 4.3 Precautions about EIT --------------------------------------------------------------------------- Appendix 4-3

Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory --------- Appendix 4-3

Appendix 4.5 Precautions to Be Observed after Reset ---------------------------------------------------- Appendix 4-4

Appendix 4.5.1 Input/output Ports -------------------------------------------------------------------------- Appendix 4-4

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Appendix 4.6 Precautions about Input/Output Ports --------------------------------------------------- Appendix 4-4

Appendix 4.6.1 When Using Input/Output Ports in Output Mode ------------------------------- Appendix 4-4

Appendix 4.6.2 About the Port Input Disable Function -------------------------------------------- Appendix 4-4

Appendix 4.7 Precautions about the DMAC-------------------------------------------------------------- Appendix 4-5

Appendix 4.7.1 About Writing to the DMAC Related Registers---------------------------------- Appendix 4-5

Appendix 4.7.2 Manipulating the DMAC Related Registers by DMA Transfer -------------- Appendix 4-5

Appendix 4.7.3 About the DMA Interrupt Request Status Register----------------------------- Appendix 4-5

Appendix 4.7.4 About the Stable Operation of DMA Transfer ----------------------------------- Appendix 4-5

Appendix 4.8 Precautions about the Multijunction Timers-------------------------------------------- Appendix 4-6

Appendix 4.8.1 Precautions on Using TOP Single-Shot Output Mode ------------------------ Appendix 4-6

Appendix 4.8.2 Precautions on Using TOP Delayed Single-Shot Output Mode ------------ Appendix 4-8

Appendix 4.8.3 Precautions on Using TOP Continuous Output Mode------------------------- Appendix 4-9

Appendix 4.8.4 Precautions on Using TIO Measure Free-Run/Clear Input Modes--------- Appendix 4-9

Appendix 4.8.5 Precautions on Using TIO PWM Output Mode---------------------------------- Appendix 4-9

Appendix 4.8.6 Precautions on Using TIO Single-Shot Output Mode ------------------------- Appendix 4-9

Appendix 4.8.7 Precautions on Using TIO Delayed Single-Shot Output Mode-------------- Appendix 4-10

Appendix 4.8.8 Precautions on Using TIO Continuous Output Mode-------------------------- Appendix 4-10

Appendix 4.8.9 Precautions on Using TMS Measure Input--------------------------------------- Appendix 4-10

Appendix 4.8.10 Precautions on Using TML Measure Input -------------------------------------- Appendix 4-11

Appendix 4.9 Precautions about the A-D Converters -------------------------------------------------- Appendix 4-12

Appendix 4.10 Precautions about Serial I/O--------------------------------------------------------------- Appendix 4-15

Appendix 4.10.1 Precautions on Using CSIO Mode------------------------------------------------- Appendix 4-15

Appendix 4.10.2 Precautions on Using UART Mode ------------------------------------------------ Appendix 4-16

Appendix 4.11 Precautions about RAM Backup Mode ------------------------------------------------- Appendix 4-17

Appendix 4.11.1 Precautions to Be Observed at Power-On -------------------------------------- Appendix 4-17

Appendix 4.12 Precautions about JTAG ------------------------------------------------------------------- Appendix 4-18

Appendix 4.12.1 Notes on Board Design when Connecting JTAG------------------------------- Appendix 4-18

Appendix 4.12.2 Processing Pins when Not Using JTAG------------------------------------------ Appendix 4-19

Appendix 4.13 Precautions about Noise ------------------------------------------------------------------- Appendix 4-20

Appendix 4.13.1 Reduction of Wiring Length --------------------------------------------------------- Appendix 4-20

Appendix 4.13.2 Inserting a Bypass Capacitor between VSS and VCC Lines --------------- Appendix 4-23

Appendix 4.13.3 Processing Analog Input Pin Wiring ---------------------------------------------- Appendix 4-23

Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin ---------------------------- Appendix 4-24

Appendix 4.13.5 Processing Input/Output Ports ----------------------------------------------------- Appendix 4-28

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