Features
•Floating channel designed for bootstrap operation
Fully operational up to +200V
Tolerant to negative transient voltage, dV/dt immune
•Gate drive supply range from 10V to 20V
•Independent low and high side channels
•Input logicHIN/LIN active high
•Undervoltage lockout for both channels
•3.3V and 5V input logic compatible
•CMOS Schmitt-triggered inputs with pull-down
•Matched propagation delay for both channels
•8-Lead SOIC is also available LEAD-FREE (PbF)
Packages
HIGH AND LOW SIDE DRIVER
Product Summary
VOFFSET 200V max.
IO+/- 1.0A /1.0A typ.
VOUT 10 - 20V
ton/off 80 & 60 ns typ.
Delay Matching 20 ns max.
IR2011(S) & (PbF )
www.irf.com 1
Typical Connection
(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please
refer to our Application Notes and DesignTips for proper circuit board layout.
Data Sheet No.PD60217 Rev A
Applications
•Audio Class D amplifiers
•High power DC-DC SMPS converters
•Other high frequency applications
Description
The IR2011 is a high power, high speed power MOSFET driver with independent high
and low side referenced output channels, ideal for Audio Class D and DC-DC converter
applications. Logic inputs are compatible with standard CMOS or LSTTL output, down
to 3.0V logic. The output drivers feature a high pulse current buffer stage designed for
minimum driver cross-conduction. Propagation delays are matched to simplify use in
high frequency applications. The floating channel can be used to drive an N-channel
power MOSFET in the high side configuration which operates up to 200 volts. Propri-
etary HVIC and latch immune CMOS technologies enable ruggedized monolithic con-
struction.
8-Lead SOIC
IR2011S
also available
LEAD-FREE (PbF)
8-Lead PDIP
IR2011
200V
TO
LOAD
VCC
COM
LIN
HIN VS
VB
HO
HIN
COM
VCC
LIN
LO 18
45
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IR2011(S) & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol Definition Min. Max. Units
VBHigh side floating supply voltage -0.3 250
VSHigh side floating supply offset voltage VB - 25 VB + 0.3
VHO High side floating output voltage VS - 0.3 VB + 0.3
VCC Low side fixed supply voltage -0.3 25
VLO Low side output voltage -0.3 VCC +0.3
VIN Logic input voltage (HIN & LIN) COM -0.3 VCC +0.3
dVs/dt Allowable offset supply voltage transient (figure 2) — 50 V/ns
PDPackage power dissipation @ TA ≤ +25°C (8-lead DIP) — 1.0
(8-lead SOIC) — 0.625
RTHJA Thermal resistance, junction to ambient (8-lead DIP) — 125
(8-lead SOIC) — 200
TJJunction temperature — 150
TSStorage temperature -55 150
TLLead temperature (soldering, 10 seconds) — 300
°C/W
W
V
°C
Note 1: Logic operational for VS of -4 to +200V. Logic state held for VS of -4V to -VBS.
Symbol Definition Min. Max. Units
VBHigh side floating supply absolute voltage VS + 10 VS + 20
VSHigh side floating supply offset voltage Note 1 200
VHO High side floating output voltage VSVB
VCC Low side fixed supply voltage 10 20
VLO Low side output voltage 0 VCC
VIN Logic input voltage (HIN & LIN) COM 5.5
TAAmbient temperature -40 125 °C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. The VS and COM offset ratings
are tested with all supplies biased at 15V differential.
V
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IR2011(S) & (PbF)
Symbol Definition Min. Typ. Max. Units Test Conditions
VIH Logic “1” input voltage 2.2 — —
VIL Logic “0” input voltage — — 0.7
VOH High level output voltage, VBIAS - VO— — 2.0 IO = 0A
VOL Low level output voltage, VO— — 0.2 20mA
ILK Offset supply leakage current — — 50 VB=VS = 200V
IQBS Quiescent VBS supply current — 90 210 VIN = 0V or 3.3V
IQCC Quiescent VCC supply current — 140 230 VIN = 0V or 3.3V
IIN+ Logic “1” input bias current — 7.0 20 VIN = 3.3V
IIN- Logic “0” input bias current — — 1.0 VIN = 0V
VBSUV+ VBS supply undervoltage positive going 8.2 9.0 9.8
threshold
VBSUV- VBS supply undervoltage negative going 7.4 8.2 9 .0
threshold
VCCUV+ VCC supply undervoltage positive going 8.2 9.0 9 .8
threshold
VCCUV- VCC supply undervoltage negative going 7 .4 8.2 9.0
threshold
IO+ Output high short circuit pulsed current — 1.0 — VO = 0V,
PW ≤ 10 µs
IO- Output low short circuit pulsed current — 1.0 — VO = 15V,
PW ≤ 10 µs
V
µA
V
A
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15V, and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to
COM and are applicable to all logic input leads: HIN and LIN. The VO and IO parameters are referenced to COM and are
applicable to the respective output leads: HO or LO.
VCC = 10V - 20V
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, CL = 1000 pF, TA = 25 °C unless otherwise specified. Figure 1 shows the timing definitions.
Symbol Definition Min. Typ. Max. Units Test Conditions
ton Turn-on propagation delay — 80 — V S = 0V
toff Turn-off propagation delay — 75 — VS = 200V
trTurn-on rise time — 35 50
tfTurn-off fall time — 20 35
DM 1 Turn-on delay matching | ton (H) - ton (L) | — 5 20
DM 2 Turn-off delay matching | toff (H) - toff (L) | — 5 20
ns
4www.irf.com
IR2011(S) & (PbF)
Functional Block Diagram
Lead Definitions
Symbol Description
8-Lead PDIP 8-Lead SOIC also available LEAD-FREE (PbF)
IR2011 IR2011S
Part Number
Lead Assignments
HIN Logic input for high side gate driver output (HO), in phase
LIN Logic input for low side gate driver output (LO), in phase
VBHigh side floating supply
HO High side gate drive output
VSHigh side floating supply return
VCC Low side supply
LO Low side gate drive output
COM Low side return
VB
LIN
UV
DETECT
DELAY
VCC
UV
DETECT
LO
VS
COM
S
R
UV Q
HIN
HO
LEVEL
SHIFT
CIRCUIT
LOW
VOLTAGE
LEVEL
SHIFT
3V S-TRIGGER
3V S-TRIGGER
HIGH
VOLTAGE
BUFFER
LOW
VOLTAGE
LEVEL
SHIFT
VS
VB
HO
HIN
COM
VCC
LIN
LO 1
8
4
5
6
7
3
2
VS
VB
HO
HIN
COM
VCC
LIN
LO 1
8
4
5
6
7
3
2
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IR2011(S) & (PbF)
Figure 1. Timing Diagram
50% 50%
10%
90%
10%
90%
10%
90%
HIN / LIN
HO
LO
trise tfall
ton(H)
ton(L)
toff(H)
toff(L)
DM1 DM2
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IR2011(S) & (PbF)
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
T emperature (oC)
Turn-on P ropagati on Delay (ns)
Typ.
F igure 2A. Turn-on P ropagation Delay
vs. Temperature
0
100
200
300
400
500
10 12 14 16 18 20
Su pply Voltage (V)
Turn-on Propagati on Dela y (ns)
Figure 2B. Turn-on P ropagation Delay
vs. S upply Voltage
Typ.
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
T emperature (oC)
Turn-off Propagation Del ay (ns)
Typ.
F igure 3A. Turn-off Propagation Delay
vs. Temperature
0
100
200
300
400
500
10 12 14 16 18 20
Supply Voltage (V)
Turn-off Propagati on Del a y (ns)
Figure 3B. Tu rn-off P ropa g ation Del ay
vs. S upply Voltage
Typ.
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IR2011(S) & (PbF)
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
T emperature (oC)
Tu rn -o n Rise Time (n s)
Typ.
M ax.
Figure 4 A . Turn-on Rise Time vs. Temperature
0
20
40
60
80
100
10 12 14 16 18 20
Su ppl y Voltage (V)
Turn-on Ri se Ti me (ns)
Figure 4 B. Turn-on Rise Time v s. Supply Voltage
Typ.
M ax.
0
10
20
30
40
50
-50 -25 0 25 50 75 100 125
T emperature (oC)
Turn-of f F all Time (ns)
Typ.
M ax.
Figure 5A. Turn-off Fall Time vs. Temperature
0
10
20
30
40
50
10 12 14 16 18 20
Su pply Voltage (V)
Tu rn-off Fall Ti me (n s)
Figure 5B. Turn-off Fall Time vs. Supply Voltage
Typ.
M ax.
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IR2011(S) & (PbF)
0
10
20
30
40
50
-50-250 255075100125
T emperature (oC)
Delay Matching Time (ns)
Figure 6 A . Turn-on Dela y Ma tc hi ng Ti me
vs. Temperature
Typ.
M ax.
0
10
20
30
40
50
10 12 14 16 18 20
Supply Voltage (V)
Dealy Matching Time (ns)
Figure 6B. Turn-on Delay Matching Time
vs. Supply Voltage
Typ.
M ax.
0
10
20
30
40
50
-50 -25 0 25 50 75 100 125
T emperature (oC)
Delay Matching Time (ns)
Figure 7 A . Turn-off Dela y Matching Time
vs. Temperature
Typ.
M ax.
0
10
20
30
40
50
10 12 14 16 18 20
Supply Voltage (V)
Dealy Matching Time (ns)
Figu re 7B. Turn-off Delay Matching Time
vs. S upply Voltage
Typ.
M ax.
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IR2011(S) & (PbF)
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
T emperature (oC)
Logic "1" Input Voltage (V)
Min.
Figure 8 A . Logi c "1" I npu t Voltag e
vs. Temperature
0
1
2
3
4
5
10 12 14 16 18 20
Su pply Voltage (V)
Logic "1" Input Voltage (V)
Figure 8 B. Lo gi c "1" Input Voltag e
vs. Supply Voltage
Min.
0
1
2
3
4
5
-50-25 0 25 50 75100125
T emperature (oC)
Logic "0" Input Voltage (V)
M ax.
Figure 9A . Logic " 0 " I nput Voltage
vs. Temperature
0
1
2
3
4
5
10 12 14 16 18 20
Su pply Voltage (V)
Logic "0" Input Vo ltage (V)
Figure 9 B. Logic " 0" I np ut Volta ge
vs. S upply Voltage
M ax.
10 www.irf.com
IR2011(S) & (PbF)
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
T emperature (oC)
High Level Output (V)
M ax.
Figure 10A. Hi gh Level Output v s.Tempera ture
0
1
2
3
4
5
10 12 14 16 18 20
Su pply Voltage (V)
High Level Output (V )
Figure 1 0B. High L evel Output vs. Supply Volta ge
M ax.
0.0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125
T emperature (oC)
Low Level Output (V)
M ax.
Figure 1 1 A. Low Level Output vs. Temperature
0.0
0.1
0.2
0.3
0.4
0.5
10 12 14 16 18 20
Su pply Voltage (V)
Low Level Output (V)
Figure 11B. Low Level O utput v s. Supply Voltage
M ax.
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IR2011(S) & (PbF)
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (oC)
Offset Supply Leakage Current (µA)
M ax.
Figure 12A. Offset Supply Leakage Current
vs. Temperature
0
100
200
300
400
500
50 80 110 140 170 200
VB Boost Voltage (V)
Offset Supply Leakage Current (µA)
M ax.
0
100
200
300
400
500
600
-50 -25 0 25 50 75 100 125
Temperature (oC)
VBS Supply Current (µA)
Typ.
M ax.
0
100
200
300
400
500
600
10 12 14 16 18 20
VBS Floating Supply Voltage (V)
VBS Supply Current (µA)
Typ.
M ax.
12 www.irf.com
IR2011(S) & (PbF)
0
100
200
300
400
500
600
-50-25 0 25 50 75100125
Temperature (oC)
VCC Supply Current (µA)
Figure 1 4A. VCC Supply Cu rrent
v s. Temperature
Typ.
M ax.
0
100
200
300
400
500
600
10 12 14 16 18 20
VCC Supply Voltage (V)
VCC Supply Current (µA)
Figure 1 4B. VCC Supply Current
vs. VCC Supply Voltage
Typ.
M ax.
0
20
40
60
80
100
-50-250 255075100125
Temperature (oC)
Logic "1" Input Bias Current (
µA)
Figure 15A. Logic "1" Input Bias Current
v s. Temperature
Typ.
M ax.
0
20
40
60
80
100
10 12 14 16 18 20
Supply Voltage (V)
Logic "1" Input Bias Current (
µA)
Typ.
M ax.
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IR2011(S) & (PbF)
0
1
2
3
4
5
-50-250 255075100125
Temperature (oC)
Logic "0" Input Bias Current (
µA)
Figure 1 6A. Logic "0" Input Bi as Current
vs. Temperature
M ax.
0
1
2
3
4
5
10 12 14 16 18 20
Su pply Voltage (V)
Logic "0" Input Bias Current (µA)
Figure 16B. Logic "0" Input Bias Current
vs. Supply Voltage
M ax.
7
8
9
10
11
12
-50 -25 0 25 50 75 100 125
Temperature (oC)
VCC and VBS UV Th reshold (+) (V)
Min.
Figure 17. VCC and VBS Undervoltage Threshold (+)
v s. Temperature
Typ.
M ax.
7
8
9
10
11
12
-50 -25 0 25 50 75 100 125
T emperature (oC)
VCC and VBS UV Thresh old (-) (V)
Min.
Figure 18. VCC and VBS Undervoltage Threshold (-)
vs. Temperature
Typ.
M ax.
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IR2011(S) & (PbF)
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
T emperature (oC)
Output S ource Current (A)
Figure1 9A. Output Source Current
vs. Temperature
Typ.
0
1
2
3
4
5
10 12 14 16 18 20
Su ppl y Voltage (V)
Output Source Current (A)
Figure 1 9 B. Output S ource Current
vs. Supply Volta ge
Typ.
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (oC)
Output Sink Cu rren t (A)
Figure 20 A . Output Sink Current
v s. Temperature
Typ.
0
1
2
3
4
5
10 12 14 16 18 20
Su ppl y Voltage (V)
Output Sink Current (A)
Figure 20B. Output Sink C urrent
vs. Supply Voltage
Typ.
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IR2011(S) & (PbF)
-15
-12
-9
-6
-3
0
10 12 14 16 18 20
VBS F loating Supply Voltage (V)
Maximum VS Negati ve Offset (V)
Figure 21. Maximum VS Negative Offset
vs. VBS Floa ti ng Supp l y Voltage
Typ.
16 www.irf.com
IR2011(S) & (PbF)
01-6014
01-3003 01 (MS-001AB)
8-Lead PDIP
Case outlines
01-6027
01-0021 11 (MS-012AA)
8-Lead SOIC
87
5
65
D B
E
A
e
6X
H
0. 25 [.010 ] A
6
4312
4 . OUT L INE CONFORMS TO JEDEC OUTLINE MS-0 1 2AA .
NOTES:
1. DI MENSIONING & TOLERANCI NG PER ASME Y14.5M-1994.
2 . CONT ROL LING DIMENSION: MIL LIMETER
3 . D IMENSIONS ARE SHOW N IN MILL IMET ERS [INCHES].
7
K x 4 5°
8X L 8X c
y
FOOTPRINT
8X 0.72 [ . 02 8]
6. 46 [ . 2 55]
3X 1.27 [ . 05 0] 8X 1.78 [ . 07 0]
5 D IMENSION DOES NOT INCLUD E MOLD PROTRUSIONS.
6 D IMENSION DOES NOT INCLUD E MOLD PROTRUSIONS.
MOLD PROTRUSI ONS NOT TO EXCEED 0.25 [.010].
7 D IMENSION IS THE LENGT H OF LEAD FOR SOLD ERING T O
A SUBSTRATE.
MOLD PROTRUSI ONS NOT TO EXCEED 0.15 [.006].
0. 25 [.010 ] CAB
e1 A
A1
8X b
C
0. 10 [.004 ]
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX MILLIMETERSINC HE S MIN MAX
DIM
8°
e
c .0075 .0098 0.19 0.25
.025 BASIC 0.635 BASIC
www.irf.com 17
IR2011(S) & (PbF)
LEADFREE PART MARKING INFORMATION
ORDER INFORMATION
Lead Free Released
Non-Lead Free
Released
Part number
Date code
IRxxxxxx
YWW?
?XXXX
Pin 1
Identifier
IR logo
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
P
?MARKING CODE
Basic Part (Non-Lead Free)
8-Lead PDIP IR2011 order IR2011
8-Lead SOIC IR2011S order IR2011S
Leadfree Part
8-Lead PDIP IR2011 Not available
8-Lead SOIC IR2011S order IR2011SPbF
This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s W eb Site http://www.irf.com/.
Data and specifications subject to change without notice
WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105
5/25/2004
