74LVC2G02
Dual 2-input NOR gate
Rev. 13 — 20 April 2018 Product data sheet
1 General description
The 74LVC2G02 provides a 2-input NOR gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
these devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2 Features and benefits
•Wide supply voltage range from 1.65 V to 5.5 V
•5 V tolerant outputs for interfacing with 5 V logic
•High noise immunity
•±24 mA output drive (VCC = 3.0 V)
•CMOS low power consumption
•Complies with JEDEC standard:
–JESD8-7 (1.65 V to 1.95 V)
–JESD8-5 (2.3 V to 2.7 V)
–JESD8-B/JESD36 (2.7 V to 3.6 V)
•Latch-up performance exceeds 250 mA
•Direct interface with TTL levels
•Inputs accept voltages up to 5 V
•ESD protection:
–HBM JESD22-A114F exceeds 2000 V
–MM JESD22-A115-A exceeds 200 V
•Multiple package options
•Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
2 / 20
3 Ordering information
Table 1. Ordering information
PackageType number
Temperature range Name Description Version
74LVC2G02DP -40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC2G02DC -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC2G02GT -40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
74LVC2G02GF -40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
SOT1089
74LVC2G02GM -40 °C to +125 °C XQFN8 plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm
SOT902-2
74LVC2G02GN -40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm
SOT1116
74LVC2G02GS -40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm
SOT1203
4 Marking
Table 2. Marking codes
Type number Marking code[1]
74LVC2G02DP V02
74LVC2G02DC V02
74LVC2G02GT V02
74LVC2G02GF VB
74LVC2G02GM V02
74LVC2G02GN VB
74LVC2G02GS VB
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
3 / 20
5 Functional diagram
001aah780
1A
1B 1Y
2A
2B 2Y
Figure 1.  Logic symbol
001aah781
1
1
Figure 2.  IEC logic symbol
mna105
B
A
Y
Figure 3.  Logic diagram (one gate)
6 Pinning information
6.1 Pinning
74LVC2G02
1A VCC
1B 1Y
2Y 2B
GND 2A
001aab642
1
2
3
4
6
5
8
7
Figure 4.  Pin configuration SOT505-2 and SOT765-1
74LVC2G02
2B
1Y
VCC
2A
2Y
1B
1A
GND
001aab643
3 6
2 7
1 8
4 5
Transparent top view
Figure 5.  Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
001aae971
1B2B
1A
V
C
C
2Y
1Y
GND
2A
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
74LVC2G02
Figure 6.  Pin configuration SOT902-2
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
4 / 20
6.2 Pin description
Table 3. Pin description
PinSymbol
SOT505-2, SOT765-1, SOT833-1, SOT1089,
SOT1116 and SOT1203
SOT902-2
Description
1A, 2A 1, 5 7, 3 data input
1B, 2B 2, 6 6, 2 data input
GND 4 4 ground (0 V)
1Y, 2Y 7, 3 1, 5 data output
VCC 8 8 supply voltage
7 Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Input Output
nA nB nY
LLH
X H L
H X L
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
5 / 20
8 Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +6.5 V
VIinput voltage [1] -0.5 +6.5 V
Active mode [1] -0.5 VCC + 0.5 VVOoutput voltage
Power-down mode; VCC = 0 V [1] -0.5 +6.5 V
IIK input clamping current VI < 0 V -50 - mA
IOK output clamping current VO < 0 V or VO > VCC - ±50 mA
IOoutput current VO = 0 V to VCC - ±50 mA
ICC supply current - 100 mA
IGND ground current -100 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation Tamb = -40 °C to +125 °C [2] - 300 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8 and XQFN8 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9 Recommended operating conditions
Table 6. Operating conditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 1.65 5.5 V
VIinput voltage 0 5.5 V
Active mode 0 VCC VVOoutput voltage
Power-down mode; VCC = 0 V 0 5.5 V
Tamb ambient temperature -40 +125 °C
VCC = 1.65 V to 2.7 V - 20 ns/VΔt/ΔV input transition rise and fall rate
VCC = 2.7 V to 5.5 V - 10 ns/V
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
6 / 20
10 Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Tamb = -40 °C to +85 °C
VCC = 1.65 V to 1.95 V 0.65 × VCC - - V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VIH HIGH-level input voltage
VCC = 4.5 V to 5.5 V 0.7 × VCC - - V
VCC = 1.65 V to 1.95 V - - 0.35 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VIL LOW-level input voltage
VCC = 4.5 V to 5.5 V - - 0.3 × VCC V
VI = VIH or VIL
IO = -100 μA; VCC = 1.65 V to 5.5 V VCC - 0.1 - - V
IO = -4 mA; VCC = 1.65 V 1.2 1.53 - V
IO = -8 mA; VCC = 2.3 V 1.9 2.13 - V
IO = -12 mA; VCC = 2.7 V 2.2 2.50 - V
IO = -24 mA; VCC = 3.0 V 2.3 2.60 - V
VOH HIGH-level output voltage
IO = -32 mA; VCC = 4.5 V 3.8 4.10 - V
VI = VIH or VIL
IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.1 V
IO = 4 mA; VCC = 1.65 V - 0.08 0.45 V
IO = 8 mA; VCC = 2.3 V - 0.14 0.3 V
IO = 12 mA; VCC = 2.7 V - 0.19 0.4 V
IO = 24 mA; VCC = 3.0 V - 0.37 0.55 V
VOL LOW-level output voltage
IO = 32 mA; VCC = 4.5 V - 0.43 0.55 V
IIinput leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - ±0.1 ±1 μA
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±2 μA
ICC supply current VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
- 0.1 4 μA
ΔICC additional supply current per pin; VI = VCC - 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
- 5 500 μA
CIinput capacitance - 2.5 - pF
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
7 / 20
Symbol Parameter Conditions Min Typ[1] Max Unit
Tamb = -40 °C to +125 °C
VCC = 1.65 V to 1.95 V 0.65 × VCC - - V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VIH HIGH-level input voltage
VCC = 4.5 V to 5.5 V 0.7 × VCC - - V
VCC = 1.65 V to 1.95 V - - 0.35 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VIL LOW-level input voltage
VCC = 4.5 V to 5.5 V - - 0.3 × VCC V
VI = VIH or VIL
IO = -100 μA; VCC = 1.65 V to 5.5 V VCC - 0.1 - - V
IO = -4 mA; VCC = 1.65 V 0.95 - - V
IO = -8 mA; VCC = 2.3 V 1.7 - - V
IO = -12 mA; VCC = 2.7 V 1.9 - - V
IO = -24 mA; VCC = 3.0 V 2.0 - - V
VOH HIGH-level output voltage
IO = -32 mA; VCC = 4.5 V 3.4 - - V
VI = VIH or VIL
IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.1 V
IO = 4 mA; VCC = 1.65 V - - 0.70 V
IO = 8 mA; VCC = 2.3 V - - 0.45 V
IO = 12 mA; VCC = 2.7 V - - 0.60 V
IO = 24 mA; VCC = 3.0 V - - 0.80 V
VOL LOW-level output voltage
IO = 32 mA; VCC = 4.5 V - - 0.80 V
IIinput leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - ±1 μA
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - ±2 μA
ICC supply current VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
- - 4 μA
ΔICC additional supply current per pin; VI = VCC - 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
- - 500 μA
[1] All typical values are measured at Tamb = 25 °C.
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
8 / 20
11 Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground 0 V); for test circuit see Figure 8.
-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ[1] Max Min Max
Unit
nA, nB to nY; see Figure 7 [2]
VCC = 1.65 V to 1.95 V 1.2 3.8 8.9 1.2 11.2 ns
VCC = 2.3 V to 2.7 V 0.8 2.4 5.4 0.8 6.8 ns
VCC = 2.7 V 0.8 3.2 6.0 0.8 7.5 ns
VCC = 3.0 V to 3.6 V 0.6 2.4 4.9 0.6 6.2 ns
tpd propagation delay
VCC = 4.5 V to 5.5 V 0.6 1.8 4.3 0.6 5.5 ns
CPD power dissipation
capacitance
per gate; VI = GND to VCC
[3] - 14 - - - pF
[1] Typical values are measured at nominal VCC and at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD x VCC
2 x fi x N + Σ(CL x VCC
2 x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL x VCC
2 x fo) = sum of outputs.
11.1 Waveforms and test circuit
001aae972
nA, nB input
nY output
tPLH
tPHL
GND
VI
VM
VM
VOH
VOL
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Figure 7.  Input (nA, nB) to output (nY) propagation delays
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
9 / 20
Table 9. Measurement points
Supply voltage Input Output
VCC VMVM
1.65 V to 1.95 V 0.5 x VCC 0.5 x VCC
2.3 V to 2.7 V 0.5 x VCC 0.5 x VCC
2.7 V 1.5 V 1.5 V
3.0 V to 3.6 V 1.5 V 1.5 V
4.5 V to 5.5 V 0.5 x VCC 0.5 x VCC
VEXT
VCC
VIVO
001aae235
DUT
CL
RT
RL
RL
PULSE
GENERATOR
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Figure 8.  Test circuit for measuring switching times
Table 10. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPLH, tPHL
1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open
2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open
2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open
3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open
4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
10 / 20
12 Package outline
Figure 9.  Package outline SOT505-2 (TSSOP8)
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
11 / 20
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT765-1 MO-187
sot765-1_po
07-06-02
16-05-31
Unit
mm
max
nom
min
0.15 0.27 0.23 2.1
0.5
0.4
A
max.
Dimensions (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1
A1A2
0.85
A3bpc D(1) E(2) e HEL
0.4
LpQ v w
1 0.12 0.10.2 0.08
y Z(1)
3.0 0.152.2 0.190.00 0.17 0.08 1.9 0.10.60 0°
3.2 0.402.4 0.21 8°
θ
0
scale
5 mm
detail X
A
y
e
X
v A
bp
w
D
Z
1 4
85
θ
A2
A1
Q
Lp
(A3)
A
L
HE
E
c
pin 1 index
Figure 10.  Package outline SOT765-1 (VSSOP8)
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
12 / 20
terminal 1
index area
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT833-1 - - -
MO-252
---
SOT833-1
07-11-14
07-12-07
DIMENSIONS (mm are the original dimensions)
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17
2.0
1.9
0.35
0.27
A1
max b E
1.05
0.95
D e e1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
8
2
7
3
6
4
5
8×
(2)
4×
(2)
A
Figure 11.  Package outline SOT833-1 (XSON8)
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
13 / 20
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1089 MO-252
sot1089_po
10-04-09
10-04-12
Unit
mm
max
nom
min
0.5 0.04 1.40
1.35
1.30
1.05
1.00
0.95
0.55 0.35
0.35
0.30
0.27
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm SOT1089
A1b L1
0.40
0.35
0.32
0.20
0.15
0.12
D E e e1L
0 0.5 1 mm
scale
terminal 1
index area
E
D
detail X
A
A1
L
L1
b
e1
e
terminal 1
index area
1
4
8
5
(4×)(2)
(8×)(2)
X
Figure 12.  Package outline SOT1089 (XSON8)
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
14 / 20
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT902-2 - - -
MO-255
- - -
sot902-2_po
16-07-14
16-11-08
Unit(1)
mm
max
nom
min
0.5 0.05
0.00
1.65
1.60
1.55
1.65
1.60
1.55
0.55 0.5
0.15
0.10
0.05
0.1 0.05
A
0.2
k
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
XQFN8: plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2
A1b
0.25
0.20
0.15
D E e e1L
0.35
0.30
0.25
L1
0.25
0.20
0.15
L2
0.35
0.30
0.25
L3v w
0.05
y y1
0.05
0 1 2 mm
scale
terminal 1
index area
B AD
E
X
C
y
C
y1
terminal 1
index area
3
L k
L1
L2
b
e1
e
AC Bv
Cw
2
1
5
6
7
metal area
not for soldering
8
k
4
L
L3
A1
A
detail X
Figure 13.  Package outline SOT902-2 (XQFN8)
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
15 / 20
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1116
sot1116_po
10-04-02
10-04-07
Unit
mm
max
nom
min
0.35 0.04 1.25
1.20
1.15
1.05
1.00
0.95
0.55 0.3
0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm SOT1116
A1b
0.20
0.15
0.12
D E e e1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
E
D
(4×)(2)
(8×)(2)
A1A
e1e1e1
e
L
L1
b
4321
5678
Figure 14.  Package outline SOT1116 (XSON8)
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
16 / 20
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1203
sot1203_po
10-04-02
10-04-06
Unit
mm
max
nom
min
0.35 0.04 1.40
1.35
1.30
1.05
1.00
0.95
0.55 0.35
0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203
A1b
0.20
0.15
0.12
D E e e1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
E
D
(4×)(2)
(8×)(2)
A
A1
e
L
L1
b
e1e1e1
1
8
2
7
3
6
4
5
Figure 15.  Package outline SOT1203 (XSON8)
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
17 / 20
13 Abbreviations
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
14 Revision history
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC2G02 v.13 20180420 Product data sheet - 74LVC2G02 v.12
Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
•Legal texts have been adapted to the new company name where appropriate.
•Type number 74LVC2G02GD (SOT996-2) removed.
74LVC2G02 v.12 20161212 Product data sheet - 74LVC2G02 v.11
Modifications: •Table 7: The maximum limits for leakage current and supply current have changed.
74LVC2G02 v.11 20130408 Product data sheet - 74LVC2G02 v.10
Modifications: •For type number 74LVC2G02GD XSON8U has changed to XSON8.
74LVC2G02 v.10 20120622 Product data sheet - 74LVC2G02 v.9
Modifications: •For type number 74LVC2G02GM the SOT code has changed to SOT902-2.
74LVC2G02 v.9 20111130 Product data sheet - 74LVC2G02 v.8
Modifications: •Legal pages updated.
74LVC2G02 v.8 20101020 Product data sheet - 74LVC2G02 v.7
74LVC2G02 v.7 20080606 Product data sheet - 74LVC2G02 v.6
74LVC2G02 v.6 20080222 Product data sheet - 74LVC2G02 v.5
74LVC2G02 v.5 20070904 Product data sheet - 74LVC2G02 v.4
74LVC2G02 v.4 20060515 Product data sheet - 74LVC2G02 v.3
74LVC2G02 v.3 20050201 Product specification - 74LVC2G02 v.2
74LVC2G02 v.2 20040915 Product specification - 74LVC2G02 v.1
74LVC2G02 v.1 20031015 Product specification - -
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
18 / 20
15 Legal information
15.1 Data sheet status
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product
development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local Nexperia
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Notwithstanding any damages that
customer might incur for any reason whatsoever, Nexperia's aggregate and
cumulative liability towards customer for the products described herein shall
be limited in accordance with the Terms and conditions of commercial sale of
Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification. Customers are responsible for the
design and operation of their applications and products using Nexperia
products, and Nexperia accepts no liability for any assistance with
applications or customer product design. It is customer’s sole responsibility
to determine whether the Nexperia product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products. Nexperia does not accept
any liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using Nexperia products in order to avoid a default of the
applications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Nexperia 74LVC2G02
Dual 2-input NOR gate
74LVC2G02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved.
Product data sheet Rev. 13 — 20 April 2018
19 / 20
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications. In the event that customer
uses the product for design-in and use in automotive applications to
automotive specifications and standards, customer (a) shall use the product
without Nexperia's warranty of the product for such automotive applications,
use and specifications, and (b) whenever customer uses the product for
automotive applications beyond Nexperia's specifications such use shall be
solely at customer’s own risk, and (c) customer fully indemnifies Nexperia
for any liability, damages or failed product claims resulting from customer
design and use of the product for automotive applications beyond Nexperia's
standard warranty and Nexperia's product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Nexperia 74LVC2G02
Dual 2-input NOR gate
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© Nexperia B.V. 2018. All rights reserved.
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 20 April 2018
Document identifier: 74LVC2G02
Contents
1 General description ............................................ 1
2 Features and benefits .........................................1
3 Ordering information .......................................... 2
4 Marking .................................................................2
5 Functional diagram ............................................. 3
6 Pinning information ............................................ 3
6.1 Pinning ............................................................... 3
6.2 Pin description ................................................... 4
7 Functional description ........................................4
8 Limiting values ....................................................5
9 Recommended operating conditions ................ 5
10 Static characteristics .......................................... 6
11 Dynamic characteristics .....................................8
11.1 Waveforms and test circuit ................................ 8
12 Package outline .................................................10
13 Abbreviations .................................................... 17
14 Revision history ................................................ 17
15 Legal information ..............................................18