Multiple Range, 16-/12-Bit, Bipolar/Unipolar
Voltage Output DACs with 2 ppm/°C Reference
Data Sheet AD5761R/AD5721R
Rev. C Document Feedback
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FEATURES
8 software-programmable output ranges: 0 V to +5 V, 0 V to
+10 V, 0 V to +16 V, 0 V to +20 V, ±3 V, ±5 V, ±10 V, and −2.5 V
to +7.5 V; 5% overrange
Low drift 2.5 V reference: ±2 ppm/°C typical
Total unadjusted error (TUE): 0.1% FSR maximum
16-bit resolution: ±2 LSB maximum INL
Guaranteed monotonicity: ±1 LSB maximum
Single channel, 16-/12-bit DACs
Settling time: 7.5 μs typical
Integrated reference buffers
Low noise: 35 nV/√Hz
Low glitch: 1 nV-sec (0 V to 5 V range)
1.7 V to 5.5 V digital supply range
Asynchronous updating via LDAC
Asynchronous RESET to zero scale/midscale
DSP-/microcontroller-compatible serial interface
Robust 4 kV HBM ESD rating
16-lead, 3 mm × 3 mm LFCSP package
16-lead TSSOP package
Operating temperature range: −40°C to +125°C
APPLICATIONS
Industrial automation
Instrumentation, data acquisition
Open-/closed-loop servo control, process control
Programmable logic controllers
GENERAL DESCRIPTION
The AD5761R/AD5721R are single channel, 16-/12-bit serial
input, voltage output, digital-to-analog converters (DACs).
They operate from single supply voltages from +4.75 V to
+30 V or dual supply voltages from −16.5 V to 0 V VSS and
+4.75 V to +16.5 V VDD. The integrated output amplifier,
reference buffer, and reference provide a very easy to use,
universal solution.
The devices offer guaranteed monotonicity, integral nonlinearity
(INL) of ±2 LSB maximum, 35 nV/√Hz noise, and 7.5 μs settling
time on selected ranges.
The AD5761R/AD5721R use a serial interface that operates at
clock rates of up to 50 MHz and are compatible with DSP and
microcontroller interface standards. Double buffering allows the
asynchronous updating of the DAC output. The input coding
is user-selectable twos complement or straight binary. The
asynchronous reset function resets all registers to their default
state. The output range is user selectable, via the RA[2:0] bits
in the control register.
The devices available in a 3 mm × 3 mm LFCSP package and a
16-lead TSSOP package offer guaranteed specifications over the
−40°C to +125°C industrial temperature range.
FUNCTIONAL BLOCK DIAGRAM
12-BIT/
16-BIT
DAC
LDAC
V
OUT
REFERENCE
BUFFERS
SDI
SCLK
SYNC
SDO
RESET
V
DD
V
SS
DV
CC
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
DGND AGND
AD5761R/AD5721R
CLEAR
INPUT
REG
DAC
REG
12/16
12/16
2.5V
REFERENCE
ALERT
V
REFIN
/
V
REFOUT
DNC
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
12355-001
0V TO 5V
0V TO 10V
0V TO 16V
0V TO 20V
±3V
±5V
±10V
−2.5V TO +7.5V
Figure 1.
AD5761R/AD5721R Data Sheet
Rev. C | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Performance Characteristics ................................................ 6
Timing Characteristics ................................................................ 7
Timing Diagrams .......................................................................... 7
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characterstics............................................. 12
Terminology .................................................................................... 23
Theory of Operation ...................................................................... 25
Digital-to-Analog Converter .................................................... 25
Transfer Function ....................................................................... 25
DAC Architecture ....................................................................... 25
Serial Interface ............................................................................ 26
Hardware Control Pins .............................................................. 26
Thermal Hysteresis .................................................................... 27
Register Details ............................................................................... 28
Input Shift Register .................................................................... 28
Control Register ......................................................................... 29
Readback Control Register ....................................................... 30
Update DAC Register from Input Register ............................. 31
Readback DAC Register ............................................................ 31
Write and Update DAC Register .............................................. 31
Readback Input Register ............................................................ 32
Disable Daisy-Chain Functionality .......................................... 32
Software Data Reset ................................................................... 32
Software Full Reset ..................................................................... 33
No Operation Registers ............................................................. 33
Applications Information .............................................................. 34
Typical Operating Circuit ......................................................... 34
Power Supply Considerations ................................................... 34
Evaluation Board ........................................................................ 34
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 36
REVISION HISTORY
1/2018—Rev. B to Rev. C
Changes to Transfer Function Section ......................................... 25
Moved DAC Output Amplifier Section ....................................... 26
Change to DB[15:11] Column, Table 11 and RA[2:0]
Description Column, Table 12 ...................................................... 29
Change to DB[15:13] Column, Table 15 ..................................... 30
Updated Outline Dimensions ....................................................... 35
Moved Ordering Guide Section.................................................... 36
Changes to Ordering Guide .......................................................... 36
10/2016—Rev. A to Rev. B
Changes to Features Section ........................................................... 1
5/2015—Rev. 0 to Rev. A
Added LFCSP Package ....................................................... Universal
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 6
Changes to Table 4 ............................................................................ 9
Added Figure 6 and Table 6; Renumbered Sequentially ........... 11
Changes to Figure 21 to Figure 24 ................................................ 14
Changes to Figure 35 ...................................................................... 16
Changes to Figure 37 ...................................................................... 17
Changes to Figure 50 ...................................................................... 19
Changes to Figure 58 to Figure 60 ................................................ 20
Changes to Figure 61 to Figure 66 ................................................ 21
Changes to Figure 69 ...................................................................... 22
Added Figure 71 ............................................................................. 22
Changes to Terminology Section ................................................. 23
Changes to Digital-to-Analog Converter Section and Internal
Reference Section ........................................................................... 25
Changes to Asynchronous Clear Function (CLEAR) Section ....... 27
Changes to Table 12 ....................................................................... 29
Changes to Power Supply Considerations Section and
Figure 77 .......................................................................................... 34
Added Figure 79 ............................................................................. 35
Updated Outline Dimensions ....................................................... 35
Changes to Ordering Guide .......................................................... 35
11/2014—Revision 0: Initial Version
Data Sheet AD5761R/AD5721R
Rev. C | Page 3 of 36
SPECIFICATIONS
VDD1 = 4.75 V to 30 V, VSS1 = −16.5 V to 0 V, AGND = DGND = 0 V, VREFIN/VREFOUT = 2.5 V external, DVCC = 1.7 V to 5.5 V, RLOAD = 1 kΩ
for all ranges except 0 V to 16 V and 0 V to 20 V for which RLOAD = 2 kΩ, CLOAD = 200 pF, all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter2 Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
External reference3 and internal reference, outputs
unloaded
Programmable Output Ranges 0 5 V
0 10 V
0 16 V
0 20 V
−2.5 +7.5 V
−3 +3 V
−5 +5 V
−10 +10 V
AD5761R
Resolution
16
Bits
Relative Accuracy, INL
A Grade −8 +8 LSB External reference3 and internal reference
B Grade4 −2 +2 LSB All ranges except 0 V to 16 V and 0 V to 20 V,
VREFIN/VREFOUT = 2.5 V external and internal reference
Differential Nonlinearity, DNL −1 +1 LSB
AD5721R
Resolution 12 Bits
Relative Accuracy, INL
B Grade −0.5 +0.5 LSB External reference3 and internal reference
Differential Nonlinearity, DNL −0.5 +0.5 LSB
Zero-Scale Error
−6
+6
mV
All ranges except ±10 V and 0 V to 20 V, external
reference3
−10 +10 mV 0 V to 20 V, ±10 V ranges, external reference3
−6 +6 mV All ranges except ±5 V, ±10 V and 0 V to 20 V,
internal reference
−8 +8 mV ±5 V range, internal reference
−9
+9
mV
0 V to 20 V range, internal reference
−13 +13 mV ±10 V range, internal reference
Zero-Scale Temperature
Coefficient (TC)5
±5 µV/°C Unipolar ranges, external reference3 and internal
reference
±15 µV/°C Bipolar ranges, external reference3 and internal
reference
Bipolar Zero Error −5 +5 mV All bipolar ranges except ±10 V
−7 +7 mV ±10 V output range
Bipolar Zero TC5 ±2 µV/°C ±3 V range, external reference3 and internal
reference
±5 µV/°C All bipolar ranges except ±3 V range, external
reference3 and internal reference
Offset Error −6 +6 mV All ranges except ±10 V and 0 V to 20 V, external
reference3
−10 +10 mV 0 V to 20 V, ±10 V ranges, external reference3
−6 +6 mV All ranges except ±5 V, ±10 V, and 0 V to 20 V;
internal reference
−8 +8 mV ±5 V range, internal reference
−9 +9 mV 0 V to 20 V range, internal reference
−13 +13 mV ±10 V range, internal reference
AD5761R/AD5721R Data Sheet
Rev. C | Page 4 of 36
Parameter2 Min Typ Max Unit Test Conditions/Comments
Offset Error TC5 ±5 µV/°C Unipolar ranges, external reference3 and internal
reference
±15 µV/°C Bipolar ranges, external reference3 and internal
reference
Gain Error −0.1 +0.1 % FSR External reference3
−0.15 +0.15 % FSR Internal reference
Gain Error TC5 ±1.5 ppm FSR/°C External reference3 and internal reference
TUE −0.1 +0.1 % FSR External reference3
−0.15 +0.15 % FSR Internal reference
REFERENCE INPUT (EXTERNAL)5
Reference Input Voltage (VREF) 2.5 V ±1% for specified performance
Input Current −2 ±0.5 +2 µA
Reference Range 2 3 V
REFERENCE OUTPUT (INTERNAL)5
Output Voltage 2.5 V ±3 mV, at ambient temperature
Voltage Reference TC 2 5 ppm/°C
Output Impedance 25 kΩ
Output Voltage Noise 6 µV p-p 0.1 Hz to 10 Hz
Noise Spectral Density 10 nV/√Hz At ambient; f = 10 kHz
Line Regulation 6 µV/V At ambient
Thermal Hysteresis 80 ppm First temperature cycle
Start-Up Time 3.5 ms Coming out of power-down mode with a 10 nF
capacitor on the VREFIN/VREFOUT pin to improve noise
performance; outputs unloaded
OUTPUT CHARACTERISTICS
5
Output Voltage Range −VOUT +VOUT See Table 7 for the different output voltage ranges
available
−10 +10 V VDD/VSS = ±11 V, ±10 V output range
−10.5 +10.5 V VDD/VSS = ±11 V, ±10 V output range with 5%
overrange
Capacitive Load Stability 1 nF
Headroom 0.5 1 V RLOAD = 1 kΩ for all ranges except 0 V to16 V and 0 V
to 20 V ranges (RLOAD = 2 kΩ)
Output Voltage TC ±3 ppm FSR/°C ±10 V range, external reference
Short-Circuit Current 25 mA Short on the VOUT pin
Resistive Load
1
kΩ
All ranges except 0 V to16 V and 0 V to 20 V
2 kΩ 0 V to 16 V, 0 V to 20 V ranges
Load Regulation 0.3 mV/mA Outputs unloaded
DC Output Impedance 0.5 Ω Outputs unloaded
LOGIC INPUTS5 DVCC = 1.7 V to 5.5 V, JEDEC compliant
Input Voltage
High, VIH 0.7 × DVCC V
Low, VIL 0.3 × DVCC V
Input Current
Leakage Current −1 +1 µA SDI, SCLK, SYNC
−1 +1 µA LDAC, CLEAR, RESET pins held high
−55 µA LDAC, CLEAR, RESET pins held low
Pin Capacitance 5 pF Per pin, outputs unloaded
Data Sheet AD5761R/AD5721R
Rev. C | Page 5 of 36
Parameter2 Min Typ Max Unit Test Conditions/Comments
LOGIC OUTPUTS (SDO, ALERT)5
Output Voltage
Low, VOL 0.4 V DVCC = 1.7 V to 5.5 V, sinking 200 µA
High, VOH DVCC − 0.5 V DVCC = 1.7 V to 5.5 V, sourcing 200 µA
High Impedance, SDO Pin
Leakage Current −1 +1 µA
Pin Capacitance 5 pF
POWER REQUIREMENTS
VDD 4.75 30 V
VSS −16.5 0 V
DVCC 1.7 5.5 V
IDD 5.1 6.5 mA Outputs unloaded, external reference
ISS 1 3 mA Outputs unloaded
DICC 0.005 1 µA VIH = DVCC, VIL = DGND
Power Dissipation 67.1 mW ±11 V operation, outputs unloaded, TSSOP package
DC Power Supply Rejection
Ratio (PSRR)5
0.1 mV/V VDD ± 10%, VSS = −15 V
0.1 mV/V VSS ±10%, VDD = +15 V
AC PSRR5 65 dB VDD ±200 mV, 50 Hz/60 Hz, VSS = −15 V, internal
reference, CLOAD = 100 nF
65 dB VSS ±200 mV, 50 Hz/60 Hz, VDD = +15 V, internal
reference, CLOAD = 100 nF
80 dB VDD ±200 mV, 50 Hz/60 Hz, VSS = −15 V, external
reference, CLOAD = unloaded
80
dB
VSS ±200 mV, 50 Hz/60 Hz, VDD = +15 V, external
reference, CLOAD = unloaded
1 For specified performance, headroom requirement is 1 V.
2 Temperature range: −40°C to +125°C, typical at +25°C.
3 External reference means 2 V to 2.85 V with overrange and 2 V to 3 V without overrange.
4 Integral nonlinearity error is specified at ±4 LSB (min/max) for 16 V and 20 V ranges with VREFIN/VREFOUT = 2.5 V external and internal, and for all ranges with VREFIN/VREFOUT =
2 V to 2.85 V with overrange and 2 V to 3 V without overrange.
5 Guaranteed by design and characterization, not production tested.
AD5761R/AD5721R Data Sheet
Rev. C | Page 6 of 36
AC PERFORMANCE CHARACTERISTICS
VDD1 = 4.75 V to 30 V, VSS1 = −16.5 V to 0 V, AGND = DGND = 0 V, VREFIN/VREFOUT = 2.5 V external, DVCC = 1.7 V to 5.5 V, RLOAD = 1 kΩ
for all ranges except 0 V to 16 V and 0 V to 20 V for which RLOAD = 2 kΩ, CLOAD = 200 pF, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2 Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE3
Output Voltage Settling Time 9 12.5 µs 20 V step to 1 LSB at 16-bit resolution
7.5 8.5 µs 10 V step to 1 LSB at 16-bit resolution
5 µs 512 LSB step to 1 LSB at 16-bit resolution
Digital-to-Analog Glitch Impulse
8
nV-sec
±10 V range
1 nV-sec 0 V to 5 V range
Glitch Impulse Peak Amplitude 15 mV ±10 V range
10 mV 0 V to 5 V range
Power-On Glitch 100 mV p-p
Digital Feedthrough 0.6 nV-sec
Output Noise
0.1 Hz to 10 Hz Bandwidth 15 µV p-p
100 kHz Bandwidth 45 µV rms 0 V to 20 V and 0 V to 16 V ranges, 2.5 V external reference
35 µV rms 0 V to 10 V, ±10 V, and −2.5 V to +7.5 V ranges, 2.5 V external reference
25 µV rms ±5 V range, 2.5 V external reference
15 µV rms 0 V to 5 V and ±3 V ranges, 2.5 V external reference
Output Noise Spectral Density,
at 10 kHz
80 nV/√Hz ±10 V range, 2.5 V external reference
35 nV/√Hz ±3 V range, 2.5 V external reference
70 nV/√Hz ±5 V, 0 V to 10 V, and −2.5 V to +7.5 V ranges, 2.5 V external reference
110 nV/√Hz 0 V to 20 V range, 2.5 V external reference
90
nV/√Hz
0 V to 16 V range, 2.5 V external reference
45 nV/√Hz 0 V to 5 V range, 2.5 V external reference
Total Harmonic Distortion (THD)4 −87 dB 2.5 V external reference, 1 kHz tone
Signal-to-Noise Ratio (SNR) 92 dB At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz
Peak Harmonic or Spurious
Noise (SFDR)
92 dB At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz
Signal-to-Noise-and-Distortion
(SINAD) Ratio
85 dB At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz
1 For specified performance, headroom requirement is 1 V.
2 Temperature range: −40°C to +125°C, typical at +25°C.
3 Guaranteed by design and characterization, not production tested.
4 Digitally generated sine wave at 1 kHz.
Data Sheet AD5761R/AD5721R
Rev. C | Page 7 of 36
TIMING CHARACTERISTICS
DVCC = 1.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Limit at TMIN, TMAX Unit Description
t11 20 ns min SCLK cycle time
t2 10 ns min SCLK high time
t3 10 ns min SCLK low time
t4 15 ns min SYNC falling edge to SCLK falling edge setup time
t5 10 ns min SCLK falling edge to SYNC rising edge time
t
6
20
ns min
Minimum SYNC high time (write mode)
t7 5 ns min Data setup time
t8 5 ns min Data hold time
t9 10 ns min LDAC falling edge to SYNC falling edge
t10 20 ns min SYNC rising edge to LDAC falling edge
t11 20 ns min LDAC pulse width low
t
12
9
µs typ
DAC output settling time, 20 V step to 1 LSB at 16-bit resolution (see Table 2)
7.5 µs typ DAC output settling time, 10 V step to 1 LSB at 16-bit resolution
t13 20 ns min CLEAR pulse width low
t14 200 ns typ CLEAR pulse activation time
t15 10 ns min SYNC rising edge to SCLK falling edge
t16 40 ns max SCLK rising edge to SDO valid (CL_SDO2 = 15 pF)
t17 50 ns min Minimum SYNC high time (readback/daisy-chain mode)
1 Maximum SCLK frequency is 50 MHz for write mode and 33 MHz for readback mode.
2 CL_SDO is the capacitive load on the SDO output.
TIMING DIAGRAMS
DB23
SCLK
SYNC
SDI
LDAC
CLEAR
V
OUT
V
OUT
V
OUT
4221
DB0
t12
t12
t10
t11
t14
t13
t9
t8
t7
t4
t6t3t2
t1
t5
12355-002
Figure 2. Serial Interface Timing Diagram
AD5761R/AD5721R Data Sheet
Rev. C | Page 8 of 36
t
4
t
10
t
16
t
8
t
7
t
11
t
3
t
2
t
5
t
1
t
15
LDAC
SDO
SDI
SYNC
SCLK
8
4
4
2
DB0
DB23
DB0DB23
DB23
INPUT WORD FOR DAC N
UNDEFINED
INPUT WORD FOR DAC N – 1
INPUT WORD FOR DAC N
DB0
t
17
12355-003
Figure 3. Daisy-Chain Timing Diagram
SDO
SDI
SYNC
SCLK 24 24
DB23 DB0 DB23 DB0
SELECTED REGISTER DATA
CLOCKED OUT
UNDEFINED
NOP CONDITIONINPUT WORD SPECIFIES
REGISTER TO BE READ
11
DB23 DB0 DB23 DB0
t17
12355-004
Figure 4. Readback Timing Diagram
Data Sheet AD5761R/AD5721R
Rev. C | Page 9 of 36
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
200 mA do not cause silicon controlled rectifier (SCR) latch-up.
Table 4.
Parameter Rating
V
DD
to AGND
−0.3 V to +34 V
VSS to AGND +0.3 V to −17 V
VDD to VSS −0.3 V to +34 V
DVCC to DGND −0.3 V to +7 V
Digital Inputs to DGND −0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
Digital Outputs to DGND −0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
VREFIN/VREFOUT to DGND −0.3 V to +7 V
VOUT to AGND VSS to VDD
AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range,
TA Industrial
−40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature, TJ MAX 150°C
16-Lead TSSOP Package
θJA Thermal Impedance 113°C/W1
θ
JC
Thermal Impedance
28°C/W
16-Lead LFCSP Package
θJA Thermal Impedance 75°C/W1
θJC Thermal Impedance 4.5°C/W2
Power Dissipation (TJ MAX − TA)/θJA
Lead Temperature JEDEC industry standard
Soldering J-STD-020
ESD (Human Body Model) 4 kV
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
2 Measured to exposed paddle, with infinite heat sink on package top surface.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD5761R/AD5721R Data Sheet
Rev. C | Page 10 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
AGND
V
OUT
V
SS
V
REFIN/
V
REFOUT
V
DD
16
15
14
13
12
11
10
9
SDI
DGND
SDO
DV
CC
DNC
SCLK
SYNC
CLEAR
RESET
LDAC
ALERT
12355-006
TOP VIEW
(Notto Scale)
AD5761R/
AD5721R
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT
TO THIS PIN.
Figure 5. 16-Lead TSSOP Pin Configuration
Table 5. 16-Lead TSSOP Pin Function Descriptions
Pin No. Mnemonic Description
1 ALERT Active Low Alert. This pin is asserted low when the die temperature exceeds approximately 150°C, or when an
output short circuit or a brownout occurs. This pin is also asserted low during power-up, a full software reset, or
a hardware reset, for which a write to the control register asserts the pin high.
2 CLEAR Falling Edge Clear Input. Asserting this pin sets the DAC register to zero scale, midscale, or full-scale code (user
selectable) and updates the DAC output. This pin can be left floating because there is an internal pull-up resistor.
3 RESET Active Low Reset Input. Asserting this pin returns the AD5761R/AD5721R to their default power-on status
where the output is clamped to ground and the output buffer is powered down. This pin can be left floating
because there is an internal pull-up resistor.
4 VREFIN/VREFOUT Internal Reference Voltage Output and External Reference Voltage Input. For specified performance,
VREFIN/VREFOUT = 2.5 V. Connect a 10 nF capacitor with the internal reference to minimize the noise.
5 AGND Ground Reference Pin for Analog Circuitry.
6 VSS Negative Analog Supply Connection. A voltage in the range of −16.5 V to 0 V can be connected to this pin. For
unipolar output ranges, connect this pin to 0 V. VSS must be decoupled to AGND.
7
V
OUT
Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load.
8 VDD Positive Analog Supply Connection. A voltage in the range of 4.75 V to 30 V can be connected to this pin for
unipolar output ranges. Bipolar output ranges accept a voltage in the range of 4.75 V to 16.5 V. VDD must be
decoupled to AGND.
9 DNC Do Not Connect. Do not connect to this pin.
10 SDO Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode. Data is clocked
out on the rising edge of SCLK and is valid on the falling edge of SCLK.
11 LDAC Load DAC. This logic input updates the DAC register and, consequently, the analog output. When tied
permanently low, the DAC register is updated when the input register is updated. If LDAC is held high during
the write to the input register, the DAC output register is not updated, and the DAC output update is held off
until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor.
12
SDI
Serial Data Input. Data must be valid on the falling edge of SCLK.
13 SYNC Active Low Synchronization Input. This pin is the frame synchronization signal for the serial interface. While
SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC.
14 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at
clock speeds of up to 50 MHz.
15 DVCC Digital Supply. The voltage range is from 1.7 V to 5.5 V. The applied voltage sets the voltage at which the digital
interface operates.
16 DGND Digital Ground.
Data Sheet AD5761R/AD5721R
Rev. C | Page 11 of 36
12335-106
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
AD5761R/
AD5721R
TOP VIEW
(Not to Scale)
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PAD MUST BE MECHANICAL LY CONNECTED TO THE PCB
COPPER PLANE FOR OPTIMAL THERMAL PERFORMANCE. THE EXPOSED PAD
CAN BE LEFT ELECTRICALLY FLOATING.
RESET
V
REFIN
/V
REFOUT
AGND
V
SS
SCLK
DV
CC
DGND
ALERT
CLEAR
SYNC
SDI
LDAC
V
OUT
V
DD
DNC
SDO
Figure 6. 16-Lead LFCSP Pin Configuration
Table 6. 16-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Description
1 RESET Active Low Reset Input. Asserting this pin returns the AD5761R/AD5721R to their default power-on status
where the output is clamped to ground and the output buffer is powered down. This pin can be left floating
because there is an internal pull-up resistor.
2 VREFIN/VREFOUT Internal Reference Voltage Output and External Reference Voltage Input. For specified performance,
VREFIN/VREFOUT = 2.5 V. Connect a 10 nF capacitor with the internal reference to minimize the noise.
3 AGND Ground Reference Pin for Analog Circuitry.
4 VSS Negative Analog Supply Connection. A voltage in the range of −16.5 V to 0 V can be connected to this pin. For
unipolar output ranges, connect this pin to 0 V. VSS must be decoupled to AGND.
5 VOUT Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load.
6 VDD Positive Analog Supply Connection. A voltage in the range of 4.75 V to 30 V can be connected to this pin for
unipolar output ranges. Bipolar output ranges accept a voltage in the range of 4.75 V to 16.5 V. VDD must be
decoupled to AGND.
7
DNC
Do Not Connect. Do not connect to this pin.
8 SDO Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode. Data is clocked
out on the rising edge of SCLK and is valid on the falling edge of SCLK.
9 LDAC Load DAC. This logic input updates the DAC register and, consequently, the analog output. When tied
permanently low, the DAC register is updated when the input register is updated. If LDAC is held high during
the write to the input register, the DAC output register is not updated, and the DAC output update is held off
until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor.
10 SDI Serial Data Input. Data must be valid on the falling edge of SCLK.
11 SYNC Active Low Synchronization Input. This pin is the frame synchronization signal for the serial interface. While
SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC.
12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at
clock speeds of up to 50 MHz.
13 DVCC Digital Supply. The voltage range is from 1.7 V to 5.5 V. The applied voltage sets the voltage at which the digital
interface operates.
14 DGND Digital Ground.
15 ALERT Active Low Alert. This pin is asserted low when the die temperature exceeds approximately 150°C, or when an
output short circuit or a brownout occurs. This pin is also asserted low during power-up, a full software reset, or
a hardware reset, for which a write to the control register asserts the pin high.
16 CLEAR Falling Edge Clear Input. Asserting this pin sets the DAC register to zero scale, midscale, or full-scale code (user
selectable) and updates the DAC output. This pin can be left floating because there is an internal pull-up resistor.
EPAD Exposed Pad. The exposed pad must be mechanically connected to the PCB copper plane for optimal thermal
performance. The exposed pad can be left electrically floating.
AD5761R/AD5721R Data Sheet
Rev. C | Page 12 of 36
TYPICAL PERFORMANCE CHARACTERSTICS
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0 10000 20000 30000 40000 50000 60000
DAC CODE
INL ERROR (LSB)
+5V SPAN
+10V SPAN
+16V SPAN
+20V SPAN
VDD = +21V
VSS =–11V
12355-007
Figure 7. AD5761R INL Error vs. DAC Code, Unipolar Output
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0 500 1000 1500 2000 2500 3000 3500 4000
DAC CODE
INL ERROR (LSB)
+5V SPAN
+10V SPAN
+16V SPAN
+20V SPAN
V
DD
= +21V
V
SS
= –11V
12355-008
Figure 8. AD5721R INL Error vs. DAC Code, Unipolar Output
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0 10000 20000 30000 40000 50000 60000
DAC CODE
INL ERROR (LSB)
±3V SPAN
±5V SPAN
±10V SPAN
–2.5V TO +7.5V SPAN
VDD = +21V
VSS = –11V
12355-009
Figure 9. AD5761R INL Error vs. DAC Code, Bipolar Output
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0500 1000 1500 2000 2500 3000 3500 4000
DAC CODE
INL ERROR (LSB)
V
DD
= +21V
V
SS
= –11V
±3V SPAN
±5V SPAN
±10V SPAN
–2.5V TO +7.5V SPAN
12355-010
Figure 10. AD5721R INL Error vs. DAC Code, Bipolar Output
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0 10000 20000 30000 40000 50000 60000
DAC CODE
DNL ERROR (LSB)
V
DD
= +21V
V
SS
=–11V
+5V SPAN
+10V SPAN
+16V SPAN
+20V SPAN
12355-011
Figure 11. AD5761R DNL Error vs. DAC Code, Unipolar Output
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0 500 1000 1500 2000 2500 3000 3500 4000
DAC CODE
DNL ERROR (LSB)
+5V SPAN
+10V SPAN
+16V SPAN
+20V SPAN
V
DD
= +21V
V
SS
= –11V
12355-012
Figure 12. AD5721R DNL Error vs. DAC Code, Unipolar Output
Data Sheet AD5761R/AD5721R
Rev. C | Page 13 of 36
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0 10000 20000 30000 40000 50000 60000
DAC CODE
DNL ERROR (LSB)
V
DD
= +21V
V
SS
=–11V
±3V SPAN
±5V SPAN
±10V SPAN
–2.5V TO +7.5V SPAN
12355-013
Figure 13. AD5761R DNL Error vs. DAC Code, Bipolar Output
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0 500 1000150020002500300035004000
DAC CODE
DNL ERROR (LSB)
V
DD
= +21V
V
SS
= –11V
±3V SPAN
±5V SPAN
±10V SPAN
–2.5V TO +7.5V SPAN
12355-014
Figure 14. AD5721R DNL Error vs. DAC Code, Bipolar Output
–1.5
–1.0
–0.5
0
0.5
1.0
1.5 +5V U1 INT MAX INL
+5V U2 EXT MAX INL
±10V U1 INT MAX INL
±10V U2 EXT MAX INL
+5V U1 INT MIN INL
V
DD
= +21V
V
SS
= –11V
INL ERROR (LSB)
+5V U2 EXT MIN INL
±10V U1 INT MIN INL
±10V U2 EXT MIN INL
–40 –20 0 25 50 85 105 125
TEMPERATURE (°C)
12355-015
Figure 15. INL Error vs. Temperature
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
–40 –20 0 25 50 85 105 125
DNL ERROR (LSB)
+5V U2 EXT MAX DNL
±10V U2 EXT MAX DNL
+5V U1 INT MAX DNL
±10V U1 INT MAX DNL
+5V U2 EXT MIN DNL
±10V U2 EXT MIN DNL
+5V U1 INT MIN DNL
±10V U1 INT MIN DNL
TEMPERATURE (°C)
V
DD
= +21V
V
SS
= –11V
12355-016
Figure 16. DNL Error vs. Temperature
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
+5V SPAN V
DD
/V
SS
= +6V/–1V
±10V SPAN V
DD
/V
SS
= +11V/–11V
V
DD
/V
SS
= +7.5V/–1V
V
DD
/V
SS
= +12.5V/–12.5V
V
DD
/V
SS
= +10V/–1V
V
DD
/V
SS
= +13.5V/–13.5V
V
DD
/V
SS
= +12.5V/–1V
V
DD
/V
SS
= +14.5V/–14.5V
V
DD
/V
SS
= +16.5V/–1V
V
DD
/V
SS
= +16.5V/–16.5V
SUPPLY VOLTAGE (V)
INL ERROR (LSB)
V
DD
= +21V
V
SS
= –11V
T
A
= 25°C
NO LOAD
+5V U2 EXT MAX INL
+5V U2 EXT MIN INL
+5V U1 INT MAX INL
+5V U1 INT MIN INL
±10V U2 EXT MAX INL
±10V U2 EXT MIN INL
±10V U1 NT MAX INL
±10V U1 INT MIN INL
12355-017
Figure 17. INL Error vs. Supply Voltage
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
+5V SPAN V
DD
/V
SS
= +6V/–1V
±10V SPAN V
DD
/V
SS
= +11V/–11V
V
DD
/V
SS
= +7.5V/–1V
V
DD
/V
SS
= +12.5V/–12.5V
V
DD
/V
SS
= +10V/–1V
V
DD
/V
SS
= +13.5V/–13.5V
V
DD
/V
SS
= +12.5V/–1V
V
DD
/V
SS
= +14.5V/–14.5V
V
DD
/V
SS
= +16.5V/–1V
V
DD
/V
SS
= +16.5V/–16.5V
SUPPLY VOLTAGE (V)
DNL ERROR (LSB)
V
DD
= +21V
V
SS
= –11V
T
A
= 25°C
NO LOAD
+5V U2 EXT MAX DNL
+5V U2 EXT MIN DNL
+5V U1 INT MAX DNL
+5V U1 INT MIN DNL
±10V U2 EXT MAX DNL
±10V U2 EXT MIN DNL
±10V U1 NT MAX DNL
±10V U1 INT MIN DNL
12355-018
Figure 18. DNL Error vs. Supply Voltage
AD5761R/AD5721R Data Sheet
Rev. C | Page 14 of 36
–3
–2
–1
0
1
2
3
2.00 2.25 2.50 2.75 3.00
INL ERROR (LSB)
REFERENCE VOLTAGE (V)
V
DD
= +21V
V
SS
= –11V
MAX INL, +5V SPAN
MAX INL, ±10V SPAN
MIN INL, +5V SPAN
MIN INL, ±10V SPAN
12355-019
Figure 19. INL Error vs. Reference Voltage
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
12355-020
2.00 2.502.25 2.75 3.00
DNL ERROR (LSB)
REFERENCE VOLTAGE (V)
V
DD
= +21V
V
SS
= –11V
MAX DNL, ±10V SPAN
MAX DNL, +5V SPAN
MIN DNL, ±10V SPAN
MIN DNL, +5V SPAN
Figure 20. DNL Error vs. Reference Voltage
12355-021
–0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
0.006
0.008
0.010
–40 –20
0 25 50 85 105 125
TEMPERATURE (°C)
ZERO-SCALE ERROR (V)
V
DD
= +21V
V
SS
= –11V +5V U1 EXT
+5V U2 INT
±10V U1 EXT
±10V U2 INT
Figure 21. Zero-Scale Error vs. Temperature
–40 –20 0 25 50 85 105 125
–0.006
–0.004
–0.002
0
0.002
0.004
0.006
MIDSCALE ERROR (V)
TEMPERATURE (°C)
V
DD
= +21V
V
SS
= –11V
12355-022
+5V U1 EXT
+5V U2 INT
±10V U1 EXT
±10V U2 INT
Figure 22. Midscale Error vs. Temperature
12355-023
–0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
0.006
0.008
0.010
–40 –20 0 25 50 85 105 125
TEMPERATURE (°C)
FULL-SCALE ERROR (V)
V
DD
= +21V
V
SS
= –11V +5V U1 EXT
+5V U2 INT
±10V U1 EXT
±10V U2 INT
Figure 23. Full-Scale Error vs. Temperature
–40 –20 0 25 50 85 105 125
TEMPERATURE (°C)
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
GAIN ERROR (%FSR)
V
DD
= +21V
V
SS
= –11V
12355-024
+5V U1 EXT
+5V U2 INT
±10V U1 EXT
±10V U2 INT
Figure 24. Gain Error vs. Temperature
Data Sheet AD5761R/AD5721R
Rev. C | Page 15 of 36
–0.0050
–0.0045
–0.0040
–0.0035
–0.0030
–0.0025
–0.0020
–0.0015
–0.0010
–0.0005
0
0.0005
0.0010
+5V SPAN V
DD
/V
SS
= +6V/–1V
±10V SPAN V
DD
/V
SS
= +11V/–11V
V
DD
/V
SS
= +7.5V/–1V
V
DD
/V
SS
= +12.5V/–12.5V
V
DD
/V
SS
= +10V/–1V
V
DD
/V
SS
= +13.5V/–13.5V
V
DD
/V
SS
= +12.5V/–1V
V
DD
/V
SS
= +14.5V/–14.5V
V
DD
/V
SS
= +16.5V/–1V
V
DD
/V
SS
= +16.5V/–16.5V
SUPPLY VOLTAGE (V)
+5V U2 EXT
+5V U1 INT
±10V U2 EXT
±10V U1 INT
ZERO-SCALE ERROR (V)
T
A
= 25°C
V
REF
= 2.5V
12355-025
Figure 25. Zero-Scale Error vs. Supply Voltage
–0.0030
–0.0025
–0.0020
–0.0015
–0.0010
–0.0005
0
0.0005
MIDSCALE ERROR (V)
+5V SPAN V
DD
/V
SS
= +6V/–1V
±10V SPAN V
DD
/V
SS
= +11V/–11V
V
DD
/V
SS
= +7.5V/–1V
V
DD
/V
SS
= +12.5V/–12.5V
V
DD
/V
SS
= +10V/–1V
V
DD
/V
SS
= +13.5V/–13.5V
V
DD
/V
SS
= +12.5V/–1V
V
DD
/V
SS
= +14.5V/–14.5V
V
DD
/V
SS
= +16.5V/–1V
V
DD
/V
SS
= +16.5V/–16.5V
SUPPLY VOLTAGE (V)
+5V U2 EXT
+5V U1 INT
±10V U2 EXT
±10V U1 INT
T
A
= 25°C
V
REF
= 2.5V
12355-026
Figure 26. Midscale Error vs. Supply Voltage
–0.0020
–0.0015
–0.0010
–0.0005
0
0.0005
0.0010
+5V SPAN V
DD
/V
SS
= +6V/–1V
±10V SPAN V
DD
/V
SS
= +11V/–11V
V
DD
/V
SS
= +7.5V/–1V
V
DD
/V
SS
= +12.5V/–12.5V
V
DD
/V
SS
= +10V/–1V
V
DD
/V
SS
= +13.5V/–13.5V
V
DD
/V
SS
= +12.5V/–1V
V
DD
/V
SS
= +14.5V/–14.5V
V
DD
/V
SS
= +16.5V/–1V
V
DD
/V
SS
= +16.5V/–16.5V
SUPPLY VOLTAGE (V)
+5V U2 EXT
+5V U1 INT
±10V U2 EXT
±10V U1 INT
FULL-SCALEERROR (V)
T
A
= 25°C
V
REF
= 2.5V
12355-027
Figure 27. Full-Scale Error vs. Supply Voltage
–0.030
–0.025
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
0.020
0.025
0.030
GAIN ERROR (%FSR)
+5V SPAN V
DD
/V
SS
= +6V/–1V
±10V SPAN V
DD
/V
SS
= +11V/–11V
V
DD
/V
SS
= +7.5V/–1V
V
DD
/V
SS
= +12.5V/–12.5V
V
DD
/V
SS
= +10V/–1V
V
DD
/V
SS
= +13.5V/–13.5V
V
DD
/V
SS
= +12.5V/–1V
V
DD
/V
SS
= +14.5V/–14.5V
V
DD
/V
SS
= +16.5V/–1V
V
DD
/V
SS
= +16.5V/–16.5V
SUPPLY VOLTAGE (V)
+5V U2 EXT
+5V U1 INT
±10V U2 EXT
±10V U1 INT
T
A
= 25°C
V
REF
= 2.5V
12355-028
Figure 28. Gain Error vs. Supply Voltage
–0.005
–0.003
–0.001
0.001
0.003
0.005
2.0 2.5 3.0
+5V SPAN
±10V SPAN
REFERENCE VOLTAGE (V)
ZERO-SCALE ERROR (V)
V
DD
= +21V
V
SS
= –11V
T
A
= 25⁰C
12355-029
Figure 29. Zero-Scale Error vs. Reference Voltage
–0.0010
–0.0008
–0.0006
–0.0004
–0.0002
0
0.0002
0.0004
0.0006
0.0008
0.0010
2.0 2.5 3.0
REFERENCE VOLTAGE (V)
MIDSCALE ERROR (V)
+5V SPAN
±10V SPAN
V
DD
= +21V
V
SS
= –11V
T
A
= 25°C
12355-030
Figure 30. Midscale Error vs. Reference Voltage
AD5761R/AD5721R Data Sheet
Rev. C | Page 16 of 36
–0.005
–0.003
–0.001
0.001
0.003
0.005
2.0 2.5 3.0
REFERENCE VOLTAGE (V)
FULL-SCALE ERROR (V)
+5V SPAN
±10V SPAN
V
DD
= +21V
V
SS
= –11V
T
A
= 25°C
12355-031
Figure 31. Full-Scale Error vs. Reference Voltage
–0.05
–0.03
–0.01
0.01
0.03
0.05
2.0 2.5 3.0
+5V SPAN
±10V SPAN
REFERENCE VOLTAGE (V)
GAIN ERROR (%FSR)
V
DD
= +21V
V
SS
= –11V
T
A
= 25°C
12355-032
Figure 32. Gain Error vs. Reference Voltage
–0.05
–0.03
–0.01
0.01
0.03
0.05
TUE (%FSR)
010000 20000 30000 40000 50000 60000
+5V SPAN_INT
+16V SPAN_INT
+5V SPAN_EXT
+16V SPAN_EXT
+10V SPAN_INT
+20V SPAN_INT
+10V SPAN_EXT
+20V SPAN_EXT
T
A
= 25°C
CODE
12355-033
Figure 33. TUE vs. Code, Unipolar Output
–0.05
–0.03
–0.01
0.01
0.03
0.05
010000 20000 30000 40000 50000 60000
± 5V SPAN_INT ±10V SPAN_INT
–2.5V TO +7.5V SPAN_INT ±3V SPAN_INT
±5V SPAN_EXT ±10V SPAN_EXT
–2.5V TO +7.5V SPAN_EXT ±3V SPAN_EXT
CODE
TUE (%FSR)
12355-034
T
A
= 25°C
Figure 34. TUE vs. Code, Bipolar Output
0
0.01
0.02
0.03
0.04
0.05
0.06
–40 –20 020 40 60 80 100 120
+5V_U1_EXTREF
+5V_U2_INTREF
+5V_U3_INTREF
±10V_U1_EXTREF
±10V_U2_INTREF
±10V_U3_INTREF
TEMPERATURE (⁰C)
TUE (%FSR)
VDD = +21V
VSS = –11V
12355-035
Figure 35. TUE vs. Temperature
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
0.020
0.022
0.024
0.026
0.028
0.030
TUE (%FSR)
+5V SPAN V
DD
/V
SS
= +6V/–1V
±10V SPAN V
DD
/V
SS
= +11V/–11V
V
DD
/V
SS
= +7.5V/–1V
V
DD
/V
SS
= +12.5V/–12.5V
V
DD
/V
SS
= +10V/–1V
V
DD
/V
SS
= +13.5V/–13.5V
V
DD
/V
SS
= +12.5V/–1V
V
DD
/V
SS
= +14.5V/–14.5V
V
DD
/V
SS
= +16.5V/–1V
V
DD
/V
SS
= +16.5V/–16.5V
SUPPLY VOLTAGE (V)
+5V U2 EXT
+5V U1 INT
±10V U2 EXT
±10V U1 INT
TA = 25°C
VREF = 2.5V
12355-036
Figure 36. TUE vs. Supply Voltage
Data Sheet AD5761R/AD5721R
Rev. C | Page 17 of 36
12355-037
200µs/DIV
500mV
5V
5V
SYNC
V
REF
V
OUT
Figure 37. Reference Output Voltage Turn On Transient
–10
–8
–6
–4
–2
0
2
4
6
8
10
–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0
NOISE (µV PEAK)
TIME (Seconds)
V
DD
= +21V
V
SS
= –11V
T
A
= 25⁰C
12355-038
Figure 38. Internal Reference Noise (100 kHz Bandwidth)
–10
–8
–6
–4
–2
0
2
4
6
8
10
–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0
NOISE (µV PEAK)
TIME (Second)
V
DD
= +21V
V
SS
= –11V
T
A
= 25⁰C
12355-039
Figure 39. Internal Reference Noise (0.1 Hz to 10 Hz Bandwidth)
REFERENCE OUTPUT NOISE
SPECTRAL DENSITY (V/√Hz)
0.00001
0.000001
0.0000001
0.00000001
0.000000001
10 100 1k
FREQUENCY (Hz)
10k 100k 1M
AV
DD
= 21V
AV
SS
= –11V
DV
CC
= 5V
LOAD = 2kΩ||200pF
CAP ON V
REF
= 10nF
12355-138
Figure 40. Reference Output Noise Spectral Density vs. Frequency
2.4998
2.5000
2.5002
2.5004
2.5006
2.5008
2.5010
2.5012
2.5014
V
SS
–13.50 –13.75 –14.00 –14.25 –14.50 –14.75 –15.00 –15.25 –15.50 –15.75 –16.00 –16.25
V
DD
13.50 13.75 14.00 14.25 14.50 14.75 15.00 15.25 15.50 15.75 16.00 16.25
V
REFOUT
(V)
SUPPLY VOLTAGE (V)
12355-139
Figure 41. Reference Output Voltage (VREFOUT) vs. Supply Voltage
1.5
2.0
2.5
3.0
–10 –8 –6 –4 –2 0246810
BIPOLAR 10V
UNIPOLAR 10V
BIPOLAR 5V
UNIPOLAR 5V
–2.5V TO 7.5V
BIPOLAR 3V
UNIPOLAR 16V
UNIPOLAR 20V
LOAD CURRENT (µA)
INTERN
A
L REFERENCE (V)
V
DD
= +21V
V
SS
= –11V
T
A
= 25°C
12355-040
Figure 42. Internal Reference vs. Load Current
AD5761R/AD5721R Data Sheet
Rev. C | Page 18 of 36
2.50000
2.50025
2.50050
2.50075
2.50100
2.50125
2.50150
2.50175
2.50200
–40 –20 0 25 55 85 105 125
V
REFOUT
(V)
TEMPERATURE (°C)
12355-041
Figure 43. Reference Output Voltage vs. Temperature
0
10
20
30
40
50
60
70
NUMBER OF UNITS
TEMPERATURE DRIFT (ppm/°C)
0.412
0.634
0.856
1.078
1.301
1.523
1.745
1.967
2.189
2.412
2.634
2.856
12355-042
Figure 44. Reference Output TC
–15000
–10000
–5000
0
5000
10000
15000
20000
25000
30000
–30 –20 –10 0 10 20 30
OUTPUT VOL
T
AGE DELT
A
(µV)
40
SOURCE/SINK CURRENT (mA)
V
DD
= +21V
V
SS
= –11V
T
A
= 25°C
±10V
+10V
±5V
+5V
–2.5V TO +7.5V
±3V
+16V
+20V
12355-043
Figure 45. Source and Sink Capability of Output Amplifier with
Positive Full Scale Loaded
–20000
–15000
–10000
–5000
0
5000
10000
15000
SOURCE/SINK CURRENT (mA)
OUTPUT VOLTAGE DELT
A
(µV)
–30 –20 –10 0 10 20 30
V
DD
= +21V
V
SS
= –11V
T
A
= 25°C
±10V
+10V
±5V
+5V
–2.5V TO +7.5V
±3V
+16V
+20V
12355-044
Figure 46. Source and Sink Capability of Output Amplifier with
Negative Full Scale Loaded
0
0.0001
0.0002
0.0003
0.0004
0.0005
0.0006
0.0007
0.0008
0.0009
0.0010
012345
SUPPLY CURRENT (A)
LOGIC INPUT VOLTAGE (V)
IDVCC 3V
IDVCC 5V
VDD = +21V
VSS = –11V
TA = 25⁰C
LOAD = 2kΩ || 200pF
INTERNAL REFERENCE
12355-045
Figure 47. Supply Current vs. Logic Input Voltage
12355-046
–6
–4
–2
0
2
4
6
–8.0 –6.0 –4.0 –2.0 0 2.0 4.0 6.0 8.0 10.0 12.0 14.0
V
OUT
(V)
TIME (µs)
SYNC
±5V,
ZERO SCALE TO FULL SCALE
V
DD
= +21V
V
SS
=–11V
T
A
= 25°C
LOAD = 2kΩ||200pF
Figure 48. Full-Scale Settling Time (Rising Voltage Step), ±5 V Range
Data Sheet AD5761R/AD5721R
Rev. C | Page 19 of 36
12355-047
–6
–4
–2
0
2
4
6
–8.0 –6.0 –4.0 –2.0 02.0 4.0 6.0 8.0 10.0 12.0 14.0
V
OUT
(V)
TIME (µs)
VDD =+21V
VSS = –11V
TA= 25°C
LOAD =2kΩ||200pF
SYNC
±5V, FULL SCALE TO ZERO SCALE
Figure 49. Full-Scale Settling Time (Falling Voltage Step), ±5 V Range
12355-048
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
12
–3 –2 –1 01234 5 678 9 10 11 12 13 14 15
TIME (µs)
V
OUT
(V)
SYNC
±10V, ZERO SCALE TO FULL SCALE
V
DD
= +21V
V
SS
=–11V
T
A
= 25°C
LOAD =2kΩ||200pF
Figure 50. Full-Scale Settling Time (Rising Voltage Step), ±10 V Range
12355-049
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
12
–3.0 –1.0 1.0 3.0 5.0 7.0 9.0 11.0 13.0 15.0
TIME (µs)
SYNC
±10V, FULL
SCALE TO ZERO SCALE
V
OUT
(V)
V
DD
= +21V
V
SS
=–11V
T
A
= 25°C
LOAD =2kΩ||200pF
Figure 51. Full-Scale Settling Time (Falling Voltage Step), ±10 V Range
–0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
–2 –1 01234 5
TIME (µs)
VOUT (V)
SYNC
500-CODE STEP, ±5V SPAN
12355-050
VDD = +21V
VSS =–11V
TA = 25°C
LOAD =2kΩ||200pF
Figure 52. 500-Code Step Settling Time, ±5 V Range
–0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.20
–2 –1 012345
TIME (µs)
V
OUT
(V)
V
DD
= +21V
V
SS
= –11V
T
A
= 25°C
LOAD = 2kΩ||200pF
SYNC
500-CODE STEP
, ±10V S
PAN
12355-051
Figure 53. 500-Code Step Settling Time, ±10 V Range
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
12
–5 0 5 10 15 20
TIME (µs)
0nF
1nF
5nF
7nF
10nF
V
OUT
(V)
V
DD
=+21V
V
SS
= –11V
T
A
= 25°C
LOAD = 2kΩ
12355-052
Figure 54. Full-Scale Settling Time at Various Capacitive Loads, ±10 V Range
AD5761R/AD5721R Data Sheet
Rev. C | Page 20 of 36
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
–3 –2 –1 12345678910 11 12 13 14 15
TIME (µs)
0nF
1nF
5nF
7nF
10nF
V
OUT
(V)
V
DD
= +21V
V
SS
= –11V
T
A
= 25⁰C
LOAD = 2kΩ
12355-053
Figure 55. Full-Scale Settling Time at Various Capacitive Loads,
0 V to 5 V Range
–0.010
–0.009
–0.008
–0.007
–0.006
–0.005
–0.004
–0.003
–0.002
–0.001
0
0.001
0.002
0.003
0.004
0.005
00.5 1.0 1.5 2.0 2.5 3.0 3.5
V
OUT
(V)
TIME (µs)
V
DD
= 21V
V
SS
= –11V
LOAD = 2kΩ||200pF
T
A
= 25°C
12355-054
Figure 56. Digital-to-Analog Glitch Energy, 5 V Range
00.5 1.0 1.5 2.0 2.5 3.0 3.5
V
OUT
(V)
TIME (µs)
–0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
V
DD
= 21V
V
SS
= –11V
LOAD = 2kΩ||200pF
T
A
= 25°C
12355-055
Figure 57. Digital-to-Analog Glitch Energy, ±10 V Range
12355-156
2
VDD
20ms/DIV
10V
5V
20mV
10V
VOUT
VSS
VREFIN/VREFOUT
Figure 58. Power-Up Glitch
12355-057
200µs/DIV
5V
5V
1V
5V
SCLK
SYNC
SDI
V
OUT
Figure 59. Software Full Reset Glitch from Full Scale with Output Loaded,
0 V to 5 V Range
12355-058
SCLK
200µs/DIV
5V
5V
500mV
5V SYNC
SDI
VOUT
Figure 60. Software Full Reset Glitch from Midscale with Output Loaded,
5 V Range
Data Sheet AD5761R/AD5721R
Rev. C | Page 21 of 36
12355-059
SCLK
SYNC
SDI
V
OUT
200µs/DIV
5V
5V
200mV
5V
Figure 61. Software Full Reset Glitch from Zero Scale with Output Loaded,
0 V to 5 V Range
12355-060
SCLK
200µs/DIV
5V
5V
2V
5V SYNC
SDI
VOUT
Figure 62. Software Full Reset Glitch from Full Scale with Output Loaded,
±10 V Range
12355-161
SCLK
200µs/DIV
5V
5V
500mV
5V SYNC
SDI
V
OUT
Figure 63. Software Full Reset Glitch from Midscale with Output Loaded,
±10 V Range
12355-162
SCLK
SDI
200µs/DIV
5V
5V
2V
5V SYNC
V
OUT
Figure 64. Software Full Reset Glitch from Zero Scale with Output Loaded,
±10 V Range
12355-263
200µs/DIV
5V
5V
1V
5V
SCLK
SYNC
SDI
V
OUT
Figure 65. Output Range Change Glitch, 0 V to 5 V Range
12355-164
200µs/DIV
5V
5V
200mV
5V
SCLK
SYNC
SDI
V
OUT
Figure 66. Output Range Change Glitch, ±10 V Range
AD5761R/AD5721R Data Sheet
Rev. C | Page 22 of 36
–4
–2
0
2
4
6
8
10
–2.0 –1.5 –1.0 –0.5 00.5 1.0 1.5 2.0
NOISE (µVp-p)
TIME (Seconds)
V
DD
= +21V
V
SS
= –11V
V
REFIN
= 2.5V
T
A
= 25⁰C
NOISE INT REF
NOISE EXT REF
12355-265
Figure 67. Peak-to-Peak Noise (Voltage Output Noise), 0.1 Hz to 10 Hz
Bandwidth
–2.0 –1.5 –1.0 –0.5 00.5 1.0 1.5 2.0
NOISE (µV RMS)
TIME (Seconds)
VDD = +21V
VSS = –11V
VREFIN = 2.5V
TA = 25°C
–30
–20
–10
0
10
20
30 NOISE EXT REF
NOISE INT REF
12355-266
Figure 68. Peak-to-Peak Noise (Voltage Output Noise), 100 kHz Bandwidth
0
200
400
600
800
1000
1200
1400
1600
10 100 1k 10k 100k 1M
NSD (nV/√Hz)
FREQUENCY (Hz)
DAC OUTPUT NSD (nV/√Hz), INTREF, ZS
DAC OUTPUT NSD (nV/√Hz), INTREF, MS
DAC OUTPUT NSD (nV/√Hz), INTREF, FS
VDD = +21V
VSS = –11V
TA = 25°C
12355-163
Figure 69. DAC Output Noise Spectral Density (NSD) vs. Frequency,
±10 V Range
–0.0010
–0.0005
0
0.0005
0.0010
0.0015
24.1
24.1
24.2
24.3
24.4
24.5
24.5
24.6
24.7
24.8
24.9
24.9
25.0
25.1
25.2
25.3
25.3
25.4
25.5
25.6
25.7
25.7
25.8
25.9
DIGITAL FEEDTHROUGH (V p-p)
TIME (µs)
T
A
=25°C
V
DD
=21V
V
SS
= –11V
DV
CC
=5V
2.5V EXT REF
LOAD =2kΩ||200pF
12355-168
Figure 70. Digital Feedthrough
–160
0 2 4 6 8 10 12 14 16 18 20
–140
–120
–100
–80
–60
–40
–20
0
THD (dBV)
FREQUENCY (kHz)
12355-071
Figure 71. Total Harmonic Distortion
Data Sheet AD5761R/AD5721R
Rev. C | Page 23 of 36
TERMINOLOGY
Total Unadjusted Error (TUE)
Total unadjusted error is a measure of the output error taking
all the various errors into account, namely INL error, offset
error, gain error, and output drift over supplies, temperature,
and time. TUE is expressed in % FSR.
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy, or integral nonlinearity, is a
measure of the maximum deviation, in LSB, from a straight line
passing through the endpoints of the DAC transfer function.
A typical INL error vs. DAC code plot is shown in Figure 7.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent codes.
A specified differential nonlinearity of ±1 LSB maximum ensures
monotonicity. The AD5761R/AD5721R are guaranteed monotonic.
A typical DNL error vs. code plot is shown in Figure 11.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5761R/AD5721R
are monotonic over their full operating temperature range.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (straight binary coding) or 0x0000 (twos complement
coding) for the AD5761R/AD5721R.
Bipolar Zero Temperature Coefficient (TC)
Bipolar zero TC is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in µV/°C.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when
0x0000 (straight binary coding) or 0x8000 (twos complement
coding) is loaded to the DAC register. Ideally, the output voltage
is negative full scale. A plot of zero-scale error vs. temperature is
shown in Figure 21.
Zero-Scale Error Temperature Coefficient (TC)
Zero-scale error TC is a measure of the change in zero-scale
error with a change in temperature. It is expressed in µV/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function.
Offset Error Temperature Coefficient (TC)
Offset error TC is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed in % FSR. A plot of gain error vs. temperature is
shown in Figure 24.
Gain Error Temperature Coefficient (TC)
Gain error TC is a measure of the change in gain error with
changes in temperature. It is expressed in ppm FSR/°C.
DC Power Supply Rejection Ratio (DC PSRR)
DC power supply rejection ratio is a measure of the rejection of
the output voltage to dc changes in the power supplies applied
to the DAC. It is measured for a given dc change in power
supply voltage and is expressed in mV / V.
AC Power Supply Rejection Ratio (AC PSRR)
AC power supply rejection ratio is a measure of the rejection of
the output voltage to ac changes in the power supplies applied
to the DAC. It is measured for a given amplitude and frequency
change in power supply voltage and is expressed in decibels.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input
change. Full-scale settling time is shown in Figure 48 to Figure 51.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by 1 LSB at
the major carry transition (see Figure 56 and Figure 57).
Glitch Impulse Peak Amplitude
Glitch impulse peak amplitude is the peak amplitude of the
impulse injected into the analog output when the input code in
the DAC register changes state. It is specified as the amplitude
of the glitch in mV and is measured when the digital input code
is changed by 1 LSB at the major carry transition.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus.
Noise Spectral Density (NSD)
Noise spectral density is a measurement of the internally
generated random noise characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to full scale and
measuring noise at the output. It is measured in nV/√Hz. A plot
of noise spectral density is shown in Figure 69.
AD5761R/AD5721R Data Sheet
Rev. C | Page 24 of 36
Voltage Reference Temperature Coefficient (TC)
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given
temperature range expressed in ppm/°C as follows:
6
_
_
_
10×
×
−
=RangeTempV
VV
TC
NOMREF
MINREF
MAXREF
where:
VREF_MAX is the maximum reference output measured over the
total temperature range.
VREF_MIN is the minimum reference output measured over the
total temperature range.
VREF_NOM is the nominal reference output voltage, 2.5 V.
Temp Range is the specified temperature range, −40°C to
+125°C.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental.
For the AD5761R/AD5721R, it is defined as
1
2
6
2
5
2
4
2
3
2
2
log20)( V
VVVVV
dBTHD ++++
×=
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Data Sheet AD5761R/AD5721R
Rev. C | Page 25 of 36
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5761R/AD5721R are single channel, 16-/12-bit voltage
output DACs. The AD5761R/AD5721R output ranges are
software selectable and can be configured as follows:
Unipolar output voltage: 0 V to 5 V, 0 V to 10 V, 0 V to
16 V, 0 V to 20 V
Bipolar output voltage: −2.5 V to +7.5 V, ±3 V, ±5 V, ±10 V
Data is written to the AD5761R/AD5721R in a 24-bit word
format via a 4-wire, serial peripheral interface (SPI) compatible,
digital interface. The devices also offer an SDO pin to facilitate
daisy-chaining and readback.
TRANSFER FUNCTION
The internal reference is on by default. The input coding to the
DAC can be straight binary or twos complement (bipolar ranges
case only). Therefore, the transfer function is given by
C
D
MVV N
REF
OUT 2
where:
VREF is 2.5 V.
M is the slope for a given output range.
D is the decimal equivalent of the code loaded to the DAC
register as follows:
0 to 4095 for the 12-bit device.
0 to 65,535 for the 16-bit device.
N is the number of bits. N is 12 for the AD5721R and 16 for the
AD5761R.
C is the offset for a given output range.
The values for M and C are as shown in Table 7.
Table 7. M and C Values for Various Output Ranges
Range M C
±10 V 8 4
±5 V 4 2
±3 V 2.4 1.2
−2.5 V to +7.5 V 4 1
0 V to 20 V 8 0
0 V to 16 V 6.4 0
0 V to 10 V 4 0
0 V to 5 V 2 0
DAC ARCHITECTURE
The DAC architecture consists of an R-2R DAC followed by an
output buffer amplifier. Figure 72 shows a block diagram of the
DAC architecture. Note that the reference input is buffered
prior to being applied to the DAC. The AD5761R/AD5721R
offer a 2.5 V, 5 ppm/°C maximum internal reference on chip.
The output voltage range obtained from the configurable output
amplifier is selected by writing to the 3 LSBs (RA[2:0]) in the
control register.
AGND
R- 2R
V
REFIN
AGND
CONFIGURABLE
OUTPUT
AMPLIFIER
OUTPUT
RANGE CONTROL
V
REFIN
/
V
REFOUT
DAC REGISTER V
OUT
12355-061
Figure 72. DAC Architecture
R-2R DAC
The architecture of the AD5761R consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 73. The
6 MSBs of the 16-bit data-word are decoded to drive 63 switches,
E0 to E62, while the remaining 10 bits of the data-word drive
the S0 to S9 switches of a 10-bit voltage mode R-2R ladder
network.
The code loaded into the DAC register determines which arms
of the ladder are switched between VREF and ground (AGND).
The output voltage is taken from the end of the ladder and
amplified afterwards to provide the selected output voltage.
2R
S0
2R 2R
10-BIT R-2R LADDER 6 MSBs DECODED INTO
63 EQUAL SEGMENTS
S1
2R
S9
2R
RRR
E62
2R ...
...
...
... E61
2R
V
OUT
V
REF
AGND
E0
12355-062
Figure 73. DAC Ladder Structure
Internal Reference
The AD5761R/AD5721R feature an on-chip reference. The
on-chip reference is on at power-up, and this reference can be
turned off by setting the software-programmable bit, DB5, in
the control register. Table 12 shows how the state of the bit
corresponds to the mode of operation.
The internal reference is available at the VRFEFIN/VREFOUT pin.
A buffer is required if the reference output is used to drive
external loads. Place a capacitor in the range of 1 nF to 100 nF
between the reference output and DGND to improve the noise
performance.
Reference Buffer
The AD5761R/AD5721R can operate with either an external or
internal reference. The reference input has an input range of 2 V
to 3 V with 2.5 V for specified performance. This input voltage
is then buffered before it is applied to the DAC core.
AD5761R/AD5721R Data Sheet
Rev. C | Page 26 of 36
DAC Output Amplifier
The output amplifier is capable of generating both unipolar and
bipolar output voltages. It is capable of driving a load of 2 kΩ in
parallel with 1 nF to AGND. The source and sink capabilities of
the output amplifier are shown in Figure 45.
SERIAL INTERFACE
The AD5761R/AD5721R 4-wire digital interface (SYNC, SCLK,
SDI, and SDO) is SPI compatible. The write sequence begins
after bringing the SYNC line low, and maintaining this line low
until the complete data-word is loaded from the SDI pin. Data
is loaded in at the SCLK falling edge transition (see Figure 2).
When SYNC is brought high again, the serial data-word is
decoded according to the instructions in Table 10. The
AD5761R/AD5721R contain an SDO pin to allow the user
to daisy-chain multiple devices together or to read back the
contents of the registers.
Standalone Operation
The serial interface works with both a continuous and
noncontinuous serial clock. A continuous SCLK source can
be used only when SYNC is held low for the correct number
of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and SYNC must be taken high
after the final clock to latch the data. The first falling edge of
SYNC starts the write cycle. Exactly 24 falling clock edges must
be applied to SCLK before SYNC is brought high again. If
SYNC is brought high before the 24th falling SCLK edge, the
data written is invalid. If more than 24 falling SCLK edges are
applied before SYNC is brought high, the input data is also
invalid.
The input shift register is updated on the rising edge of SYNC.
For another serial transfer to take place, SYNC must be brought
low again. After the end of the serial data transfer, data is
automatically transferred from the input shift register to the
addressed register. When the write cycle is complete, the output
can be updated by taking LDAC low while SYNC is high.
Readback Operation
The contents of the input, DAC, and control registers can be
read back via the SDO pin. Figure 4 shows how the registers are
decoded. After a register has been addressed for a read, the next
24 clock cycles clock the data out on the SDO pin. The clocks
must be applied while SYNC is low. When SYNC is returned
high, the SDO pin is placed in tristate. For a read of a single
register, the no operation (NOP) function clocks out the data.
Alternatively, if more than one register is to be read, the data of
the first register to be addressed clocks out at the same time that
the second register to be read is being addressed. The SDO pin
must be enabled to complete a readback operation. The SDO pin
is enabled by default.
Daisy-Chain Operation
For systems that contain several devices, use the SDO pin to
daisy chain several devices together. Daisy-chain mode is useful
in system diagnostics and in reducing the number of serial
interface lines. The first falling edge of SYNC starts the write
cycle. SCLK is continuously applied to the input shift register
when SYNC is low. If more than 24 clock pulses are applied, the
data ripples out of the shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge.
By connecting the SDO of the first device to the SDI input of
the next device in the chain, a multidevice interface is constructed.
Each device in the system requires 24 clock pulses. Therefore,
the total number of clock cycles must equal 24 × N, where N is
the total number of AD5761R/AD5721R devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high, which latches the input data in each device in the
daisy chain and prevents any further data from being clocked
into the input shift register.
*
ADDITIONAL PINS OMITTED FOR CLARITY.
CONTROLLER
DATA IN
SDI
SCLK
DATA OUT
SERIAL CLOCK
CONTROL OUT
SDO
SCLK
SDO
SCLK
SDO
SDI
SDI
SYNC
SYNC
SYNC
AD5761R/
AD5721R*
AD5761R/
AD5721R*
AD5761R/
AD5721R*
12355-063
Figure 74. Daisy-Chain Block Diagram
HARDWARE CONTROL PINS
Load DAC Function (LDAC)
After data transfers into the input register of the DAC, there are
two ways to update the DAC register and DAC output. Depend-
ing on the status of both SYNC and LDAC, one of two update
modes is selected: synchronous DAC update or asynchronous
DAC update.
Data Sheet AD5761R/AD5721R
Rev. C | Page 27 of 36
Synchronous DAC Update
In synchronous DAC update mode, LDAC is held low while
data is being clocked into the input shift register. The DAC
output is updated on the rising edge of SYNC.
Asynchronous DAC Update
In asynchronous DAC update mode, LDAC is held high while
data is being clocked into the input shift register. The DAC output
is asynchronously updated by taking LDAC low after SYNC is
taken high. The update then occurs on the falling edge of LDAC.
Reset Function (RESET)
The AD5761R/AD5721R can be reset to their power-on state
by two means: either by asserting the RESET pin or by using the
software full reset registers (see Table 26).
Asynchronous Clear Function (CLEAR)
The CLEAR pin is a falling edge active input that allows the
output to be cleared to a user defined value. The clear code
value is programmed by writing to Bit 10 and Bit 9 in the
control register (see Table 11 and Table 12). Maintain CLEAR
low for the minimum time of 20 ns to complete the operation
(see Figure 2). When the CLEAR signal is returned high, the
output remains at the clear value until a new value is loaded to
the DAC register.
Alert Function (ALERT)
When the ALERT pin is asserted low, a readback from the control
register is required to clarify whether a short-circuit or brownout
condition occurred, depending on the values of Bit 12 and Bit 11,
the SC and BO bits, respectively (see Table 15 and Table 16). If
neither of these conditions occurred, the temperature exceeded
approximately 150°C.
The ALERT pin is low during power-up, a software full reset, or
a hardware reset. After the first write to the control register to
configure the DAC, the ALERT pin is asserted high.
In the event of the die temperature exceeding approximately
150°C, the ALERT pin is low and the value of the ETS bit
determines the state of the digital supply of the device, whether
the internal digital supply is powered on or powered down. If
the ETS bit is set to 0, the internal digital supply is powered on
when the internal die temperature exceeds approximately
150°C. If the ETS bit is set to 1, the internal digital supply is
powered down when the internal die temperature exceeds
approximately 150°C, and the device becomes nonfunctional
(see Table 11 and Table 12).
The AD5761R/AD5721R temperature at power-up must be less
than 150°C for proper operation of the devices.
THERMAL HYSTERESIS
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient to
cold, to hot, and then back to ambient. Thermal hysteresis data
was tested for the AD5761R as shown in Figure 75. It is measured
by sweeping the temperature from ambient to −40°C, then to
125°C, and returning to ambient. The VREF delta is then
measured between the two ambient measurements (shown in
Figure 75).
0
1
2
3
4
5
–120 –100 –80 –60 –40 –20
NUMBER OF HITS
DISTORTION (ppm)
12355-169
Figure 75. Thermal Hysteresis
AD5761R/AD5721R Data Sheet
Rev. C | Page 28 of 36
REGISTER DETAILS
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input,
SCLK, which can operate at rates of up to 50 MHz. The input shift register consists of three don’t care bits, one fixed value bit (DB20 = 0),
four address bits, and a 16-bit or 12-bit data-word as shown in Table 8 and Table 9, respectively.
Table 8. AD5761R 16-Bit Input Shift Register Format
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB[15:0]
X1 X1 X1 0 Register address Register data
1 X is don’t care.
Table 9. AD5721R 12-Bit Input Shift Register Format
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB[15:4] DB[3:0]
X1
X1
X1
0
Register address
Register data
XXXX1
1 X is don’t care.
Table 10. Input Shift Register Commands
Register Address
DB19 DB18 DB17 DB16 Command
0 0 0 0 No operation
0 0 0 1 Write to input register (no update)
0 0 1 0 Update DAC register from input register
0 0 1 1 Write and update DAC register
0 1 0 0 Write to control register
0 1 0 1 No operation
0 1 1 0 No operation
0 1 1 1 Software data reset
1 0 0 0 Reserved
1
0
0
1
Disable daisy-chain functionality
1 0 1 0 Readback input register
1 0 1 1 Readback DAC register
1 1 0 0 Readback control register
1 1 0 1 No operation
1 1 1 0 No operation
1 1 1 1 Software full reset
Data Sheet AD5761R/AD5721R
Rev. C | Page 29 of 36
CONTROL REGISTER
The control register controls the mode of operation of the AD5761R/AD5721R. The control register options are shown in Table 11 and
Table 12.
On power-up, after a full reset, or after a hardware reset, the output of the DAC is clamped to ground through a 1 kΩ resistor and the
output buffer remains in power-down mode. A write to the control register is required to configure the device, remove the clamp to
ground, and power up the output buffer.
When the DAC output range is reconfigured during operation, a software full reset command (see Table 26) must be written to the device
before writing to the control register.
Table 11. Write to Control Register
MSB LSB
DB[23:21] DB20 DB[19:16] DB[15:11] DB[10:9] DB8 DB7 DB6 DB5 DB[4:3] DB[2:0]
Register address Register data
XXX1 0 0100 XXXXX1 CV[1:0] OVR B2C ETS IRO PV[1:0] RA[2:0]
1 X is don’t care.
Table 12. Control Register Functions
Bit Name Description
CV[1:0] CLEAR voltage selection.
00: zero scale
01: midscale
10, 11: full scale
OVR 5% overrange.
0: 5% overrange disabled
1: 5% overrange enabled
B2C Bipolar range.
0: DAC input for bipolar output range is straight binary coded
1: DAC input for bipolar output range is twos complement coded
ETS Thermal shutdown alert. The alert may not work correctly if the device powers on with temperature conditions >150°C
(greater than the maximum rating of the device).
0: internal digital supply does not power down if die temperature exceeds 150°C.
1: internal digital supply powers down if die temperature exceeds 150°C.
IRO Internal reference.
0: internal reference turned off
1: internal reference turned on
PV[1:0] Power up voltage.
00: zero scale
01: midscale
10, 11: full scale
RA[2:0] Output range. Before an output range configuration, the device must be reset.
000: −10 V to +10 V
001: 0 V to +10 V
010: −5 V to +5 V
011: 0 V to 5 V
100: −2.5 V to +7.5 V
101: −3 V to +3 V
110: 0 V to 16 V
111: 0 V to 20 V
AD5761R/AD5721R Data Sheet
Rev. C | Page 30 of 36
Table 13. Bipolar Output Range Possible Codes
Straight Binary Decimal Code Twos Complement
1111 7 0111
1110 6 0110
1101 5 0101
1100 4 0100
1011 3 0011
1010 2 0010
1001 1 0001
1000 0 0000
0111 −1 1111
0110
−2
1110
0101 −3 1101
0100 −4 1100
0011 −5 1011
0010 −6 1010
0001 −7 1001
0000
−8
1000
READBACK CONTROL REGISTER
The readback control register operation provides the contents of the control register by setting the register address to 1100. Table 14
outlines the 24-bit shift register for this command, where the last 16 bits are don’t care bits.
During the next command, the control register contents are shifted out of the SDO pin with the MSB shifted out first. Table 15 outlines
the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out.
Table 14. Readback Control Register, 24-Bit Shift Register to the SDI Pin
MSB LSB
DB[23:21] DB20 DB[19:16] DB[15:0]
Register address Register data
XXX1 0 1100 Don’t care
1 X is don’t care.
Table 15. Readback Control Register, 24-Bit Data Read from the SDO Pin
MSB LSB
DB[23:21] DB20 DB[19:16] DB[15:13] DB12 DB11 DB[10:9] DB8 DB7 DB6 DB5 DB[4:3] DB[2:0]
Register address Register data
XXX1 0 1100 XXXX1 SC BO CV[1:0] OVR B2C ETS IRO PV[1:0] RA[2:0]
1 X is don’t care.
Table 16. Readback Control Register Bit Descriptions
Bit Name Description
SC Short-circuit condition. The SC bit is reset at every control register write.
0: no short-circuit condition detected
1: short-circuit condition detected
BO
Brownout condition. The BO bit is reset at every control register write.
0: no brownout condition detected
1: brownout condition detected
Data Sheet AD5761R/AD5721R
Rev. C | Page 31 of 36
UPDATE DAC REGISTER FROM INPUT REGISTER
The update DAC register function loads the DAC register with the data saved in the input register and updates the DAC output voltage.
This operation is equivalent to a software LDAC. Table 17 outlines how data is written to the DAC register.
Table 17. Update DAC Register from Input Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB[15:0]
Register address Register data
X1 X1 X1 0 0010 Don’t care
1 X is don’t care.
READBACK DAC REGISTER
The readback DAC register operation provides the contents of the DAC register by setting the register address to 1011. Table 18 outlines
the 24-bit shift register for this command. During the next command, the DAC register contents are shifted out of the SDO pin with the
MSB shifted out first. Table 19 outlines the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out.
Table 18. Readback DAC Register, 24-Bit Shift Register to SDI Pin
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB[15:0]
Register address Register data
X1 X1 X1 0 1011 Don’t care
1 X is don’t care.
Table 19. Readback DAC Register, 24-Bit Data Read from SDO Pin
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB[15:0]
Register address Register data
X1 X1 X1 0 1011 Data read from DAC register
1 X is don’t care.
WRITE AND UPDATE DAC REGISTER
The write and update DAC register (Register Address 0011) updates the input register and the DAC register with the entered data-word
from the input shift register, irrespective of the state of LDAC.
Setting the register address to 0001 writes the input register with the data from the input shift register, clocked in MSB first on the SDI pin.
Table 20. Write and Update DAC Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB[15:0]
Register address Register data
X
1
X
1
X
1
0
0001
Data loaded
X1 X1 X1 0 0011 Data loaded
1 X is don’t care.
AD5761R/AD5721R Data Sheet
Rev. C | Page 32 of 36
READBACK INPUT REGISTER
The readback input register operation provides the contents of the input register by setting the register address to 1010. Table 21 outlines
the 24-bit shift register for this command. During the next command, the input register contents are shifted out of the SDO pin with the
MSB shifted out first. Table 22 outlines the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out.
Table 21. Readback Input Register, 24-Bit Shift Register to the SDI Pin
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB[15:0]
Register address Register data
X1 X1 X1 0 1010 Don’t care
1 X is don’t care.
Table 22. Readback Input Register, 24-Bit Data Read from the SDO Pin
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB[15:0]
Register address Register data
X1
X1
X1
0
1010
Data read from input register
1 X is don’t care.
DISABLE DAISY-CHAIN FUNCTIONALITY
The daisy-chain feature can be disabled to save the power consumed by the SDO buffer when this functionality is not required (see Table 23).
When disabled, a readback request is not accepted because the SDO pin remains in tristate.
Table 23. Disable Daisy-Chain Functionality Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB[15:1] DB0
Register address Register data
X1 X1 X1 0 1001 Don’t care DDC
1 X is don’t care.
Table 24. Disable Daisy-Chain Bit Description
Bit Name Description
DDC
DDC decides whether daisy-chain functionality is enabled or disabled for the device. By default, daisy-chain functionality is
enabled.
0: daisy-chain functionality is enabled for the device.
1: daisy-chain functionality is disabled for the device.
SOFTWARE DATA RESET
The AD5761R/AD5721R can be reset via software to zero scale, midscale, or full scale (see Table 25). The value to which the device is
reset is specified by the PV[1:0] bits, which are set in the write to control register command (see Table 11 and Table 12).
Table 25. Software Data Reset Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB[15:0]
Register address
Register data
X1 X1 X1 0 0111 Don’t care
1 X is don’t care.
Data Sheet AD5761R/AD5721R
Rev. C | Page 33 of 36
SOFTWARE FULL RESET
The device can also be reset completely via software (see Table 26). When the register address is set to 1111, the device behaves in a
power-up state, where the output is clamped to AGND and the output buffer is powered down. The user must write to the control register
to configure the device, remove the 1 kΩ resistor clamp to ground, and power up the output buffer.
The software full reset command is also issued when the DAC output range is reconfigured during normal operation.
Table 26. Software Full Reset Register
MSB LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB[15:0]
Register address Register data
X1 X1 X1 0 1111 Don’t care
1 X is don’t care.
NO OPERATION REGISTERS
The no operation registers are ignored and do not vary the state of the device (see Table 27).
Table 27. No Operation Registers
MSB LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB[15:0]
Register address Register data
X1 X1 X1 0 0000/0101/0110/1101/1110 Don’t care
1 X is don’t care.
AD5761R/AD5721R Data Sheet
Rev. C | Page 34 of 36
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
Figure 76 shows the typical operating circuit for the AD5761R/
AD5721R. The only external components needed for this
precision 16-/12-bit DAC are decoupling capacitors on the
supply pins and supply voltage. Because the AD5761R/AD5721R
incorporate a voltage reference and reference buffers, they
eliminate the need for an external bipolar reference and
associated buffers, resulting in overall savings in both cost and
board space.
In Figure 76, VDD is connected to 15 V and VSS is connected to
−15 V, but VDD and VSS can operate with supplies from 4.75 V to
30 V and from −16.5 V to 0 V, respectively.
1
2
3
4
5
6
7
8
V
OUT
–15V
10µF
10µF
100nF
100nF
V
REFIN
+15V
16
15
14
13
12
11
10
9
SDI
DGND
SDO
DV
CC
DNC
SCLK
AD5761R/
AD5721R
SYNC
CLEAR
RESET
LDAC
SDI
SDO
SCLK
SYNC
LDAC
ALERT
AGND
V
OUT
V
SS
V
DD
CLEAR
RESET
ALERT +
100nF
10µF
+5V
12355-064
V
REFIN
/
V
REFOUT
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 76. Typical Operating Circuit
POWER SUPPLY CONSIDERATIONS
The AD5761R/AD5721R must be powered by the following
three supplies to provide any of the eight output voltage ranges
available on the DAC: VDD = 21 V, VSS = −11 V, and DVCC = 5 V.
For applications requiring optimal high power efficiency and
low noise performance, it is recommended to use the ADP5070
switching regulator to convert the 5 V input rail into two
intermediate rails (+23 V and −13 V). These intermediate rails
are then postregulated by very low noise, low dropout (LDO)
regulators (ADP7142 and ADP7182). Figure 77 shows the
recommended method.
ADP7182
LDO –11V: VSS
ADP7142
LDO +5V: DVCC
ADP7142
LDO +21V: VDD
+5V INPUT
+23V
–13V
+5V INPUT
12355-070
ADP5070
DC-TO-DC
SWITCHING
REGULATOR
ADP5070
DC-TO-DC
SWITCHING
REGULATOR
Figure 77. Postregulation by ADP7142 and ADP7182
EVALUATION BOARD
An evaluation board is available for the AD5761R to aid
designers in evaluating the high performance of the device
with minimum effort. The AD5761R evaluation kit includes a
populated and tested AD5761R printed circuit board (PCB).
The evaluation board interfaces to the USB port of a PC. Software
is available with the evaluation board to allow the user to easily
program the AD5761R. The EVAL-AD5761RSDZ user guide
provides full details on the operation of the evaluation board.
Data Sheet AD5761R/AD5721R
Rev. C | Page 35 of 36
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 78. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
0.30
0.23
0.18
1.75
1.60 SQ
1.45
3.10
3.00 SQ
2.90
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
0.50
0.40
0.30
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS MO-220-WEED-6.
PKG-005138
SEATING
PLANE
SIDE VIEW
EXPOSED
PAD
02-23-2017-E
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 79. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
AD5761R/AD5721R Data Sheet
Rev. C | Page 36 of 36
ORDERING GUIDE
Model1, 2
Resolution
(Bits)
Internal
Reference (V)
Temperature
Range
INL
(LSB)
Package
Description
Package
Option
Marking
Code
AD5721RBRUZ 12 2.5 −40°C to +125°C ±0.5 16-Lead TSSOP RU-16
AD5721RBRUZ-RL7 12 2.5 −40°C to +125°C ±0.5 16-Lead TSSOP RU-16
AD5721RBCPZ-RL7 12 2.5 −40°C to +125°C ±0.5 16-Lead LFCSP CP-16-22 DHN
AD5761RARUZ 16 2.5 −40°C to +125°C ±8 16-Lead TSSOP RU-16
AD5761RARUZ-RL7 16 2.5 −40°C to +125°C ±8 16-Lead TSSOP RU-16
AD5761RBRUZ 16 2.5 −40°C to +125°C ±2 16-Lead TSSOP RU-16
AD5761RBRUZ-RL7 16 2.5 −40°C to +125°C ±2 16-Lead TSSOP RU-16
AD5761RACPZ-RL7 16 2.5 −40°C to +125°C ±8 16-Lead LFCSP CP-16-22 DJ5
AD5761RBCPZ-RL7 16 2.5 −40°C to +125°C ±2 16-Lead LFCSP CP-16-22 DJ6
EVAL-AD5761RSDZ Evaluation Board
EVAL-SDP-CB1Z
SDP Controller Board
1 Z = RoHS Compliant Part.
2 The EVAL-AD5761RSDZ can be used to evaluate the AD5721R.
©2014–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12355-0-1/18(C)
