ADF4106BRUZ-REEL - Analog Devices

REV. A

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ADF4106

PLL Frequency Synthesizer

FEATURES

6.0 GHz Bandwidth

2.7 V to 3.3 V Power Supply

Separate Charge Pump Supply (VP) Allows Extended

Tuning Voltage in 3 V Systems

Programmable Dual-Modulus Prescaler

8/9, 16/17, 32/33, 64/65

Programmable Charge Pump Currents

Programmable Antibacklash Pulsewidth

3-Wire Serial Interface

Analog and Digital Lock Detect

Hardware and Software Power-Down Modes

APPLICATIONS

Broadband Wireless Access

Instrumentation

Wireless LANs

Base Stations for Wireless Radio

FUNCTIONAL BLOCK DIAGRAM

14-BIT

R COUNTER

LATCH

FUNCTION

LATCH

AB COUNTER

LATCH

24-BIT INPUT

REF

CLK

DATA

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

REFERENCE

CPGND R

SET

CURRENT

SETTING 2

CURRENT

SETTING 1

CPI3 CPI2 CPI1 CPI6 CPI5 CPI4

LOCK

DETECT

MUXOUT

OUT

HIGH Z

13-BIT

B COUNTER

PRESCALER

P/P + 1

6-BIT

A COUNTER

FROM

FUNCTION

LATCH

LOAD

M3 M2 M1

MUX

N = BP + A

CE AGND DGND

ADF4106

GENERAL DESCRIPTION

The ADF4106 frequency synthesizer can be used to implement

local oscillators in the upconversion and downconversion sections

of wireless receivers and transmitters. It consists of a low noise

digital PFD (phase frequency detector), a precision charge pump,

a programmable reference divider, programmable A and B

counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit)

and B (13-bit) counters, in conjunction with the dual-modulus

prescaler (P/P + 1), implement an N divider (N = BP + A). In

addition, the 14-bit reference counter (R counter) allows selectable

REF

frequencies at the PFD input. A complete PLL (phase-

locked loop) can be implemented if the synthesizer is used with

an external loop filter and VCO (voltage controlled oscillator).

Its very high bandwidth means that frequency doublers can be

eliminated in many high frequency systems, simplifying system

architecture and lowering cost.

REV. A–2–

ADF4106–SPECIFICATIONS

(AVDD = DVDD = 3 V  10%; AVDD ≤ VP ≤ 5.5 V; AGND = DGND = CPGND = 0 V;

RSET = 5.1 k; dBm referred to 50 ; TA = TMIN to TMAX, unless otherwise noted.)

BChips

Parameter B Version

(Typ) Unit Test Conditions/Comments

RF CHARACTERISTICS See Figure 3 for Input Circuit

RF Input Frequency (RF

)

0.5/6.0 0.5/6.0 GHz min/max

RF Input Sensitivity –10/0 –10/0 dBm min/max

Maximum Allowable

Prescaler Output Frequency

300 300 MHz max

REF

CHARACTERISTICS

REF

Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, Use DC-Coupled

Square Wave (0 to V

)

REF

Input Sensitivity

0.8/AV

V p-p min/max AC-Coupled; When DC-Coupled,

0 to V

max (CMOS Compatible)

REF

Input Capacitance 10 10 pF max

REF

Input Current ±100 ±100 µA max

PHASE DETECTOR

Phase Detector Frequency

56 56 MHz max

CHARGE PUMP

Sink/Source Programmable, See Table V

High Value 5 5 mA typ With R

SET

= 5.1 kΩ

Low Value 625 625 µA typ

Absolute Accuracy 2.5 2.5 % typ With R

SET

= 5.1 kΩ

SET

Range 2.7/10 2.7/10 kΩ typ See Table V

Three-State Leakage Current 1 1 nA typ

Sink and Source Current Matching 2 2 % typ 0.5 V ⱕ V

ⱕ V

– 0.5 V

vs. V

1.5 1.5 % typ 0.5 V ⱕ V

ⱕ V

– 0.5 V

vs. Temperature 2 2 % typ V

= V

LOGIC INPUTS

INH

, Input High Voltage 1.4 1.4 V min

INL

, Input Low Voltage 0.6 0.6 V max

INH

INL

, Input Current ±1±1µA max

, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

, Output High Voltage 1.4 1.4 V min Open-Drain Output Chosen 1 kΩ

Pull-up to 1.8 V

, Output High Voltage V

– 0.4 V

– 0.4 V min CMOS Output Chosen

100 100 µA max

, Output Low Voltage 0.4 0.4 V max I

= 500 µA

POWER SUPPLIES

2.7/3.3 2.7/3.3 V min/V max

/5.5 AV

/5.5 V min/V max AV

ⱕ V

ⱕ 5.5 V

DD7

(AI

+ DI

)1513mA max 13 mA typ

0.4 0.4 mA max T

= 25°C

Power-Down Mode

(AI

+ DI

)10 10 µA typ

REV. A

ADF4106

–3–

BChips

Parameter B Version

(Typ) Unit Test Conditions/Comments

NOISE CHARACTERISTICS

ADF4106 Phase Noise Floor

–174 –174 dBc/Hz typ @ 25 kHz PFD Frequency

–166 –166 dBc/Hz typ @ 200 kHz PFD Frequency

–159 –159 dBc/Hz typ @ 1 MHz PFD Frequency

Phase Noise Performance

@ VCO Output

900 MHz Output

–93 –93 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

5800 MHz Output

–74 –74 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

5800 MHz Output

–84 –84 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency

Spurious Signals

900 MHz Output

–90/–92 –90/–92 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

5800 MHz Output

–65/–70 –65/–70 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

5800 MHz Output

–70/–75 –70/–75 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD Frequency

NOTES

Operating temperature range (B Version) is –40°C to +85°C.

The BChip specifications are given as typical values.

Use a square wave for lower frequencies, below the mimimum stated.

The maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency

that is less than this value.

= DV

= 3 V.

Guaranteed by design. Sample tested to ensure compliance.

= 25°C; AV

= DV

= 3 V; P = 16; RF

= 6.0 GHz.

= 25°C; AV

= DV

= 3.3 V; R = 16383; A = 63; B = 891; P = 32; RF

= 6.0 GHz.

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

The phase noise is measured with the EVAL-ADF4106EB1 evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REF

for

the synthesizer (f

REFOUT

= 10 MHz @ 0 dBm).

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset Frequency = 1 kHz; f

= 900 MHz; N = 4500; Loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset Frequency = 1 kHz; f

= 5800 MHz; N = 29000; Loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 1 MHz; Offset Frequency = 1 kHz; f

= 5800 MHz; N = 5800; Loop B/W = 100 kHz.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

(AVDD = DVDD = 3 V  10%; AVDD ≤ VP ≤ 5.5 V; AGND = DGND = CPGND = 0 V; RSET = 5.1 k;

TA = TMIN to TMAX, unless otherwise noted.)

Limit at

MIN

to T

MAX

Parameter (B Version) Unit Test Conditions/Comments

10 ns min DATA to CLOCK Setup Time

10 ns min DATA to CLOCK Hold Time

25 ns min CLOCK High Duration

25 ns min CLOCK Low Duration

10 ns min CLOCK to LE Setup Time

20 ns min LE Pulsewidth

NOTES

Guaranteed by design but not production tested.

Specifications subject to change without notice.

CLOCK

DB23 (MSB) DB22 DB2 DB1 (CONTROL

BIT C2)

DATA

DB0 (LSB)

(CONTROL BIT C1)

Figure 1. Timing Diagram

REV. A–4–

ADF4106

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

ADF4106 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS

1, 2

= 25°C, unless otherwise noted.)

to GND

. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V

to DV

. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V

to AV

. . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V

Digital I/O Voltage to GND . . . . . . . . –0.3 V to V

+ 0.3 V

Analog I/O Voltage to GND . . . . . . . . . . –0.3 V to V

+ 0.3 V

REF

, RF

A, RF

B to GND . . . . . . –0.3 V to V

+ 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C

TSSOP ␪

Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W

ORDERING GUIDE

Model Temperature Range Package Option*

ADF4106BRU –40°C to +85°CRU-16

ADF4106BRU-REEL –40°C to +85°CRU-16

ADF4106BRU-REEL7 –40°C to +85°CRU-16

ADF4106BCP –40°C to +85°CCP-20

ADF4106BCP-REEL –40°C to +85°CCP-20

ADF4106BCP-REEL7 –40°C to +85°CCP-20

EVAL-ADF4106EB1

*RU = Thin Shrink Small Outline Package (TSSOP).

CP = Lead Frame Chip Scale Package (LFCSP).

Contact the factory for chip availability.

Note that aluminum bond wire should not be used with the ADF4106 die.

LFCSP ␪

Thermal Impedance . . . . . . . . . . . . . . . . 122°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

This device is a high performance RF integrated circuit with an ESD rating of

<2 kV, and it is ESD sensitive. Proper precautions should be taken for handling

and assembly.

GND = AGND = DGND = 0 V.

REV. A

ADF4106

–5–

PIN CONFIGURATIONS

TSSOP

TOP VIEW

(Not to Scale)

SET

CPGND

AGND

REF

MUXOUT

DATA

CLK

DGND

ADF4106

LFCSP

15 MUXOUT

14 LE

13 DATA

12 CLK

CPGND 1

AGND 2

AGND 3

20 CP

11 CE

AV DD 6

AV DD 7

REFIN 8

DGND 9

DGND 10

RFINB 4

RFINA 5

19 RSET

18 VP

17 DVDD

16 DVDD

PIN 1

INDICATOR

TOP VIEW

ADF4106

NOTE: TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR)

PIN FUNCTION DESCRIPTIONS

Mnemonic Function

SET

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal

voltage potential at the R

SET

pin is 0.6 V. The relationship between I

and R

SET

CP MAX

SET

=25 5.

So, with R

SET

= 5.1 kΩ, I

CP MAX

= 5 mA.

CP Charge Pump Output. When enabled, this provides ±I

to the external loop filter, which in turn drives the

external VCO.

CPGND Charge Pump Ground. This is the ground return path for the charge pump.

AGND Analog Ground. This is the ground return path of the prescaler.

BComplementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass

capacitor, typically 100 pF. See Figure 3.

AInput to the RF Prescaler. This small signal input is ac-coupled to the external VCO.

Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to this pin. AV

must be the same value as DV

REF

Reference Input. This is a CMOS input with a nominal threshold of V

/2 and a dc equivalent input resistance of

100 kΩ. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

DGND Digital Ground.

CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state

mode. Taking the pin high powers up the device, depending on the status of the power-down bit F2.

CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

DATA Serial Data Input. The serial data is loaded MSB first with the 2 LSB being the control bits. This input is a

high impedance CMOS input.

LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches, the latch being selected using the control bits.

MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be

accessed externally.

Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane

should be placed as close as possible to this pin. DV

must be the same value as AV

Charge Pump Power Supply. This should be greater than or equal to V

. In systems where V

is 3 V, it can be

set to 5 V and used to drive a VCO with a tuning range of up to 5 V.

REV. A–6–

ADF4106–Typical Performance Characteristics

FREQ UNIT – GHz

PARAM TYPE – S

DATA FORMAT – MA

FREQ MAGS11 ANGS11

3.300 0.42777 – 102.748

3.400 0.42859 – 107.167

3.500 0.43365 – 111.883

3.600 0.43849 – 117.548

3.700 0.44475 – 123.856

3.800 0.44800 – 130.399

3.900 0.45223 – 136.744

4.000 0.45555 – 142.766

4.100 0.45313 – 149.269

4.200 0.45622 – 154.884

4.300 0.45555 – 159.680

4.400 0.46108 – 164.916

4.500 0.45325 – 168.452

4.600 0.45054 – 173.462

4.700 0.45200 – 176.697

4.800 0.45043 178.824

4.900 0.45282 174.947

5.000 0.44287 170.237

5.100 0.44909 166.617

5.200 0.44294 162.786

5.300 0.44558 158.766

5.400 0.45417 153.195

5.500 0.46038 147.721

5.600 0.47128 139.760

5.700 0.47439 132.657

5.800 0.48604 125.782

5.900 0.50637 121.110

6.000 0.52172 115.400

FREQ MAGS11 ANGS11

0.500 0.89148 – 17.2820

0.600 0.88133 – 20.6919

0.700 0.87152 – 24.5386

0.800 0.85855 – 27.3228

0.900 0.84911 – 31.0698

1.000 0.83512 – 34.8623

1.100 0.82374 – 38.5574

1.200 0.80871 – 41.9093

1.300 0.79176 – 45.6990

1.400 0.77205 – 49.4185

1.500 0.75696 – 52.8898

1.600 0.74234 – 56.2923

1.700 0.72239 – 60.2584

1.800 0.69419 – 63.1446

1.900 0.67288 – 65.6464

2.000 0.66227 – 68.0742

2.100 0.64758 – 71.3530

2.200 0.62454 – 75.5658

2.300 0.59466 – 79.6404

2.400 0.55932 – 82.8246

2.500 0.52256 – 85.2795

2.600 0.48754 – 85.6298

2.700 0.46411 – 86.1854

2.800 0.45776 – 86.4997

2.900 0.44859 – 88.8080

3.000 0.44588 – 91.9737

3.100 0.43810 – 95.4087

3.200 0.43269 – 99.1282

KEYWORD – R

IMPEDANCE  – 50

TPC 1. S-Parameter Data for the RF Input

RF INPUT FREQUENCY – GHz

–30

OUTPUT POWER – dB

246

–5

–10

–25

–20

–15

VDD = 3V

VP = 3V

TA = +85C

TA = +25C

TA = –40C

TPC 2. Input Sensitivity

FREQUENCY

–60

–2kHz

OUTPUT POWER – dB

–10

–50

–70

–90

–30

–40

–80

–20

2kHz900MHz–1kHz 1kHz

REF LEVEL = –14.3dBm

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 10

–93.0dBc/Hz

–100

TPC 3. Phase Noise (900 MHz, 200 kHz, and 20 kHz)

FREQUENCY OFFSET FROM 900MHz CARRIER

100Hz 1MHz

PHASE NOISE – dBc/Hz

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

10dB/DIV

RL = –40dBc/Hz

RMS NOISE = 0.36

–140

TPC 4. Integrated Phase Noise (900 MHz, 200 kHz,

and 20 kHz)

FREQUENCY

–60

–400kHz

OUTPUT POWER – dB

–10

–50

–70

–90

–30

–40

–80

–20

400kHz900MHz–200kHz 200kHz

REF LEVEL = –14.0dBm

= 3V, V

= 5V

= 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 30

–91.0dBc/Hz

–100

TPC 5. Reference Spurs (900 MHz, 200 kHz, and 20 kHz)

FREQUENCY

–60

–2kHz

OUTPUT POWER – dB

–10

–50

–70

–90

–30

–40

–80

–20

2kHz5800MHz–1kHz 1kHz

REF LEVEL = –10dBm

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 10

–84.0dBc/Hz

–100

TPC 6. Phase Noise (5.8 GHz, 1 MHz, and 100 kHz)

REV. A

ADF4106

–7–

FREQUENCY OFFSET FROM 5800MHz CARRIER

100Hz 1MHz

PHASE NOISE – dBc/Hz

–40

–50

–140

–60

–70

–80

–90

–100

–110

–120

–130

10dB/DIV

= –40dBc/Hz

RMS NOISE = 1.8

TPC 7. Integrated Phase Noise (5.8 GHz, 1 MHz,

and 100 kHz)

–60

–100

–2

OUTPUT POWER – dB

–1 5800 1 2

–10

–50

–70

–90

–30

–40

–80

–20

= 3V, V

= 5V

= 5mA

PDF FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 13 SECONDS

AVERAGES = 1

REF LEVEL = –10.0dBm

–65.0dBc

FREQUENCY – MHz

–66.0dBc

TPC 8. Reference Spurs (5.8 GHz, 1 MHz, and 100 kHz)

TEMPERATURE – C

–60

–70

–100

–40 100–20

PHASE NOISE – dBc/Hz

020406080

–80

–90

= 3V

= 5V

TPC 9. Phase Noise (5.8 GHz, 1 MHz, and 100 kHz)

vs. Temperature

TUNING VOLTAGE – V

–5

–15

–105 051234

–45

–75

–85

–95

–25

–35

–65

–55

FIRST REFERENCE SPUR – dBc

VDD = 3V

VP = 5V

TPC 10. Reference Spurs vs. V

TUNE

(5.8 GHz,

1MHz, and 100 kHz)

PHASE DETECTOR FREQUENCY – Hz

–120

–130

–180

10k 100M100k

OUTPUT POWER – dBc/Hz

1M 10M

–140

–150

–160

–170

VDD = 3V

VP = 5V

TPC 11. Phase Noise (Referred to CP Output) vs.

PFD Frequency

PRESCALER VALUE

8/9 64/6516/17

AIDD – mA

32/33

TPC 12. AI

vs. Prescaler Value

REV. A–8–

ADF4106

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 2. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REF

on power-down.

POWER-DOWN

CONTROL

100k

REF

SW1

SW2

SW3

BUFFER

TO R COUNTER

NC = NO CONNECT

Figure 2. Reference Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 3. It is followed by a

two-stage limiting amplifier to generate the CML clock levels

needed for the prescaler.

500

1.6V

500

AGND

BIAS

GENERATOR

Figure 3. RF Input Stage

PRESCALER OUTPUT FREQUENCY

3.5

3.0

050 300100

– mA

150 200 250

2.0

1.5

1.0

0.5

2.5

= 3V

TPC 13. DI

vs. Prescaler Output Frequency

– V

–6

0 5.00.5

– mA

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

–2

–4

= 5V

= 5mA

TPC 14. Charge Pump Output Characteristics

PRESCALER (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and B

counters, enables the large division ratio, N, to be realized (N =

BP + A). The dual-modulus prescaler, operating at CML levels,

takes the clock from the RF input stage and divides it down to a

manageable frequency for the CMOS A and B counters. The

prescaler is programmable. It can be set in software to 8/9, 16/17,

32/33, or 64/65. It is based on a synchronous 4/5 core. There is

a minimum divide ratio possible for fully contiguous output

frequencies. This minimum is determined by P, the prescaler

value, and is given by (P

– P).

A AND B COUNTERS

The A and B CMOS counters combine with the dual-modulus

prescaler to allow a wide ranging division ratio in the PLL feed-

back counter. The counters are specified to work when the

prescaler output is 300 MHz or less. Thus, with an RF input

frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a

value of 8/9 is not.

Pulse Swallow Function

The A and B counters, in conjunction with the dual-modulus

prescaler, make it possible to generate output frequencies that

are spaced only by the reference frequency divided by R. The

equation for the VCO frequency is as follows:

fPBA

VCO

REFIN

=×

()

[]

VCO

Output frequency of external voltage controlled

oscillator (VCO).

PPreset modulus of dual-modulus prescaler

(8/9, 16/17, and so on).

BPreset divide ratio of binary 13-bit counter

(3 to 8191).

APreset divide ratio of binary 6-bit swallow

counter (0 to 63).

REFIN

External reference frequency oscillator.

REV. A

ADF4106

–9–

PRESCALER

P/P + 1

13-BIT B

COUNTER

LOAD

N = BP + A

FROM RF

INPUT STAGE

TO PFD

MODULUS

CONTROL

N DIVIDER

6-BIT A

COUNTER

Figure 4. A and B Counters

R COUNTER

The 14-bit R counter allows the input reference frequency to be

divided down to produce the reference clock to the phase fre-

quency detector (PFD). Division ratios from 1 to 16,383 are

allowed.

PHASE FREQUENCY DETECTOR AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter (N =

BP + A) and produces an output proportional to the phase and

frequency difference between them. Figure 5 is a simplified

schematic. The PFD includes a programmable delay element

that controls the width of the antibacklash pulse. This pulse

ensures that there is no dead zone in the PFD transfer function

and minimizes phase noise and reference spurs. Two bits in the

reference counter latch, ABP2 and ABP1, control the width of

the pulse. See Table III.

CLR1

CLR2

DOWN

CHARGE

PUMP

ABP2 ABP1

CPGND

R DIVIDER

N DIVIDER

R DIVIDER

N DIVIDER

CP OUTPUT

PROGRAMMABLE

DELAY U3

Figure 5. PFD Simplified Schematic and Timing (In Lock)

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4106 allows the user to access

various internal points on the chip. The state of MUXOUT is

controlled by M3, M2, and M1 in the function latch. Table V

shows the full truth table. Figure 6 shows the MUXOUT section

in block diagram form.

Lock Detect

MUXOUT can be programmed for two types of lock detect:

digital lock detect and analog lock detect.

Digital lock detect is active high. When LDP in the R counter

latch is set to 0, digital lock detect is set high when the phase

error on three consecutive phase detector cycles is less than 15 ns.

With LDP set to 1, five consecutive cycles of less than 15 ns are

required to set the lock detect. It will stay set high until a phase

error of greater than 25 ns is detected on any subsequent PD cycle.

The N-channel open-drain analog lock detect should be operated

with an external pull-up resistor of 10 kΩ nominal. When lock

has been detected, this output will be high with narrow low-

going pulses.

ANALOG LOCK DETECT

MUXOUT

CONTROL

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

MUX

DVDD

DGND

Figure 6. MUXOUT Circuit

INPUT SHIFT REGISTER

The ADF4106 digital section includes a 24-bit input shift register,

a 14-bit R counter, and a 19-bit N counter, comprising a 6-bit A

counter and a 13-bit B counter. Data is clocked into the 24-bit

shift register on each rising edge of CLK. The data is clocked

in MSB first. Data is transferred from the shift register to one

of four latches on the rising edge of LE. The destination latch

is determined by the state of the two control bits (C2, C1) in

the shift register. These are the two LSBs, DB1 and DB0, as

shown in the timing diagram of Figure 1. The truth table for these

bits is shown in Table VI. Table I shows a summary of how

the latches are programmed.

Table I. C2, C1 Truth Table

Control Bits

C2 C1 Data Latch

00R Counter

01N Counter (A and B)

10Function Latch (Including Prescaler)

11Initialization Latch

REV. A–10–

ADF4106

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13

R14

ABP1ABP2T1T2LDP

CONTROL

BITS

14-BIT REFERENCE COUNTER

TEST

MODE BITS

DB21DB22DB23

ANTI-

BACKLASH

WIDTH

REFERENCE COUNTER LATCH

N COUNTER LATCH

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (1)A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6

CONTROL

BITS

6-BIT A COUNTER

13-BIT B COUNTER

DB21

RESERVED

DB22DB23

CP GAIN

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (0)F1PD1M1M2M3F3P1P2 CPI1CPI2CPI5CPI6 TC4PD2 F2

CONTROL

BITS

COUNTER

RESET

POWER-

DOWN 1

MUXOUT

CONTROL

POLARITY

POWER-

DOWN 2

CURRENT

SETTING

PRESCALER

VALUE

TIMER COUNTER

CONTROL

CPI3CPI4

DB21

CURRENT

SETTING

TC3 TC2 TC1

DB22DB23

FASTLOCK

ENABLE

FASTLOCK

MODE

F4F5

FUNCTION LATCH

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (1)

F1PD1M1

M2M3

P1P2 CPI1CPI2

CPI5

CPI6 TC4PD2 F2

CONTROL

BITS

COUNTER

RESET

POWER-

DOWN 1

MUXOUT

CONTROL

POLARITY

POWER-

DOWN 2

CURRENT

SETTING

PRESCALER

VALUE TIMER COUNTER

CONTROL

CPI3

CPI4

DB21

CURRENT

SETTING

TC3 TC2 TC1

DB22DB23

FASTLOCK

ENABLE

FASTLOCK

MODE

INITIALIZATION LATCH

LOCK

DETECT

PRECISION

CP THREE-

STATE

CP THREE-

STATE

RESERVED

Table II. Latch Summary

REV. A

ADF4106

–11–

Table III. Reference Counter Latch Map

LDP OPERATION

0THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15 ns MUST OCCUR BEFORE LOCK DETECT IS SET.

1FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15 ns MUST OCCUR BEFORE LOCK DETECT IS SET.

TEST MODE BITS

SHOULD BE SET

TO 00 FOR NORMAL

OPERATION

ABP2 ABP1 ANTIBACKLASH PULSEWIDTH

002.9 ns

011.3 ns

106.0 ns

112.9 ns

R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO

000.......... 0011

000.......... 0102

000.......... 0113

000.......... 1004

............. ....

111.......... 10016380

111.......... 10116381

111.......... 11016382

111.......... 11116383

= DON’T CARE

BOTH OF THESE BITS

MUST BE SET TO 0 FOR

NORMAL OPERATION

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14

ABP1

ABP2T1T2LDP

CONTROL

BITS

14-BIT REFERENCE COUNTER

TEST

MODE BITS

DB21DB22DB23

ANTI-

BACKLASH

WIDTH

LOCK

DETECT

PRECISION

RESERVED

REV. A–12–

ADF4106

Table IV. AB Counter Latch Map

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (1)

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6

CONTROL

BITS

6-BIT A COUNTER

13-BIT B COUNTER

DB21

RESERVED

DB22DB23

CP GAIN

THESE BITS ARE NOT USED

BY THE DEVICE AND ARE

DON'T CARE BITS.

F4 (FUNCTION LATCH)

FASTLOCK ENABLE CP GAIN OPERATION

00CHARGE PUMP CURRENT SETTING

1 IS PERMANENTLY USED.

01CHARGE PUMP CURRENT SETTING

2 IS PERMANENTLY USED.

10CHARGE PUMP CURRENT SETTING

1IIS PERMANENTLY USED.

11CHARGE PUMP CURRENT IS

SWITCHED TO SETTING 2. THE

TIME SPENT IN SETTING 2 IS

DEPENDENT ON WHICH FASTLOCK

MODE IS USED. SEE FUNCTION

LATCH DESCRIPTION

A COUNTER

A6 A5 .......... A2 A1 DIVIDE RATIO

00.......... 0 0 0

00.......... 0 1 1

00.......... 1 0 2

00.......... 1 1 3

............ . . .

11.......... 0 0 60

11.......... 0 1 61

11.......... 1 0 62

11.......... 1 1 63

N = BP + A; P IS PRESCALER VALUE SET IN THE FUNCTION LATCH.

B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY

ADJACENT VALUES OF (N  FREF), AT THE OUTPUT, NMIN, IS (P

–

P).

X = DON’T CARE

B13 B12 B11 B3 B2 B1 B COUNTER DIVIDE RATIO

00 0.......... 0 0 0 NOT ALLOWED

00 0.......... 0 0 1 NOT ALLOWED

00 0.......... 0 1 0 NOT ALLOWED

00 0.......... 1 1 1 3

.. ........... . . . .

11 1.......... 1 0 0 8188

11 1.......... 1 0 1 8189

11 1.......... 1 1 0 8190

11 1.......... 1 1 1 8191

REV. A

ADF4106

–13–

Table V. Function Latch Map

P2 P1 PRESCALER VALUE

008/9

0116/17

1032/33

1164/65

CE PIN PD2 PD1 MODE

0XXASYNCHRONOUS POWER-DOWN

1X0NORMAL OPERATION

101ASYNCHRONOUS POWER-DOWN

111SYNCHRONOUS POWER-DOWN

CPI6 CPI5 CPI4 ICP (mA)

CPI3 CPI2 CPI1 3 k 5.1 k11 k

0001.06 0.625 0.289

0012.12 1.25 0.580

0103.18 1.875 0.870

0114.24 2.5 1.160

1005.30 3.125 1.450

1016.36 3.75 1.730

1107.42 4.375 2.020

1118.50 5.0 2.320

TIMEOUT

TC4 TC3 TC2 TC1 (PFD CYCLES)

00003

00017

001011

001115

010019

010123

011027

011131

100035

100139

101043

101147

110051

110155

111059

111163

M3 M2 M1

000

001

010

011DVDD

100

101

110

111

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (0)

F1PD1M1

M2M3

P1P2 CPI1CPI2

CPI5

CPI6 TC4PD2 F2

CONTROL

BITS

COUNTER

RESET

POWER-

DOWN 1

MUXOUT

CONTROL

POLARITY

THREE-

STATE

POWER-

DOWN 2

CURRENT

SETTING

PRESCALER

VALUE TIMER COUNTER

CONTROL

CPI3

CPI4

DB21

CURRENT

SETTING

TC3 TC2 TC1

DB22DB23

FASTLOCK

ENABLE

FASTLOCK

MODE

CHARGE PUMP

OUTPUT

NORMAL

THREE-STATE

FASTLOCK MODE

FASTLOCK DISABLED

FASTLOCK MODE 1

FASTLOCK MODE 2

COUNTER

OPERATION

NORMAL

R, A, B COUNTERS

HELD IN RESET

OUTPUT

THREE-STATE OUTPUT

DIGITAL LOCK DETECT

(ACTIVE HIGH)

N DIVIDER OUTPUT

DVDD

R DIVIDER OUTPUT

N-CHANNEL OPEN-DRAIN

LOCK DETECT

SERIAL DATA OUTPUT

DGND

PHASE DETECTOR

POLARITY

NEGATIVE

POSITIVE

REV. A–14–

ADF4106

Table VI. Initialization Latch Map

P2 P1 PRESCALER VALUE

008/9

0116/17

1032/33

1164/65

CE PIN PD2 PD1 MODE

0XXASYNCHRONOUS POWER-DOWN

1X0NORMAL OPERATION

101ASYNCHRONOUS POWER-DOWN

111SYNCHRONOUS POWER-DOWN

CPI6 CPI5 CPI4 I

(mA)

CPI3 CPI2 CPI1 3 k 5.1 k11 k

0001.06 0.625 0.289

0012.12 1.25 0.580

0103.18 1.875 0.870

0114.24 2.5 1.160

1005.30 3.125 1.450

1016.36 3.75 1.730

1107.42 4.375 2.020

1118.50 5.0 2.320

TIMEOUT

TC4 TC3 TC2 TC1 (PFD CYCLES)

00003

00017

001011

001115

010019

010123

011027

011131

100035

100139

101043

101147

110051

110155

111059

111163

M3 M2 M1

000

001

010

011DVDD

100

101

110

111

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (1)

F1PD1M1

M2M3

P1P2 CPI1CPI2

CPI5

CPI6 TC4PD2 F2

CONTROL

BITS

COUNTER

RESET

POWER-

DOWN 1

MUXOUT

CONTROL

POLARITY

THREE-

STATE

POWER-

DOWN 2

CURRENT

SETTING

PRESCALER

VALUE TIMER COUNTER

CONTROL

CPI3

CPI4

DB21

CURRENT

SETTING

TC3 TC2 TC1

DB22DB23

FASTLOCK

ENABLE

FASTLOCK

MODE

CHARGE PUMP

OUTPUT

NORMAL

THREE-STATE

FASTLOCK MODE

FASTLOCK DISABLED

FASTLOCK MODE 1

FASTLOCK MODE 2

COUNTER

OPERATION

NORMAL

R, A, B COUNTERS

HELD IN RESET

OUTPUT

THREE-STATE OUTPUT

DIGITAL LOCK DETECT

(ACTIVE HIGH)

N DIVIDER OUTPUT

R DIVIDER OUTPUT

N-CHANNEL OPEN-DRAIN

LOCK DETECT

SERIAL DATA OUTPUT

DGND

PHASE DETECTOR

POLARITY

NEGATIVE

POSITIVE

REV. A

ADF4106

–15–

FUNCTION LATCH

With C2, C1 set to 1, 0, the on-chip function latch will be

programmed. Table V shows the input data format for program-

ming the function latch.

Counter Reset

DB2 (F1) is the counter reset bit. When this is 1, the R counter

and the A, B counters are reset. For normal operation, this bit

should be 0. Upon power-up, the F1 bit needs to be disabled (set to 0).

The N counter then resumes counting in close alignment with the R

counter. (The maximum error is one prescaler cycle.)

Power-Down

DB3 (PD1) and DB21 (PD2) on the ADF4106 provide program-

mable power-down modes. They are enabled by the CE pin. When

the CE pin is low, the device is immediately disabled regardless of

the states of PD2, PD1. In the programmed asynchronous power-

down, the device powers down immediately after latching a 1 into

bit PD1, with the condition that PD2 has been loaded with a 0. In

the programmed synchronous power-down, the device power-

down is gated by the charge pump to prevent unwanted frequency

jumps. Once the power-down is enabled by writing a 1 into bit

PD1 (on condition that a 1 has also been loaded to PD2), the

device will go into power-down on the occurrence of the next

charge pump event. When a power-down is activated (either

synchronous or asynchronous mode including CE pin-activated

power-down), the following events occur:

•All active dc current paths are removed.

•The R, N, and timeout counters are forced to their load

state conditions.

•The charge pump is forced into three-state mode.

•The digital lock detect circuitry is reset.

•The RF

input is debiased.

•The reference input buffer circuitry is disabled.

•The input register remains active and capable of loading

and latching data.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1 on

the ADF4106. Table V shows the truth table.

Fastlock Enable Bit

DB9 of the function latch is the fastlock enable bit. Only when

this is 1 is fastlock enabled.

Fastlock Mode Bit

DB10 of the function latch is the fastlock mode bit. When fastlock

is enabled, this bit determines which fastlock mode is used. If

the fastlock mode bit is 0, Fastlock Mode 1 is selected, and if

the fastlock mode bit is 1, Fastlock Mode 2 is selected.

Fastlock Mode 1

The charge pump current is switched to the contents of Current

Setting 2. The device enters fastlock by having a 1 written to the

CP gain bit in the AB counter latch. The device exits fastlock by

having a 0 written to the CP gain bit in the AB counter latch.

Fastlock Mode 2

The charge pump current is switched to the contents of Current

Setting 2. The device enters fastlock by having a 1 written to the

CP gain bit in the AB counter latch. The device exits fastlock

under the control of the timer counter. After the timeout period

determined by the value in TC4 through TC1, the CP gain bit in

the AB counter latch is automatically reset to 0 and the device

reverts to normal mode instead of fastlock. See Table V for the

timeout periods.

Timer Counter Control

The user has the option of programming two charge pump

currents. The intent is that the Current Setting 1 is used when the

RF output is stable and the system is in a static state. Current

Setting 2 is meant to be used when the system is dynamic and in a

state of change (e.g., when a new output frequency is pro-

grammed). The normal sequence of events is as follows.

Users initially decide what the preferred charge pump currents

will be. For example, they may choose 2.5 mA as Current

Setting 1 and 5 mA as Current Setting 2. At the same time, they

must also decide how long they want the secondary current to stay

active before reverting to the primary current. This is controlled

by the timer counter control bits DB14 to DB11 (TC4 through

TC1) in the function latch. The truth table is provided in Table V.

When users want to program a new output frequency, they can

simply program the AB counter latch with new values for A and B.

At the same time, they can set the CP gain bit to a 1, which sets

the charge pump with the value in CPI6 through CPI4 for a period

of time determined by TC4 through TC1. When this time is up,

the charge pump current reverts to the value set by CPI3 through

CPI1. At the same time, the CP Gain bit in the AB counter latch

is reset to 0 and is ready for the next time the user wants to change

the frequency.

Note that there is an enable feature on the timer counter. It is

enabled when Fastlock Mode 2 is chosen when the fastlock mode

bit (DB10) in the function latch is set to 1.

Charge Pump Currents

CPI3, CPI2, and CPI1 program Current Setting 1 for the charge

pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the

charge pump. The truth table is in Table V.

Prescaler Value

P2 and P1 in the function latch set the prescaler values. The

prescaler value should be chosen so that the prescaler output

frequency is always less than or equal to 300 MHz. Thus, with

an RF frequency of 4 GHz, a prescaler value of 16/17 is valid,

but a value of 8/9 is not.

PD Polarity

This bit sets the phase detector polarity bit. See Table V.

CP Three-State

This bit controls the CP output pin. With the bit set high, the

CP output is put into three-state. With the bit set low, the CP

output is enabled.

REV. A–16–

ADF4106

INITIALIZATION LATCH

When C2, C1 = 1, 1, the initialization latch is programmed. This is

essentially the same as the function latch (programmed when C2,

C1 = 1, 0).

However, when the initialization latch is programmed, there is

an additional internal reset pulse applied to the R and AB

counters. This pulse ensures that the AB counter is at the load

point when the AB counter data is latched, and the device will

begin counting in close phase alignment.

If the latch is programmed for synchronous power-down (CE

pin is high; PD1 bit is high; PD2 bit is low), the internal pulse

also triggers this power-down. The prescaler reference and the

oscillator input buffer are unaffected by the internal reset pulse,

so close phase alignment is maintained when counting resumes.

When the first AB counter data is latched after initialization, the

internal reset pulse is again activated. However, subsequent AB

counter loads will not trigger the internal reset pulse.

DEVICE PROGRAMMING AFTER INITIAL POWER-UP

After the device is initially powered up, there are three ways to

program it.

Initialization Latch Method

•Apply V

•Program the initialization latch (11 in 2 LSB of input

word). Make sure that F1 bit is programmed to 0.

•Do a function latch load (10 in 2 LSB of the control

word), making sure that the F1 bit is programmed to a 0.

•Do an R load (00 in 2 LSB).

•Do an AB load (01 in 2 LSB).

When the initialization latch is loaded, the following occurs:

1. The function latch contents are loaded.

2. An internal pulse resets the R, A, B, and timeout counters

to load state conditions and three-states the charge pump.

Note that the prescaler band gap reference and the oscilla-

tor input buffer are unaffected by the internal reset pulse,

allowing close phase alignment when counting resumes.

3. Latching the first AB counter data after the initialization

word will activate the same internal reset pulse. Successive

AB loads will not trigger the internal reset pulse unless

there is another initialization.

CE Pin Method

•Apply V

•Bring CE low to put the device into power-down. This is an

asynchronous power-down (it happens immediately).

•Program the function latch (10).

•Program the R counter latch (00).

•Program the AB counter latch (01).

•Bring CE high to take the device out of power-down.

The R and AB counters will then resume counting in close

alignment. Note that after CE goes high, a duration of 1 µs may

be required for the prescaler band gap voltage and oscillator

input buffer bias to reach steady state.

CE can be used to power the device up and down to check for

channel activity. The input register does not need to be repro-

grammed each time the device is disabled and enabled as long as it

has been programmed at least once after V

was initially applied.

Counter Reset Method

•Apply V

•Do a function latch load (10 in 2 LSB). As part of

this, load 1 to the F1 bit. This enables the counter reset.

•Do an R counter load (00 in 2 LSB).

•Do an AB counter load (01 in 2 LSB).

•Do a function latch load (10 in 2 LSB). As part of

this, load 0 to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the initial-

ization method. It offers direct control over the internal reset.

Note that counter reset holds the counters at load point and

three-states the charge pump but does not trigger synchronous

power-down.

APPLICATION

Local Oscillator for LMDS Base Station Transmitter

Figure 7 shows the ADF4106 being used with a VCO to pro-

duce the LO for an LMDS base station operation in the

5.4 GHz to 5.8 GHz band.

The reference input signal is applied to the circuit at FREF

and, in this case, is terminated in 50 Ω. A typical base station

system would have either a TCXO or an OCXO driving the

reference input without any 50 Ω termination.

To have a channel spacing of 1 MHz at the output, the 10 MHz

reference input must be divided by 10, using the on-chip refer-

ence divider of the ADF4106.

The charge pump output of the ADF4106 (Pin 2) drives the

loop filter. In calculating the loop filter component values, a

number of items need to be considered. In this example, the

loop filter was designed so that the overall phase margin for the

system would be 45 degrees. Other PLL system specifications

are given below:

= 2.5 mA

= 80 MHz/V

Loop Bandwidth = 50 kHz

REF

= 1 MHz

N = 5800

Extra Reference Spur Attenuation = 10 dB

All of these specifications are needed and used to come up with

the loop filter component values shown in Figure 7.

Figure 7 gives a typical phase noise performance of –83 dBc/Hz

at 1 kHz offset from the carrier. Spurs are better than –62 dBc.

The loop filter output drives the VCO, which, in turn, is fed

back to the RF input of the PLL synthesizer. It also drives the

RF output terminal. A T-circuit configuration provides 50 Ω

matching between the VCO output, the RF output, and the

terminal of the synthesizer. Note that the ADF4106 RF

input looks like 50 Ω at 5.8 GHz, so no terminating resistor is

needed. When operating at lower frequencies, however, this is

not the case.

In a PLL system, it is important to know when the system is

locked. In Figure 7, this is accomplished by using the MUXOUT

signal from the synthesizer. The MUXOUT pin can be pro-

grammed to monitor various internal signals in the synthesizer.

One of these is the LD or (lock detect) signal.

REV. A

ADF4106

–17–

Figure 7. Local Oscillator for LMDS Station

INTERFACING

The ADF4106 has a simple SPI

compatible serial interface for

writing to the device. CLK, DATA, and LE control the data

transfer. When LE (latch enable) goes high, the 24 bits that

have been clocked into the input register on each rising edge of

SCLK get transferred to the appropriate latch. See Figure 1 for

the timing diagram and Table I for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

833 kHz or one update every 1.2 µs. This is certainly more than

adequate for systems that have typical lock times in hundreds of

microseconds.

ADuC812 Interface

Figure 8 shows the interface between the ADF4106 and the

ADuC812 MicroConverter

. Since the ADuC812 is based on

an 8051 core, this interface can be used with any 8051 based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4106 needs a

24-bit word. This is accomplished by writing three 8-bit bytes

from the MicroConverter to the device. When the third byte has

been written, the LE input should be brought high to complete

the transfer.

On first application of power to the ADF4106, three writes are

needed (one to the R counter latch, one to the N counter latch,

and one to the function latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control

power-down (CE input) and to detect lock (MUXOUT config-

ured as lock detect and polled by the port input).

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed is 166 kHz.

ADuC812 ADF4106

CLK

DATA

MUXOUT

(LOCK DETECT)

SCLOCK

MOSI

I/O PORTS

Figure 8. ADuC812 to ADF4106 Interface

ADF4106

V940ME03

FREF

OUT

CLK

DATA

SPI COMPATIBLE SERIAL BUS

1000pF 1000pF

REF

NOTE

DECOUPLING CAPACITORS (0.1



F/10pF) ON AV

, DV

OF THE ADF4106 AND ON V

OF THE V940ME03 HAVE

BEEN OMITTED FROM THE DIAGRAM TO AID

CLARITY.

100pF

MUXOUT LOCK

DETECT

CPGND

AGND

DGND

100pF

1.5nF

20pF

100pF

1, 3, 4, 5, 7, 8,

9, 11, 12, 13

SET

5.1k

51

6.2k

4.3k

100pF

18

REV. A–18–

ADF4106

ADSP-2181 Interface

Figure 9 shows the interface between the ADF4106 and the

ADSP-21xx digital signal processor. The ADF4106 needs a 24-bit

serial word for each latch write. The easiest way to accomplish

this using the ADSP-21xx family is to use the autobuffered

transmit mode of operation with alternate framing. This provides

a means for transmitting an entire block of serial data before an

interrupt is generated. Set up the word length for eight bits and use

three memory locations for each 24-bit word. To program each

24-bit latch, store the three 8-bit bytes, enable the autobuffered

mode, and then write to the transmit register of the DSP. This

last operation initiates the autobuffer transfer.

ADSP-21xx ADF4106

CLK

DATA

MUXOUT

(LOCK DETECT)

SCLOCK

MOSI

I/O FLAGS

TFS

Figure 9. ADSP-21xx to ADF4106 Interface

REV. A

ADF4106

–19–

OUTLINE DIMENSIONS

16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

16 9

PIN 1

SEATING

PLANE

8

0

4.50

4.40

4.30

6.40

BSC

5.10

5.00

4.90

0.65

BSC

0.15

0.05

1.20

MAX

0.20

0.09 0.75

0.60

0.45

0.30

0.19

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MS-153AB

20-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-20)

Dimensions shown in millimeters

BOTTOM

VIEW

2.25

2.10 SQ

1.95

0.75

0.55

0.35

0.30

0.23

0.18

0.50

BSC

12 MAX

0.20

REF

0.80 MAX

0.65 NOM

0.05

0.02

0.00

1.00

0.90

0.80

SEATING

PLANE

PIN 1

INDICATOR

TOP

VIEW

3.75

BSC SQ

4.0

BSC SQ

COPLANARITY

0.08

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

0.60

MAX

0.60

MAX

REV. A

C02720–0–5/03(A)

–20–

ADF4106

Revision History

Location Page

5/03—Data Sheet changed from REV. 0 to REV. A.

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to TPC 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Update OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19