ADV MICRO PLA/PLE/ARRAYS Eee COML MIL PAL20R8 Family 24-pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS @ As fast as 7.5 ns maximum propagation delay Popular 24-pin architectures: 20L8, 20R8, 20R6, 20R4 @ Programmable replacement for high-speed TTL logic @ Power-up reset for initlallzation 28E D GM 0257526 O029443 3 mMAND2 ci Advanced _ Micro Devices T-46-19-13 B Easy design with PALASM software Programmable on standard PAL device programmers BH 24-pin SKINNYDIP and 28-pin PLCC . packages save space GENERAL DESCRIPTION The PAL20R8 Family (PAL20L8, PAL20R8, PAL20R6, PAL20R4) is AMD's standard 24-pin PAL device family. The devices provide user-programmable logic for re- placing conventional SSI/MS!I gates and flip-flops at a reduced chip count. The family allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections be- tween gates, which previously required time-consuming layout, are lifted from the PC board and placed on sili- con, where they can be easily modified during prototyp- ing or production. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is @ programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. In addition, the PAL device provides the following op- tions: Variable input/output pin ratio Programmable three-state outputs ~ Registers with feedback Product terms with all connections opened assume the logical HiGH state; product terms connected to both true and complement of any single input assume the logical LOW state. Registers consist of D-type flip-flops that are loaded on the LOW-to-HIGH transition of the clock. Un- used input pins should be tied to Voc or GND. The entire PAL device family is supported by the PALASM software package. The PAL family is pro- grammed on conventional PAL device programmers with appropriate personality and socket adapter-mod- ules. See the Programmer Reference Guide for ap- proved programmers. Once the PAL device is pro- grammed and verified an additional connection may be opened to prevent pattern readout. This feature secures proprietary circuits. PRODUCT SELECTOR GUIDE DEDICATED PRODUCT TERMS/ DEVICE INPUTS OUTPUTS OUTPUT FEEDBACK ENABLE PAL20L8 14 6 comb. 7 VO prog. 2 comb. 7 = prog. PAL20R8 12 8 reg. 8 reg. pin PAL20R6 12 6 reg. 8 reg. pin 2 comb. 7 li prog. PAL20R4 12 4 reg. 8 reg. pin 4 comb. 7 lA prog. PAL, PALASM, and SKINNYDIP are registered trademarks of Advanced Micro Devices. Publication # 10294 Rev. B Amendment 0 This part is covered by various U.S. and lorsign patants owned by Advanced Micro Devices, issue Date: January 1999 2-107ADV MICRO PLA/PLE/ARRAYS 28 D @M@ 0257526 oo2944u4 5 mMAND2 PERFORMANCE OPTIONS (Commercial) 35 | A-2 (ten, NS) 15 B 10 -10 7.6 -7 105 | 210 Power (lec, mA} Note: For low power and high speed, the EE CMOS PALCE20V8 can diractly replace tha PAL20R8 Family. OPERATING RANGES Commercial Milltary -7 -12 -10 -15 B (15 ns) B (20 ns) B-2 (25 ns) A (25 ns) A (30 ns) A-2 (35 ns) A-2 (50 ns} 2-108 PAL20R8 FamilyADV MICRO PLA/PLE/ARRAYS ese D 0257526 OOed44s 7 MBANDe BLOCK DIAGRAMS PAL20L8 T-46-19-13 INPUTS PROGRAMMABLE AND ARRAY (40 X 64) : | PAL20R8 INPUTS 12350-001A a i za 12 <pa8 PROGRAMMABLE ANO ARRAY {40 X 64) Lt; de He of oC} 2 Lea +2 =} He vane = an = Ho ofc a od rane > Or db Ch a de oct} o Cr oC} Oy Q, 4 12350-002A, PAL20R8 Family 2-109ADV MICRO PLA/PLE/ARRAYS CSE D BM 02575e2b 0029446 41 BAND? BLOCK DIAGRAMS PAL20R6 clk INPUTS OE PROGRAMMABLE AND ARRAY (40 X 64) Y Bi de tH] 2 KY oh fe g L Pr ge Lis, + Ho of CH | o dt THe 2 oC] og o<}< oC}h< 12350-003A las qe cLK INPUTS QE | } V PROGRAMMABLE AND ARRAY (40 X 64) wo tig 12350-0044 2-110 PAL20R8 FamilyADV MICRO PLA/PLE/ARRAYS CSE D Bw O2c575eb O0CI44? O BAAMD2 CONNECTION DIAGRAMS T-46-1 9-] 3 . Top View SKINNYDIP/FLATPACK PLCC/LCC a, JEOEC: Applles to -7(-12 mil), -10{-15 mh, (NOTE 1) [_] 1+ 241_] Veo B-2 Series Only ', CI 2 23 ma he 3 1,((}3 22 [_] {NOTE 10) 1,04 21 [__] (NOTE 9} ',.Cjs 20 |] (NOTE 8) i, 6 19 [_] (NOTE 7) 25 |) nore 9) 1,Cl7 1a |__] {NOTE 6) ai] WOTE A) 1,[]3 17 [__] {NOTE 5) zs} ore Lys 8 LT} NOTE 21[_] sore 1, ]}it0 15 [_} (NOTE 3) oo woes) eC] wih, _ 40[] (notes) eno [__| 12 13 [_] (NOTE 2) 12380-005A 12350-006A = = us # onre $ 22 Note | 20L8 20R8 20R6 20R4 | Lut 1 lo CLK CLK CLK no(c]s . 26 |} motes) = == == aL_Js 24] note 8) 2 his OE OE OE wi? af] wore 3 O1 Or VO, er ey_|e za] Wore &) sD Te 2iL_] {kore 5) 4 Oo Oo Os /O2 HCC] 20 __] (NOTE 4) ] ro 5 VO3 Os Qs O3 NG 14 . . % ae 6 | Ws Os Os Ox = = 3 us z= u 7 WOs Os Os Os 2 2 8 Os Os Os Os Loc Applies to B, A, A-2 Series Only 9 VO7 O7 O7 VO7 _ 10 Os Os Vs Oe ; Ba we zMMris F Ig esl wo Ng 24 | (NOTE 9} PIN DESIGNATIONS Ig 2a| (OTE ay CLK Clock 's (NOTE 7} GND Ground "7 - at] (NOTES) { input 'p 20] (NOTES) VO Input/Output NG 19} (NOTE 4) NC No Connect 3 1s 17 oO] Output 2 gaF a 2 OE Output Enable 2 2 Vec Supply Voltage Note: Pin 1 is marked for orientation. PAL20R8 Family - 2-411ADV MICRO PLA/PLE/ARRAYS 28 D MM@ O25752b OO29448 2 EMAND2 ORDERING INFORMATION . Commercial Products (AMD Marking Only) T~46-]9-73 AMD programmable logic products for commercial applications are available with several ordaring options. The order number (Valid Combination) is formed by a combination of: Family Type Number of Array Inputs Output Type Number of Outputs Speed Packaga Type Operating Conditions Optional Processing yargange PAL 20 R8-7PC a, FAMILY TYPE dt PAL = Programmable Array Logic b. NUMBER OF h. OPTIONAL PROCESSING ARRAY INPUTS Blank = Standard Processing c. QUTPUT TYPE g. OPERATING CONDITIONS R = Registered C = Commercial (0C to +75C) L = Active-Low Combinatorial d. NUMBER OF OUTPUTS e. SPEED 7 = 7.508 tpo -10 = 10nstpp f. PACKAGE TYPE P = 24-Pin 300-Mil Plastic SKINNYDIP (PD3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028) D = 24-Pin 300-Mil Ceramic SKINNYDIP (CD3024) ; Valld Combinations Vatld Combinations The Valid Combinations table lists configurations PAL20L8 planned to be supported in volume for this device. Consult the local AMD sales office ta cantirm PAL20R8 availability of specific valid combinations, and to -7, -10 PC, JC, DC check on newly released combinations. PAL20R6 ; PAL20R4 Note: Marked with AMD logo. 2-112 PAL20R8 FamilyADV MICRO PLA/PLE/ARRAYS 286 D mM 0257526 0029445 4 BMAMDZ _ ORDERING INFORMATION F-a6-19-13. Commercial Products (MMI Marking Only) AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: Family Type Number of Array Inputs Output Type Number of Outputs Speed Power Operating Conditions Package Type Optional Processing Fare ap ep PAL 20 R88 -2 CNS a. FAMILY TYPE PAL = Programmable Array Logic b. NUMBER OF ARRAY INPUTS i. OPTIONAL PROCESSING Blank = Standard Processing h, PACKAGE TYPE NS = 24-Pin 300-Mil Plastic SKINNYDIP (PD3024) c, OUTPUT TYPE FN = 28-Pin Plastic Leaded R = Registered Chip Carrier (PL 028), L = Active-Low Combinatorial JEDEC pinout NL = 28-Pin Plastic Leaded d. NUMBER OF OUTPUTS Chip Carrier (PL028), e. SPEED nonJEDEG pinout B = Very High Speed (15-25 ns tpp) WS = SKINNYDIP (CDSCoay" A = High speed (25-35 ns tpp) _. g. OPERATING CONDITIONS f. POWER C = Commercial (0C ta +75C) Blank = Full Power (210 mA Icc) -2 = Half Power (105 mA lec) Valid Combinations Valid Combinations The Valid Combinations table lists configurations . planned to be supported in volume for this davice. PAL20L8, B-2 CNS, CFN, CJS Consult the local AMD sales office to confirm PAL20R8, availability of specific valid combinations, and to check on newly released combinations. PAL20R6, B, A, CNS, CNL, CJS PAL20R4 A-2 Note: Marked with MMI logo. PAL20R8 Family 2-113ADV MICRO PLA/PLE/ARRAYS ede Dp ORDERING INFORMATION APL Products (AMD Marking Only) MA 0257526 0029450 O mMAND2 AMD programmable logic products for Aerospace and Defense applications are available with several ordering op- tions. APL (Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of: yFaspaogp Family Type Number of Array Inputs Output Type Number of Outputs Speed Davice Class Package Type Lead Finish PAL 20 R 8-12/B LA a, FAMILY TYPE PAL = Programmable Array Logic b. NUMBER OF ARRAY INPUTS c. OUTPUT TYPE R = Ragistered L = Active-Low Combinatorial d. NUMBER OF OUTPUTS 6. SPEED h. LEAD FINISH A = Hot Solder Dip PACKAGE TYPE L. = 24-Pin 300-Mil Ceramic SKINNYDIP (CD3024) 3 = 28-Pin Ceramic Leadless Chip Carrier (CL 028) -12 = 12nstpo 15 = 15nstpp f. DEVICE CLASS B= Class B Valid Combinations PAL20L8 PAL20R8 | -12, PAL20oR6 | -15 PAL20R4 /BLA, /B3A Group A Tests Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume forthis device, . Consult the focal AMD sales office to confirm availability of specific valid combinations, to check on newly relaased .combinations, and to obtain additional data on AMD's standard military. grade products. Note: Marked with AMD logo. Group A Tasts consist of Subgroups: 1, 2, 3, 7, 8,9, 10, 11. Military Burn-In Military burn-in is in accordance with the current revision of MIL-STD-883, Test Methods 101 5, Conditions A through E. Test conditions are selected at AMD's option. 2-114 PAL20R8 FamilyADV MICRO PLA/PLE/ARRAYS 28 D M@ 0257526 0029451) 2 BMAMD2 ORDERING INFORMATION aoe APL Products (MMI Marking Only) T-46-19-1 AMD programmabte logic products for Aerospace and Defense applications are available with several ordering options. APL (Approved Products List} products are fully compliant with MIL-STD-883 requirements. The order number {Valid Combination) is formed by a combination of: Family Type Number of Array Inputs Qutput Type Number of Outputs Speed Power Operating Conditions Package Type Optional Processing mya rsa re PAL 20 R8 A -2 M JS/883B a, FAMILY TYPE PAL = Programmable Array Logic b. NUMBER OF |. OPTIONAL PROCESSING ARRAY INPUTS /883B = MIL-STD-883, Class B c. OUTPUT TYPE h. PACKAGE TYPE (Per 09-000) R = Registered JS = 24-Pin 300-Mil Ceramic L = Active-Low Combinatorial Ww SON Cons (on 024) d. NUMBER OF OUTPUTS _ (CFLO24) apa L = 28-Pin Ceramic Leadiess 8. SPEED Chip Cartier (GL028) B = Vary High Speed (20 ns tpp) . A = High speed (30-50 ns tpp) _g. OPERATING CONDITIONS M = Military f. POWER Blank = Full Power (210 mA fcc) -2 = Half Power (105 mA Icc) Valid Combinations Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. PALZOL8 MJS/8838, Consult the local AMD sales office to confirm PAL20R8 B, A, MW/8838, availability of specific valid combinations, and to check on newly released combinations, PAL20R6 A-2 ML/8838 PAL20R4 Note: Marked with MMI logo. Group A Tests Group A Tests consist of Subgroups: 1, 2, 3, 7, 8,9, 10, 11. Military Burn-in Military burn-in is in accordance with the current revision of MIL-STD-883, Test Methods 1015, Conditions A through E. Tast conditions ara selected at AMD's option. PAL20R8 Family 2-115ADV MICRO PLA/PLE/ARRAYS FUNCTIONAL DESCRIPTION Standard 24-pin PAL Family The standard 24-pin PAL family is comprised of four dif- ferent devices, including both registered and combina- torial devices. Ail parts are produced with a fuse link at each input to the AND gate array, and connections may be selectively removed by applying appropriate volt- ages to the circuit. Utilizing an easily-implemented pro- gramming algorithm, these products can be rapidly pro- grammed to any customized pattern. Information on ap- proved programmers can be found in the Programmer Reference Guide. Extra test words are pre-programmed during manufacturing to ensure extremely high field pro- gramming yields, and provide extra test paths to achieve excellent parametric correlation. Variable Input/Output Pin Ratio The registered devices have twelve dedicated input lines, and each combinatorial output is an I/O pin. The PAL20L8 has fourteen dedicated input lines, and only six of the eight combinatorial outputs are IO pins. Buif- ers for device inputs have complementary outputs to Provide user-programmable input signal polarity, Un- used input pins should be tied to Vec or GND. Programmable Three-State Outputs Each output has a three-state output buffer with three- state control. On combinatorial outputs, a product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feed- back. The combinatorial output provides a bidirectional V/O pin, and may be configured as a dedicated input if the buffer is always disabled. On registered outputs, an input pin controls the enabling of the three-state outputs. Registers with Feedback Registered outputs are provided for data storage and syfchronization. Registers are composed of D-type flip- flops that are loaded on the LOW-to-HIGH transition of the clock input. Power-Up Reset All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the PAL20R8 Family will be HIGH due to the active-low outputs. The Vcc rise 26E D MM 0257526 0029452 4 BMAMDE must be monotonic and the reset delay time is 1000 ns maximum. Register Preload T-46~19-13 Applies to -7 (-12 Mil), -10 (-15 Mil), Serles Only The register on the listed Series can be preloaded from the output pins to facilitate functional testing of complex State machine designs. This feature allows direct foad- ing of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Security Fuse After programming and verification, a PAL20R8 Family design can be secured by programming the security fuse. Once programmed, this fuse defeats readback of the internal programmed pattern by a device program- mer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as if every fuse is unprogrammed. An exception is the -7 (-12 Mil) Series, where the array will read as if every fuse is programmed. Pinouts All members of the PAL20R8 Family have the same SKINNYDIP pinouts independent of technology, per- formance, and operating conditions. Because the 24-pin SKINNYDIP requires four no-connects when mapped into the 28-pin PLCC/LCC packages, the PLCC/LCC pinouts can vary. . Two different PLCC pinouts are offered. Newerdevices and all future devices will follow the JEDEC electronics committee's standard pinout (JEDEC pinout) with no- connects on pins 1,8, 15, and 22. The devices following this pinout are the -7, -10, and 8-2 Series. Older devices retain their original pinouts, with no-connects on pins 5, - 8, 11, and 19. These include the B, A, arid-A-2 Series. PAL20R8 Family devices with the MMI marking indicate the PLCC pinout by the package designator: FN indi- cates JEDEC, and NL indicates non-JEDEC. Devices with the AMD marking all follow the JEDEC pinout. 2-116 PAL20R8 FamilyADV MICRO PLA/PLE/ARRAYS 28E D EM 0257526 0029453 & EBAMD2 -_ Two different LCC pinouts are offered for military prod- ucts. Newer devices and all future devices will follow the JEDEC pinout with no-connects on pins 1,8, 15, and 22. These include the -12 and -15 Series. Older devices re- tain their original pinouts, with no-connects on pins 4, 11, 18, and 25. These include the B, A, and A-2 Series. Series Com! Mil PLCC Lcc No-connects No-connects -7, -10, 1,8, 15, 22 N/A B-2 (JEDEC) 12, -15 N/A 1,8, 15, 22 (JEDEC) B, A, A-2 5,8, 11, 19 4,11, 18, 25 Quality and Testability ~ T-46-19-13 The PAL20R8 Family offers a very high level of built-in quality. Extra programmable fuses provide a means of. verifying performance of all AC and DC parameters. in addition, this verifies complete programmability and functionality of the device to provide the highest pro- gramming yields and post-programming functional yields in the industry. Technology The high-speed -7 (-12 Mil} and -10 {-15 Mil) Series are fabricated with AMD's advanced oxide-isolated bipolar process. This process reduces parasitic capacitances and minimum geometries to provide higher perform- ance. The array connections are formed with proven PtSi fuses for the -7 and TIW fuses for the -10. The B, B-2, A, and A-2 Series are fabricated with AMDs junc- tion-isolated process, utilizing TIW fuses. , PAL20R8 Family 2-117ADV MICRO PLA/PLE/ARRAYS ChE D MM 0257S5eb OOe2FW4SYH 8 GA ANDE LOGIC DIAGRAM DIP (JEDEC PLCC and LCC) Pinouts T-46-19-13 | See Connection Diagrams for B, A, A-2 Serles PLCC/LCC Pinouts 20L8 f24|voq 0 394 7 8 1112 1816 1920 2324 2728 3192 3536 39 . 28) ko : Og Ig 10 (12) Iyql 4! (13) ono [2} 0 34 78 1112 1516 192% 2324 2728 9132 93536 39 (14) 12350-007A 2-118 PAL20R8 FamilyADV MICRO PLA/PLE/ARRAYS 28 D Mm 0257526 0029455 T Ea AND2 LOGIC DIAGRAM oo DIP (JEDEC PLCC and LCC) Pinouts T-46-19-13, See Connection Diagrams for B, A, A-2 Series PLCC/LCC Pinouts CLK (1 20R8 Blvce 034 7 8 #1112 1816 192 2924 2728 3192 353 39 (28) - phe 27) Oa (26) lo [3 07 g 6 (24) 45 Os 's [6 O4 is E Og (20} yf 02 (19) tg (9 o% (18) Sg [1 (42) Holt 4 (13) . GO OE GNo fz} 0 34 7B 1112 1816 1920 2324 2728 9192 3536 439 (16) (14) 12350-008A PAL20R8 Family 2-119ADV MICRO PLA/PLE/ARRAYS 28E D MM 0257526 OO2945b 1b BANDA LOGIC DIAGRAM 70.13 DIP (JEDEC PLCC and LCC) Pinouts ~ T-A6 See Connection Diagrams for B, A, A-2 Series PLCC/LCC Pinouts : 20R6 Bil Veo 0 3 4 78 1112 1516 1920 2324 27298 3192 9596 39 . . (28) CLK 1 (27) Vg (26) O7 (25) lg L4 06 O4 (21) Og vO, 4 (13) Guo fray 0 34 7 8 1112 1516 1920 2324 2728 3132 3526 49 (14) (16) 12350-009A 2-120 PAL20R8 FamilyADV MICRO PLA/PLE/ARRAYS esE D MM 0257526 0029457 3 ma AND2 LOGIC DIAGRAM DIP (JEDEC PLCC and LCC) Pinouts T-46-19-13. > See Connection Diagrams for B, A, A-2 Series PLCC/LCC Pinouts 20R4 Pilvec 0 34 78 112 1516 1920 2324 2728 3192 3536 39 (28) ha V0g vO, 16}VO5 15]vo, 14} yy ono [if 0 394 78 112 1516 1920 2324 2798 39192 3536 39 43] OE (14) _ 12350-010A PAL20R8 Family . 2-121ADV MICRO PLA/PLE/ARRAYS 2ed D MM 0257526 00209454 5 BHANDc ABSOLUTE MAXIMUM RATINGS Storage Temperature 65C to +150C Ambient Temperature with Power Applied ~55C to +125C Supply Voltage with Respect to Ground -0.5 Vito +7.0V DC Input Voltage DC Output or 1/O Pin Voltage Static Discharge Voltage -1.2 Vto Veco + 0.5 V 0.5 V to Veo +0.5V 2001 V Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. OPERATING RANGES Commercial (C} Devices T-46~-]9-13 Ambient Temperature (Ta) Operating in Free Air 0C to +75C Supply Voltage (Vcc) a with Respect to Ground +4.75 V to 45.25 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symboi Parameter Description Test Conditions Min. | Max, | Unit Vou Output HIGH Voitage low = -3.2 MA Vin = Vin OF Vit 2.4 Vv Vcc = Min. Vor Output LOW Voltage ln =24mA Vin= Vin or Vit . 05 Vv Vcc = Min. Vie input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voitage for all Inputs (Note 1) Vit Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) 7 Input Clamp Voltage Iin=18 mA, Veo = Min. 12 ] Vi { li Input HIGH Current Vin = 2.7 V, Voc = Max. (Note 2) 25 | pA lie Input LOW Current Vin = 0.4 V, Voc = Max. (Note 2) -250 | pA li Maximum Input Current Vin = 5.5 V, Voc = Max. 1} mA fozH Off-State Output Leakage Vout = 2.7 V, Veo = Max. 100 | BA Current HIGH Vin = Vin or Vit (Note 2) lozt Otf-State Output Leakage Vout = 0.4 V, Veo = Max. -100 | pA Current LOW Vin = Vin or Vit (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Vec = Max. (Note 3) 30 | -130 | mA lec Supply Current Vin = 0 V, Outputs Open (lour = 0 mA) 210 | mA Veco = Max. Notes: 1, These ara absolute values with respect to device ground and all overshoots due to system and/or tester noise ara included, 2. VO pin leakage is the worst case of Ii and lozz (or ky and lozH). 3. Not more than one output should be tested at atime. Duration of the short-circuit should not exceed one second. Vout =0.5V _ has been chosen to avoid test problams caused by tester ground degradation. 2-122 PAL20R8-7 Serles (Coml)ADV MICRO PLA/PLE/ARRAYS CSE D B@ 0257Seb 0029459 ? mB AMD2 CAPACITANCE (Note 1) JT~46-19-13 Parameter Symbol Parameter Description Test Conditions Typ. Unit Cin Input Capacitance Vin=2.0V Veco = 5.0 V 7 Ta = +25C pF Cout Output Capacitance Vout = 2.0 V f=1MHz 8 Note: 1. These parameters ara not 100% tested, but are evaluated at initial characterization and at any time tha design is modified where capacitance may be affected. , SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Min, Symbo! | Parameter Description (Note 3)| Max. | Unit teo Input or Feedback to 20L8, 20R6 3 7.5 Combinatorial Output 1 Output Switching 20R4 3 7 ns ts Setup Time from Input or Feedback to Clock 7 ns tH Hold Time 0 ns tco Clock to Output 3 6.5 | ns tor Clock to Feedback (Note 4) 3 ns (skew Skew Between Registered Outputs (Note 5) 20R8, 20R6, 1 ns tw. Clock Width LOW 20R4 5 Fons. twH HIGH 5 | ons Maximum External Feedback| 1/(ts + tco} 74 MHz fax Frequency Intemal Feedback | 1/{ts + tor) 100 MHz (Note 6) No Feedback 1(twe + tw) 100 MHz tpzx OE to Output Enable 3 8 ns tpxz OE to Output Disable 3 8 ns. tea Input to Output Enable Using Product Term Control 20L8, 20R6 3 10 ns ter Input to Output Disable Using Product Term Control 20R4 3 10 ns Notes: 2. Sea Switching Test Circuit for test conditions. Output delay minimums are measured under best-case conditions, Calculated from measured fmax internal. Skaw is measured with ail outputs switching in the same direction. These parameters ara not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affectad. : Pane we PAL 20R8-7 Series (Coml) 2-123ADV MICRO PLA/PLE/ARRAYS 28E D MM O25752b OO29460 3 BMAND2 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES ~ 7-46-19. 13. ~ Storage Temperature -65C to +150C Military (M) Devices (Note 1) , Ambient Temperature Operating Case (Tc) OS with Power Applied 55C to +125C Temperature 55C to +125C Supply Voltage with Supply Voltage (Vcc) Respect to Ground 0.5 Vto +7.0V with Respect to Ground +4.50 V to +5.50 V DC input Voltage -1.2V toVec +0.5V Operating ranges define those limits between which the func- DC Output of I/O Pin Voltage -0.5V to Voc +0.5V tionality of the device is guaranteed, Static Discharge Voltage 2001 V Note: - Stresses above those listed under Absolute Maximum Rat- - 5 orn - ings may cause permanent device failure. Functionality at or 1. Military products are tested at Tc = +25C , +125C, above these limits is not implied. Exposure to Absolute Maxi- and -55C per MIL-STD-883,_ mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. Absolute Maximum Ratings are for system design reference; parameters given are not tested. DC CHARACTERISTICS over MILITARY operating sthrwise specified (Note 2) Parameter cs Symbol Parameter Description , [Test Conditions > Min. | Max. | Unit Von Output HIGH Voltage _ loa S2mA, Vin = Vin or Vin 2.4 V. 4 ea | ~ Veo = Min. . Voi Output LOW Voltage. i =12mMA Vin = Vin or Vit 05] V aes : Vec = Min. a Vin Input HIGH Voltage * 3 Guaranteed Input Logical HIGH 2.0 V moa Voltage for all Inputs (Note 3) Viv Input LOW Voltage Guaranteed Input Logical LOW 08) Vv ma Voltage for ail Inputs (Note 3) vi Input Clamp Voltage lin=~-18 MA, Voc = Min. -1.2 Vv dia Input HIGH Current Vin = 2.4 V, Voc = Max. (Note 4) 25} pA In, Input LOW Current Vin = 0.4 V, Voc = Max. (Note 4) 250 | pA I Maximum Input Current Vin = 5.5 V, Veco = Max. t| mA lozH Off-State Output Leakage Vout = 2.4 V, Vec = Max. 100 | pA Current HIGH Vin = Vin or Vi, (Note 4) , loz Off-State Output Leakage Vout = 0.4 V, Veco = Max. ~100 | pA Current LOW Vin = Vin or Vi (Note 4) Ise Output Short-Circuit Current Vout = 0.5 V, Veco = Max. (Note 5) -30 | -130 | mA lec Supply Current Vin= 0 V, Outputs Open (four = 0 mA) 210} mA Veco = Max. Notes: 2. For APL Products, Group A, Subgroups 1, 2, and 3 are tested per MIL-STD-883, Method 5005, unless otherwise noted. 3. Vit and Viz are input conditions of output tests and are not themselves diractly tested. Vi_ and Viy are absolute voltages with respect to device ground and include alt overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. 4. V/O pin leakage is the worst case of lL and loze (or ty and Iozy). 5. Not more thanone output should be tesied at a time. Duration of the short-circuit should not exceed one second. VouT=0.5 V - has been chosen to avoid test problems caused by tester ground degradation. 2-124 PAL20R8-12 Series (Mil)ADV MICRO PLA/PLE/ARRAYS 23E D MM 0257526 OO294b1 5 MMAND2 CAPACITANCE (Note 1) J~46-19-13 Parameter Symbol Parameter Description Test Conditions Typ. Unit Cin Input Capacitance Vin=2.0V Vec = 5.0 V 9 i Ta = +25C - pF Cour Output Capacitance Vout = 2.0 V f= 1 MHz 10 Note: 1, These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 2) Parameter Symbol Parameter Description Max. | Unit tpo Input or Feedback to 12.5 Combinatorial Output 1 Output Switching 12 ns ts Setup Time from Input or Feedback to Clock ns tH Hold Time ns tco Clock to Output i ns _ {cr Clock to Feedback (Note 4) __ 6.5 ns tskEW Skew Between Registered Outputs (Note 5) 1 ns two Clock Width Low A MS 20R8, 20R6 10 ns twas 20R4 8 ns Maximum V(ts + tco) 43.4 MHz tax Frequency ; ti{ts + tcr) 54 MHz (Note 8) 1Atwu + tw) 55.5 | MHz tpzx OE to Output Enable (Note 7) 3 20 ns tpxz OE to Output Disable (Note 7) 3 20 ns tEA Input to Output Enable Using Product Term Control (Note 7) 20L8, 20R6 3 20 ns ter input to Output Disable Using Product 20R4 Term Control {Note 7) 3 20 | As Notes: 2. See Switching Test Circuit for test conditions. For APL products Group A, Subgroups 9, 10, and 11 are tested per MIL-STD-883, Mathad 5005, unless otherwise noted. 3. Minimum value for tp, tco, tpzx, tpxz, tea, and ten parameters should be used for simulation purposes only and are not tested. 4. Calculated from measured {Max internal. 5. Skew is measured with all outputs switching in the same direction. 6. These parameters ara not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 7, These parameters are not 100% tested, but are evaluated at initia] characterization and at any time ithe design is is modified where these parameters may be affected. PAL20R8-12 Series (Mil) 2-125ADV MICRO PLA/PLE/ARRAYS C6E D MM 0257S2b O0e94uLe 2 MEAMD2 MEASURED SWITCHING CHARACTERISTICS 7 Voc = 5.25 V, Ta = 75C (Note 1) eae T-46-19-13 75-7 Tr tpp, ns 65 + 6 {t-_$ ++} 4 1 2 3 4 5 6 7 8 # OF CUTPUTS SWITCHING tpp vs. Number of Outputs Switching 10294-0054 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where tpp may be affected. 2-126 PAL20R8-7/12 Series (Com//Mil)ADV MICRO PLA/PLE/ZARRAYS cde D Me 02575eb odedba 9 BBAMDe CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS Vec = 5.0 V, Ta = 25C W-46-19-13 lo, MA 18 -T 10 -T 5 _- + t t t Voi, V 0.6 -0.4 -0.2 0.2 0.4 0.6 el 15 = Output, LOW 10240008 fo, MA 20 T tt Vou, V 3 -2 +1 -60 4 -80 + Output, HIGH 10040-0044 1, pA 20 -T { {+} i VV ~3 -2 -4 3 2 Input i. 10240-005A PAL20R8-7/12 Serles (ComI/Mil) 2-127ADV MICRO PLA/PLE/ARRAYS 2&E D 0257526 OO294b4 O MAND ABSOLUTE MAXIMUM RATINGS OPERATING RANGES T-46-19-1 3 Storage Temperature 65C to +150C Commercial (C) Devices . Ambient Temperature with Ambient Temperature (Ta) Power Applied 55C to +125C Operating in Free Air 0C to +75C Supply Voltage with Supply Voltage (Vcc) Respect to Ground 0.5 Vto +7.0V with Respect to Ground 44.75 V to +5.25 V DC input Voltage 0.5 Vto Veo +0.5V ; Operating ranges define those limits betwaen which the tunc- DC Output or /O Pin Voltage -0.5 V to Veco Max. tionality of the device is guaranteed. DC Input Current 30 mA to +5 mA Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min. | Max.j} Unit Vou Output HIGH Voltage lon =-3.2 MA Vin = Vin or Vit 2.4 Vv Veco = Min. Vot Output LOW Voltage la=24mMA Vinn=Vin or Vit 0.5 Vv Vcc = Min. Vin Input HIGH Voltage _| Guaranteed Input Logical HIGH 2.0 FOV Voltage for all Inputs (Note 1) Vit Input LOW Voltage Guaranteed Input Logical LOW 08 Vv Voltage for all Inputs (Note 1) V1 Input Clamp Voltage lin = -18 MA, Vec = Min. 15] V Ie Input HIGH Current Vin = 2.7 V, Voc = Max. (Note 2) 25] wA fe Input LOW Current Vin = 0.4 V, Voc = Max. (Note 2) -250 | pA I Maximum Input Current Vin = 5.5 V, Vcc = Max. 100 | yA lozH Off-State Output Leakage Vout = 2.7 V, Vcc = Max. 100 | pA Current HIGH Vin = Vin or Vit (Note 2) . loz. Olf-State Output Leakage Vout = 0.4 V, Vee = Max. 100 | WA Current LOW Vin = Vinor Vit (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Vec = Max. (Note 3) -30 | -130 | mA lec Supply Current Vin= 0 V, Outputs Open (lout = 0 mA) 210 | mA Vee = Max. Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. VO pin leakage is the worst casa of fi, and lozt (or Ii and lozH). 3. Not more than one output should be tested at atime. Duration of the short-circuit should not exceed one second. Vout =0.5V has been chosen to avoid test problems caused by tester ground degradation. 2-128 PAL20R8-10 Series (Coml)ADV MICRO PLA/PLE/ARRAYS eae D BB O2575eb O0eS4bS 2 MBAND2 it CAPACITANCE (Note 1) _T-46-1 9-13 Parameter Symbol Parameter Description Test Conditions Typ. Unit Cin Input Capacitance Vin=2.0V Veo = 5.0 V | CLK, OE 12 Ta= 25C | Other Inputs 7 pF Court Output Capacitance Vout = 2.0 V | f=1MHz Outputs 8 = Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may ba affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Nin. Symbol Parameter Description (Note 3)| Max. | Unit tep Input or Feedback to 20L8, 20R6 3 10 ns Combinatorial Output 20R4 ; ts Setup Time from Input or Feedback to Clock 10 ns. ty Hold Time 0 ns tco Clock to Output 2 8 ns tor Clock to Feedback (Note 4) 20R8, 20R6 7 ns tw Clock Widih LOW 20R4 7 ns {wu HIGH 7 ns Maximum External Feedback| 1/(ts + tco) 55.5 MHz fax Frequency Intemal Feedback | 1/(ts + tor) 58.8 MHz (Note 5) No Feedback 1Witwn + twa) 71.4 MHz tezx OE to Output Enable 1 10. ns texz GE to Output Disable 1 10 ns tea Input to Output Enable Using Product Term Control 20L8, 20R6 3 10 ns ter {Input to Output Disable Using Product Term Control 20R4 3 10. ns Notes: 2. See Switching Test Circuit for test conditions. . Output delay minimums are measured under best-case conditions. 3 4. Calculated from measured {ax internal. 5 . These parameters ara not 100% tested, but are calculated at initial characterization and at any time the design i is modified where the frequency may be affected. PAL20R8-10 Series (Coml) 2-129ADV MICRO PLA/PLE/ARRAYS 2Pe4E D MM 0257526 OO2T4bb 4 MBAND2 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES , : ee Storage Temperature -65C to +150C Military (M) Devices (Note1) T-46-19-]3 Ambient Temperature Ambient Temperature (Ta) TR se with Power Applied ~55C to +125C Operating in Free Air ~55C Min. Supply Voltage with Operating Case (Tej Respect to Ground -0.5 V to +7.0 V Temperature +125C Max. DC Input Voltage 0.5 V to+5.5V Supply Voltage (Vcc) : DC Output or VO Pin Voltage -0.5 V to Voc Max. with Respect to Ground +4.50 V to +5.50 V DC Input Current 30 mA to +5 mA Operating ranges define those limits between which the func- tionality of the device is guaranteed, : Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- Note: mum Ratings for extended periods may affect device reliabil- 1. Military products are tested at To = +25C, +125C; ity. Programming conditions may differ, Absolute Maximum > Ralings are for system design reference; parameters given and -55C per MIL-STD-883. are not tested. DC CHARACTERISTICS over MILITARY operating ranges unless otherwise specified (Note 2) Parameter Symbol Parameter Description Test Conditions Min. | Max. | Unit Vor Output HIGH Voltage lon =-2MA Vin = Vin oF VIL 2.4 Vv Vec = Min. Vor Output LOW Voltage lo = 12 MA Vin = Vin or Vir 0.5 Vv Vec = Min. Vin input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all inputs (Note 3) Vit Input LOW Voltage Guaranteed Input Logical LOW 0.8 V. Voltage for all Inputs (Note 3) Vi input Clamp Voltage lin=~-18 MA, Voc = Min. -1.5 Vv din Input HIGH Current Vin = 2.4 V, Veco = Max. {Note 4) 25) pA ie Input LOW Current Vin = 0.4 V, Voc = Max. (Note 4) -250 pA I Maximum Input Current Vin = 5.5 V, Veco = Max. 100 | pA lozH Off-State Output Leakage Vout = 2.7 V, Veco = Max. 100} pA Current HIGH Vin = Vinor Vit (Note 4) . loz Off-State Output Leakage Vout = 0.4 V, Veco = Max. -100 |] pA Current LOW Vin = Vinor Vit (Note 4) - Isc Output Short-Circuit Current Vout = 0.5 V, Vcc = Max. (Note 5) -30 | -190 | mA lec Supply Current Vin= 0 V, Outputs Open (lour = 0 MA) 210; mA Veco = Max. Notes: 2. For APL Products, Group A, Subgroups 1, 2, and 3 are tested per MIL-STD-883, Method 5005, unless otherwise noted. 3. Vit and Vin are input conditions of cutout tests and are not themselves directly tested. Vi_ and Vixq are absolute voltages with respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. 4. lO pin leakage is the worst casa of li, and lozt (or liq and loz). 5. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. Vout =0.5 V has been chosen to avoid test problems caused by tester ground degradation. . 2-130 PAL20R8-15 Series (Mil)ADV MICRO PLA/PLE/ARRAYS 25E D MM O25752b OO294b7 & BMAND2 -arwwima4ias.% CAPACITANCE (Note 1) ~ T-46-19-13 Parameter Symboi Parameter Description Test Conditions Typ. Unit Cw Input Capacitance Vin=2.0V Vec=5.0V}CLK,OE | 12 Ta = 25C Other Inputs 7 pF Cour Output Capacitance Vout=2.0V | f=1MHz Cutputs 8 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 2) Parameter Min. Symbol | Parameter Description (Note 3); Max. | Unit trp Input or Feedback to 20L8, 20R6 3 15 ns Combinatorial Output 20R4 ts Setup Time from Input or Feedback to Clock 15 ns tH Hold Time 0 ns tco Clock to Output 2 13 ns tor Clock to Feedback (Note 4) {2 ns tw. Clock Width LOW 20R8, 20R6 10 Ns. tw HIGH 20R4 10 ns Maximum External Feedback | 1/{ts + tco) 35,7 MHz fax Frequency Internal Feedback | 1/{ts + tcr) 37 MHz (Note 5) No Feedback t(tw + two) 50 MHz tpzx GE to Output Enable (Note 6) 1 15 ns texz OE to Output Disable (Note 6) 1 15 ns tEA Input to Output Enable Using Product Term Control (Note 6} 20L8, 20R6 3 15 ns ter Input to Output Disable Using Product 20R4 Term Control (Note 6) 3 15 ns Notes: 2. See Switching Tast Circuit for test conditions. For APL products Group A, Subgroups 9, 10, and 11 are tested par MIL-STD-883, Method 5005, unless otherwise noted. 3. Minimum value for tep, tco, tezx, tpxz, tea, and ten parameters should be used for simulation purposes only and are not tested. 4. Calculated from measured {max internal. 5. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design Is. modified where frequency may be affected. 6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where these parameters may be affected. PAL20R8-15 Series (Mil) 2-131ADV MICRO PLA/PLE/ARRAYS e6 D EH 0257526 O02594ba 8 EAAND2 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES a : Storage Temperature -65C to +150C Commercial (C) Devices T-46-19-13 Ambient Temperature with Ambient Temperature (Ta) Power Applied 55C to +125C Operating in Free Air 0C to +75C: Supply Voltage with ; Supply Voltage (Vcc) Respect to Ground 0.6 Vio +7.0V with Respect to Ground +4,75 V to +5.25 V DC Input Voltage 1.5 Vto Veco +05 V Operating ranges define those limits between which the fune- DC Output or VO Pin Voltage -0.5V to Vcc +0.5V tionality of the device is guaranteed, Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless othetwise specified cee . Parameter Symbol Parameter Description Max. } Unit Vou Output HIGH Voltage Vv Vor Output LOW Voltage Oo5; -V oat . cc = Min. , Vin Input HIGH Voltage __..- |, Guaranteed Input Logicaf HIGH Vv oa Voltage tor all Inputs (Note Vin Input LOW Voltage Guaranteed Input Logical LOW 0.8] Vv : we Voltage for alf Inputs (Note: Vi Input Clamp Voltage In= 718 MA, Veo = Min * -1.5 Vv I Input HIGH Current =] Vin = 2.7 V,.Vec = Max. (Note 2) 25] pA lit inputLOW Current =. Vin = 0.4 V, Veco = Max. (Note 2) ~250 | pA I Maximum Input Current. | Vin =5.5 V, Veco = Max. 100 | pA lozy Oft-State Output Leakage - & Vout = 2.7 V, Veo = Max. 100 | pA Current HIGH SB Vin = Vin or Vit (Note 2) lozu Off-State Output Leakage Vout = 0.4 V, Vec = Max. -100 | pA Current LOW Vin = Vin or Vit (Note 2) Isc Output Short-Circuit Current | Vour = 0.5 V, Voc = Max. (Note 3) -30 | ~130 | mA lec Supply Current Vin = 0 V, Outputs Open (lout = 0 mA) 210 | mA Veco = Max. Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included, 2. VO pin leakage is the worst case of I, and loz (or liq and lozH). 3, Not more than one output should be tested at atime, Duration of the short-circuit should not exceed one second. Vour =0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-132 PAL20R88 Series (Com'l)ADV MICRO PLA/PLE/ARRAYS esE ) 025752b g029ub4 T EM ANDC SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) roymbol Parameter Description T-46-19-13 Min. Max, | Unit teo Input or Feedback to 20L8, 20R6 15 ns Combinatorial Output 20R4 / ts Setup Time from Input or Feedback to Clock 15 ns tH Hold Time 0 : ns tco Clock to Output or Feedback 20R8 12 ns tw Clock Width LOW 20R6 10 ns twH HIGH 20R4 ns Maximum External Feedback| 1/(ts +tco) MHz {Max Frequency (Note 2) No Feedback V/(twH + twt) MHz tpzx OE to Output Enable ns. texz OE to Output Disable ns tea Input to Output Enable Using Product Term Control? = 18 ns ter Input to Output Disable Using Product t Term Sqntrol.. 15 | ns Notes: 1. See Switching Test Circuit for test conditions; 2. These paramaters are not 100% tasted; BUE. where frequency may be affected. he design is modified PAL20R8B Series (Com'l) 2-133ADV MICRO PLA/PLE/ARRAYS 28E D BM 0257526 0029470 & BMANDS ABSOLUTE MAXIMUM RATINGS OPERATING RANGES 2 : a Storage Temperature 65C to +150C Military (M) Devices (Note 1) T+46-] 9~] 3 : Ambient Temperature Ambient Temperature (Ta) to with Power Applied 55C to +125C Operating in Free Air 55C Min. Supply Voitage with Operating Case (Tc) Respect to Ground -0.5 Vito +7.0V Temperature +125C Max. DC Input Voltage -1.5V to+55V Supply Voltage (Vcc) OO DC Output or VO Pin Voltage 5.5V - with Respect to Ground +4.50 V to +5.50 V Stresses above those listed under Absolute Maximum Rat- Operating ranges define those limits between which the func- -~ ings may cause permanent device failure. Functionality at or tionality of the device is guaranteed. above these limits is not implied. Exposura to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- Note: ily. Programming conditions may differ. Absolute Maximum te Ratings are for systam design reference; parameters given 1. Military products are te 25C, +125C, are not tested. and -55C per MIL-S (Ne CHARACTERISTICS over MILITARY operating ranges unless.otherWis specified Note 2) Parameter Symbol Parameter Description Max. | Unit Vou Output HIGH Voltage Vv Vow Output LOW Voltag tr, 0.5 Vv Vin input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv ee) Voltage for. ali Inputs (Not 3)" Vi | Input LOW Voltage Guaranteed Input Logical LOW 08] Vv cs POON AOA BAL SS | Voltage for all Inputs (Note 3) Vi input Clamp Voitage ok lin= "18 MA, Voc = Min. -1.5 Vv hi , Input HIGH Current. EVin$,2.4V, Voc = Max. (Note 4) 25] pA n Input LOW Current Vin = 0.4 V, Voc = Max. (Note 4) -250 | pA i Maximum Input Current #8 Vin = 5.5 V, Voc = Max. 1] mA lozH Oft-State Output Leakage Vout = 2.4 V, Vee = Max. 100] pA Current HIGH Vin = Vin or Vit (Note 4) loz Off-State Output Leakage Vout = 0.4 V, Voc = Max. 100; pA Current LOW Vin = Vin or Vit (Note 4) | Isc Output Short-Circuit Current | Vout = 0.5 V, Vcc = Max. (Note 5) -30 | -130 | mA lec Supply Current Vin = 0 V, Outputs Open (lout = 0 mA) 210 | mA Voc = Max. Notes: 2. For APL Products, Group A, Subgroups 1, 2, and 3 are testad per MIL-STD-883, Method 5005, unless otherwise noted. 3. Vir and Vin are input conditions of Output tests and are not themselves directly tested. Vit and Vin are absolute voltages with respect to device ground and include all overshaots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. : 4. VO pin leakage is the worst case of Ii, and loze (or li and lozy). 5. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-134 PAL20R8B Series (Mil)ADV MICRO PLA/PLE/ARRAYS 28 ) @ 0257526 OO29471 8 MMAMD2 SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 1) a T~46~19-13 Parameter - Symbol Parameter Description Min. Max. | Unit tpo Input or Feedback to 20L8, 20R6 20 ns Combinatorial Output 20R4 | ts Setup Time from Input or Feedback to Clock 20 ns tH Hold Time Oo + ns tco Clock to Output or Feedback 15 ns tw. ; LOW 20R8, 20R6 12 ons tw | Clock Width THIGH 20R4 12 "As {Max Maximum External Feedback | 1/{ts + tco) MHz . Frequency (Note 2) No Feedback 1/(twH + twt) MHz tpzx OE to Output Enable (Note 3) ns texz OE to Output Disable (Note 3) ns tea Input to Output Enable Using Product Term Control (Note 3) ns ter Input to Output Disable Using Product Term Control (Note 3) fs Notes: 1. See Switching Test Circuit for test conditighs. Pip tested par MIL-STD-893, Method 5005; unless ther ig 2. These parameters are not.{00% tested: where frequency may k bs affected. PAL20R8B Serles (Mil) 2-135ADV MICRO PLA/PLE/ARRAYS 28E D O25752b OO2ZI472 T MMAND2 ABSOLUTE MAXIMUM RATINGS Storage Temperature 65C to +150C Ambient Temperature with Power Applied - 56C to +125C Supply Voltage with Respect to Ground -0.5Vto +7.0V DC Input Voltage DC Output or VO Pin Voltage -1.5 V to Veco + 0.5 V -0.5V to Veo +0.5V Strasses above those listed under Absolute Maximum Rat- ings may cause permanent device failure, Functionality at or above these limits is not impliad. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may diffar. DC CHARACTERISTICS over COMMERCIAL operating ranges unt OPERATING RANGES * T=46-19-13 : Commercial (C) Devices . so Ambient Temperature (Ta) Operating in Free Air 0C to +75C Supply Voltage (Vcc) mo with Respect to Ground +4.75 V to +5.25 V Operating ranges detine those limits between which the func- tionality of the device is guaranteed. specified Parameter Symbol Parameter Description Max. | Unit Vou Output HIGH Voltage v Voi Output LOW Voltage 0.5 Vv. VIH Input HIGH Voltage _ Vv Vit Input LOW Voltage 08 | V Vi Input Clamp Voltage In==18 mA, Voc = Mir} -15/ V hy Input HIGH Current _a | Vin 5.2.7 V, Vec-=:Max. (Note 2) 25 | pA In > Input LOW Current "1 Vin = 0.4 VeVeG = Max. (Note 2) ~250 | pA I Maximum Input Current. 1 Vin 35.5 V, Voc = Max. 100 | pA lozn Off-State Output Leakage ~.| Vout = 2.7 V, Veo = Max. 100 | pA Current HIGH = "2" 7 Vin = Visor Vie (Note 2) lozt Off-State Output Leakage Vour = 0.4 V, Veco = Max. -100 | pA Current LOW = Vin = Vin or Vit (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Vec = Max. (Note 3) -30 | -180 | mA Ice Supply Current Vin = 0 V, Outputs Open (lout = 0 mA) 105 | mA Voc = Max. Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. VO pin leakage is the worst case of ht and loz. (or liq and lozH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-136 PAL20R8B-2 Series (Com'l)ADV MICRO PLA/PLE/ARRAYS Ce6E D MM 0257526 0029473 1 MAMD2 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) TT TTT DET raymbol Parameter Description T-46-19-13 Min. Max. } Unit. tro Input or Feedback to 20L8, 20R6 25 . ns Combinatorial Output 20R4 ts Setup Time from Input or Feedback to Clock 25 ns ty Hold Time 0 ns tco Clock to Output 15 | ns ter Clock to Feedback (Note 2) 20R8, 20R6 10 ns tw Clock Width LOW 20R4 15 ns twH HIGH ns Maximum External Feedback| 1/(ts + tco) MHz fax Frequency Intemal Feedback | 1/(ts + tcr) MHz (Note 3) No Feedback 1(twu + tw) MHz | te2x OE to Output Enable ns tpxz OE to Output Disable = . ns tea Input to Output Enable Using Product Term Contrai = f* 20L8, 20R6 25 | ter Notes: 2. Calculated from measured fraax internal. 3. These parameters are not 100% tested, where frequency may be affected, PAL20R8B-2 Series (Com'l) 2-137ADV MICRO PLA/PLE/ARRAYS COE D EM 0257526 0029474 3 BAND ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature with Power Applied Supply Voltage with Respect to Ground DC Input Voltage DC Output or I/O Pin Voltage OPERATING RANGES 65C to +150C Commercial (C) Devices Ambient Temperature (Ta) ~56C to +125C Operating in Free Air Supply Voltage (Vcc) -O.5 Vito +7.0V with Respect to Ground -1.5V to Veco + 0.5 V -O.5V to Vece+0.5V Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Falings for extended periods may affect device reliabil- ily. Programming conditions may differ. DC CHARACTERISTICS over COMM ~T-46-19-13. 0C to +75C +4.75 V to +5.25 V Operating ranges define those limits between which the func-. tionality of the device is guaranteed. ERCIAL operating ranges untase otfierwise. specified Parameter Symbol Parameter Description Test Conditions... Max. 1 Unit Vou Output HIGH Voltage lon = -3.2.m : Vv Vot Output LOW Voltage 0.5 Vv Vin Input HIGH Voltage _} Guaranteed input Logical HIGH: Vv {| Voltage for all Inputs (Note Vit Input LOW Voltage Guaranteed Input Logical Li 0.8 Vv aan Voltage for al! Inputs (Not Vi Input Clamp Voltage In = =18-MA, Vc = Mine -15] =V Ig {Input HIGH Current *| Vin = 2.7 V,.Vec"s Max. (Note 2) 25 | pA I . Input LOW Current =.= Vin = 0.4. V,:Vcc = Max. (Note 2) -250 | yA h - Maximum Input Currant. | Vin= 5.5 V, Voc = Max. | 100 | pA loz Off-State Output Leakage -~.}: Vour = 2.7 V, Vee = Max. 100 | pA Current HIGH . {4 Vin = Vin or Vit (Note 2) lozt Off-State Output Leakage Vout = 0.4. V, Vee = Max, -100 | WA Current LOW Vin = Vinor Vit (Note 2) Ise Output Short-Circuit Current | Vout = 0.5 V, Vec = Max. (Note 3) ~80 | ~130 | ma lec Supply Current Vin = 0 V, Outputs Open (lour = 0 mA) 210 | mA Vec = Max. Notes: t. These are absolute values with respect to device ground and all overshoots due ta system and/or tester noise are included. 2. VO pin leakage is the worst case of li and loz. (or ti and lozy). 3. Not more than one output should be tested at atime. Duration of the short-circuit should not exceed one second. Vout =0.5 V has been chosen to avoid test prablems caused by tester ground degradation. 2-138 PAL20R8A Series (Com'l)ADY MICRO PLA/PLE/ARRAYS 26E D MM 0257526 oo24u75 5 me AnD2 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) SS ape an aa. roymbor Parameter Description T-46-19-13 / Min, | Max. | Unit tpp Input or Feedback to 20L8, 20R6 25 ns Combinatorial Output 20R4 ts Setup Time from input or Feedback to Clock 25 ns tH Hold Time 0 ns ico Clock to Output 15 | ns ter Clock to Feedback (Note 2) 20R8, 20R6 10 | ns two Clock Width LOW 20R4 15 ns tw HIGH ns Maximum External Feedback| 1/(ts + tco) MHz fax Frequency Internal Feedback | t/{ts + tcr) MHz (Note 3) No Feedback 1/(twi + tw.) MHz _ tpzx OE to Output Enable ns texz OE to Output Disable - ns tea Input to Output Enable Using Product Term. Control: ns ter Input to Output Disable Using Product Term Control ns Notes: 1. See Switching Test Circuit for test c PAL20R8A Series (Com'l) 2-139ADV MICRO PLA/PLE/ARRAYS ABSOLUTE MAXIMUM RATINGS OPERATING RANGES T-46 19-13 Storage Temperature ~65C to +150C Military (M ) Devices (Note 1) , Ambient Temperature Ambient Temperature (Ta) with Power Applied 55C to +125C Operating in Free Air -~55C Min. Supply Voltage with Operating Case (Tc) Respect to Ground 0.5 Vio +7.0V Temperature +125C Max. DC input Voltage -1.5V to+5.5V Supply Voltage (Vcc) DC Output or YO Pin Voitage 5.5 V with Respect to Ground +4.50 V to +5.50 V Strasses above those listed under Absolute Maximum Rat- Operating ranges define those limits betwen which the func- ings may cause permanent device failure. Functionality at or tionality of the device is guaranteed. : above these limits is not implied. Exposura to Absolute Maxi- mum Ratings for extanded periods may affect device reliabil- ity. Programming conditions may differ. Absolute Maximum Note: Ratings are for system design reference; parameters given 1. Military products are teste #25C, +125C, are not tested. and 5C per MIL-ST: DC CHARACTERISTICS over MILITARY operating ranges ut th Nis specified (Note 2) Parameter Symbol Parameter Descriptlon _Max, | Unit Vow Output HIGH Voltage | ve Voi 0.5 V Vin Vv Vi 0.8 Vv Vi * age | 1.5 hy = {Input HIGH Current. Nin#Z-4'V, Voc = Max. (Note 4) 25] pA I b-finput LOW Current S .ViN'= 0.4 V, Voc = Max. (Note 4) --250 | HA lh Maximum Input Current Vin=5.5 V, Vec = Max. 1{> mA lozH Oft-State Output Leakage Vout = 2.4 V, Veo = Max. 100} pA Current HIGH Vin = Vin or Vit (Note 4) loz Off-State Output Leakage Vout = 0.4 V, Voc = Max. -100 } pA Current LOW Vin = Vinor Vit (Note 4) Isc Output Short-Circuit Current Vout = 0.5 V, Vcc = Max. (Note 5) -30 | -130 | mA icc Supply Current Vin = 0 V, Outputs Open (lour = 0 mA) 210] mA Vec = Max. Notes: 2. For APL Products, Group A, Subgroups 1, 2, and 3 are tested per MIL-STD-883, Mathod 5005, unless otherwise noted. 3. Vit and Vix are input conditions of output tests and are not themsalves directly tested. Vi_ and Vip are absolute voltages with respect to device ground and include afl overshoots due to system and/or tester noise. Do not attempt to tast these values without suitable equipment. - 4, VO pin leakage is the worst case of IIL and loz (or liq and lozu)}. 5. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second, Vout =0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-140 PAL20R8A Series (Mil) 28E D MM 0257526 0029476 7 MMAND2ADV MICRO PLA/PLE/ARRAYS 2bE D 0257526 002947? 9 MEANDC T-46+19-13 SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 1) Parameter . Symbol Parameter Description Min. | Max. | Unit ten Input or Feedback to 20L8, 20R6 30 | ns Combinatorial Output 20R4 ts Setup Time from Input or Feedback to Clock 30 ns tH Hold Time 0 , ns tco Clock to Output or Feedback 20 ns twe Clock Width LOW 20R8, 20R6 20 ns twH HIGH 20R4 20 _ hs Maximum External Feedback j 1/(ts + tco) MHz fMAX Frequency (Note 2) No Feedback 1/(twH + tw.) MHz tezx OE to Output Enable (Note 3) texz OE to Output Disable (Note 3) tEA Input to Output Enable Using Product Term Control (Note 3) ter Input to Output Disable Using Product Term Control (Note 3) Notes: tested per MIL-STD-883, Method 5008, sen otherwise noted. 2. Thase parameters are not t00% testad t aut are. B caiclilated at ini i PAL20R8A Series (Mil) 2-141ADV MICRO PLA/PLE/ARRAYS 28E ) Bm 0257526 ooesu7a o mE AND? ABSOLUTE MAXIMUM RATINGS OPERATING RANGES T- 16. 19~ 13 , Storage Temperature -65C to +150C Commercial (C) Devices Ambient Temperature with Ambient Temperature (Ta) Power Applied ~55C to +125C Operating in Free Air 0S to +75C Supply Voltage with Supply Voltage (Vcc) Respect to Ground 0.5 Vito +7.0V with Respect to Ground +4.75 V to +5.25 V DC Input Voltage DC Output or /O Pin Voltage -1.5 V to Veo +0.5V Operating ranges deline those limits betwean which the func- -0.5V to Voc + 0.5 V tionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods ity. Programming conditions may differ. may affect davice reliabil- DC CHARACTERISTICS over COMMERCIAL operating ranges unfes C herwise - specified s Parameter Symbol Parameter Description Test Conditions=., Max. | Unit Vou Output HIGH Voitage iN. V Vot Output LOW Voltage 0.5 Vv Vin Input HIGH Voltage Vv Vit input LOW Veltage "Guaranteed Input kogigat E 08} -V _ Voltage for alt Inputs (Note Vi input Clamp. Voltage Vee 15) V ft Input HIGH Cuyrent 25 LA iL 2" Taput LOW Current -250 |] uA hi . | Maximum Input Cuifent /ini5.5 V, Voc = Max. 100 | pA loz Of-State Output Leakag Vout = 2.7 V, Veo = Max. 100 | pA Current HIGH * 2 | Vin = Vinor Vn (Note 2) lozt Off-State Output Leakage Vout = 0.4 V, Vee = Max. -100 | pA Current LOW Vin = Vin or Vit (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Veo = Max. (Note 3) -30 | -130 | mA lec Supply Current Vin= 0 V, Outputs Open (lout = 0 mA) 105 | mA Vec = Max. Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester nalse are included. 2. VO pin leakage is the worst case of lit and loz (or liq and lozn). 3. Not more than ona output should be tested at a time. Duration of the short-circuit should not exceed one second, Vout = 0.5 V has been chosan to avoid test problems caused by tester ground degradation. 2-142 PAL20R6A-2 Series (Com'l)ADV MICRO PLA/PLE/ARRAYS 2aF D M 025752b 0029479 2? BEAMD2 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) Symbol Parameter Description 1-46-1 9-13 . Min. | Max. | Unit tro Input or Feedback to 20L8, 20R6 35 | ns Combinatorial Output 20R4 7 Is Setup Time from Input or Feedback to Clock 35 ns tH Hold Time 0 hs tco Clock to Output or Feedback 20R8, 20R6 25 ns twee Clock Width LOW 20R4 25 ns tw HIGH 25 ns Maximum External Feedback| 1/(ts + tco) MHz {ax Frequency (Note 2) No Feedback TttwH + tw.) MHz tpzx OE to Output Enable ns tpxz SE to Output Disable ns. tea Input to Output Enable Using Product Term Control ==. ns ter Input to Output Disable Using Product Term Cantrl ns Notes: 1, See Switching Test Circuit for test conditionse: 2. These parameters ara nat 100% test where frequency may be affected. design is madified PAL20R8A-2 Series (Com'l) 2-143ADV MICRO PLA/PLE/ARRAYS ede D mm 0257526 OO294a0 9 BMAMD2 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES T-46~-19-1 3 Storage Temperature -65C to +150C Milltary (M ) Devices (Note 1) Ambient Temperature Ambient Temperature (Ta) with Power Applied ~55C to +125C Operating in Free Air 5BC to +125C- Supply Voitage with Supply Voltage (Vcc) Respect to Ground 0.5 V to +7.0V with Respect to Ground +4.50 V to +5.50.V DC Input Voltage -1.5V to+5.5V . . , . DC Output or VO Pin Voltage 5.5 V Operating ranges define those limits between which the func- Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. Absolute Maximum Ratings are for system design reference; parameters given are net tested. tionality of the device is guaranteed. . Note: - 1. Military products are testad at To = +25C, +125C, and -55C per MIL-STD-8a3., DC CHARACTERISTICS over MILITARY operating ranges ui (Note 2) Parameter Symbol Parameter Description Max. | Unit Vou Output HIGH Voltage Vv Vow Output LOW Voltage 0.5 Vv 4 Veo-s \ Vin Input HIGH Voltage Guaranteed Input Logical HIGE V EATS Voltage for all Inputs (Note 3 Viv input LOW Voltage Guatdnteed Inpit Logical LOW 08] Vv ee | Voltage for all Inputs (Note 3) Vv | Input Clamp Voltage Alin = ~48 MAI Vc = Min. -15|] V le Input HIGH Current 7%. | Vin =2.4V, Voc = Max. (Note 4) 251 yA i Input LOW Current <8. 1 Viw'= 0.4 V, Veo = Max. (Note 4) -2501 pA I Maximum Input Current Vin = 5.5 V, Voc = Max. 1} mA lozH Off-State Output Leakage Vout = 2.4V, Voc = Max. 100} pA Current HIGH . Vin = Vinor Vit (Note 4) loz Off-State Output Leakage Vout = 0.4 V, Vcc = Max. -100] pA Current LOW Vin = Vin or Vit (Note 4) _ Isc Output Short-Circuit Current Vout = 0.5 V, Voc = Max. (Note 5) +30 | -130 |] mA loc Supply Current Vin = 0 V, Outputs Open (lour = 0 mA) 105 | mA Vec = Max. Notes: 2. For APL Products, Group A, Subgroups 1, 2, and 3 are tested per MIL-STD-883, Method 5005, unless otherwise noted. 3. Vit and Vin are input conditions of output tests and are not themselves directly tested. Vi_ and Viy are absolute voltages with raspect to device ground and include all overshoots dua to system and/or tester noise. Do not attempt to test these values without suitable aquipment. 4. VO pin leakage is the worst case of Ii, and fozy (or Ina and Iozy). 5. Not more than one output should be tested at a time. Duration af the short-circuit should not exceed one second. VouT=0.5 V - has been chosen to avoid test problems caused by tester ground degradation. 2-144 PAL20R8A-2 Serles (Mil)ADV MICRO PLA/PLE/ARRAYS c&&t D EM 02575ceb qoed4ai a EAANDe SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 1) Parameter Symbol Parameter Description Min. Max. { Unit. teo Input or Feedback to 20L8, 20R6 50 ns Combinatorial Output 20R4 ts Setup Time from Input or Feedback to Clock 50 ns tH Hold Time 0 ns tco Clock to Output or Feedback 25 ns tw Clock Width LOW 20R8, 20R6 25 ns twH HIGH 20R4 25 es Maximum External Feedback | 1/{ts + tco) MHz fmMax Frequency (Note 2} No Feedback T(twH + twe) MHz tp2x OE to Output Enable (Note 3) ns texz OE to Output Disable (Note 3) ns tEA Input to Output Enable Using Product ns Term Control (Note 3) . ter Input to Cutput Disable Using Product ns Term Control (Note 3) Notes: . 1. See Switching Test Circuit for test conidit te 2. These parameters ara not 400% tested Sut are d caltlated at in abchatact zation ant at ay time the design is modified where frequency oa be, atfecjed. i . : 3. PAL20R8A-2 Series (Mil) 2-145ADV MICRO PLA/PLE/ARRAYS 26E D RM O25752b 0029482 2 BMANDZ SWITCHING WAVEFORMS ~"T-46-19-13. > Input or Input or Feadback Vr Feedback tpp Combinatorial Vr pu Clock 12015-010A ComblInatorlai Output Registered y Output T 12015-0124 Registered Output . CLK ts + tcr [ naan {--., | ant | Vv Clock T | Locic |"S_.] recisTerR | , I i : | 12149-0254 tor Clock to Feedback (fax Internal) Ne a a ee 4 See Path at Right 12015-021A Clock / twH Clock Vr Registered Output 1 Vr tw tsKew 12015-0114 Registered Vr Clock Width Output 2 12350-015A Registered Output Skew for Outputs Switching In the Same Direction Input VT Vr OE . teR tEA tpxz w tpzx WW Vi - 0.5V/77/ YG Vv -05V/77 R_VOH R_YOH 7 U.9' Vv V Output [TLE ion + 0.5VNANK Outpt To 0s 12015-013A 12015-014A Input to Output Disable/Enable OE to Output Disabie/Enable _ Notes: 1.Vre215V 2. Input pulse amplitude 0 V to 3.0 V 3. Input rise and fall times 2-5 ns typical. (2-4 ns for -7 (-12 Mil) and -10 (-15 Mil) Series) 2-146 PAL20R6& FamilyADV MICRO PLA/PLE/ARRAYS 286 D M 0257524 go29483 4 MAMDe KEY TO SWITCHING WAVEFORMS ne \ T-46~19-13 : WAVEFORM INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing from H to L from H to L May Will be Change Changing from L toH from L to H Don't Care; Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance Off State . KS000010-PAL SWITCHING TEST CIRCUIT 5V Si Ri Output Tast Point : I . = = 12350-0194 Commercial Milita . . ry Measured Specification Si CL R, Rz Ri Ra Output Value tpp, tco, ter Closed 15V tpzx, fea Z H: Open 50 pF 15V ZL: Closed 2002 1 3900 | 3909 | 7502 . tpxz, tern H - Z: Open 5 pF H 2: Von~ 0.5 V L >Z: Closed LZ: VoL +0.5V PAL20R8 Family . 2-147ADV MICRO PLA/PLE/ARRAYS ede D 02575eb 0029484 b EMANDC T-46-19-13 INPUT/OUTPUT EQUIVALENT SCHEMATICS Typical Input Typical Output 40 Q NOM Input 12350-0208 Qutput Program/Varity Input Program/Verify/ Circuitry Pins Test Circuitry Preload Circuitry (if available) , " 10294-002A 2-148 PAL20R8 Family