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Copyright ©2000 Alliance Semiconductor. All rights reserved.
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• Organization:512K words × 8 bits
• Industrial and co mmercial temperatur e
• Sector architecture
- Eig ht 64K byte se ctors
- Erase any combination of sectors or full chip
• Single 5.0±0 .5V po wer supply for rea d/writ e operations
• Sector protection
• High s peed 55/70/90/120/150 ns ad dress access time
• A ut omated on- c hi p prog ramming alg o rithm
- Automatic a l ly pr ogr am s / v er i fies data at specifie d
address
• Automate d on- chip eras e al gorit hm
- Automatically pre p rogr am s/e ras es chip or spec ified
sectors
• 10,0 0 0 write/ erase cycl e en du rance
• Low power consumption
- 30 mA maximum read current
- 60 mA maximum program current
- 400 µA ty pi cal st an d by current
• JEDEC standard software, packages and pinouts
- 32-pin TSOP
- 32-pin PLCC
• D etection of program/erase cycle completion
-DQ7 DATA
polling
- DQ6 toggle bit
• Erase suspend/resume
- Supports reading data from or programming data to
a sector not being erased
• Low VCC write lock-out below 2.8V
/RJLF#EORFN#GLDJUDP
X decoder
VCC
VSS
Cell matr
Y decoder Y gating
Data latch
Chip enable
Address latch
Input/output
buffers
Sector protect
Command
register
Program/erase
control
VCC detector
Erase voltage
generator
Program voltage
generator
Timer
A0–A18
CE
OE
STB
STB
Output enable
Logic
WE
DQ0–DQ7
switches
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VCC
WE
A17
A14
A13
A8
A9
A11 OE
A10
CE
DQ7
DQ6
DQ5
A18
A16
A15
A12
A7
A6
A5
A4 A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
20
19
15
16 18
17
32-pin TSOP
32-pin PLCC
1232313043 29
28
27
26
25
24
23
21
A7
A6
A5
A4
A3
A2
A1
DQ0
VSS DQ4 DQ6DQ1
22
5
6
7
8
9
10
11
13
12
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DQ2 DQ3 DQ5
A0
A14
A13
A8
A9
A11
OE
A10
DQ7
CE
A16 VCC A17A12 A15 A18 WE
AS29F040
AS29F040
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AS29F040-55 AS29F040-70 AS29F040-90 AS29F040-120 AS29F040-150 Unit
Maximum access time tAA 55 70 90 120 150 ns
Maximum chip enable access time tCE 55 70 90 120 150 ns
Maximum output enab le access time tOE 25 30 35 50 55 ns
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The AS29F040 is a 4-megabit, 5-volt-only Flash memory device organized as 512K bytes of 8 bits each. For flexible erase an
program capability, the 4 megabits of data is divided into eight 64K-byte sectors. The ×8 data appears on DQ0–DQ7. The
AS29F040 is offered in JEDEC standard 32-pin TSOP and 32-pin PLCC packages. This device is designed to be programmed an
erased in-sys te m with a single 5.0V VCC su pply. The device can also be reprogrammed in standard EPROM programmers.
The AS29F040 offers access times of 55/70/90/120/ 15 0 ns, allowing 0-wait state op eration of high-speed microprocessors. To
eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls
The AS 29F040 is fully co mpatible with the JEDE C single pow er supply Flash standa r d. Write commands to the command r egister
use s t and ard micr oprocessor write timings. An internal state mac hine uses re gis ter contents to control the eras e and programming
circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data
operates from the device in the same manner as other Flash or EP ROM devices. The program command sequence is used to invoke
the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin.
The erase command sequence is used to invoke the automated o n -chip erase al gorithm that prepro grams the sector if it is not
already programmed before executing the erase operation, times the erase pulse widths, an d verifi es proper cell margin.
Sector era s e architecture allows specified sectors of me mo r y t o be erased and reprogrammed witho ut altering da ta in other sectors.
A sect or t ypi c al l y e rases and verifies within 1.0 seconds. Ha rd ware s ec tor protection disable s bo th program a nd eras e o per at io ns i n
any or all combinations of the eight sectors. The device provides true background erase with Erase Suspend, which puts erase
operations on hold to either read data from or program data to a sector that is not being erased. The chip erase command will
autom atically erase all unprotected sectors.
A factory shipped AS29F040 is f ul ly erased (a ll bits = 1). The programming op e ration sets bits to 0. Data is progr ammed into the
ar ray one byte at a time in any sequence and across secto r boundaries. A sector must be er ased to cha nge bits fro m 0 to 1. Erase
return s all bytes in a sector to the erased state (all bits = 1). Each sec tor is era s ed individually with no effect on other sectors.
The device features single 5.0V power supply operation for read, write, and erase functions. Internally generated and regulate
voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during
power transtitions. DATA polling of DQ7 or toggle bit (DQ6) may be used to detect end-of-program or erase operations. The
device automatically resets to read mode after program and/or erase operations are completed.
The AS29F040 resists accidental erasure or spurious programming signals resulting from power transitions. Control register
arc hitect ure pe rmits the alterat ion of mem ory con tents only afte r successful completi on of spec ific command sequences. D uring
power up, the device is set to read mod e with all p r ogram an d/or eras e commands disabled when VCC is less than V LKO (loc kout
voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. CE and WE must be logical
zero and OE a logical one to initiate write commands.
The AS29F040 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are programme
one at a time using th e EPROM programming mechanism of ho t electron injection.
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L = Low (<VIL); H = High (>VIH); VID = 12.0 ± 0.5V; X = don’t car .
0RGH#GHILQLWLRQV
Mode CE OE WE A0 A1 A6 A9 DQ0-DQ7
ID read MFR code L L H L L L VID Code
ID read device code L L H H L L VID Code
Read L L H A0A1A6A9D
OUT
Standby HXXXXXXHigh Z
Output disable L H H X X X X High Z
Write L H L A0 A1 A6 A9 DIN
Ena ble sect or protect L VID Pulse/L L H L VID X
Sector un protect L VID Pulse/LL HHV
ID X
Verify sector protect L L H L H L VID Code
Item Description
ID MFR code,
device code
Selected by A9 = VID(11.5–12.5V), CE = OE = A1 = A6 = L, enabling outputs.
When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.
When A0 is high (VIH), DOUT represents the device code for the AS29F040.
Read mode Sele cted with CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low
and tOE after OE is low.
Standby Sel ected with CE = H. Part is powered down, and ICC reduced to <1.0 mA for TTL input lev els and <100 µA
for CMOS levels. If activated during an au tomated on-chip algorithm, the device completes the operation
before en tering st andby.
Output disable Part remains powered up; but outputs disabled with OE pulled high.
Write
Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command
register. Contents of command regi ster serve as inputs to the internal state machine. Address latching occurs
on the falling edge of WE or CE, whiche v er occurs late . Data latching occurs on the rising edge WE or CE,
which ever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.
Enable
sect or protect Hardware protection circuitry implemented with external programming eq uipment causes the device to
disable program and erase operations for specified sectors.
Sector
unprotect Disables sector protection for all sectors using external programming equipment. All sectors must be
protected prior to s ector unprotec ti on.
Verify
sect or protect
Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
progr amming eq uipment . Dete rmine if secto r pro tecti on ex ists in a s ystem b y writing the I D r ead c omma nd
sequence and reading loc atio n XXX0 2h, wher e addre ss bi ts A 16–18 select the defined sect or addresses.
A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.
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L = Low (<VIL); H = High (>VIH); X = Don’t care.
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1 B us operations defined in "Mode definitions," on page 3.
2 R eading from or programming to non-erasing sectors allowed in Erase Suspend mode.
3 A ddress bi t A15 = X = Don’t care for all address c ommands except Program Address.
4 A ddress bi t A16 = X = Don’t care for all address c ommands except Program Address and Sector Address.
5 A ddress bi t A17 = X = Don’t care for all address c ommands except Program Address and Sector Address.
6 A ddress bi t A18 = X = Don’t care for all address c ommands except Program Address and Sector Address.
Sector Equal sector architecture ID sector address
Addresses Size (Kbytes) A18 A17 A16
0 00000h–0FFFFh 64 0 0 0
1 10000h–1FFFFh 64 0 0 1
2 20000h–2FFFFh 64 0 1 0
3 30000h–3FFFFh 64 0 1 1
4 40000h–4FFFFh 64 1 0 0
5 50000h–5FFFFh 64 1 0 1
6 60000h–6FFFFh 64 1 1 0
7 70000h–7FFFFh 64 1 1 1
Mode A18–A16 A9 A8–A7 A6 A5–A2 A1 A0 Code on DQ0–DQ7
MFG code (Alliance
Semiconductor) XV
ID XLX LL52h
Device code X VID XLX LHA4h
Sector protection Sector
address VID Sector
address LSector
address HL 01h protected
00h unprotected
Command
sequence Required
bus cycles
1st bus write
cycle 2nd bus write
cycle 3rd bus write
cycle 4th bus read/ write
cycle 5th bus write
cycle 6th bus write
cycle
Address Data Address Data Address Data Address Data Address Data Address Data
Reset/read 1 XXXXh F0h Read
Address Read
Data
Reset/read 4 5555h AAh 2AAAh 55h 5555h F0h Read
Address Read
Data
Autoselect ID
read 4 5555h AAh 2AAAh 55h 5555h 90h
00h
MFR code 52h
01h
Device code A4h
XXX02h
Sector
protection
01 = protected
00 = unprotected
Program 4 5555h AAh 2AAAh 55h 5555h A0h Program
Address Program
Data
Chip erase 6 5555h AAh 2AAAh 55h 5555h 80h 5555h AAh 2AAAh 55h 5555h 1 0h
Sector erase 6 5555h AAh 2AAAh 55h 5555h 80h 5555h AAh 2AAAh 55h Sector
Address 30h
Sector erase
suspend 1 XXXXh B0h
Sector erase
resume 1 XXXXh 30h
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Item Description
Reset/read
Initiate read or reset operations by writing the read/rese t command sequence in to the command
regis ter. This al lo ws the micro proce ssor to r etri ev e data fro m the memory . D evic e remain s in read mo de
until command regist er cont en ts are altered.
Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no
spurious memory content alterations during power up.
ID read
AS29F040 provides manufacturer and devic e codes in two ways. External PR OM progra mm ers typ ic a lly
access the device codes by driving +12V on A9. AS29F040 also contains an ID read command to read
the device code with only +5V, since multiplexing +12V on address lines is generally undesirable.
Initiate dev ice ID read by writing the ID read command sequence into the command register. Follow
with a read sequence from address XXX00h to re turn MFG code. Follow ID read comm and sequence
with a read sequence from address XXX01h to return device code.
To verify write protect stat us on sector s, read address XXX02h . Secto r addresses A1 8–A16 produc e a1
on DQ0 for protected sector and a 0 for unprotected sector.
Exit from ID read mode with Read/Reset command seq uence.
Byte/w ord
programming
Programming the AS29F040 is a four bus cycle operation performed on a byte-by-byte basis. Two
unlock write cycles precede the program setup command and program data wr ite cycle. Upon
execution of the program command, no additional CPU controls or timings are necessary. Addresses are
latched on the falling edge of CE or WE, whichever is last; data is latched on the rising edge of CE or
WE, whic hever is first. The AS29F040’s automated on-c hip program algor ithm provides adequate
internally-generated programming pulses and verifies the programmed cell margin.
Check programming status by sampling data on the DATA polling (DQ7), or toggle bit (DQ6). The
AS29F040 returns the equivalent data that was written to it (as opposed to complemented data), to
complete the programming operation.
The AS29F040 ignores commands wri tten d uring the programming operation.
AS29F040 al lows programming i n any sequence, acro ss any sector boundary. Changing data from 0 to 1
requires an erase operation. Attempting to program data 0 to 1 results in DQ5 = 1 (exceeded
programming time limits); reading this data after a read/reset operation returns a 0. When
programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state , areset
command returns the device to read mode.
Chip erase
Chip erase requires six bus cycles: two unlock write cycles; a s etup co mma nd , two additional unlock
write cycles; and finally th e Chip erase command.
Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase
algorithm is invok ed with the Chip erase command sequence, AS29F040 automatically programs and
verifies the entire memor y array for an all-zero pattern pri or to erase. The AS29F040 returns to read
mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit.
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Sector erase
Sector erase requires six bus cycles: two unlock write cycles, a setup command, two addit ional unlock
write cycles, and finally the sector erase command. Identify the sector to be erased by addressing any
location in the sector. The address is latched on the falling edge of WE; the command, 30h, is latched
on the rising edge of WE. The sector erase operation begins after a 80 µs time-out.
To erase multiple se ctors, write the sector erase comma nd to each of the addresses of sectors to erase
after foll owing the six bus cycle operation above. Timing between writes of additional sectors must be
<80 µs, or the AS29 F040 ignores the command and erasure begins. During the erase time-out period
any falling edge of WE resets the time-out. Any command (oth er than sector erase o r era se suspend)
during the time-out period resets the AS29F040 to read mode, and the device ignores the sector erase
command string. Erase such ignored sectors by restarting the sector erase command on the ignored
sectors.
The entire array need not be written with 0s prior to erasure. AS29F040 writes 0s to the entire sector
pri or to e l ectrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors
unaffected. AS29F040 requires no CPU control or timing signals during sector erase operations.
Automatic sector erase begins after erase time-out from the last rising edge of WE from the sector eras e
command st re am and end s when the D ATA polling (DQ7) is logica l 1. D ATA pol lin g mu st be per formed
on addresses that fall within the sectors being erased. AS29F040 returns to read mode after sector erase
unless DQ5 is set high by exceeding the time limit.
Erase suspend
Erase suspend allows interruption of sector erase operations to perform data reads from or writes to
a sector not being erased. Erase suspend applies only during sector erase operations, including the time-
out period. Writing an erase suspend command during sector erase time-out results in immediate
termination of the time-out period and suspension of erase operation.
AS29F040 ignores any commands during erase suspend other than read/reset, program, or erase
resume commands. Writing the Erase Resume command continues erase operations. Addresses are
DON’T CARE when writing Erase suspend or Erase resume commands.
AS29F040 takes 0.2–15 µs to suspend erase operations after receiving erase suspend command. To
determine completion of erase suspend, check DQ6 after selecting an address of a sector not being
erased. Check DQ2 in conjunction with DQ6 to determine if a sector is being erased. AS29F040
ignores redundant writes of erase suspend.
While in erase-suspend mode AS29F040 allows reading data (erase-suspend-read mode) from or
programming data (erase-suspend-program mode) to an y sector not undergoing sector erase, treated as
standard read or standard programming mode. AS29F040 defaults to erase-suspend-read mode while
an erase operation has been suspended.
Write t he resu me comma nd 30h to c ont inue operation of sector erase. AS29F0 4 0 ig nores redundant
writes of the resume command. AS29F040 permits multiple suspend/resume operations during sector
erase.
Sector protect
When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for
about <1 µs. When attempting to erase a protected sector, DATA polling and Toggle Bit 1 (DQ6) are
activated for about <5 µs. In both cases , the device returns to read mo de without alterin g the specified
sectors.
Item Description
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DATA polling
(DQ7)
Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects complement
of data last written when read dur ing the automated on-chip algorithm (0 during erase algorithm);
reflects true data when read after completion of an automated on-chip algorithm (1 after completion of
erase agorithm).
Toggle bit 1 (DQ6)
Active during automated on-chip algorithms or sector time outs. DQ6 toggles when CE or OE toggles,
or an Erase Resume command is invoked. When the automated on-chip algorithm is complete, DQ6
stops toggling and valid data can be read. DQ6 is valid after the rising edge of the fourth pulse of WE
during programming; after the rising edge of the sixth WE pulse dur ing chip erase; after the last rising
edge of the sector erase WE pulse for sector erase. F or protect ed sectors, DQ6 toggles for <1 µs d ur ing
writes, and <5 µs during erase (if all selected sectors are protected).
Exceeding time
limit (DQ5)
Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains
active; CE powers the device down to 2 mA. If DQ5 = 1 during chip erase, all or some sectors are
defective; during sect or e r ase, the sector is defective ( in this case, reset the dev i ce and execute
a program or erase command sequence to continue working with functional sectors); during byte
programming, that particular byte is defecti v e. Attempting to program 0 to 1 will set DQ5 = 1.
Sector erase timer
(DQ3)
Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands will
be accepted. If DQ3 = 0, the de vice will accept additional sector erase commands. Check DQ3 before
and after each Sector Erase command to verify that the command was accepted.
Toggle bit 2 (DQ2)
During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector be in g erased.
During chip erase, DQ2 toggles wi th OE or CE for all addresses. If DQ5 = 1, DQ2 toggles only at sector
addresses where failure occurred, and will not toggle at other sector addresses. Use DQ2 in conjunction
with DQ6 to determine whether device is in auto erase or erase suspend mode.
Status DQ7 DQ6 DQ5 DQ3 DQ2
In progress
Auto programming (byte) DQ7 Toggle 0 0 No toggl e
Program/erase in auto erase 0 Toggle 0 1 Toggle*
* Toggle s with OE or CE only for erasing or erase suspended sector addresses.
Erase
suspend
mode
Read erasing sector 1 No toggle 0 0 Toggle
Read non-erasing
sector Data Data Data Data Data
Program in erase
suspend DQ7 Toggle 0 0 Toggle*
Exceeded time limits Auto programming (byte) DQ7 Toggle 1 0 No togg l e
Program/erase in auto erase 0 Toggle 1 1 Toggle†
† Toggle s with OE or CE only for erasing or erase suspended sector addresses.
Program in erase suspend DQ7 Togg l e 1 0 No togg le†
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*The system software should check the status of DQ3 prior to and
following each subsequent sector erase command to ensure command
completion. The device may not have accepted the command if DQ3 is
high on second status check.
Write program command sequence
(see below)
DATA poll device-program
Programming completed
5555h/AAh
2AAAh/55h
5555h/A0h
Program address/program data
Prog ram command sequence
Erase complete
DATA polling or toggle bit
successfull y compl eted
Write erase command sequence
(see below)
5555h/AAh
2AAAh/55h
5555h/80h
Chip erase command sequence
5555h/AAh
2AAAh/55h
5555h/10h
Sector erase command sequence
Sector address/30h
Sector address/ 30h
Sector address/ 30h
Optional mu ltip le
sector erase commands*
5555h/AAh
2AAAh/55h
5555h/80h
5555h/AAh
2AAAh/55h
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*VA = Byte address for programming. VA = any of the sector addresses
within the sector being erased during sector erase. VA = valid address
equals any non-protected sector group address during chip erase.
†DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not change
simultaneously.
7RJJOH#ELW#DOJRULWKP
* DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling when
DQ5 changes to 1.
Read byte (DQ0–DQ7)
Address = VA
*
Read byte (DQ0–DQ7)
Address
=
VA
*
NO
DONE
NO
NO
YES
YES
YES
DONE
DQ7 =
data?
YES
NO
Is time
elapsed = 1ms?
DON
E
START
Issue Reset/read
command
Addr = X
Data = F0h
DQ5 = 1?
DQ7 =
data†?
Read byte (DQ0–DQ7)
Address = don’t care
Read byte (DQ0–DQ7)
Address = don’t care
NO
DONE
YES
YES
YES
NO
NO
DONE
DQ6
toggle?
toggle*?
DQ5 = 1?
START
two times with OE toggling
Does
two times with OE toggling
Does
DQ6
DONE
Issue Reset/read
command
Addr = X
Data = F0h
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Start
VA* = 0000h
Is VA = VA_Start†?
Increment VA
NO
YES
Program byte with customer data
ADDR = VA
Increment VA
Is VA = VA_End**?
NO
Increment VA
YES
Prog ram byte with 00h
ADDR = VA
Program byte with 00h
ADDR = VA
NO
Increment VA Is VA = 7FFFFh?
YES
Verify data
ADDR = VA
Verify OK? NO FAIL
YES
Is VA = VA_End?
Increment VA NO
YES
PASS
Reset VA = 0000
* VA = Current Address
† VA_Start = Starting Address of Customer Code
** VA_End = Ending Address of Customer Code
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* Not more than one output tested simultaneously. Duration of the short circuit must not be >1 second. OUT = 0.5V was selected to avoid test problems
caused by tester ground degradation. (This para m eter is sampl ed and not 100% tested, but guaranteed by characterization.)
† Th e ICC current listed includes bot h the DC o perating c urrent and the frequency de pendent compo nent (@ 6 MHz). The frequency component typically is
less than 2 mA /MHz w ith OE at VIH.
** ICC active while program or erase operations are in prog ress.
0D[LPXP#QHJDWLYH#RYHUVKRRW#ZDYHIRUP
0D[LPXP#SRVLWLYH#RYHUVKRRW#ZDYHIRUP
Parameter Symbol Test conditions Min Max Unit
Input load current ILI VIN = VSS to VCC, VCC = VCC M AX -±1
µA
A9 Input load current ILIT VCC = VCC MAX, A9 = 12.5V 90 µA
Output le akage curren t ILO VOUT = VSS to VCC, VCC = VCC MAX -±1
µA
Output short circuit current*IOS VOUT = 0.5V - 200 mA
Acti ve current, read @ 6MHz†ICC CE = VIL, OE = VIH -30mA
Active cur rent, program/erase** ICC2 CE = VIL, OE = VIH -60mA
Standby current (TTL) ISB1 CE = OE = VIH, VCC = VCC MAX -1.0mA
Standby current (CMOS) ISB2 CE = VCC + 0.5V, OE = VIH,
VCC = VCC MAX -400µA
Input lo w voltage VIL -0.5 0.8 V
Input high voltage VIH 2.0 VCC + 0.5 V
Output low voltage VOL IOL = 12mA, VCC = VCC MIN -0.45V
Output high volta ge VOH1 IOH = -2.5 mA, VCC = VCC MIN 2.4 - V
VOH2 IOH = -100 µA, VCC = VCC MI N VCC - 0.4 - V
Low VCC lock out voltage VLKO 2.8 4.2 V
Input HV select voltage VID 11.5 12.5 V
20 n s20 ns20 n s
-2.0V
-0.5V
+0.8V
20 ns20 ns20 ns
VCC + 2.0V
VCC + 0.5V
+ 2.0V
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JEDEC
Symbol Std
Symbol Parameter
-55 -70 -90 -120 -150
UnitMin Max Min Max Min Max Min Max Min Max
tAVAV tRC Read cycle time 55 - 70 - 90 - 120 - 150 - ns
tAVQV tACC Address to output delay - 55 - 70 - 90 - 120 - 150 ns
tELQV tCE Chip enable to output - 55 - 70 - 90 - 120 - 150 ns
tGLQV tOE Output enable to output - 25 - 30 - 35 - 50 - 55 ns
tEHQZ tDF Chip enable to output High Z - 15 - 20 - 20 - 30 - 35 ns
tGHQZ tDF Output enable to output High Z - 15 - 20 - 20 - 30 - 35 ns
tAXQX tOH Output hold time from addresses,
CE or OE, whicheve r occurs first 0-0-0-0-0-ns
Undefined / don’t care
Falling input
Rising input
Addresses stable
Addresses
tRC
tACC
tOE
tCE tOH
tDF
CE
OE
WE
Outputs High Z High Z
Output valid
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4646
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JEDEC
Symbol Std
Symbol Parameter
-55 -70 -90 -120 -150
UnitMin Max Min Max Min Max Min Max Min Max
tAVAV tWC Write cycle time 55 - 70 - 90 - 120 - 150 - ns
tAVWL tAS Address setup time 0 - 0 - 0 - 0 - 0 - ns
tWLAX tAH Address hold time 40 - 45 - 45 - 50 - 50 - ns
tDVWH tDS Data setup time 25 - 30 - 45 - 50 - 50 - ns
tWHDX tDH Data hold time 0-0-0-0-0- ns
tOES Output enable setup time 0 - 0 - 0 - 0 - 0 - ns
tOEH Output enable hold time:
Toggle and DATA polling 10 - 10 - 10 - 10 - 10 - ns
tGHWL tGHWL Read recover time before write 0 - 0 - 0 - 0 - 0 - ns
tELWL tCS CE setup time 0-0-0-0-0- ns
tWHEH tCH CE hold time 0-0-0-0-0- ns
tWLWH tWP Write pulse width 35 - 35 - 45 - 50 - 50 - ns
tWHWL tWPH Write pulse width high 20 - 20 - 20 - 20 - 20 - ns
tWHWH1 tWHWH1 Programming pulse time 15 - 15 - 15 - 15 - 15 - µs
tWHWH2 tWHWH2 Erase operation 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - sec
Addresses
CE
OE
WE
DATA
VSS
tWC tAS
tAH
tGHWL;tOES
tWP
tCS tWPH
tDH
tWHWH1 or 2
tDS
DQ7DOUT
Program
5555h Program address Program address
3rd bus cycle
tCH
DATA polling
data
A0h
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JEDEC
Symbol Std
Symbol Parameter
-55 -70 -90 -120 -150
UnitMin Max Min Max Min Max Min Max Min Max
tAVAV tWC Write cycle time 55 - 70 - 90 - 120 - 150 - ns
tAVEL tAS Address setup time 0 - 0 - 0 - 0 - 0 - ns
tELAX tAH Address hold time 40 - 45 - 45 - 50 - 50 - ns
tDVEH tDS Data setup time 25 - 30 - 45 - 50 - 50 - ns
tEHDX tDH Data hold time 0-0-0-0-0-ns
tOES Output enable setup time 0 - 0 - 0 - 0 - 0 - ns
tOEH Output enable hold time:
Toggle and DATA p ollin g 10 - 10 - 10 - 10 - 10 - ns
tGHEL tGHEL Read recover time before
write 0-0-0-0-0- ns
tWLEL tWS WE setup time 0-0-0-0-0- ns
tEHWH tWH WE hold time 0-0-0-0-0-ns
tELEH tCP CE pulse width 35 - 35 - 45 - 50 - 50 - ns
tEHEL tCPH CE pulse width high 20 - 20 - 20 - 20 - 20 - ns
tWHWH1 tWHWH1 Programming pulse tim e 15 - 15 - 15 - 15 - 15 - µs
tWHWH2 tWHWH2 Erase operation 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - sec
Addresses
WE
OE
CE
DATA
Program addr e ss5555h Pro gram address
A0h Program DQ7D
OUT
tWC tAS tAH
tCP
tCPH tDH
tDS
tWHWH1 or 2
DATA polling
data
tGHEL, tOES
tWS
tWH
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4848
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Addresses
CE
OE
WE
Data
5555h 2AAAh 5555h 5555h 2AAAh Sector address
tWC tAS
tAH
tGHWL
AAh 55h 80h AAh 55h 30h
10h for Chip Erase
tWP
tCS
tWPH
tDH
tDS
tWC
CE
OE
WE
DQ7
tCH
tOH
tWHWH 1 or 2
tOE
tOEH
tCE
tDF
High Z
Input DQ7 Output DQ7 Output
CE
WE
OE
DQ6
tOEH
tDH tOE
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(UDVH#DQG#SURJUDPPLQJ#SHUIRUPDQFH
/DWFKXS#WROHUDQFH#
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time.
$&#WHVW#FRQGLWLRQV
$EVROXWH#PD[LPXP#UDWLQJV
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause pe rmanent damag e to the device. Th is is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time.
Parameter Limits UnitMin Typical Max
Sector erase and verify-1 time (excludes 00h programming prior to erase) -1.0 - sec
Byte program time - 45 - µs
Chip programming time - 23 -sec
Erase/program cycles - - 10,000 cycles
Parameter Min Max Unit
Input voltage with respect to VSS on A9 and OE -1.0 +13.0 V
Input voltage with respect to VSS on all DQ, address and control pins -1.0 VCC+1.0 V
Current -100 +100 mA
Parameter Symbol Min Max Unit
Input voltag e (Input or DQ pin) VIN –2.0 +7.0 V
Input vol tag e (A9 pin, OE)V
IN –2.0 +13.0 V
Power supply voltage VCC -0.5 +5.5 V
Operating temperature T OPR –55 +125 °C
Storage temperature (plast ic) TSTG –65 +125 °C
Short circuit output current IOUT -200mA
100 pF*
Device under Test
*including s cope
and jig capacitance
VSS
Test condition Unit
Output load 1 TTL gate
Input rise and fall times 5 ns
Input p ul s e leve ls 0.0- 3. 0 V
Input timi ng measurem ent reference l evels 1. 5 V
Output timing measurem ent refere nce levels 1.5
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Parameter Symbol Min Typ Max Unit
Supply voltage VCC +4.5 5.0 +5.5 V
VSS 000V
Input voltage VIH 2.0 - VCC + 0.5 V
VIL –0.5 - 0.8 V
Symbol Parameter Test setup Typ Max Unit
CIN Input capacitance VIN = 0 6 7.5 pF
COUT Outp ut capac itance VOUT = 0 8.5 12 pF
CIN2 Control pi n capacitance VIN = 0 7.5 9 pF
Symbol Parameter Test setup Typ Max Unit
CIN Input capacitance VIN = 0 6 7.5 pF
COUT Outp ut capac itance VOUT = 0 8.5 12 pF
CIN2 Control pi n capacitance VIN = 0 7.5 9 pF
P ar amet er Temp . (°C) Min Unit
Mini mum pattern data ret ent ion ti me 150° 10 years
125° 20 years
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DID 11-20011-A. Copyright ©2000 Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and Intelliwatt™ are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this web site and its products at any tim e without notice. Allian ce ass umes no responsibility for a ny errors that may a pp e ar in this web site . Alli ance does not assume any responsi-
bility o r li a bi li t y a risi ng o u t of t he ap pl ic ation or use of an y pr oduc t desc ri b ed he rei n, and disc l aims any express or implied warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except
as expres sly a gre e d to i n A llia nc e' s Terms and Co ndit ions of Sale (ava ilable from Allia n ce ). All sale s of Al li an ce products are made exclusively according to Alliance's Terms and Conditions of S ale. The purchase of products from Alliance does not
convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems
where a malfunction o r failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indem-
nify Alliance against all claims arising from such use.
®
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Package \ Access time 5 5ns
(commercial/industrial) 70 ns
(commercial/industrial) 90 ns
(commercial/industrial) 120 ns
(commercial/industrial) 150 ns
(commercial/industrial)
TSOP, 8×20 mm, 32-pin AS29F040-55TC
AS29F040-55TI AS29F040-70TC
AS29F040-70TI AS29F040-90TC
AS29F040-90TI AS29F040-120TC
AS29F040-120TI AS29F040-150TC
AS29F040-150T
PLCC, 0.55×0 .45”, 32-p in AS29F040-55LC
AS29F040-55LI AS29F040-70LC
AS29F040-70LI AS29F040-90LC
AS29F040-90LI AS29F040-120LC
AS29F040-120LI AS29F040-150LC
AS29F040-150LI
* Industrial and Commercial temperature ran ge available
AS29F 040 –XXX X X
Flash EEPROM prefix Device number Addres s ac cess time Package : L= PLCC
T= TSOP
Temperature range:
C = Commercial: 0°C to 70°C
I = Industrial: -40°C to 85°C
e
f
g
b
a
c
d
i
h
j
0–5°
32-pin TSOP
min
(mm) max
(mm)
a1.20
b0.25
c0.50.7
d0.10.21
e 18.30 18.50
f 19.80 20.20
g 7.90 8.10
h 0.95 1.05
i 0.05 0.15
j0.50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
20
19
15
16 18
17
32-pin TSOP
32-pin PLCC
12 32313043 29
28
27
26
25
24
23
21
22
5
6
7
8
9
10
11
13
12
1716 18 19 2014 15
a
b
dce
fg
h
i
j
JEDEC o utline MS-016 AE
Body size 0.450 in. × 0.550 in.
Package thickness 0.110 in.
Board standoff 0.020 i n. (min)
Lead pitch 0.050 in.
Coplanarity 0.004 in. (max)
32-pin PLCC
typical (inch)
a0.49
b0.45
c0.59
d0.55
e0.52
f0.09
g0.136
h0.075
i0.52
j0.028
