LT3965/LT3965-1
1
Rev. B
For more information www.analog.comDocument Feedback
TYPICAL APPLICATION
FEATURES DESCRIPTION
8-Switch Matrix LED Dimmer
The LT
®
3965/LT3965-1 is an LED bypass switching
device for dimming individual LEDs in a string using a
common current source. It features eight individually
controlled floating source 17V/330mΩ NMOS switches.
The eight switches can be connected in parallel and/or
in series to bypass current around one or more LEDs in
a string. The LT3965 is initialized with all switches off
(LEDs on), and the LT3965-1 is initialized with all switches
on (LEDs off)The LT3965/LT3965-1 uses the I2C serial
interface to communicate with the microcontroller. Each
of the eight channels can be independently programmed
to bypass the LED string in constant on or off, or PWM
dimming with or without fade transition. Using the fade
option provides 11-bit resolution logarithmic transition
between PWM dimming states. The LT3965/LT3965-1
provides an internal clock generator and also supports
external clock source for PWM dimming. The LT3965/
LT3965-1 reports fault conditions for each channel such
as open LED and shorted LED. The four address select
pins allow 16 LT3965/LT3965-1 devices to share the I2C
bus. The device is available in a 28-lead TSSOP package.
APPLICATIONS
n Eight Independent 17V 330mΩ NMOS Switches
n Independent On/Off/Dimming Control of 1 to 4 LEDs
for Each Switch
n I2C Multidrop Serial Interface with Programmable
Open LED and Shorted LED Fault Reporting
n 16 Unique I2C Addresses
n VDD Range: 2.7V to 5.5V and VIN Range: 8V to 60V
n Digital Programmable 256:1 PWM Dimming
n Fade Transition Between PWM Dimming States
n Optional Internal Clock Generator or External Clock
Source for PWM Dimming
n Open LED Overvoltage Protection
n Flicker Free PWM Dimming
n AEC-Q100 Qualified for Automotive Applications
n Automotive LED Headlight Clusters
n Large LED Displays
n Automated Camera Flash Equipment
n RGBW Color Mixing Lighting
3965 TA01
L1
33µH
D1
D2 D3
D4
D5
500mA
LED+
LED+
LED–
VLED
26V
VIN
40V
0.01µF
VIN ISP
0.5Ω
ISN
RT DIM/SS VC
LT3955
EN/UVLO
PWM
VREF
CTRL
PGND
INTVCC
PWMOUT
SYNC
VMODE
FB
GND
GNDK
SW
28.7k
375kHz
VCC
5V
SDA
SCL
ALERT
28k
500Hz DIMMING FREQUENCY
L1: WURTH 744066330
D1: DFLS260
D2, D3: CMSD6263S 2 IN 1 PACKAGE
D4, D5: PMEG6010CEH
M1: VISHAY Si7309DN
Q1, Q3: ZETEX FMMT593
Q2: ZETEX FMMT493
10k10k10k
1k
20k
1µF
50V
2.2nF 1µF
0.1µF
100V
0.1µF
28k
49.9k
EN/UVLO
BIAS
BIAS UVLO DETECT
BIAS
9.09k
1k
IN4148
Q1
M1
Q2
750Ω
1k
GND
LT3965/
LT3965-1
VDD
EN/UVLO EN/UVLO
SDA
SCL
ALERT
RTCLK
ADDR1
ADDR2
ADDR3
ADDR4
LEDREF
DRN8
DRN7
SRC8
DRN6
SRC7
DRN5
SRC6
DRN4
SRC5
DRN3
SRC4
DRN2
SRC3
DRN1
SRC2
SRC1
VIN
0.1µF
1µF
100V
Q3
Matrix LED Dimmer Powered by a Buck Mode LED Driver
All registered trademarks and trademarks are the property of their respective owners.
LT3965/LT3965-1
2
Rev. B
For more information www.analog.com
ABSOLUTE MAXIMUM RATINGS
VIN ............................................................................60V
VIN-SRC[8:1] ..........................................................–0.3V
DRN[8:1] ...................................................................60V
SRC[8:1] ....................................................................60V
LEDREF .....................................................................60V
DRN[8:1]-SRC[8:1] (Each Channel) ................–0.3V, 25V
EN/UVLO ...................................................................12V
VDD .............................................................................6V
SDA, SCL, ALERT ............................ –0.3V to VDD + 0.3V
RTCLK ......................................................................... 6V
ADDR[4:1] ...................................................................6V
Operating Junction Temperature Range (Note 2)
LT3965E/LT3965E-1/LT3965I/LT3965I-1 –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Note 1)
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3965EFE#PBF LT3965EFE#TRPBF LT3965FE 28-Lead Plastic TSSOP –40°C to 125°C
LT3965EFE-1#PBF LT3965EFE-1#TRPBF LT39651FE 28-Lead Plastic TSSOP –40°C to 125°C
LT3965IFE#PBF LT3965IFE#TRPBF LT3965FE 28-Lead Plastic TSSOP –40°C to 125°C
LT3965IFE-1#PBF LT3965IFE-1#TRPBF LT39651FE 28-Lead Plastic TSSOP –40°C to 125°C
AUTOMOTIVE PRODUCTS**
LT3965EFE#WPBF LT3965EFE#WTRPBF LT3965FE 28-Lead Plastic TSSOP –40°C to 125°C
LT3965IFE#WPBF LT3965IFE#WTRPBF LT3965FE 28-Lead Plastic TSSOP –40°C to 125°C
LT3965EFE-1#WPBF LT3965EFE-1#WTRPBF LT39651FE 28-Lead Plastic TSSOP –40°C to 125°C
LT3965IFE-1#WPBF LT3965IFE-1#WTRPBF LT39651FE 28-Lead Plastic TSSOP –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
thesemodels.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
FE PACKAGE
28-LEAD PLASTIC TSSOP
θJC = 10°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DRN8
VIN
EN/UVLO
ALERT
SCL
SDA
VDD
RTCLK
ADDR1
ADDR2
ADDR3
ADDR4
LEDREF
SRC1
SRC8
DRN7
SRC7
DRN6
SRC6
DRN5
SRC5
DRN4
SRC4
DRN3
SRC3
DRN2
SRC2
DRN1
29
GND
PIN CONFIGURATION
LT3965/LT3965-1
3
Rev. B
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 40V, VDD = EN/UVLO = 5V, LEDREF = 3V, SRC = 0V, ADDR[4:1] not
connected, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Input Supply Voltage l2.7 5.5 V
VDD Operating IQSCL = SDA =5V (I2C Bus Idle), RTCLK = 28k 1.3 1.8 mA
VDD Shutdown IQEN/UVLO < 0.4V
EN/UVLO = 1.15V
0.1 1
8
µA
µA
VIN Operating Voltage All Channels VOTH[1:0] = VSTH[1:0] = “00” (Note 3) l8 60 V
VIN Operating IQ (Channel Not Switching) All Channels VOTH[1:0] = VSTH[1:0] = “00”, LED ON 1 1.4 mA
All Channels VOTH[1:0] = VSTH[1:0] = “11”, LED OFF 2.5 3.3 mA
All Channels VOTH[1:0] = “11”, VSTH[1:0] = “00”,
LED ON
1.5 2 mA
VIN Shutdown IQEN/UVLO < 1.15V 0.1 1 µA
DRN[8:1] Operating Voltage lVIN – 3V V
SRC[8:1] Operating Voltage lVIN – 7.1V V
Current Out of SRC[8:1] Pins (Each Channel) Channel LED Is On (Channel Switch Is Off)
Channel LED Is Off (Channel Switch Is On)
l
l
9
40
13
55
µA
µA
Switch On-Resistance 330 mΩ
Switch Leakage Current DRN = 16V, VOTH[1:0] = 11 5 µA
Switch Transition Time (tr/tf) DRN to 10V through 50Ω Resistor 0.35 0.5 0.65 µs
DRN[8:1] to SRC[8:1] Crowbar Protection
Clamp Voltage
LED or Switch Bypass Current is 500mA l22 25 V
Response Time from SW Crowbar Protection
to SW Secure Protection
LED or Switch Bypass Current is 500mA l1 1.6 µs
Programmable Open LED Threshold (VOTH) VOTH[1:0] = “00” (Note 3)
VOTH[1:0] = “01” (LT3965-1 POR State)
VOTH[1:0] = “10”
VOTH[1:0] = “11” (LT3965 POR State)
l
l
l
l
4.25
8.5
12.75
17
4.5
9
13.5
18
4.75
9.5
14.25
19
V
V
V
V
Programmable Shorted LED Threshold (VSTH)
for LEDREF = 0V
VSTH[1:0] = “00” (Note 3)
VSTH[1:0] = “01”
VSTH[1:0] = “10”
VSTH[1:0] = “11”
l
l
l
l
0.85
0.85
0.85
0.85
1
1
1
1
1.15
1.2
1.25
1.3
V
V
V
V
Programmable Shorted LED Threshold (VSTH)
for LEDREF = 3V
VSTH[1:0] = “00” (Note 3)
VSTH[1:0] = “01”
VSTH[1:0] = “10”
VSTH[1:0] = “11”
l
l
l
l
0.85
3.8
6.7
9.6
1
4
7
10
1.15
4.2
7.3
10.4
V
V
V
V
Programmable Shorted LED Threshold (VSTH)
for LEDREF ≥ 4V
VSTH[1:0] = “00” (Note 3)
VSTH[1:0] = “01”
VSTH[1:0] = “10”
VSTH[1:0] = “11”
l
l
l
l
0.85
4.7
8.5
12.3
1
5
9
13
1.15
5.3
9.5
13.7
V
V
V
V
EN/UVLO Threshold Voltage Falling l1.15 1.24 1.35 V
EN/UVLO Threshold Voltage Rising Hyst. 10 mV
EN/UVLO Input Bias Current Low EN/UVLO = 1.15V 2.2 2.7 3.2 µA
EN/UVLO Input Bias Current High EN/UVLO = 1.33V 10 100 nA
RTCLK Programmable Internal Oscillator or External Clock Source
LED PWM Dimming Frequency
(=RTCLK Programmed Oscillator
Frequency/2048 or External Clock
Frequency/2048)
RTCLK = 80.6kΩ
RTCLK = 28kΩ
RTCLK = 10kΩ
l
l
l
170
450
950
195
500
1090
220
550
1250
Hz
Hz
Hz
LT3965/LT3965-1
4
Rev. B
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 40V, VDD = EN/UVLO = 5V, LEDREF = 3V, SRC = 0V, ADDR[4:1] not
connected, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
RTCLK Output Voltage (Using Internal
Oscillator)
RTCLK = 28kΩ 0.83 0.88 0.93 V
RTCLK Input Low Threshold (RTVIL)l0.4 V
RTCLK Input High Threshold (RTVIH)l1.5 V
RTCLK Input Clock Frequency 2.5 MHz
RTCLK Input Clock Pulse Width High (TRTH) 100 ns
RTCLK Input Clock Pulse Width Low (TRTL) 100 ns
RTCLK Input Clock Ramp Time between RTVIL
and RTVIH (TRTRAMP)
TRTL = 10µs 2.3 µs
Address Select
ADDR[4:1] Input Low l0.25VDD V
ADDR[4:1] Input High l0.75VDD V
ADDR[4:1] Pull-Up Resistance to VDD 300 500 700 kΩ
Alert Status Output
ALERT Output Low Voltage IALERT = 3mA 0.3 0.4 V
ALERT Output High Leakage Current ALERT = 5.5V 0.1 µA
External LED Reference Voltage for Shorted LED Detection
LEDREF Input Linear Range 0 4 V
LEDREF Input Bias Current 0V ≤ LEDREF ≤ 4V –100 100 nA
I2C Port (See Note 5 for I2C Timing Diagram)
SDA and SCL Input Threshold Rising l0.7VDD V
SDA and SCL Input Threshold Falling l0.25VDD V
SDA and SCL Input Hysteresis l0.05VDD V
SDA and SCL Input Current SDA = SCL = 0V to 5.5V –250 250 nA
SDA Output Low Voltage ISDA = 3mA l0.4 V
SCL Clock Operating Frequency l400 kHz
(Repeated) Start Condition Hold Time (tHD_STA)l0.6 μs
Repeated Start Condition Set-Up Time
(tSU_STA)
l0.6 µs
Stop Condition Setup Time (tSU_STO)l0.6 μs
Data Hold Time Output (tHD_DAT(O))l0 900 ns
Data Hold Time Input (tHD_DAT(I))l0 ns
Data Set-Up Time (tSU_DAT)l100 ns
SCL Clock Low Period (tLOW)l1.3 µs
SCL Clock High Period (tHIGH)l0.6 μs
Data Rise Time (tr) CB = Capacitance of One BUS Line (pF) (Note 4) 20 + 0.1CB300 ns
Data Fall Time (tf) CB = Capacitance of One BUS Line (pF) (Note 4) 20 + 0.1CB300 ns
Input Spike Suppression Pulse Width (tSP) 50 ns
Bus Free Time (tBUF)l1.3 µs
LT3965/LT3965-1
5
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
VDD Quiescent Current
vs Temperature
VIN Quiescent Current
vs Temperature
EN/UVLO Threshold
vs Temperature
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3965E/LT3965E-1 is guaranteed to meet performance
specifications from the 0°C to 125°C junction temperature. Specifications
over the –40°C to 125°C operating junction temperature range are
assured by design, characterization and correlation with statistical process
controls. The LT3965I/LT3965I-1 is guaranteed over the full –40°C to
125°C operating junction temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
temperatures greater than 125°C.
Note 3: VOTH[1:0] and VSTH[1:0] register bits are set by LT3965/LT3965-1
I2C commands. VOTH/VSTH programmed by VOTH[1:0]/VSTH[1:0] refer to
the open/shorted LED threshold between DRN and SRC of a channel. For
a channel, VIN > VSRC + VOTH + 2.5V is required for accurate open LED
detection.
Note 4: Rise and fall times are measured at 30% and 70% levels.
Note 5: I2C interface timing diagram.
tSP
tBUF
tSU,STO
tSP
tHD,STA
START
CONDITION
STOP
CONDITION
tSU,STA
tHD,DATI
tHD,DATO
REPEATED START
CONDITION
REPEATED START
CONDITION
tSU,DAT
SDA
SCL
tHD,STA
3965 TD
TEMPERATURE (°C)
–50
V
DD
, I
Q
(mA)
1.8
1.6
1.2
1.4
1.0
0.8 0 50–25 25 100
3965 G01
150
75 125
VDD = 5V
ALL SWITCHES ARE ON
ALL SWITCHES ARE OFF
TEMPERATURE (°C)
–50
V
IN
, I
Q
(mA)
2.8
2.6
2.4
2.2
1.8
2.0
1.6
1.2
1.4
1.0
0.8 0 50–25 25 100
3965 G02
150
75 125
VIN = 40V, LEDREF = 3V
VOTH[1:0] = 11, VSTH[1:0] = 00,
SWITCHES ARE OFF
VOTH[1:0] = VSTH[1:0] = 00,
SWITCHES ARE OFF
VOTH[1:0] = VSTH[1:0] = 11,
SWITCHES ARE ON
TEMPERATURE (°C)
–50
EN/UVLO THRESHOLD (V)
1.27
1.26
1.24
1.25
1.23
1.22
1.21 0 50–25 25 100
3965 G03
150
75 125
FALLING
RISING
TA = 25°C, unless otherwise noted.
LT3965/LT3965-1
6
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Switch Open LED Protection
Response Time vs Temperature
Open LED Threshold Rising vs VIN,
Temperature for VOTH[1:0] = 00
Open LED Threshold Rising vs VIN,
Temperature for VOTH[1:0] = 01
Switch On-Resistance
vs Temperature
Switching Transition Time
vs Temperature
Shorted LED Threshold Falling vs
LEDREF
EN/UVLO Hysteresis Current
vs Temperature
RTCLK vs PWM Dimming
Frequency
PWM Dimming Frequency
vs Temperature
TEMPERATURE (°C)
–50
EN/UVLO CURRENT (µA)
3.0
2.8
2.4
2.6
2.2
2.0 0 50–25 25 100
3965 G04
150
75 125
TEMPERATURE (°C)
–50
SWITCH ON-RESISTANCE (mΩ)
550
500
400
450
350
250
300
200 0 50–25 25 100
3965 G07
150
75 125
TEMPERATURE (°C)
–50
RESPONSE TIME (µs)
1.40
1.30
1.35
1.25
1.15
1.20
1.10
1.00
1.05
0 50–25 25 100
3965 G10
150
75 125
VIN VOLTAGE (V)
5
4.8
4.6
4.4
4.2
4.9
4.7
4.5
4.3
4.1
4.0 25 4515 35 55
20 4010 30 50
SRC = 0V –50°C
25°C
150°C
VIN VOLTAGE (V)
5
OPEN LED THRESHOLD (V)
10
8
9
7
625 4515 35 55
3965 G12
6020 4010 30 50
SRC = 0V –50°C
25°C
150°C
TEMPERATURE (°C)
–50
TRANSITION TIME (ns)
600
550
450
500
400 0 50–25 25 100
3965 G08
150
75 125
RISING
FALLING
LEDREF (V)
0
SHORTED LED THRESHOLD (V)
14
6
10
2
8
12
4
031 2 4
3965 G09
5
VSTH[1.0] = 00
VSTH[1.0] = 01
VSTH[1.0] = 10
VSTH[1.0] = 11
VIN – SRC > 15V
DIMMING FREQUENCY (Hz)
0
R
TCLK
(kΩ)
160
140
100
120
80
40
60
20
0400 800200 600
3965 G05
1000
TEMPERATURE (°C)
–50
DIMMING FREQUENCY (Hz)
540
500
520
480
460 0 50–25 25 100
3965 G06
150
75 125
RTCLK = 28k
TA = 25°C, unless otherwise noted.
LT3965/LT3965-1
7
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Open LED Threshold Rising vs VIN,
Temperature for VOTH[1:0] = 10
Open LED Threshold Rising vs VIN,
Temperature for VOTH[1:0] = 11
Shorted LED Threshold Falling vs
VIN, Temperature for VOTH[1:0] = 00
Shorted LED Threshold Falling vs
VIN, Temperature for VSTH[1:0] = 01
RTCLK Input Clock Frequency vs
Fading Time RTCLK vs Fading Time
Shorted LED Threshold Falling vs
VIN, Temperature for VSTH[1:0] = 11
Shorted LED Threshold Falling vs
VIN, Temperature for VSTH[1:0] = 10
Current Out of SRC Pin vs
Temperature
VIN VOLTAGE (V)
5
OPEN LED THRESHOLD (V)
15.0
12.0
9.0
13.5
10.5
7.5
6.0 25 4515 35 55
3965 G13
60
20 4010 30 50
SRC = 0V
–50°C
25°C
150°C
VIN VOLTAGE (V)
5
OPEN LED THRESHOLD (V)
20
16
12
8
18
14
10
625 4515 35 55
3965 G14
60
20 4010 30 50
SRC = 0V
–50°C
25°C
150°C
VIN VOLTAGE (V)
5
SHORTED LED THRESHOLD (V)
1.2
1.0
1.1
0.9
0.8 25 4515 35 55
3965 G15
60
20 4010 30 50
LEDREF = 3V
SRC = 0V
–50°C
25°C
150°C
VIN VOLTAGE (V)
5
SHORTED LED THRESHOLD (V)
4.2
4.0
4.1
3.9
3.8 25 4515 35 55
3965 G15
60
20 4010 30 50
LEDREF = 3V
SRC = 0V
–50°C
25°C
150°C
FADING TIME (ms)
300
RTCLK INPUT CLOCK FREQUENCY (MHz)
3.0
2.6
1.8
2.2
1.4
0.6
1.0
0.2 600450 900
3965 G20
1200
750 1050
FADING UP
FADING DOWN
PWM DIMMING END POINTS
0.4% AND 99.6%
FADING TIME (ms)
300
R
TCLK
(kΩ)
55
50
40
45
35
20
25
15
10
30
5600450 900
3965 G21
1200
750 1050
FADING UP
FADING DOWN
PWM DIMMING END POINTS
0.4% AND 99.6%
VIN VOLTAGE (V)
15
SHORTED LED THRESHOLD (V)
11
9
10
8
7
625 4535 55
3965 G18
60
20 4030 50
LEDREF = 3V
SRC = 0V
–50°C
25°C
150°C
TEMPERATURE (°C)
–50
CURRENT OUT OF SRC (µA)
50
40
20
30
10
00 50–25 25 100
3965 G19
150
75 125
SWITCH IS ON
SWITCH IS OFF
VIN VOLTAGE (V)
10
SHORTED LED THRESHOLD (V)
7.5
6.5
7.0
6.0
5.5 25 4515 35 55
3965 G17
60
20 4030 50
LEDREF = 3V
SRC = 0V
–50°C
25°C
150°C
TA = 25°C, unless otherwise noted.
LT3965/LT3965-1
8
Rev. B
For more information www.analog.com
PIN FUNCTIONS
VIN: Input Supply Pin for LED Bypass Switches and
Fault Detectors. Must be locally by-passed with a 1µF
(or larger) capacitor placed close to this pin. For proper
channel switch bypass operation, V
IN
must be at least
7.1V higher than channel source voltage.
EN/UVLO: Shutdown and Undervoltage Detect Pin. An
accurate 1.24V (nominal) falling threshold with exter-
nally programmable hysteresis detects when VIN – SRC
is okay to enable the part. Rising hysteresis is generated
by an external resistor and an accurate internal 2.7µA
pull-down current. EN/UVLO going high (from below the
falling threshold to above the rising threshold) resets the
device to an initial power-on condition, which all registers
are loaded with a default value. Tie to 0.4V, or less, to dis-
able the device and reduce VDD and VIN quiescent current
below 1µA. Typically this pin is tied to a PNP based level
shifter to ensure the part is enabled only when VIN is at
least 7.1V higher than channel source voltage.
ALERT: Alert Output for Fault Condition Report. ALERT pin
is asserted (pulled low) to indicate that an open LED fault
condition or/and a shorted LED fault condition or/and an
overheat fault condition are detected. The ALERT pin is
deasserted (released to high) after the part sends its Alert
Response Address successfully or the fault condition is
cleared by an I2C write command.
RTCLK: External PWM Clock Input and Internal Oscillator
Frequency Programming Pin. Set the internal oscillator
frequency using a resistor to GND if the internal oscillator
is used for PWM dimming. An external clock source able
to sink 500µA at 0.4V can be used for PWM dimming by
driving RTCLK above and below VIH and VIL respectively
to override the internal oscillator. Do not leave the RTCLK
pin open. Place the resistor close to the IC if a resis-
tor is used to set the internal oscillator frequency. LED
PWM dimming frequency equals the programmed internal
oscillator frequency divided by 2048 or the external clock
frequency divided by 2048.
LEDREF: LED Reference Voltage Input. This pin is used to
set the normal operating VF of the LED. The shorted LED
threshold VSTH can be programmed through I2C Serial
Interface to one of the following four values: 1V, VLEDREF
+ 1V, 2 • VLEDREF + 1V and 3 • VLEDREF + 1V. Connecting
this pin to GND sets the shorted LED threshold to 1V.
The internal value of VLEDREF becomes fixed at 4V if more
than 4V is applied to this pin. Do not leave this pin open.
VDD: Supply Voltage for I2C Serial Port and Input Supply
Pin for Internal Bias and Logic. This pin sets the logic
reference level of I2C SCL and SDA pins. SCL and SDA
logic levels are scaled to VDD. When the VDD pin is 2.7V or
above, the I2C interface is active. The LT3965/LT3965-1
will acknowledge communications to its address and data
can be written to and read back from LT3965/LT3965-1
registers. This is true even if EN/UVLO is low. However,
when EN/UVLO goes high, the LT3965/LT3965-1 resets
all registers to default values (see Table1 and Table2 for
default values). Connect a 0.1μF (or larger) decoupling
capacitor from this pin to ground.
SCL: Clock Input Pin for the I2C Serial Port. The I2C logic
levels are scaled with respect to VDD.
SDA: Data Input and Output Pin for the I
2
C Serial Port. The
I2C logic levels are scaled with respect to VDD.
ADDR[4:1]: Programmable Address Select Pins. The
device address is 010xxxx0 for all channel mode
(ACMODE) write, 010xxxx1 for all channel mode
(ACMODE) read, 101xxxx0 for single channel mode
(SCMODE) write, and 101xxxx1 for single channel mode
(SCMODE) read. ADDR[4] is MSB and ADDR[1] is LSB.
A total of 16 LT3965/LT3965-1 devices can be connected
to the same I2C bus. ADDR[4:1] are pulled up to VDD
through a 500k resistor inside the LT3965/LT3965-1, so
ADDR[4:1] default value is 1111. Each bit of ADDR[4:1]
default value can be overwritten by connecting the pin to
the ground. For robust design, use an external resistor to
connect ADDR pins to VDD or to GND.
DRN[8:1]: Floating N-Channel FET Drain Side Pins. Tie to
VDD with a 100k resistor if not used.
SRC[8:1]: Floating N-Channel FET Source Side Pins. The
channel source voltage (SRC[8:1]) must be at least 7.1V
lower than VIN for proper channel switch bypass opera-
tion. Tie to GND if not used.
GND: Exposed Pad Pin. Solder the exposed pad directly
to ground plane (GND).
LT3965/LT3965-1
9
Rev. B
For more information www.analog.com
BLOCK DIAGRAM
1
FAULT
DETECTOR
LED
FAULT
SW
CH8 DRN8
LED+
28
SRC8
DRIVER
27
FAULT
DETECTOR
LED
FAULT
SW
CH7 DRN7
26
SRC7
DRIVER
25
FAULT
DETECTOR
LED
FAULT
SW
CH6 DRN6
24
SRC6
DRIVER
REGISTERS
AND
CONTROL
LOGIC
I2C
SERIAL
INTERFACE
BANDGAP
REFERENCE
INTERNAL
BIAS
23
FAULT
DETECTOR
LED
FAULT
SW
CH5 DRN5
22
SRC5
DRIVER
21
FAULT
DETECTOR
LED
FAULT
SW
CH4 DRN4
20
SRC4
DRIVER
19
FAULT
DETECTOR
LED
FAULT
SW
CH3 DRN3
18
SRC3
DRIVER
17
FAULT
DETECTOR
LED
FAULT
SW
CH2 DRN2
16
SRC2
DRIVER
15
FAULT
DETECTOR
LED
FAULT
SW
CH1 DRN1
14
13
29
SRC1
LEDREF LED–
3965 F01
DRIVER
8
8
LED FAULT
12 ADDR4
ALERT
ADDR4
8
+
–
+
–
1.2V
0.88V
0.6V
PWMCLK
RTCLK
RT
INTERNAL
OSCILLATOR
0
1
ALERT
SET LED FAULT
SET OVERHEAT FAULT
4
TSD
–170°C
11 ADDR3
ADDR3
10 ADDR2
ADDR2
9ADDR1
5SCL
6SDA
7
VDD
3EN/UVLO
2VIN
SCL
SDA
VDD
5V C2
R4
ADDR1
C1
VIN
40V
R5
R6
R1
Q1LED+
R2
R3
+
–
1.24V
POR
ENABLE
IS1
2.7µA
+
–
Figure1. Block Diagram
LT3965/LT3965-1
10
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
OVERVIEW
The LT3965/LT3965-1 is an 8-channel LED bypass switch-
ing device with I2C serial interface, designed for dimming
LED strings using a common current source. Each of the
eight channels can be independently programmed to
bypass the LED string in constant on or off, or dimming
with or without fade transition. Operation can be best
understood by referring to the block diagram in Figure1.
The LT3965/LT3965-1 operates over the VDD input sup-
ply range of 2.7V to 5.5V. The eight channel switches are
powered by the VIN input supply and can be connected in
parallel and/or in series. Each of the eight channel switches
can bypass one or more LEDs up to 17V in a string.
Each channel has an LED fault detector which can be pro-
grammed to detect an open LED fault at one of the four
threshold levels: 4.5V, 9V (default setting of LT3965-1),
13.5V and 18V (default setting of LT3965). If EN/UVLO is
high, when an open LED fault is detected in a channel, the
channel switch will be turned on to bypass the faulty LED to
maintain the continuity of the string and for self protection.
The PWM dimming for this channel is interrupted until reset
by the serial interface. With a proper LED reference voltage
(<4V) applied to the LEDREF pin, each channel LED fault
detector can be programmed to detect a single-shorted LED
fault (default setting), a 2-shorted LED fault, a 3-shorted
LED fault or a 4-shorted LED fault in a multi-LED segment.
When a shorted LED fault is detected in a channel, the
channel switch will continue with the programmed PWM
dimming. Besides LED faults, the LT3965/LT3965-1 also
detects and reports an overheat fault condition (≥170°C).
The LT3965/LT3965-1 asserts (pulls down) the ALERT pin
to interrupt the bus master when an LED fault and/or an
overheat fault is detected. The master can use the alert
response address (ARA) to determine which device is send-
ing the alert.
The LT3965/LT3965-1 I2C serial interface contains nine
command registers for configuring channel switches and
LED fault detectors. It also contains two read-only fault
status registers for reporting the LED and overheat faults.
The I2C serial interface supports random addressing of
any register. The LT3965/LT3965-1 address select pins
ADDR4, ADDR3, ADDR2 and ADDR1 allow up to 16
LT3965/LT3965-1 devices to share the I2C bus.
If a resistor is connected between the RTCLK pin and the
ground, the internal oscillator is chosen and the LED dimming
frequency is set by the resistor. If the RTCLK pin is driven by
an external clock source, the external clock source is used to
override the internal oscillator and the dimming frequency
equals the external clock frequency divided by 2048.
DIFFERENCES BETWEEN LT3965 AND LT3965-1
The LT3965 and the LT3965-1 have different default
command register values, which result in different initial
switch states and different open LED threshold settings
after POR (Power On Reset). Otherwise they are the same
(see Table1 and Table2 for default register values).
Details of the LT3965/LT3965-1 operation are found in
the following sections.
EN/UVLO SHUTDOWN
The EN/UVLO pin resets the internal logic and controls
whether the LT3965/LT3965-1 is enabled or is in shutdown
state. The LT3965/LT3965-1 indicates that the part is in
shutdown state by setting all OLFREG and SLFREG register
bits high and deasserting the ALERT pin. In the shutdown
state, the serial interface is alive as long as VDD is applied.
Any data written while EN/UVLO is low will be reset when it
transitions high. The eight channel switches are off and the
alert function is disabled in shutdown condition. Because
VIN must be at least 7.1V higher than the channel source
voltage for proper channel switch bypass operation, it is
recommended to enable the IC when VIN is at least 7.1V
higher than VLED+. The PNP based level shifter shown in
Figure1 can be used to generate EN/UVLO input signal.
A micropower 1.24V reference, a comparator and con-
trollable current source, IS1, allow the user to accurately
program the VIN – VLED+ voltage at which the IC turns on
and off (see Figure1). When EN/UVLO is above 0.7V, and
below the 1.24V threshold, the small pull-down current
source, IS1, (typical 2.7μA) is active. The purpose of this
current is to allow the user to program the rising hyster-
esis. The typical falling threshold voltage and rising thresh-
old voltage can be calculated by the following equations:
(VIN – VLED+)(FALLING) =1.24 • R1
R2 +VBE
(VIN – VLED+)(RISING) =2.7µA •R1+(VIN – VLED+)(FALLING)
LT3965/LT3965-1
11
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
POR
1/256 DIMMING (8 CLOCK CYCLES)
PHASE SHIFT OF 1/8 DIMMING CYCLE = 256 CLOCK CYCLES
1 DIMMING CYCLE = 2048 RTCLK CLOCK CYCLES
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
3965 F02
Figure2. POR Dimming Cycle Initialization Diagram
Typically VBE is 0.6V. The recommended value of R1 is 49.9k
and therefore the rising hysteresis is 0.14V. Then the value
of R2 can be chosen to ensure that (VIN – VLED+)(FALLING) is
greater than 7.1V when the part is enabled.
POWER-ON RESET AND DIMMING CYCLE
INITIALIZATION
When the EN/UVLO pin is toggled high, an internal power-
on reset (POR) signal is generated to set all registers to
their default states. The eight channel switches are in off
state (all channel LEDs are on) upon the POR. The POR also
initializes each channel’s PWM dimming counter with one-
eighth dimming cycle shift, which can avoid simultaneous
channel switching at the beginning of dimming cycle to
reduce switching transients (see Figure2). When in PWM
dimming mode (with or without fade transition), the chan-
nel LED string is always being turned on at the beginning
of its dimming cycle. The channel LED string will be turned
off if the value of the channel counter, which is clocked by
the internal oscillator or an external clock source, equals
the dimming value stored in the channel SCMREG com-
mand register. Once the channel LED string is turned off, it
remains off until its next dimming cycle starts.
DIMMING WITHOUT FADE TRANSITION VS DIMMING
WITH FADE TRANSITION
Each channel of the LT3965/LT3965-1 can be indepen-
dently programmed to perform dimming without fade
transition or dimming with fade transition. For dimming
without fade transition, the dimming changes from the
initial value to the target value in one dimming cycle.
For dimming with fade transition, the dimming changes
transitionally from the initial value to the target value
step by step in multiple dimming cycles, following a
predetermined logarithmic curve, which can favor the
approximately logarithmic response of the human eye to
brightness. The initial value is an existing 8-bit dimming
value stored in channel SCMREG register. The target value
comes from a SCMODE long format write command and
will be stored in the register to replace the initial value
when the STOP condition is received. For dimming with
fade transition, each transitional step value is calculated
using 11 bits according to the following formula: DVNEXT
= DV
PRESENT
• CF, where DV represents a transitional step
dimming value, CF is a constant factor. CF is 1.0625 for up
transition and 0.9375 for down transition. The transition
process begins with the initial value served as the first
DVPRESENT, and ends with the target value when the last
DVNEXT is no less than the target value in up transition or
no more than the target value in down transition.
The number of the transitional steps depends on the dis-
tance between the initial value and the target value. The
maximum number of transitional steps from 1(/256) dim-
ming to 255(/256) dimming is 100 (see Figure3) and the
maximum number of transitional steps from 255(/256)
dimming to 1(/256) dimming is 92 (see Figure4). Each
step runs 4 PWM dimming cycles, and each dimming
cycle consists of 2048 RTCLK clock cycles. Then TSTEP =
TPWM • 4 = TRTCLK • 8192
LT3965/LT3965-1
12
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
LT3965/LT3965-1 I2C REGISTERS
The LT3965/LT3965-1 has nine command registers (see
Table1 and Table2) and two read-only fault status reg-
isters (see Table3). The command registers are used to
store the configuration bits sent by a master. The fault
status registers are used to store the LED/overheat fault
status bits. Both the command registers and the fault
status registers can be read by the master.
LT3965/LT3965-1 COMMAND REGISTERS AND
CHANNEL CONTROL
Upon the POR with EN/UVLO, all eight channel switches of
LT3965 are set to off, whereas all eight channel switches
of LT3965-1 are set to on, which is controlled by the
ACMREG register default value ("11111111" for LT3965;
"00000000" for LT3965-1). After data is written, each
channel switch is controlled either by the ACMODE reg-
ister or by the channel SCMREG register, depending on
which register has been last updated (see Figure5). If
SCMODE registers are dominant, the data in the ACMODE
register is retained until it is overwritten or a POR occurs.
I2C SERIAL INTERFACE
The LT3965/LT3965-1 communicates through an I2C
serial interface. The I2C serial interface is a 2-wire open-
drain interface supporting multiple slaves and multiple
masters on a single bus. Each device on the I2C bus is rec-
ognized by a unique address stored in the device and can
only operate either as a transmitter or receiver, depending
on the function of the device. A master is the device which
initiates a data transfer on the bus and generates the clock
signals to permit the transfer. Devices addressed by the
master are considered slaves. The LT3965/LT3965-1
can only be addressed as a slave. Once addressed, it
can receive configuration data or transmit register con-
tents. The serial clock line (SCL) is always an input to the
LT3965/LT3965-1 and the serial data line (SDA) is bidi-
rectional. The LT3965/LT3965-1 can only pull the serial
data line (SDA) LOW and can never drive it HIGH. SCL and
SDA are required to be externally connected to the VDD
supply through a pull-up resistor. When the data line is
not being driven LOW, it is HIGH. Data on the I2C bus can
be transferred at rates up to 100kbits/s in the standard
mode and up to 400kbits/s in the fast mode.
THE START AND STOP CONDITIONS
When the bus is idle, both SCL and SDA must be HIGH. A
bus master signals the beginning of a transmission with
a START condition by transitioning SDA from HIGH to
LOW while SCL is HIGH. When the master has finished
communicating with the slave, it issues a STOP condi-
tion by transitioning SDA from LOW to HIGH while SCL
is HIGH. The bus is then free for another transmission.
However, if the master still wishes to communicate on the
bus, it can generate a repeated START condition (Sr) and
address the same or another slave without first generating
a STOP condition. When the bus is in use, it stays busy
if a repeated START (Sr) is generated instead of a STOP
NUMBER OF STEPS
0
DIMMING VALUE (255 TO 1)
96
128
160
60 100
3865 F04
64
32
020 40 80
192
224
256
PWM DIMMING (99.6% TO 0.4%)
37.5%
50.0%
62.5%
25.0%
12.5%
0%
75.0%
87.5%
100%
Figure4. LT3965/LT3965-1 Down Transition Dimming Curve
NUMBER OF STEPS
0
DIMMING VALUE (1 TO 255)
96
128
160
60 100
3865 F03
64
32
020 40 80
192
224
256
PWM DIMMING (0.4% TO 99.6%)
37.5%
50.0%
62.5%
25.0%
12.5%
0%
75.0%
87.5%
100%
Figure3. LT3965/LT3965-1 Up Transition Dimming Curve
LT3965/LT3965-1
13
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
Table1. All Channel Mode (ACMODE) Command Register (8 Bits Long. See 1) All Channel Mode (ACMODE) Command section for how
to access this register).
NAME B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] DEFAULT
ACMREG Control Bit
for CH8
1: LED On
0: LED Off
Control Bit
for CH7
1: LED On
0: LED Off
Control Bit
for CH6
1: LED On
0: LED Off
Control Bit
for CH5
1: LED On
0: LED Off
Control Bit
for CH4
1: LED On
0: LED Off
Control Bit
for CH3
1: LED On
0: LED Off
Control Bit
for CH2
1: LED On
0: LED Off
Control Bit
for CH1
1: LED On
0: LED Off
11111111 (LT3965)
00000000 (LT3965-1)
Table2. Single Channel Mode (SCMODE) Command Registers (14 Bits Long. See 2) Single Channel Mode (SCMODE) Command
section for how to access these register bits).
NAME
B[13:12]
OPEN LED
THRESHOLD PRO-
GRAMMABLE BITS
B[11:10]
SHORTED LED
THRESHOLD
PROGRAMMABLE BITS
B[9:8]
MODE CONTROL BITS
B[7:0]
DIMMING VALUE DEFAULT
SCMREG1
(for CH1,
the channel
address: 000)
VOTH[1:0] =
“00”: 4.5V
“01”: 9.0V
“10”: 13.5V
“11”: 18.0V
VSTH[1:0] =
“00”: 1V
“01”: VLEDREF + 1V
“10”: 2 • VLEDREF + 1V
“11”: 3 • VLEDREF + 1V
MC[1:0] =
“00”: LED Off
“01”: LED On
“10”: LED Dimming without Fade Transition
“11”: LED Dimming with Fade Transition
DV[7:0] =
“00000001”: 1/256 Dimming
“00000010”: 2/256 Dimming
…….
“11111111”: 255/256 Dimming
110001 00000001
(LT3965)
010000 00000001
(LT3965-1)
SCMREG2
(for CH2,
the channel
address: 001)
VOTH[1:0] =
“00”: 4.5V
“01”: 9.0V
“10”: 13.5V
“11”: 18.0V
VSTH[1:0] =
“00”: 1V
“01”: VLEDREF + 1V
“10”: 2 • VLEDREF + 1V
“11”: 3 • VLEDREF + 1V
MC[1:0] =
“00”: LED Off
“01”: LED On
“10”: LED Dimming without Fade Transition
“11”: LED Dimming with Fade Transition
DV[7:0] =
“00000001”: 1/256 Dimming
“00000010”: 2/256 Dimming
…….
“11111111”: 255/256 Dimming
110001 00000001
(LT3965)
010000 00000001
(LT3965-1)
SCMREG3
(for CH3,
the channel
address:
010 )
VOTH[1:0] =
“00”: 4.5V
“01”: 9.0V
“10”: 13.5V
“11”: 18.0V
VSTH[1:0] =
“00”: 1V
“01”: VLEDREF + 1V
“10”: 2 • VLEDREF + 1V
“11”: 3 • VLEDREF + 1V
MC[1:0] =
“00”: LED Off
“01”: LED On
“10”: LED Dimming without Fade Transition
“11”: LED Dimming with Fade Transition
DV[7:0] =
“00000001”: 1/256 Dimming
“00000010”: 2/256 Dimming
…….
“11111111”: 255/256 Dimming
110001 00000001
(LT3965)
010000 00000001
(LT3965-1)
SCMREG4
(for CH4,
the channel
address: 011)
VOTH[1:0] =
“00”: 4.5V
“01”: 9.0V
“10”: 13.5V
“11”: 18.0V
VSTH[1:0] =
“00”: 1V
“01”: VLEDREF + 1V
“10”: 2 • VLEDREF + 1V
“11”: 3 • VLEDREF + 1V
MC[1:0] =
“00”: LED Off
“01”: LED On
“10”: LED Dimming without Fade Transition
“11”: LED Dimming with Fade Transition
DV[7:0] =
“00000001”: 1/256 Dimming
“00000010”: 2/256 Dimming
…….
“11111111”: 255/256 Dimming
110001 00000001
(LT3965)
010000 00000001
(LT3965-1)
SCMREG5
(for CH5,
the channel
address: 100)
VOTH[1:0] =
“00”: 4.5V
“01”: 9.0V
“10”: 13.5V
“11”: 18.0V
VSTH[1:0] =
“00”: 1V
“01”: VLEDREF + 1V
“10”: 2 • VLEDREF + 1V
“11”: 3 • VLEDREF + 1V
MC[1:0] =
“00”: LED Off
“01”: LED On
“10”: LED Dimming without Fade Transition
“11”: LED Dimming with Fade Transition
DV[7:0] =
“00000001”: 1/256 Dimming
“00000010”: 2/256 Dimming
…….
“11111111”: 255/256 Dimming
110001 00000001
(LT3965)
010000 00000001
(LT3965-1)
SCMREG6
(for CH6,
the channel
address: 101)
VOTH[1:0] =
“00”: 4.5V
“01”: 9.0V
“10”: 13.5V
“11”: 18.0V
VSTH[1:0] =
“00”: 1V
“01”: VLEDREF + 1V
“10”: 2 • VLEDREF + 1V
“11”: 3 • VLEDREF + 1V
MC[1:0] =
“00”: LED Off
“01”: LED On
“10”: LED Dimming without Fade Transition
“11”: LED Dimming with Fade Transition
DV[7:0] =
“00000001”: 1/256 Dimming
“00000010”: 2/256 Dimming
…….
“11111111”: 255/256 Dimming
110001 00000001
(LT3965)
010000 00000001
(LT3965-1)
SCMREG7
(for CH7,
the channel
address: 110)
VOTH[1:0] =
“00”: 4.5V
“01”: 9.0V
“10”: 13.5V
“11”: 18.0V
VSTH[1:0] =
“00”: 1V
“01”: VLEDREF + 1V
“10”: 2 • VLEDREF + 1V
“11”: 3 • VLEDREF + 1V
MC[1:0] =
“00”: LED Off
“01”: LED On
“10”: LED Dimming without Fade Transition
“11”: LED Dimming with Fade Transition
DV[7:0] =
“00000001”: 1/256 Dimming
“00000010”: 2/256 Dimming
…….
“11111111”: 255/256 Dimming
110001 00000001
(LT3965)
010000 00000001
(LT3965-1)
SCMREG8
(for CH8,
the channel
address: 111)
VOTH[1:0] =
“00”: 4.5V
“01”: 9.0V
“10”: 13.5V
“11”: 18.0V
VSTH[1:0] =
“00”: 1V
“01”: VLEDREF + 1V
“10”: 2 • VLEDREF + 1V
“11”: 3 • VLEDREF + 1V
MC[1:0] =
“00”: LED Off
“01”: LED On
“10”: LED Dimming without Fade Transition
“11”: LED Dimming with Fade Transition
DV[7:0] =
“00000001”: 1/256 Dimming
“00000010”: 2/256 Dimming
…….
“11111111”: 255/256 Dimming
110001 00000001
(LT3965)
010000 00000001
(LT3965-1)
Note: The dimming value range is 00000001 to 11111111. If the invalid dimming value 00000000 is received, 00000001 will be written to the register instead.
LT3965/LT3965-1
14
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
Table3. Read-Only Fault Status Register (See 1) All Channel Mode (ACMODE) Command section and 2) Single Channel Mode
(SCMODE) Command section for how to access these register bits).
NAME B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] DEFAULT
OLFREG Open LED
Status Bit for
CH8
1: Fault
0: No Fault
Open LED
Status Bit for
CH7
1: Fault
0: No Fault
Open LED
Status Bit for
CH6
1: Fault
0: No Fault
Open LED
Status Bit for
CH5
1: Fault
0: No Fault
Open LED
Status Bit for
CH4
1: Fault
0: No Fault
Open LED
Status Bit for
CH3
1: Fault
0: No Fault
Open LED
Status Bit for
CH2
1: Fault
0: No Fault
Open LED
Status Bit for
CH1
1: Fault
0: No Fault
00000000
SLFREG Shorted LED
Status Bit for
CH8
1: Fault
0: No Fault
Shorted LED
Status Bit for
CH7
1: Fault
0: No Fault
Shorted LED
Status Bit for
CH6
1: Fault
0: No Fault
Shorted LED
Status Bit for
CH5
1: Fault
0: No Fault
Shorted LED
Status Bit for
CH4
1: Fault
0: No Fault
Shorted LED
Status Bit for
CH3
1: Fault
0: No Fault
Shorted LED
Status Bit for
CH2
1: Fault
0: No Fault
Shorted LED
Status Bit for
CH1
1: Fault
0: No Fault
00000000
Note: The LT3965/LT3965-1 sets all OLFREG and SLFREG register bits high and asserts the ALERT pin to indicate the overheat fault condition (≥170°C).
(See LED/Overheat Fault Detection and Reporting section for detail.) The LT3965/LT3965-1 indicates that the part is in shutdown state by setting all
OLFREG and SLFREG register bits high and deasserting the ALERT pin.
S
O
ATO CONTROL
CHANNEL
SWITCH
O = A IF S = 0
O = B IF S = 1
O = A IF S = 00
O = B IF S = 01
O = C IF S = 10
O = D IF S = 11
S = 0 IF POR OR ACMREG IS WRITTEN
S = 1 IF SCMREG1 IS WRITTEN
B
S
2
O
LED CONSTANT OFF
LED CONSTANT ON
LED DWOFT
LED DWFT
DWOFT: DIMMING WITHOUT FADE TRANSITION
DWFT: DIMMING WITH FADE TRANSITION
DWOFT: DIMMING WITHOUT FADE TRANSITION
DWFT: DIMMING WITH FADE TRANSITION
A
B
C
D
DIMMING
CONTROL
CHANNEL
COUNTER
CHANNEL
LED FAULT
DETECTOR
CHANNEL
COMPARATOR
2
8
2
2
2
11
CLK
TO CH2
DRN1
LEDREF
SRC1
OPEN LED FAULT TO SET OLFREG B[0]
SCMREG1 (LT3965 POR DEFAULT: 11 00 01 00000001;
LT3965-1 POR DEFAULT: 01 00 00 00000001)
SCMREG8 (LT3965 POR DEFAULT: 11 00 01 00000001;
LT3965-1 POR DEFAULT: 01 00 00 00000001)
SHORTED LED FAULT TO SET SLFREG B[0]
POR
DV[7:0]VSTH[1:0] MC[1:0]VOTH[1:0]
B[7]-B[0]
CH1
CH2
↓
CH7
B[11:10] B[9:8]
B[0]B[7] B[5]B[6] B[4] B[3] B[2] B[1]
B[13:12]
S
O
ATO CONTROL
CHANNEL
SWITCH
O = A IF S = 0
O = B IF S = 1
O = A IF S = 00
O = B IF S = 01
O = C IF S = 10
O = D IF S = 11
S = 0 IF POR OR ACMREG IS WRITTEN
S = 1 IF SCMREG8 IS WRITTEN
B
S
2
O
LED CONSTANT OFF
LED CONSTANT ON
LED DWOFT
LED DWFT
A
B
C
D
DIMMING
CONTROL
CHANNEL
COUNTER
CHANNEL
LED FAULT
DETECTOR
CHANNEL
COMPARATOR
2
8
2
2
2
11
CLK
DRN8
LEDREF
SRC8
OPEN LED FAULT TO SET OLFREG B[7]
SHORTED LED FAULT TO SET SLFREG B[7]
POR
DV[7:0]
3965 F05
ACMREG
1: LED ON 0: LED OFF
(LT3965 POR DEFAULT: 11111111;
LT3965-1 POR DEFAULT: 00000000)
VSTH[1:0] MC[1:0]VOTH[1:0]
B[7]-B[0]
CH8
B[11:10] B[9:8]B[13:12]
•
•
•
•
•
•
TO CH3
TO CH4
TO CH5
TO CH6
TO CH7
Figure5. LT3965/LT3965-1 Command Registers and Channel Control Diagram
LT3965/LT3965-1
15
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
Figure6. LT3965/LT3965-1 I2C Serial Port ACMODE Write Protocol
Figure7. LT3965/LT3965-1 I2C Serial Port ACMODE Read Protocol
condition. The repeated START (Sr) conditions are func-
tionally identical to the START (S). Various combinations
of read/write commands are then possible within such a
transfer, except that the BCMODE write command for dim-
ming cycle synchronization and the BCMODE read com-
mand for alert inquiry and the ACMODE write command
for clearing the overheat fault bits must be self-contained
with a terminating STOP condition.
I2C SERIAL PORT DATA TRANSFER
After the START condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
LT3965/LT3965-1 slave. Data is transferred over the bus
in group of nine bits, one byte followed by one acknowl-
edge (ACK) bit. The acknowledge signal is used for hand-
shaking between the master and the slave.
When the LT3965/LT3965-1 is written to, it acknowledges
its device write address and subsequent data bytes. The
data byte is transferred to an internal holding latch upon
the return of its acknowledge by the LT3965/LT3965-1.
If desired a repeated START (Sr) condition may be initi-
ated by the master to address another device on the I2C
bus for data transfer. The LT3965/LT3965-1 remembers
the valid data it has received. Once selected channels of
the devices on the I2C bus have been addressed and sent
valid data, the master issues a STOP condition to finish
the communication. The LT3965/LT3965-1 will update its
command registers with the data it has received upon the
STOP condition, except that the VOTH[1:0] and VSTH[1:0]
bits are updated in the channel SCMREG command reg-
ister upon the return of its acknowledge by the LT3965/
LT3965-1.
When reading from the LT3965/LT3965-1, the LT3965/
LT3965-1 acknowledges its device read address and
the master acknowledges subsequent data bytes it has
received except the last one followed by a STOP or a
repeated START condition.
The master can free the I2C bus by issuing a STOP condi-
tion after the data transfer. If desired the master can verify
the data bytes written to the internal holding latches prior
to updating them to the command registers by reading
them back before sending a STOP condition.
LT3965/LT3965-1 I2C COMMANDS AND WRITE/READ
PROTOCOLS
Only a master can issue an I2C command to start a write
or read operation. The first command byte is always an
I2C device address sent by a master. If the master issues
a write command, all the remaining bytes of the com-
mand will be transmitted by the master. Otherwise, all
the remaining bytes of the command will be transmitted
by the addressed LT3965/LT3965-1 slave. The LT3965/
LT3965-1 I
2C commands can be divided into three cat-
egories based on their purposes:
START STOP
SLAVE
ACK
SLAVE
ACK
0
0 1 0 A4A3
ACMODE DEVICE ADDRESS DATA TO ACMREG
A2A10(W)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
3965 F06
0 0 SA SA1
SDA
SCL
B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]
START STOP
SLAVE
ACK
MASTER
ACK
0
0 1 0 A4A3
ACMODE DEVICE ADDRESS DATA FROM ACMREG
A2A11(R)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
3965 F07
0 1 SA MA
MASTER
ACK
MA
MASTER
NOT ACK
MNA1
SDA
SCL
B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]
DATA FROM OLFREG
B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]
DATA FROM SLFREG
B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]
LT3965/LT3965-1
16
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
1) All Channel Mode (ACMODE) Command
The ACMODE write command (see Figure6) is used to set
the ACMREG register bits (see Table1) to control the eight
channel switches together. The command is two bytes
long. The first byte is the ACMODE device write address
and the second byte is the data byte to be written to the
ACMREG register.
The ACMODE read command (see Figure7) is used to read
back the ACMREG register bits and to get the LED and
overheat fault conditions. The command is four bytes long.
The first byte is the ACMODE device read address followed
by three data bytes read respectively from the ACMREG
register, the OLFREG register and the SLFREG register.
The LT3965/LT3965-1 ACMODE device address is
010A
4
A
3
A
2
A
1
followed by an eighth bit which is a data
direction bit (R/W)—a 0 indicates a write transmission
(the master writes to the addressed LT3965/LT3965-1),
a 1 indicates a read transmission (the master reads from
the addressed LT3965/LT3965-1). A4A3A2A1 is an input
logic value from the programmable address select pins
ADDR4, ADDR3, ADDR2 and ADDR1.
ACMODE Write Command Latency
The ACMODE write command can be conveniently used
for quick status control of the eight channel LEDs. Each
ACMODE write command is two bytes long and takes
about 47µs to transmit if 400kHz SCL clock is chosen.
The command latency between the STOP condition and
channel switching on (LED turning off) is about 0.3µs,
and the command latency between the STOP condition
and channel switching off (LED turning on) is about 1µs.
Therefore, the minimum time from initiating to executing
an ACMODE write command is about 48µs if 400kHz SCL
clock is used.
ACMODE Write Command and Simultaneous Channel
Switching
The ACMODE write command can control all 8 channels
to switch together. It is possible to switch all LEDs from
on/off to off/on simultaneously using a single ACMODE
write command. A fast LED driver can respond well to a
sudden output voltage change caused by simultaneous
channel switching. An LED driver with slower response
may trigger false faults due to large transients in the string
current. When working with a slow LED driver, you should
avoid sending an ACMODE write command which can
cause simultaneous channel switching. Instead you can
use multiple ACMODE write commands, and each of them
makes one channel switch at a time.
2) Single Channel Mode (SCMODE) Command
The SCMODE write command is used for setting the
addressed channel SCMREG register bits to control the chan-
nel switch and to set the channel LED fault detecting thresh-
olds. The SCMODE write command has two formats: short
format (see Figure8) and long format (see Figure9). Both the
formats configure the channel SCMREG register. Choosing
the short format or the long format depends on which bits of
the channel SCMREG register you want to configure.
The SCMODE write command short format can program
the channel open LED threshold by setting VOTH[1:0]
(B[13:12]) and change the channel switch mode by set-
ting MC[1:0] (B[9:8]). The SCMODE write command long
format can program the channel shorted LED threshold
by setting VSTH[1:0] (B[11:10]) and change the channel
switch mode by setting MC[1:0] (B[9:8]) and set a new
dimming value by updating DV[7:0] (B[7:0]) in the chan-
nel SCMREG register.
START STOP
SLAVE
ACK
CHANNEL
ADDRESS
SHORT
FORMAT
SLAVE
ACK
1
1 0 1 A4A3
SCMODE DEVICE ADDRESS DATA TO SCMREG
A2A10(W)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
3965 F08
1 0 0SA SA0
SDA
SCL
0 CA3CA2CA1B[13]B[12] B[9] B[8]
Figure8. LT3965/LT3965-1 I2C Serial Port SCMODE Write Short Format Protocol
LT3965/LT3965-1
17
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
START STOP
SLAVE
ACK
CHANNEL
ADDRESS
LONG
FORMAT
SLAVE
ACK
1
1 0 1 A4A3
SCMODE DEVICE ADDRESS DATA TO SCMREG DATA TO SCMREG
A2A10(W)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
3965 F09
1 0 1SA SA
SLAVE
ACK
SA0
SDA
SCL
1 CA3CA2CA1B[11]B[10] B[9] B[8] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]
Figure9. LT3965/LT3965-1 I2C Serial Port SCMODE Write Long Format Protocol
The SCMODE write command short format is two bytes
long (see Figure8). The first byte is the SCMODE device
write address. The second byte consists of 3 sections—
the first section (bit 7) must be 0 to indicate the short
format, the second section (bit 6, bit 5 and bit 4) is the
channel address indicating which channel SCMREG reg-
ister is written to, the last section is the configuration data
(bit 3, bit 2 for VOTH[1:0] and bit 1, bit 0 for MC[1:0]).
The SCMODE write command long format is three bytes
long (see Figure9). The first byte is the SCMODE device
write address. The second byte consists of 3 sections—
the first section (bit 7) must be 1 to indicate the long
format, the second section (bit 6, bit 5 and bit 4) is the
channel address indicating which channel SCMREG reg-
ister is written to, the last section is the configuration data
(bit 3, bit 2 for VSTH[1:0] and bit 1, bit 0 for MC[1:0]). The
third byte is the dimming value DV[7:0].
Channel Open LED Threshold (VOTH) Programming
By using the SCMODE write command short format, you
can overwrite B[13:12] bits (i.e., VOTH[1:0]) of the chan-
nel SCMREG register to program the channel open LED
threshold (refer to Table2, Figure8 and Figure5).
VOTH = 4.5V • (1 + VOTH[1:0])
Where VOTH[1:0] represents the possible decimal value
0, 1, 2 or 3 of the two programmable bits. Therefore, the
channel open LED threshold VOTH can be programmed to
one of these four values: 4.5V, 9V, 13.5V and 18V. The
POR default V
OTH
of LT3965 is 18V. The POR default V
OTH
of LT3965-1 is 9V.
When programming VOTH, please follow the advice below
to avoid false detection or missed detection of open LED
condition:
1) Do not set VOTH to a threshold equal to or greater than
the VIN supply voltage. It is recommended to set VOTH
to a threshold at least 3V lower than the V
IN
supply
voltage.
2) Set VOTH to the lowest threshold, but at least one-fifth
of the VOTH higher than the channel LED-on voltage.
For example, if channel LED-on voltage is 3.5V or less,
to set VOTH to 4.5V is preferred. If channel LED-on volt-
age is 3.8V, to set VOTH to 9V is preferred.
It is recommended to adjust the VOTH from its default value
(18V on LT3965; 9V on LT3965-1) to a proper threshold
based on the V
IN
supply voltage and each channel LED-on
voltage, once the application circuit is powered on.
Channel Shorted LED Threshold (VSTH) Programming
By using the SCMODE write command long format, you
can overwrite B[11:10] bits (i.e., VSTH[1:0]) of the channel
SCMREG register to program the channel shorted LED
threshold (refer to Table2, Figure9 and Figure5).
VSTH = 1V + (NLED – 1) • VLEDREF
NLED = 1 + VSTH[1:0]
Where NLED is the number of LEDs in series driven by the
channel, which is programmed by VSTH[1:0], and VLEDREF
is a reference voltage set by the LEDREF pin (refer to the
curve Shorted LED Threshold Falling vs LEDREF in Typical
Performance Characteristics).
LT3965/LT3965-1
18
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
Figure10. LT3965/LT3965-1 I2C Serial Port SCMODE Read Protocol
Figure11. LT3965/LT3965-1 I2C Serial Port SCMODE Write Short Format Followed by SCMODE Read
START STOP
SLAVE
ACK
MASTER
ACK
1
1 0 1 A4A3
SCMODE DEVICE ADDRESS DATA FROM SCMREG
SHORTED LED FAULT BIT FROM SLFREG
OPEN LED FAULT BIT FROM OLFREG
A2A11(R)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
3965 F10
1 1 SA MA
MASTER
NOT ACK
MNA0
SDA
SCL
OL SL B[13] B[12] B[11] B[10] B[9] B[8]
DATA FROM SCMREG
B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]
123456789123456789 123456789123456789123456789
3965 F11
MNAMASASA0011 0 SA 111 0
STOP
MASTER
NOT ACK
MASTER
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
SDA
SCL
REPEATED
START
1 0 1 A4A3
SCMODE DEVICE ADDRESS
A2A10(W) 0 CA3CA2CA1B[9] B[8]B[13] B[12]
DATA TO SCMREG
CHANNEL
ADDRESS
SHORT
FORMAT
1 0 1 A4A3
SCMODE DEVICE ADDRESS
A2A11(R)
DATA FROM SCMREG
SHORTED LED FAULT BIT FROM SLFREG
OPEN LED FAULT BIT FROM OLFREG
OL SL B[13] B[12] B[11] B[10] B[9] B[8]
DATA FROM SCMREG
B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]
LT3965/LT3965-1
19
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
If the LEDREF pin is set to a voltage other than 0V, the
channel shorted LED threshold VSTH can be programmed
to one of these four values: 1V, 1V + VLEDREF, 1V + 2 •
VLEDREF and 1V + 3 • VLEDREF. The POR default VSTH of
the LT3965/LT3965-1 is 1V. By using this feature, each
channel is able to detect 1, 2, 3, or 4 shorted LEDs.
This feature can be turned off by grounding the LEDREF
pin. When the LEDREF pin is set to 0V, the V
STH
will be set
to 1V, no matter how the V
STH
[1:0] bits are programmed.
The SCMODE read command (see Figure10 and Figure11)
is used to read back the addressed channel SCMREG reg-
ister bits and to get the channel LED fault conditions. The
SCMODE read command is three bytes long. The first byte
is the SCMODE device read address. The second byte
comprises (from MSB to LSB) one addressed channel bit
from the OLFREG register, one addressed channel bit from
the SLFREG register, and 6 bits (V
OTH
[1:0], V
STH
[1:0] and
MC[1:0]) from the addressed SCMREG register. The third
byte is the dimming value DV[7:0] from the addressed
SCMREG register.
Unlike the SCMODE write command, the SCMODE read
command does not contain the channel address. Actually
the channel address received from the last SCMODE
write command is stored and will be used as the channel
address for incoming SCMODE read operations. In other
words, a SCMODE read command always reads the chan-
nel SCMREG register addressed by the last SCMODE write
command. If no SCMODE write command has ever been
received, the default channel address 000 (CH1) is used.
The LT3965/LT3965-1 SCMODE device address is
101A
4
A
3
A
2
A
1
followed by an eighth bit which is a data
direction bit (R/W)— a 0 indicates a write transmission
(the master writes to the addressed LT3965), a 1 indicates
a read transmission (the master reads from the addressed
LT3965/LT3965-1). A4A3A2A1 is an input logic value from
the programmable address select pins ADDR4, ADDR3,
ADDR2 and ADDR1.
3) Broadcast Mode (BCMODE) Command
The BCMODE write command (see Figure12) is used
to synchronize the dimming cycles among the multiple
LT3965/LT3965-1 slaves on the I
2
C bus. The LT3965/
LT3965-1 slaves must be operating with a common exter-
nal clock in order to be synchronized. The BCMODE write
command is only one byte long: 00011000. The com-
mand does not modify any register bits. It only resets
each channel counter to synchronize the dimming cycles.
The BCMODE read command (see Figure13) is used
to inquire about which LT3965/LT3965-1 slave on the
bus is sending the alert (see LT3965/LT3965-1 LT3965/
LT3965-1 Alert Response Protocol Using Alert Response
Address (ARA) section for detail). This command is two
bytes long. The first byte is the broadcast read address
00011001. The second byte 010A4A3A2A11 is sent by the
alerting slave to indicate its ACMODE device read address
to the master. A4A3A2A1 is an input logic value from the
programmable address select pins ADDR4, ADDR3,
ADDR2 and ADDR1.
If the BCMODE read command is issued when no LT3965/
LT3965-1 slave on the bus is sending alert, the master
receives no acknowledgement.
LT3965/LT3965-1 ALERT RESPONSE PROTOCOL
USING ALERT RESPONSE ADDRESS (ARA)
In a system where several slaves share a common inter-
rupt line, the master can use the alert response address
(ARA) to determine which device initiated the interrupt.
The master initiates the ARA procedure with a START con-
dition and the special 7-bit ARA bus address (0001100)
followed by the read bit (R) = 1. If the LT3965/LT3965-1
is asserting the ALERT pin, it acknowledges and responds
by sending its 7-bit bus address (010A4A3A2A1) and a 1.
While it is sending its address, it monitors the SDA pin to
see if another device is sending an address at the same
time using standard I2C bus arbitration. If the LT3965/
LT3965-1 is sending a 1 and reads a 0 on the SDA pin on
LT3965/LT3965-1
20
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
the rising edge of SCL, it assumes another device with
a lower address is sending and the LT3965/LT3965-1
immediately aborts its transfer and waits for the next ARA
cycle to try again. If transfer is successfully completed,
the LT3965/LT3965-1 will deassert its ALERT pin and will
not respond to further ARA requests until a new alert
event occurs. Please note that the successfully completed
ARA cycle deasserts the ALERT pin only. It does not clear
the fault status bit set in the OLFREG/SLFREG register.
LED/OVERHEAT FAULT DETECTION AND REPORTING
The LT3965/LT3965-1 detects and reports open LED,
shorted LED and overheat fault conditions via the ALERT
pin and I2C serial interface. (See the following sections
for detail.)
OPEN LED FAULT DETECTION AND ALERT ASSERTION
An open LED fault will be triggered when the voltage
between the channel DRN pin and the channel SRC pin
exceeds 22V (nominal) or when the voltage between
the channel DRN pin and the channel SRC pin exceeds
the programmed open LED threshold but less than 22V
(nominal) for more than 15µs (nominal). Once an open
LED fault is triggered in a channel, the fault status bit
START STOP
SLAVE
ACK
0
0 0 0 1 1
BCMODE DEVICE ADDRESS
0 0 0(W)
1 2 3 4 5 6 7 8 9
3965 F12
00 11 0 0 SA0
SDA
SCL
START STOP
SLAVE
ACK
MASTER
NOT ACK
0
0 0 0 1 1
BCMODE DEVICE ADDRESS
0 0 1(R)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
3965 F13
00 11 0 1 SA0
SDA
SCL
0 1 0 A4A3
ALERT RESPONSE ADDRESS FROM LT3965
A2A11
00 1 1 MNA
Figure12. LT3965/LT3965-1 I2C Serial Port BCMODE Write Protocol
Figure13. LT3965/LT3965-1 I2C Serial Port BCMODE Read Protocol
matching the channel will be set in the OLFREG status
register, which will cause the ALERT pin to be asserted
(pulled down) and the channel switch to be turned on
for the switch protection and to maintain continuity of
the string for good LEDs. The switch can be turned off
and PWM dimming reestablished by updating its registers
with the serial interface.
SHORTED LED FAULT DETECTION AND ALERT
ASSERTION
A shorted LED fault will be triggered when the voltage
between the channel DRN pin and the channel SRC pin
falls below the programmed shorted LED threshold for
more than 15µs (nominal). Once a shorted LED fault is
triggered in a channel, the fault status bit matching the
channel will be set in the SLFREG status register, which
will cause the ALERT pin to be asserted (pulled down).
However, unlike the open LED fault, the channel switch will
continue with the programmed PWM dimming.
LED FAULT STATUS BIT CLEARANCE
The fault status bit set in the OLFREG/SLFREG register
by an open/shorted LED fault can only be cleared by an
ACMODE write command or a SCMODE write command
LT3965/LT3965-1
21
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
accessing the channel. If the open/shorted LED fault no
longer exists when the write command is updating the
command register at the I
2
C STOP condition, the fault
status bit matching the channel will be cleared and the
ALERT pin will be deasserted. Otherwise, the fault status
bit will remain set, and the ALERT pin will remain asserted
or be asserted again if previously deasserted.
OVERHEAT FAULT DETECTION AND ALERT ASSERTION
An overheat fault will be triggered when the IC tempera-
ture exceeds 170°C. Once an overheat fault is triggered,
all status bits in both the OLFREG register and the SLFREG
register will be set, which will cause the ALERT pin to be
asserted (pulled down) and all eight channel switches to
be turned on (LEDs to be turned off) for cooling down
the system.
OVERHEAT STATUS BITS CLEARANCE
The fault status bits set in the OLFREG register and the
SLFREG register by an overheat fault can only be cleared
by an ACMODE write command with all 1s in its data byte.
If the IC temperature is below 160°C when the ACMODE
write command is updating the ACMREG register at the
I2C STOP condition, the fault status bits will be cleared
and the ALERT pin will be deasserted. Otherwise, the fault
status bits will remain set, and the ALERT pin will remain
asserted or be asserted again if previously deasserted.
ALERT DEASSERTION
The LT3965LT3965-1 deasserts the ALERT pin in either
of the following two situations:
1) The LT3965/LT3965-1 has successfully completed the
ARA procedure initiated by the master. Please note that
the successfully completed ARA procedure does not
clear fault status bits. It only deasserts the ALERT pin.
2) The LT3965/LT3965-1 has received an ACMODE or
SCMODE write command which cleared the fault status
bits, resulting in the ALERT pin deassertion.
PRINTED CIRCUIT BOARD LAYOUT
When laying out the printed circuit board, the following
checklist should be followed to ensure proper operation
of the LT3965/LT3965-1:
1. Connect the exposed pad of the package (Pin 29)
directly to a large ground plane to minimize thermal
and electrical impedance.
2. Keep the LED connection traces as short as possible.
3. Place power supply bypass capacitors as close as pos-
sible to the supply pins.
4. Place the RTCLK resistor as close as possible to the IC
if a resistor is used to set LED dimming frequency.
Long Wires or Cables Between LT3965/LT3965-1 and
LEDs
The best practice is to place the LT3965/LT3965-1 and the
LEDs it controls on the same PCB and to keep LED con-
nection traces as short as possible. Long wires (>>10cm)
between the LT3965/LT3965-1 and the LEDs introduce
parasitic inductance that leads to an underdamped RLC
response (ringing) in the switching voltage when chan-
nel is switching on and off. A meter of 30-gage wire can
introduce about 1µH of parasitic inductance. The ringing
can trigger open LED protection due to false open LED
detection, and cause the channel to bypass good LEDs. In
extreme cases, the ringing may exceed absolute maximum
ratings and damage the part. The parasitic inductance also
generates a step voltage waveform (relative to GND) at the
switches at the frequency of the switching regulator. The
magnitude of this step waveform depends upon the cur-
rent ripple in the source and the parasitic inductance. The
fast edges of the step waveform can cause unintended
toggling of the LT3965/LT3965-1 switches.
RC snubber circuits (shown in Figure14) can suppress
the ringing and allow use of wires up to 1 meter with
no false fault detection. The snubber should be placed
close to the IC. Please note that an 8-LED string requires
9 snubbers: one snubber across each of the 8 switches
and a snubber across all 8 switches (R9, C9). The 9th
snubber (R9, C9) softens the stepped waveform edges.
LT3965/LT3965-1
22
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
With the snubbers, the LT3965/LT3965-1 can control the
LEDs through a 1 meter ribbon cable (9 wires total) pass-
ing 0.5A with no false faults detected. The snubber value
shown here is good for most applications.
Schottky Clamping Diode for LT3965/LT3965-1
Protection
A Schottky clamping diode (D1 shown in Figure 15) con-
necting the top of the LED string (LED+ node) to the VIN
pin is required to guarantee that the absolute maximum
rating VIN – SRC ≥ –0.3V is met.
Figure14. RC Snubbers In Long Wire Application
Figure15. Clamping Diode For LT3965/LT3965-1 Protection
For the boost-buck configuration, where the voltage at
the LED string bottom (LED– node) may go below 0V, a
Schottky clamping diode (D2 shown in Figure 15) con-
necting the IC ground to the LED– node is required to
keep SRC ≥ –0.3V.
In applications with wires longer than 30cm, there is
potential for an open or shorted LED to cause ringing at
channel DRN-SRC beyond the absolute maximum rating
of –0.3V. The LT3965/LT3965-1 can be protected by plac-
ing Schottky clamping diodes (D3 to D10 shown in Figure
15) near the IC across channel pins.
GND
LT3965/
LT3965-1
DRN8
DRN7
SRC8
DRN6
SRC7
DRN5
SRC6
DRN4
SRC5
DRN3
SRC4
DRN2
SRC3
DRN1
SRC2
SRC1
3965 F15
VIN
D1
D3
D4
D5
D6
D7
D8
D9
D10
LED
+
IF NEEDED
LED
–
D2
LT3965/LT3965-1
DRN8
DRN7
SRC8
DRN2
SRC3
DRN1
SRC2
SRC1
3965 F14
LED
+
D8
C9
10nF
R9
10Ω
D7
•
•
•
•
•
•
D3
D2
D1
LED
–
UP TO 1 METER
C8
10nF
R8
10Ω
C2
10nF
R2
10Ω
C1
10nF
R1
10Ω
LT3965/LT3965-1
23
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
1µF 5.7k
GND
10k
RT SW1 BOOST INTVCC
INTVCC
INTVCC
FBH1-2
SW2
PWM1-3 CTRL1-2VREF CTRL3
47.5k 0.22µF L4
47µH
F LT 1-3SS3 SS1-2
10µF
50V
×2
10µF
50V
×2
1µF
50V
0.1µF
10µF
3965 TA02
2.2nF
499k
69.8k
ISP1-2
EN/UVLO
VIN ISN1-2
GATE3 SENSEP3 SENSEN3 GATE1SENSEP1SENSEN1ISP3 ISN3
LT3797
GATE2 SENSEP2 SENSEN2 TG1-2
0.50Ω
500mA
0.50Ω
500mA
0.05Ω0.05Ω
M5M4
D3
L3
15µH
M2M1M3
TG2TG1
FBH2
44.2k1M
FBH1
1M44.2k
ISN2
LED2+
LED2–
LED1+
LED1–
D2
D1
L2
33µH
L1
33µH
43.2k
ISP2
ISN1
ISP1
0.02Ω
FBH3 SYNC
10µF
50V
0.1µF
50V
VIN
9V TO 30V
33µF
50V
1M
49.9k
9.09k
1k
TG3
D1, D2: DIODES DFLS260
D3: DIODES PDS360
D4, D5, D10, D11: CENTRAL SEMI CMSD6263S
2 IN 1 PACKAGE
D6, D7: NXP SEMI PMEG6010CEH
D8, D9: NXP SEMI PMEG4010CEH
Q1: ZETEX FMMT591
L1, L2: WURTH ELECTRONICS 7447789133
L3: WURTH ELECTRONICS 7443551151
L4: COOPER BUSSMANN SD25-470-R
M1, M2: VISHAY Si7308DN
M3: VISHAY Si7850DP
M4, M5: VISHAY Si7309DN
VC1-2
15k
22nF
1nF
VC3
0.1µF
50V
D5D4
INTVCC
0.1µF
16V
0.1µF
16V
D11D10
SYNC
22µF
4V
22µF
4V
D8
500mA
VLED
26V
SDAALERT5V SCL
GND
LT3965/
LT3965-1
CH1
EN/UVLO
SCL
SDA
ALERT
RTCLK
ADDR1
ADDR2
ADDR3
ADDR4
LEDREF
DRN8
DRN7
SRC8
DRN6
SRC7
DRN5
SRC6
DRN4
SRC5
DRN3
SRC4
DRN2
SRC3
DRN1
SRC2
SRC1
VIN VDD
10k
10k
10k
1µF
10V
1µF
50V
D6
D9
500mA
VLED
26V
5V
1µF
50V
1µF
D7
SET
DIV
VIN
GND
350kHz SYNC
OUT
LTC6900
0.1µF
10V
10µF
50V
×2
60.4k
5V
GND
LT3965/
LT3965-1
CH2
EN/UVLO
SCL
SDA
ALERT
RTCLK
ADDR1
ADDR2
ADDR3
ADDR4
LEDREF
DRN8
DRN7
SRC8
DRN6
SRC7
DRN5
SRC6
DRN4
SRC5
DRN3
SRC4
DRN2
SRC3
DRN1
SRC2
SRC1
VIN
VDD
BIAS
VOUT
BIAS = VOUT + INTVCC + 5V
VOUT
+
Q1
Matrix LED Dimmer Powered by a Dual Buck Mode LED Driver with a Boost Pre-Regulator
LT3965/LT3965-1
24
Rev. B
For more information www.analog.com
PACKAGE DESCRIPTION
FE28 (EB) TSSOP REV L 0117
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10 11 12 13 14
192022 21 151618 17
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
2.74
(.108)
28 27 26 2524 23
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
4.75
(.187)
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation EB
LT3965/LT3965-1
25
Rev. B
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 04/17 Added LT3965-1 Option
Clarified Block Diagram
All
9
B 12/19 Added Automotive Products 2
LT3965/LT3965-1
26
Rev. B
For more information www.analog.com
ANALOG DEVICES, INC. 2016-2019
www.analog.com
12/19
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT3795 High Side 110V, 1MHz LED Driver with 3000:1 PWM
Dimming with Spread Spectrum Frequency Modulation
VIN: 4.5V to 110V, VOUT(MAX) = 110V, 3000:1 PWM, 20:1 Analog, ISD < 1µA,
TSSOP-28E Package
LT3952 60V, 4A LED Driver with 4000:1 PWM Dimming with
Spread Spectrum
VIN: 3V to 42V, VOUT(MAX) = 60V, 4000:1 PWM, 20:1 Analog, ISD < 1µA,
TSSOP-28E Package
LT3797 Triple Output LED Driver Controller with 3000:1 PWM
Dimming
VIN: 2.5V to 90V, VOUT(MAX) = 100V, 3000:1 PWM, 20:1 Analog, ISD < 1µA,
7mm × 8mm QFN-52 Package
LT3756/LT3756-1/
LT3756-2
High Side 100V, 1MHz LED Controller with 3000:1
PWM Dimming
VIN: 6V to 100V, VOUT: 5V to 100V, 3000:1 PWM, 20:1 Analog, ISD < µA,
3mm × 3mm QFN-16 and MSOP-16E Packages
IVINP
LT3952
VIN
VC
IVINCOMP
SYNC/SPRD
TG TG
ISN
ISMON
ISP
ISN
5V
ISMON
ISP
DIM
PWM
CTRL
VREF
FB
GND
EN/UVLO
OVLO
SS RT INTVCC
INTVCC
3965 TA03
2.2µF
4.7µF
50V
0.1µF
6.8nF
0.1µF
340k
60.4k
14.7k
365k
Q1
249k
64.9k
1.5k
IVINN SW
SW
L1
22µH
10µF
25V
VIN
6V TO 18V 1µF
25V
SHORTLED
OPENLED
SHORTLED
OPENLED
100k100k
350kHz
SYNC
130k
69.8k
LT3470
5V REGULATOR
0.25Ω
M1
TG
ISPISN
LED+
LED–
4V
22µF
D2 D6
D1
8 LEDs
25V
500mA
1µF
50V
D3
D5
SW
D4
0.1µF
100V
GND
LT3965/
LT3965-1
RTCLK
350kHz SYNC
(170Hz PWM)
SDA
SCL
ALERT
ADDR1
EN/UVLOEN/UVLO
D1, D6: DIODES DFLS260
D2, D3: NXP SEMI PMEG6010CEH
D4, D5: CENTRAL SEMI CMSD6263S
2 IN 1 PACKAGE
L1: WURTH 74437349220 22µH
L2: WURTH 74408943330 33µH
Q1, Q2: ZETEX FMMT591
M1: VISHAY Si7415DN
VDD
ADDR2
ADDR3
ADDR4
LEDREF
BIAS
10V
DRN8
DRN7
SRC8
DRN6
SRC7
DRN5
SRC6
DRN4
SRC5
DRN3
SRC4
DRN2
SRC3
DRN1
SRC2
SRC1
VIN
10k
10k
10k100k
5V
SDA
SCL
ALERT
10µF
10V
L2
33µH
V+
INTVCC
LTC6900
DIV
OUT SET
GND
0.1µF
LED+
49.9k
EN/UVLO
BIAS
BIAS UVLO DETECT
9.09k
1k
Q2
Matrix LED Dimmer Powered by a Boost-Buck LED Driver