1/30
L6997S
June 2004
1 Features
■FROM 3V TO 5.5V VCC RANGE
■MINIMUM OUTPUT VOLTAG E AS LOW AS
0.6V
■1V TO 35V INPUT VOLTAGE RANGE
■CONSTANT ON TIME TOPOLOGY
■VERY FAST LOAD TRANSIENTS
■0.6V, ±1% VREF
■SELECTABLE SINKIN G MODE
■LOSSLESS CURRENT LIMIT, AVAILABLE
ALSO IN SINKING MODE
■REMOTE SENSING
■OVP,UVP LATCHED PROTECTIONS
■600µA TYP QUIESCENT CURRENT
■POWER GOOD AND OVP SIGNALS
■PULSE SKIPPING AT LIGTH LOADS
■94% EFFICIENCY FROM 3.3V TO 2.5V
2 Applications
■NETWORKING
■DC/DC MODULES
■DISTRIBUTED POWER
■MOBILE APPLICATIONS
■CHIP SET, CPU, DSP AND MEMORIES
SUPPLY
3 Description
The device is a high efficient solution for networking
dc/dc modules and mobile applications compatible
with 3.3V bus and 5V bus.
It's abl e to regulate an output v oltage as low a s 0.6V.
The constant on time topo logy assures fast load tran-
sient response. The embedded voltage feed-forward
provides nearly constant switching frequency opera-
tion in spite of a wide input voltage range.
An integrator can be introduced in the control loop to
reduce the static output voltage error.
The remote sensing improv es the static and dynamic
regulation, recovering the wires voltage drop.
Pulse skipping technique reduces power consump-
tion at light loads. Drivers current capability allows
output currents in excess of 20A.
STEP DOWN CONTROLLER
FOR LOW VOLTAGE OPERATIO NS
Figure 2. Minimum Component Count Application
L6997S
SHDN
3.3V
INT
VDR
VSENSE
OVP
Vref
GND
GNDSENSE
VFB
VCC
SS
OSC
0.6V
PGOOD
PGND
LGATE
PHASE
HGATE
ILIM
BOOT
Rilim
Css
Cvref
HS
LS
Rin1Rin2
Cin
Cboot
Dboot
L
Cout
Ro1
Ro2
DS
REV. 1
Figure 1. Package
Table 1. Order Codes
Part Number Package
L6997S TSSOP20
L6997S TR Tape & Re el
TSSOP20
L6997S
2/30
Table 2. Absolute Maximum Ratings
Table 3. Thermal Data
Figure 3. Pin Connection (Top View)
Symbol Parameter Value Unit
VCC VCC to GND -0.3 to 6 V
VDR VDR to GND -0.3 to 6 V
HGATE and BOOT, to PHASE -0.3 to 6 V
HGATE and BO OT, to PGND -0.3 to 42 V
VPHASE PHASE -0.3-to 36 V
LGATE to PGND -0.3 to VDR+0.3 V
ILIM, VFB, VSENSE, NOSKIP, SHDN, PGOOD, OVP, VREF,
INT, GND SENSE to GND -0.3 to VCC+0.3 V
BOOT, HGATE
and PHAS E
PINS
Maximum Wit hs tan din g Voltage Rang e
Test Con d ition:CDF-AEC-Q100-002 “Human Body Model”
Accepatance Criteria: “Normal Performance”
±750 V
OTHER PINS ±2000 V
Ptot Power dissipation at Tamb = 25°C 1 W
Tstg Storage temperature range -40 to 150 °C
Symbol Parameter Value Unit
Rth j-amb Thermal Resistance Junction to Ambient 125 °C/W
TjJunction operating temperature range -40 to 125 °C
Table 4. Pin Function
N° Name Description
1 NOSKIP Connect to VCC to force continuous conduction mode and sink mode.
2 GNDSENSE Remote ground sensing pin
3 INT Integrator output. Short this pin to VFB pin and connect it via a capacitor to VOUT to insert the
integrator in the control loop. If the integrator is not used, short this pin to VREF.
4 VSENSE This pin must be connected to the remote output voltage to detect overvoltage and
undervoltage conditions and to provide integrator feedback input.
GNDSENSE
INT
OVP
SHDN
ILIM
OSC
VCC
NOSKIP
PGOOD
LGATE
PGND
VDR
PHASE
HGATE
BOOT1
3
2
4
5
6
7
8
9
18
17
16
15
14
13
19
20
10SS
GND
11
12
VREF
VFB
TSSOP20
INT
VSENSE
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L6997S
5V
CC IC Supply Voltage.
6 GND Signal grou nd
7 VREF 0.6V voltage reference. Connect a ceramic capacitor (max. 10nF) between this pin and
ground. This pin is capable to source or sink up to 250uA
8 VFB PWM comparator feedback input. Short this pin to INT pin to enable the integrator function, or
to VSENSE to disable the integrator function.
9 OSC Connect this pin to the input voltage through a voltage divider in order to provide the feed-
forward function don’t leave floating.
10 SS Soft Start pin. A 5µA constant current charges an external capacitor. Itsvalue sets the soft-
start time do n’t leave floating.
11 ILIM An external resistor connected between this pin and GND sets the current limit threshold don’t
leave floating..
12 SHDN Shutdown. When connected to GND the device and the drivers are OFF. It cannot be left
floating.
13 OVP Open drain output. During the over voltage condition it is pulled up by an external resistor.
14 PGOOD Open drain output. It is pulled down when the output voltage is not within the specified
thresholds. Otherwise is pulled up by external resistor. If not used it can be left floating.
15 PGND Low Side driver ground.
16 LGATE Low Side driver output.
17 VDR Low Side driver supply.
18 PHASE Return pa th of the High Side dr iver.
19 HGATE High side driver output.
20 BOOT Bootstrap capacitor pin. High Side driver is supplied through this pin.
Table 5. Electrical Characteristics
(VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY SECTION
Vin Input voltage range Vout=Vref Fsw=110Khz Iout=1A 1 35 V
VCC,
VDR 35.5V
VCC Turn-onvoltage 2.86 2.97 V
Turn-off voltage 2.75 2.9 V
Hysteresis 90 mV
IqVDR Drivers Quiescent Current VFB > VREF 7 20 µA
IqVcc Device Quiesce nt cu rre nt VFB > VREF 400 600 µA
SHUTDOWN SECTION
SHDN Device On 1.2 V
Device Off 0.6 V
ISHVDR Drivers shutdown current SHDN to GND 5 µA
ISHVCC Devices shutdown current SHDN to GND 1 15 µA
SOFT START SECTION
ISS Soft Start current VSS = 0.4V 4 6 µA
∆VSS Act ive Sof t start and voltage 300 400 500 mV
Table 4. Pin Function (continued)
N° Name Description
L6997S
4/30
CURRENT LIMIT AND ZERO CURRENT COMPARATOR
ILIM Input bias current RILIM = 2KΩ to 200KΩ4.655.4µA
Zero Crossing Comparator offset
Phase-gnd -2 2 mV
KILIM Current limit factor 1.6 1.8 2 µA
ON TIME
Ton On time duration VREF=VSENSE OSC=125mV 720 800 880 ns
VREF=VSENSE OSC=250mV 370 420 470 ns
VREF=VSENSE OSC=500mV 200 230 260 ns
VREF=VSENSE OSC=1000mV 90 115 140 ns
OFF TIME
TOFFMIN Minimum off time 600 ns
KOSC/TOFFMIN OSC=250mV 0.20 0.40
VOLTAG E RE FE RE NC E
VREF Voltage Accuracy 0µA < IREF < 100µA 0.594 0.6 0.606 V
PWM COMPARATOR
Input voltage offset -2 +2 mV
IFB Input Bias Current 20 nA
INTEGRATOR
Over Voltage Clamp VSENSE = VCC 0.62 0.75 0.88 V
Under Voltage Clamp VSENSE = GND 0.45 0.55 0.65 V
Integrator Inp ut Of fse t Voltag e
VSENSE-VREF -4 -4 mV
IVSENSE Input Bias Current 20 nA
GATE DRIVER S
High side rise time VDR=3.3V; C=7nF
HGATE - PHASE from 1 to 3V 50 90 ns
High side fall time 50 100 ns
Low side rise time VDR=3.3V; C=14nF
LGATE from 1 to 3V 50 90 ns
Low side fall time 50 90 ns
PGOOD UVP/OVP PROTECTIONS
OVP Over v oltage threshold with respect to VREF 118 121 124 %
UVP Under voltage threshold 67 70 73 %
Upper thr esh ol d
(VSENSE-VREF)VSENSE rising 110 112 116 %
Lower threshold
(VSENSE-VREF)VSENSE falling 858891%
VPGOOD ISink=2mA 0.2 0.4 V
Table 5. Electrical Characteristics (continued)
(VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
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L6997S
Figure 4. Functional & Block Diagram
+
+
-
PHASE
SENSEGND
Gm
VSENSE
VSENSE
VSENSE
VSENSE
-
-
NOSKIP
0.6V
Reference chain
INT
V
+
-
V
-
+
delay
Toff min
IN
IN
-PHASE
VSENSE
VREF
+
-
+
-
+
+
1.416
1.236V
bandgap
+
mode
no-skipno-skip
OSC
LS control
VREF
VREF
pwm comparator
FB -
+VREF
comparator
positive current limit
VSENSE
PGND
LGATE
VDR
PHASE
HGATE
BOOT
GNDVCCOVPPGOODSHDN
SS
ILIM
OSC
comparator
negative current limit
LS and HS anti-cross-conduction comparators
comp
V(LGATE)<0.5V
comp
V(PHASE)<0.2V
HS control
0.05
ILIM
0.05
overvoltage comparator
undervoltage comparator
-
+
-
IC enable SR
1.12 VREF
control
soft-start
power management
pgood comparators
0.925 VREF
1.075 VREF
-
+
0.6 VREF
5 uA
level shifter
VCC
zero-cross comparator
one-shot
one-shot
Ton min
Ton
Ton= Kosc V(VSENSE)/V(OSC)
VSENSE
mode
PHASE
HS driver
LS driver
Ton
Vcc
V
one-shot
OSC
Ton= Kosc V(VSENSE)/V(OSC)
OUT
S
R
Q
R
S
Q
R
S
Q
L6997S
6/30
4 DEVICE DESCRIPTION
4.1 Constant On Time PWM topology
Figure 5. Loop block schematic diagram
The device implements a Constant On Time control scheme, where the Ton is the high side MOSFET on time
duration forced by the one-shot generator. The On Time is directly proportional to VSENSE pin vol tage and in-
verse to OSC pin voltage as in Eq1:
(1)
where K
OSC
= 180ns and
τ
is the internal propagation delay time (typ. 40ns). The system imposes in steady
state a mini mum On Time c orresponding to V
OSC
= 1V. In fact if the V
OSC
voltage i ncr ease s above 1V the cor-
responding Ton will not decrease. Connecting the OSC pin to a voltage par tition from V
IN
to GND, it allows a
steady-state switching frequency F
SW
independent of V
IN
. It results:
(2)
where
(3)
(4)
The above equations allow setting the frequency divider ratio αOSC once output voltage has been set; note
that such equations hold only if VOSC<1V. Further the Eq2 shows how the system has a switching frequen-
cy ideal ly ind epe nde nt fr om the i npu t vo lta ge. Th e del ay in tro duc es a l igh t dep end enc e from VIN. A mini-
mum Off-Time constraint of about 500ns is introduced in order to assure the boot capacitor charge and to
Q
Vsense
R3
R4
R2
R1
R
S
Vout
Vin
HGATE
LGATE
Q
OSC
FB
Vref
HS
LS DS
PWM comparator
FFSR
One-shot generator
-
+
TON KOSCVSENSE
VOSC
----------------------τ+=
fSW VOUT
VIN
---------------1
TON
----------- αOSC
αOUT
---------------1
KOSC
--------------- αOSC
→fSWKOSCαOUT
== =
αOSC VOSC
VIN
--------------- R2
R2R1
+
--------------------==
αOUT VFB
VOUT
---------------R4
R3R4
+
--------------------==
7/30
L6997S
limit the switching frequency after a load transient as well as to mask PWM comparator output against
noise and spikes.
The system has not an internal c lock, because t his is a hys teretic controller, so the turn on pulse wi ll start if three
conditions are met contempor arily: the FB pi n voltage i s lower than the refer ence volt age, the minimum off time
is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit
value). The voltage at the OSC pin must range between 50mV and 1V to ensure the system linearity.
4.2 Closing the loop
The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin
is internally conncted to the comparator negative pin while the positive pin is connected to the reference voltage
(0.6V Typ.) as in Figure 5. When the FB goes lower than the reference voltage, the PWM comparator output
goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid
noise. After the On-Time (calculated as described in the previous section) the system resets the flip-flop, turns
off the high side MOSFET and turns on the low side MOSFET. For more details refers to the Figure 4.
The voltage drop along ground and supply metal paths connecting output capacitor to the load is a source of
DC error. Further the system regulates the output voltage valley value not the average, as shown in Figur e 6.
So, the voltage ripple on the output capacitor is a source of DC static error (well as the PCB traces). To com-
pensate the DC errors, an integrator network must be introduced in the control loop, by connecting the output
voltage to the INT pin through a capacitor and the FB pin to the INT pin directly as in Figure 7. The internal in-
tegrator amplifier with t he external c apacitor C
INT1
introduc es a DC po le in the control loop. C
INT1
also provides
an AC path for output ripple.
Figure 6. Valley regulation
The integrator amplifier generates a current, proportional to the DC errors, that increases the output capacitance
voltage in or der to compensate the total static error. A v oltage clamp within the devi ce forces anINT pin voltag e
range (V
REF
-50mV, V
REF
+150mV). This is useful to avoid or smooth output voltage overshoot during a load
transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peak-
to-peak amplitude is less than 150mV in steady state.
In case the ripple amplitude is larger than 150mV, a capacitor C
INT2
can be connected between INT pin and
ground to reduce rippl e amplitude at INT pin, otherwise the int egrator will ope rate out of its linear range. Choose
C
INT1
according to the following equation:
(5)
where g
INT
=50 µs is the integrator transconductance,
α
OUT
is the output divider ratio given from Eq4 and F
U
is
the close loop bandwidth. This equation holds if C
INT2
is connected between INT pin and ground. C
INT2
is give n
by:
Time
Vout
Vref
<Vout>
DC Error Offset
CINT1 gINT αOUT
⋅
2πFu
⋅⋅
-------------------------------=
L6997S
8/30
(6)
Where
∆
V
OUT
is the output ripple and
∆
V
INT
is the required ripple at the INT pin (100mV typ).
Figure 7. Integrator loop block diagram
Respect to a tr adi tional P WM controller, that has a n i ntern al osc il lator s etti ng the switching frequency, i n a hys-
teretic sy stem the frequency can chang e with some parameters. For examp le, whi le in a standard fixed switch-
ing frequency topology, the increase of the losses (increasing the output current, for example) generates a
variation in the On Time and Off Time, in a fixed On Time topology , the increase of the losses generates only
a variation on the Off Time, changing the switching frequency. In the device is implemented the voltage feed-
forward cir cuit that all ows c ons tant swi tchi ng fr equency during s teady -sate oper atio n and withi nthe input range
variation. Any way there are many factors affecting switching frequency accuracy in steady-state operation.
Some of these are internal as dead times, which depends on high side MOSFET driver. Others related to the
external components as high side MOSFET gate charge and gate resistance, voltage drops on supply and
ground rails, low side and high side RDSON and inductor parasitic resistance.
During a positive load transient, (the output current increases), the converter switches at its maximum frequency
(the period is TON +TOFFmin) to recover the output voltage drop. During a negative load transient, (the output
current decreases), the device stops to switch (high side MOSFET remains off).
4.3 Transition from PWM to PFM/PSK
To achieve high efficie ncy at ligh t load conditi ons, PFM mode i s provided. The PFM mode differs from the PWM
mode essentially for the off phase; the on phase is the same. In PFM after a On cycle the system turns-on the
low side MOSFET until the inductor current goes down zero, when the zero-crossing comparator turns off the
low side MOSFET. In PWM mode, after On cycl e, the system kee ps the low si de MOSFET on until t he next turn-
on cycle, so the energy stored in the output capacitor will flow through the low side MO SFET to ground. The
PFM mode is naturally implemented in an hysteretic controller enabling the zero current comparator by en-
abling, in fact in PFM mode the system reads the output voltage with a comparator and then turns on the high
side MOSFET when the output voltage goes down to r eference value. The devi ce works in discontinuous mod e
CINT2
CINT1
----------------VOUT
∆
∆VINT
------------------=
PCB TRACES
LOAD
F rom Vsense
Q
Cint1
R1
INT
Vref
FB DS
R
S
Vout
Vin
HGATE
LGATE
Q
OSC
Vref
One-shot generator
FFSR
PWM comparator
Vsense
Gndsense
R2
Cint2
HS
LS
Integrator amplifier
+
-
-
+
+
-
9/30
L6997S
at light load and in cont inuous mode at high loa d. The transition from PFM to PWM occu rs when load curre nt is
around half the inductor current ripple. This threshold value depends on V
IN
, L, and V
OUT
. Note that the higher
the inductor value is, the smaller the threshold is. On the other hand, the bigge r the inductor value is , the slower
the transient response is. The PFM waveforms may appear more noisy and asynchronous than normal opera-
tion, but th is is n orm al behav iour mai nly due to the ver y low load. If the PFM is not compatible with the applic a-
tion it can be disabled connecting to V
CC
the NOSKIP pin.
4.4 Softstart
After the devi ce is turned on the SS pin volt age begins to increase and the sys tem starts to switch. The softstar t
is realized by gradually increasing the current limit threshold to avoid output overvoltage. The active soft start
range for the V
SS
voltage (where the output current limit increase linearly) is from 0.6V to 1V. In this range an
internal current source (5
µ
A Typ) charges the c apacitor on the SS pin; the reference current ( for the current limi t
comparator) forced through ILIM pin is proportional to SS pin voltage and it saturates at 5
µ
A (Typ.). When SS
volt age is close to 1V the maximum cur rent lim it is active. Output protecti ons OVP & UVP are disabled until the
SS pin voltage reaches 1V (see figure 8).
Once the SS pin voltage reaches the 1V value, the voltage on SS pin does n't impact the system operatio n any-
more. If the SHDN pin is turned on before the supplies, the power section must be turned on before the logic
section. While if the supplies are applied with the SHND pin off, the start up sequence doesn't meter.
Figure 8. Soft -Start Diagram
Because th e sy ste m i mplements the soft start by control ling the inductor current, the soft start capacitor shoul d
be selected based on of the output capacitance, the current limit and the soft start active range (
∆
V
SS
).
In order to selec t the softstart capacitor it must be imposed that the output voltage reaches the final value befor e
the soft start voltage reaches the under voltage value (1V). After this UVP and OVP are enable.
The time necessary to charge the SS capacitor up to 1V is given by:
(7)
In order to calculate the output voltage chargin time it should be considered that the inductor current function
can be supposed linear function of the time.
(8)
Time
Time
0.6V
Maximum current limit
Soft-start active range
5µA
4.1V
1V
Ilim current
Vss
TSS CSS
()
1V
Iss
-------- CSS
⋅=
ILt,CSS
()
Rilim/Rdson KILIM ISS t⋅⋅⋅()
VSS CSS
⋅∆()
---------------------------------------------------------------------------=
L6997S
10/30
so considering zero the output load the output voltage is given by:
(9))
indicating with V
out
the final value, the output charging time can be estimated as:
(10)
the minimum C
SS
value is given imposing this condition:
T
out
=T
SS
(11)
4.5 Current limit
The curr ent li mi t com parato r sens es the induc tor current through t he lo w si de MOSFET RDS
ON
drop and c om-
pares this value with the ILIM pin voltage value. While the current is above the current limit value, the control
inhibits the high side MOSFET Turn On.
To properly set the c urrent l imi t threshol d, it sho uld be noted that thi s i s a valley cur rent li mit. The Av er age cur -
rent depends on the inductor value, V
IN
V
OUT
and switching frequency.
The average output current in current limit is given by:
(12)
Thus, to set the current threshold, choose RILIM according to the following equation:
(13)
In overc urrent conditions the s ystem keeps the current constant until the output v oltage meets the und ervoltage
threshold . The negative valley c urrent lim it, for the si nk mode, is set automati cally at the same va lue of the pos -
itive valley current limit. The average negative current limit differs from the positive average current limit by the
ripple current; this difference is due to the valley control technique.
The current limit system accuracy is function of the precision of the resistance connected to the ILIM pin and
the low side MOSFET RDS
ON
accuracy. Moreover the voltage on ILIM pin must range between 10mV and 1V
to ensure the system linearity.
Figure 9. Current limit schematic
Vout t,CSS
()
Qt,C
SS
()
Cout
-------------------------Rilim/Rdson KILIM ISS t2
⋅⋅⋅()
Cout VSS CSS 2⋅⋅∆⋅()
-----------------------------------------------------------------------------==
Vout CSS
() Vout Cout VSS CSS 2⋅⋅∆⋅⋅()
Rilim/Rdson KILIM ISS
⋅⋅()
----------------------------------------------------------------------------0.5
=
IOUTCL Imax valley I∆
2
-----+=
Imax valley RILim
Rdson
----------------- KILIM
⋅=
Positive and negative current limit
RILIM
5µA
Current
Comparator
To
logic
PGN
DPHASE
To inductor
LS
11/30
L6997S
4.6 Protection and fault
The load protection is realized by using the VSENSE pin. Both OVP and UVP are latched, and the fault condition
is indicated by the PGOOD and the OVP pins. If the output voltage is between the 89% (typ.) and 110% (typ)
of the regulated value, PGOOD is high. If a hard overvoltage or an undervoltage occurs, the device is latched:
low sid e MOSFET and, hi gh side MOSFET are turned off and PGOOD goes l ow. In ca se the system detects a n
overvoltage the OVP pin goes high.
To recover the functionality the device must be shut down and restarted the SHDN pin, or by removing the sup-
ply, and restarting the devicewith the correct sequence.
4.7 Drivers
The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching tran-
sitions. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating
driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The
drivers have the adaptive anti-cross-conduction protection, which prevents from having bothhigh side and low
side MOSFET on at the s ame ti me, avoiding a hig h cur r ent to flow from VIN to GND. When high s ide MOSFET
is turned off the voltage on the PHASE pin begins to fall; the low si de MOSFET is turned on only when the volt-
age on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage
reaches 500m V. This is important since the driv er can work properly with a large r ange of external power MOS-
FETS.
The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the
MOSFET gate charge the switching frequenc y and the dr iv er voltage. S o the power dissipati on of the devic e is
function of the external power MOSFET gate charge and switching frequency.
(14)
The maximum gate charge values for the low side and high side are given by:
(15)
(16)
Where f
SW0
= 500Khz. The equations above are vali d for T
J
= 150°C. If the system temper ature is lower the Q
G
can be higher.
For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation;
in this case the maximum value is Q
MAXLS
= 125nC.
The low side driver has been designed to have a low resistance pull-down transistor, approximately 0.5 ohms.
This prevents undesired LS MOSFET Turn On during the fast rise-time of the pin PHASE, due to the Miller ef-
fect.
When the 3.3V bus is used to supply the drivers, ULTRA LOGIC LEVEL MOSFETs should be selected , to be
sure that the MOSFETs work in pr operly way.
Pdriver Vcc QgTOT FSW
⋅⋅=
QMAXHS fSW0
fSW
-------------75nC⋅=
QMAXLS fSW0
fSW
-------------125nC⋅=
L6997S
12/30
5 APPLICATION INFORMATION
5.1 5A Demo board description
The demo board shows the device operation in this condition: VI
N
from 3.3V to 5V, I
OUT
=5A V
OUT
=1.25V. The
evaluation boa rd l et use th e sy stem wi th 2 diffe rent volta ges ( V
CC
the supply for the IC and V
IN
the power input
for the conversion) so replacing the input capacitors the power input voltage could be also 35V. When instead
the input volt age (V
IN
) is equal to the V
CC
it should be better joinin g them with a 10
Ω
resistor in order to filter the
device input voltage. On the topside demo there are two different jumpers: one jumper, near the OVP and POW-
ER GOOD test points, is used to shut down the device; when the jumper is present the device is in SHUTDOWN
mode, to r un the dev ic e remove the jumper. The other jumper , near the V
REF
test point, is used to set the PFM/
PSK mode. W hen the jumper is pres ent, at light load, th e system will go in PFM mode; if ther e is not the jumper ,
at li ght load, the system wi ll r emain in PWM mo de. In the demo bottom side the re are two others di fferent jump-
ers. They are used to set or remove the INTEGRATOR configuration. When the jumpers named with INT label
are closed AND the jumpers named with the N OINT label are open the integrator configuration is set. Some-
times the integrator configuration needs a low frequency filter the to reduce the nois e interaction. In this case
instead c lose the INT jumper s put there a resistor and after a capaci tor to grou nd (as in the s chematic diagr am);
the pole value is around 500Khz but it should be higher enough than the switching frequency (ten times). On
the opposite when the jumpers named with the NOINT are closed and the jumpers named with INT are open
the NON INTEGRATOR configuration is selected. Refer to the Table 1 and 2 for the jumpers connection.
Figure 10. Demoboard Schematic Diagram
C14,C15 R3
R10
TP1
TP2
C10
R6
Q1
D2
TP3
C2
C6
R8 C12
C9
R9
R1
D1
R2
R5
SD NS
L1
R7 C7,C13
C11
C4
R4
Rn
C3
C1
Q2
Cn
INT
INT
NOINT
NOINT
C5
C8
Vcc
SHDN VREF
OSC
NOSKIP
VDR
INT
VFB
GNDSENSE
SS
BOOT
ILIM
HGATE
PHASE
LGATE
PGND
GND
VSENSE
OVP
PGOOD
VCC
VOUT
GNDOUT
GNDin
VIin
L6997S
J1
13/30
L6997S
5.2 Jumper Connection
Table 6. Jumper connection with integrator
* This component is not necessary, depends f rom the output ESR ca pacitor. See the int egrator se ction.
Table 7. Jumper connection without integra tor
5.3 DEMOBOARD LAYOUT
Real dimensions: 4,7 cm X 2,7 cm (1.85 inch X 1. 063 inch)
Component Connection
C1 Mounted
C2 Mounted *
INT Close
NOINT Open
Component Connection
C1 Not mounted
C2 Not Mounted
INT Open
NOINT Close
Figure 11. Top side components placement
Figure 12. Bottom side Jumpers distribution
Figure 13. Top side layout
Figure 14. Bottom side layout
L6997S
14/30
Table 8. PCB Layout guidelines
Goal Suggestion
To minimize radiation and magnetic
coupling with the adjacent circuitry. 1) Minimize s witching current loop areas. (For example placing CIN, High Side
and Low side MOSFETS, Shottky diode as close as possible).
2) Place controller placed as close as possible to the power MOSFETs.
3) Group the gate drive components (Boot cap and diode) near the IC.
To maximize the efficiency. Keep power traces and load connections short and wide.
To ensure high accuracy in the
current sense system. Make Kelvin connection for Phase pin and PGND pin and keep them as close
as possible to the Low Side MOSFETS.
To reduce the noise effect on the IC. 1) Put the feedback component (like output divider, integrator network, etc) as
close as possible to the IC.
2) Keep the feedback traces parallel and as close as possible. Moreover they
must be routed as far as possible from the switching current loops.
3) Make the controller ground connection like the figure 8.
Table 9. Component list
The component list is shared in two sections: the first for the general-purpose component, the second for
power section:
Part name Value Dimensio n Notes
GENERAL-PURPOSE SECTION
RESISTOR
R1, R5, R9, R10 33kΩ0603 Pull-up resistor
R2 1kΩ0603 Output resistor divider (To set output voltage)
R3 1.1kΩ0603
R4 0603 Input resistor divider (To set switching frequency)
R6 470kΩ0603
R7 0Ω0603
R8 0603 Current limit resistor
CAPACITOR
C1 330pF 0603 First integrator capacitor
C2 N.M. 0603 Second integrator capacitor
C3 1nF 0603
C4 100nF 0603
C5 1µFTantalum
C6 10nF 0603
C9 10nF 0603 Softstart capacitor
C10 100nF 0603
C11 100nF 0603
C8, C12 47pF 0603
DIODE D1 BAR18 POWER SECTION
INPUT CAPACITORS
C7, C13 47µF ECJ4XF0J476Z
PANASONIC
15/30
L6997S
Notes: 1. N.M.=Not Mounted
2. The demoboard with this component list is set to give: VOUT = 1.25 V, FSW = 270kHz with an input voltage around VIN = VCC =
3.3V-5V and with the integrator feature.
3. The diode ef ficiency impac t is very low; it is not a necessa r y component.
4. All capacitors are intended ceramic type otherwise specified.
5.4 EFFICIENCY CURVES
Source mode
V
IN
= 3.3V V
OUT
= 1.25V F
SW
= 270kHz
Figure 15. Efficiency vs output current
Part name Value Dimensio n Notes
OUTPUT CAPACITORS
C14, C15 220µF2R5TPE220M
POSCAP
INDUCTOR
L1 2.7 µHDO3316P-272HC
COILCRAFT
POWER MOS
Q1,Q2 STS5DNF20V STMicroelectronics Double mosfet in sigle package
DIODE D2 STPS340U STMicroelectronics 3
Table 9. Component list (continued)
The component list is shared in two sections: the first for the general-purpose component, the second for
power section:
0,0
10,0
20,0
30,0
40,0
50,0
60,0
70,0
80,0
90,0
100,0
0,0 1,0 2,0 3,0 4,0 5,0 6,0
Cu rren t [ A]
Eff [%]
PFM mode PWM mode
L6997S
16/30
6 STEP BY STEP DESIGN
Application conditions: V
IN
= 3.3V, ±10% V
OUT
= 1.25V I
OUT
= 5A F
SW
= 270kHz
6.1 Input capacitor.
A pulsed current (with zero average value) flows through the input capacitor of a buck converter. The AC com-
ponent of this current is quite high and dissipates a conside rable amount of power on the ESR of the capacitor:
(17)
The RMS current, which the capacitor must provide, is given by:
(18)
Where
δ
is the duty cycle of the application
Neglecting the last term, the equation reduces to:
(19)
which maximum value corresponds to to
δ
= 1/2 and is equal I
out
/2
Therefore, in worst case, the input capacitors should be selected with a RMS ripple current rating as high as
half the respective maximum output current.
Electrolytic capacitors are the most used because theyare the cheapest ones and are available with a wide
range of RMS current ratings. The only drawback is that, for a givenripple current rating, they are physically larg-
er than other capacitors. Very good tantalum capacitors are c oming available, with very low ESR a nd small size.
The only probl em is that they occas ional ly can bur n i f subj ected to very high cur rent duri ng the char ge. So, i t is
better avoid this type of capacitors for the input filter of the device. In fact, they can be subjected to high surge
current when connected to the power supply. If available for the requested capacitance value and voltage rating,
the cerami c capacitors have usually a higher RMS current r ating for a gi ven physica l dimension (due to the very
low ESR). The drawback is the quite high cost. Possible solutions:
With our parameter from the equation 3 it is found:
Icin
rms
= 2.42A
6.2 Inductor
To define the inductor, it is necessary to determine firstly the inductance value. Its minimum value is given by:
(20)
where RF =
∆
I/I
OUT
(basically it is approximately 30%).
10µF C34Y5U1E106ZTE12 TOKIN
22µF JMK325BJ226MM
TAIYO-YUDEN
47µF ECJ4XF0J476Z
PANASONIC
33µF C3225X5R0J476M
TDK
PCIN ESRCIN Iout2Vin Vin Vout–()⋅Vin2
------------------------------------------------
⋅⋅=
Icinrms Iout2δ1δ–()
δ
12
------ IL
∆()
2
+=
Icinrms Iout δ1δ–()=
Lmin VoVinmax Vo
–()⋅
FSW Iout RF Vinmax
⋅⋅⋅
---------------------------------------------------------------
≥
17/30
L6997S
With our parameters: Lmin
≥
2
µ
H
The saturation current must be higher then 5A
6.3 Output capacitor and ripple voltage
The output capacitor is selected based on both static and dynamic output voltage accuracy. The static output
voltage accuracy depends mostly on the ERS of the output capacitor, while the dynamic accuracy usually de-
pends both on the ESR and capacitance value.
If the static precision is ±1% for the 1.25V output voltage, the output ripple is ±12.5mV.
To determine the ESR value from the output precision is necessary to calculate the ripple current:
(21)
Where F
SW
= 270kHz.
From the Eq. above the ripple current is around 1.25A.
So the ESR is given by:
(22)
The dynamic specifi cations are sometimes more relaxed than the st atic r equir ements , Any way a mi nimum out-
put capa citance must be ensured to avoid output voltage vari ation due to the charge an d discharge of Cout dur-
ing load transients.
To allow the device control loop to work properly, the zero introduced by the output capacitor ESR (
τ
= ESR ·
Cout) must be at least ten times smaller than switching frequency. Low ESR tantalum capacitors, which ESR
zero is close to ten kHz, are suitable for output filtering. Output capacitor value C
OUT
and its ESR, ESRC
OUT
,
should be large enough and small enough, respec tively, to keep o utput voltage within the accuracy range during
a load transient, and to give the device a minimum signal to noise ratio.
The current ripple flows through the output capacitors, so the should be calculated also to sustain this ripple:
the RMS current value is given by Eq. 18.
(23)
But this is usually a negligible constrain.
Possible solutions:
Multilayer capacitors can not be used because their very low ESR.
6.4 MOSFE T ’s and Sc hott ky Diod es
A 3.3V bus powers the gate drivers of the device, the use ultra low level MOSFET is highly recommended, es-
pecially for high current applications. The MOSFET breakdown voltage V
BRDSS
must be greater than VINMAX
with a certain margin.
The RDS
ON
can be selected once the allowable power dissipation has been established. By selecting identical
330µF EEFUE0D331R
PANASONIC
220µF2R5TPE220M
POSCAP
I∆Vin Vo–
L
-----------------------Vo
Vin
--------- Tsw
⋅⋅=
ESR Vripple
∆I∆
2
-----
--------------------- 25mV
1.25
----------------=20mΩ==
Icoutrms 1
23
-----------IL
∆=
L6997S
18/30
Power MOSFET for us and ls, the total power they dissipate does not depend on the duty cycle. Thus, if PON
is this power loss (few percent of the rated output power), the required
RDS
ON
(@ 25 °C) can be derived from:
(24)
α
is the temperature coefficient of RDS
ON
(typically,
α
= 510
-3
°C
-1
for these low-voltage classes) and T the
admitted temperature rise. It is worth noticing, however, that generally the lower RDS
ON
, the higher is the gate
charge Q
G
, which leads to a higher gate drive consumption. In fact, each switching cycle, a charge Q
G
moves
from the input source to ground, resulting in an equivalent drive current:
(25)
A SCHOTTKY diode can be added to increase the system efficiency at high switching frequency (where the
dead times could be an important part of total switching period).
This optional diode must be placed in parallel to the synchronous rectifier must have a reverse voltage VRRM
greater than VIN
MAX
. The current size of the diode must be s elec ted i n order to k eep it i n safe operati ng condi -
tions. In order to use l ess space than possible, a double MOSFET in a single pac kage is chos en: STS5DNF20V
6.5 Output voltage setting
The first step is choosing the output divider to set the output voltage. To select this value there isn't a criteria,
but a low divi der networ k value (around 100
Ω
) decries the effi ciency at low cur rent; inst ead a high value di vider
network (100K
Ω
) increase the noise effects. A network divider values from 1K
Ω
to 10K
Ω
is right. We chose:
R3 = 1K
Ω
R2 = 1.1K
Ω
The device output voltage is adjustable by connecting a voltage divider from output to VSENSE pin. Minimum
output volta ge is V
OUT
=VREF=0.6V. Once output di vider and frequency divider have be en designed as to obtai n
the required output voltage and switching frequency, the following equation gives the smallest input voltage,
which allows L6997S to regulate ( which corresponds to T
OFF
=T
OFFMIN
):
(26)
6.6 Voltage Feedforward
From the equations 1,2 and 3, choosing the swit ching frequency of 270kHz the resistor di vider can be selected .
For example:
R3 = 470K
Ω
R4 = 8.5K
Ω
6.7 Current limit resis tor
From the equation 8 the valley current limit can be set considering the RDS
ON
STS5DNF20V and I
CIR
= 5A:
R8 = 120K
Ω
6.8 Inte grat or cap ac ito r
Let’ s assume F
U
= 15kHz, V
OUT
= 1.25V.
Since V
REF
= 0.6V, from equation 2, of the device description, it follows
α
O
UT
= 0.348 and, from equation 5 it
foll ows C = 250pF. The output ripple is around 22 mV, so the system doesn' t need the secon d integrator capac -
itor.
RDSON PON
Iout21αT∆⋅+()⋅
-------------------------------------------------=
Iq Qg FSW
⋅=
δ1αOSC
αOUT
---------------1
KOSC
TOFF,MIN
--------------------------
MAX
----------------------------------------------
⋅–<
19/30
L6997S
6.9 Soft start capacitor
Considering the soft start equations (Eq. 11) at page 10, it can be found:
C
SS
= 150pF
The equations ar e valid without load. W hen an active load is present the equations r esult more co mplex; further
some active loads have unexpected effect, as higher current than the expected one during the soft start, can
change the start up time.
In this case the capacitor value can be selected on the application; anyway the Eq11 gives an idea about the
C
SS
value.
6.10Sink mode
Figure 16. Efficiency vs output current
7 15A DEMO BOARD DESCRIPTION
The evaluation board shows the device operation in these conditions: V
IN
= 3.3V V
OUT
= 1.8V I
OUT
= 15A, F
SW
= 200KHz wi thout the in tegra tor feature. The evaluation board has two di fferen t in put v oltages : V
CC
[from 3V to
5.5V] used to suppl y the device and the V
IN
[up to 35V] for the power conversion. In this way, changing the pow-
er components configuration (C
IN
, C
OUT
, MOSFETs, L) it is possible evaluate the device performance in differ-
ent conditions . It is also possible to mount a linear regulator on board used to generate the V
CC
. On the top side
are also present two switches and four jumpers. The tw o switches have different goals: the one nearest to the
V
CC
is used to turn on/off the device when the V
CC
and V
IN
are both present; the other one, near to R11 is used
to turn on/off the PFM feature. The device can be turned on also with the power supply, but a correct start up
sequence is mandatory. V
IN
has to be raised first and then the V
CC
can be applied too. If the correct sequence
is not respected the device will not start up. The jumpers are used to set the integrator feature and to use the
remote s ensi ng; for m ore info rmation refers to the J umper s table. Sometimes when using the integrator config-
uration a low frequency filter is required in order to reduce the noise interaction. The pole value should be at
least five times higher than the switching frequency. The low pass filter should be inserted in this way: the re-
sistor, in the place of the INT jumper position and the capacitor between the resistor and ground (refers to the
schematic).
0,0
10,0
20,0
30,0
40,0
50,0
60,0
70,0
80,0
90,0
100,0
0,01,02,03,04,05,0
Current [A]
E ff [%]
L6997S
20/30
Figure 17. L6997S Schematic diagram
7.1 UMPERS CONNECTION
Table 10. Jumper connection with integrator
*This component is not necessary, depends from the output ESR capa citor. See the int egrator section.
Table 11. Jumper connection without integrator
Component Connection
C4 Mounted
C7 Mounted*
INT Close
NOINT Open
Component Connection
C4 Not mounted
C7 Not Mounted
INT Open
NOINT Close
PGND
PHASE
GNDSENSE
VSENSE
LGATE
BOOT
HGATE
VDR
FB
OSC VCC
VREF
NOSKIP
OVP
PGOOD
SHDN
V
CC
L6997
GND
SS
INT
R10
R9
C13, C14, C15,
C16, C17, C18
R3
R4 C5
R5
C22
C3
D1
C19
Q1, Q2, Q3
Q4, Q5, Q6
D2
C7 C8 C9
C10, C11
C12
C20
C21 R8
C23
NOINT
INT
NOINT INT
C6 C25
C4
C7
C
N
R
N
TP1 TP2
TP3
R12
R11 R7
R6
V
OU
T
C2
SW1
R13 C24
L
Vin
L6997S
21/30
L6997S
7.2 DEMO BOARD LAYOUT
Real dimensions: 5.7cm x 7.7cm (2.28inch x 3. 08inch)
Figure 18. PCB layout: bottom side
Figure 19. PCB Layout: Top side
Figure 20. Internal ground plane
Figure 21. Power & signal plane
Table 12. PCB Layout guidelines
Goal Suggestion
To minimize radiation and magnetic
coupling with the adjacent circuitry. 1) Minimize s witching current loop areas. (For example placing CIN, High Side
and Low side MOSFETS, Shottky diode as close as possible).
2) Place controller placed as close as possible to the power MOSFETs.
3) Group the gate drive components (Boot cap and diode) near the IC.
To maximize the efficiency. Keep power traces and load connections short and wide.
To ensure high accuracy in the
current sense system. Make Kelvin connection for Phase pin and PGND pin and keep them as close
as possible to the Low Side MOSFETS.
To reduce the noise effect on the IC. 1) Put the feedback component (like output divider, integrator network, etc) as
close as possible to the IC.
2) Keep the feedback traces parallel and as close as possible. Moreover they
must be routed as far as possible from the switching current loops.
3) Make the controller ground connection like the figure 8.
L6997S
22/30
Table 13. Component list
The component list is shared in two sections: the first for the general-purpose component, the second for
power section:
Part name Value Dimension Notes
GENERAL-PURPOSE SECTION
RESISTOR
R1 N.M. 0603 Output resistor divider for the linear regulator.
R2 N.M. 0603
R3 560kΩ0603 Inpu t res ist or di vi der ( To set s w itc hin g fre que ncy)
R4 5.6kΩ0603
R5 47Ω0603
R6, R7, R11, R12 33kΩ0603
R8 62kΩ0603 Current limit resistor (To set current limit)
R9 2.7kΩ0603 Output resistor divider (To set output voltage)
R10 1.3kΩ0603
R13 220Ω0603
CAPACITOR
C1 220nF 0805
C2 47µF KEMET-16V
C3 220nF 0805
C4 15 0pF 0603 Fir st inte grator capacito r
C5 47pF 0603
C6 10nF 0603
C7 N.M. 0603 Second integrator capacitor
C19 220nF 0805
C20 220nF 0603 Softstart capacitor
C21 47pF 0603
C22 220nF 0805
C23 0603 N.M.
C24 1nF 0603
C25 1µFTantalum
DIODES
D1 BAT54 25V
POWER SECTION
OUTPUT CAPACITOR S
C11-C12 2X680µF T510x687(1)004AS
KEMET Output capacitor C8, C9, C10 N.M.
INPUT CA PACITORS
C13, C14, C16, C17,
C15 C18 100µF ECJ5YF0J1072
PANASONIC Input capacitor
47µF ECJ5YF1A4767
PANASONIC
INDUCTOR
L1 1.8µH ETQF6F1R8BFA
PANASONIC
POW E R MO S
Q1,Q2 SI4442DY VISHAY Siliconix Q3 N.M.
Q5,Q6 SI4442DY VISHAY Siliconix Q4 N.M.
INTEGRATED CIRCUIT
U1 L6997S
23/30
L6997S
7.3 EFFICIENCY CURVES
Figure 22. Efficiency vs output Current
Table 14. Efficiency Curves For Different Applications (VIN up to 25V)
Part name Value Dimension Notes
GENERAL-PURPOSE SECTION
RESISTOR
R1 100Ω0603 Output resistor divider f or the linear regulator.
R2 300Ω0603
R3 560kΩ0603 Input resistor divider (To set switching frequency)
R4 10kΩ0603
R5 47Ω0603
R6, R7, R11, R12 33kΩ0603
R8 47kΩ0603 Current limit resistor (To set current limit)
R9 2,7kΩ0603 Output resistor divider (To set output voltage)
R10 1kΩ0603
R13 220Ω0603
CAPACITOR
C1 220 nF 0805
C2 47µFKEMET-16V
C3 220nF 0805
C4 150pF 0603 First integrator capa cit or
C5 47pF 0603
C6 10nF 0603
C7 330pF 0603 Second integrator capacitor
C19 220nF 0805
C20 10nF 0603 Softstart capacitor
C21 47pF 0603
C22 220nF 0805
C23 0603 N.M.
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Output C ur rent (A)
Efficiency (%)
Vcc=Vin=3.3V
Fsw=200KHz
Vout=0.9V
Vout=1.2V
Vout=1.5V
Vout=1.8V
Vout=2.5V
L6997S
24/30
NOTE: For the 25V to 12V conversion the induc tor used is: 77120A core 7T.
7.4 EFFICIENCY CURVES
Part name Value Dimension Notes
C24 1nF 0603
C25 1µFTantalum
DIODES
D1 BAT54 25V
POWER SECTION
OUTPUT CAPACITORS
C11-C12 2X100µF B45197-A3107-
K409
EPCOS
Output capacitor C8, C9, C10 N.M.
INPUT CAPACITORS
C13, C14, C16,
C17, C15 C18 10µF C34Y5U1E106Z
TOKIN Input capacitor
10µF C3225Y5V1E106Z
TDK
10µF ECJ4XF1E106Z
PANASONIC
10µF TMK325F106ZH
TAIYO YUDEN
INDUCTOR
L1 3 µH T5 0-5 2 Co re, 7T
AWG15
POWER MOS
Q1,Q2 STS11NF3LL STMicroelectronics Q3 N.M.
Q5,Q6 STS11NH3LL STMicroelectronics Q4 N.M.
DIODES
D2 STPS2L25U STMicroelectronics 25V
INTEGR ATED CIR CUIT
U1 L6997S
Table 14. Efficiency Curves For Different Applications (VIN up to 25V) (continued)
Figure 23. Efficiency vs output Current Figure 24. Efficiency vs output Current
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
0.9V
1.2V
1.5V
1.8V
2.5V
Vo = 3.3V
Vin = Vcc = 5V
Fsw = 200KHz
Output Current (A)
Efficiency (%)
50
55
60
65
70
75
80
85
90
95
100
012345678910111213141516171819
Output Current (A)
Efficiency (%)
Vin = 12V
Vcc = 5V
Fsw = 200KHz
0.9V
1.2V
1.5V
2.5V
3.3V
Vo = 5V
1.8V
25/30
L6997S
Figure 25. Efficiency Vs Output Current Figure 26. Efficiency Vs Output Current
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
Output Current [A]
Eff [%]
VOUT = 12V
VIN = 25V
VCC = 5V
FSW = 200KHz
VOUT = 5V
VOUT = 3.3V
0
10
20
30
40
50
60
70
80
90
100
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
Output Current [A]
Eff [% ]
VOUT = 12V
VIN = 33V
7.5 DDR MEMORY AND TERMINATION SUPPLY
Double data rate (DDR) memories require a particular Po wer Management Architecture. This is due to fact that
the trace betw een the dr iving c hipse t and the mem ory inpu t must be termin ated wit h resis tors. Sin ce the Ch ipset
dri ving t he Memo ry has a pus h pu ll o utpu t b uffer , the Ter minati on v olt ag e mu st b e capa ble o f so urc ing and sin k-
ing current. Moreover, the Termination voltage must be equal to one half of the memory supply (the input of the
memory is a differential stage requiring a reference bias midpoint) and in tracking with it. For DDRI the Memory
Supply is 2.5V and the Termination voltage is 1.25Vwhile for the DDRII the Memory Supply is 1.8V and the Ter-
mina ti on v ol ta ge is 0.9 V . Fi gu r e 27 sh o ws a com p lete DDRII Memory and Termination Suppl y re al i z ed by us i ng
2 x L6997S. The 1.8V section is powering the memory, while the 0.9V section is providing the termination voltage.
Figure 27. Application Idea: DDRII Memory Supply
L6997
PGND
PHASE
GNDSENSE
VSENSE
LGATE
BOOT
HGATE
VCCDR
FB
OSC VCC
VREF
NOSKIP
OVP
PGOOD
SHDN
VCC
L6997
GND
SS
ILIM U2
GNDSENSE
VSENSE
FB
PGND
LGATE
PHASE
HGATE
BOOT
VCCDR
VCC
OSC
NOSKIP
INT
VREF SHDN PGOOD OVP GND
U1
SS
ILIM
VIN
VCC
INT
+
-
CHIPSET
MEMORY
SUPPLY
VREF
BUS
TERMINATION
NETWORK
Vddq
1.8V@15A
Vtt
0.9V@- 5A
+
R
2R
2R
R
STS8DNF3LL
STS11NF3LL
STS11NF3LL
L6997S
L6997S
L6997S
26/30
The current required by the Memory and Termina-
tion supply, depends on the memory type and
size. The figures 28 and 29 show the efficiency for
the termination section of the application shown in
fig. 27.
Figure 28 . Eff. vs. Outp ut Current S ource Mode
Figure 29. Eff. vs Output Current sink mode
8 Typical Operati ng Characteristics
Figure 30.
Load t ransi ent resp onse f ro m 0A t o 5 A .
.
Figure 31. Normal functionality in SINK mode..
70
75
80
85
90
95
100
0234567
Output Current (A)
Efficiency (%)
1
Vout = 0.9V
Vcc = 5V
Fsw = 200 KHz Vin = 12V
Vin=1.8V
60
65
70
75
80
85
90
95
100
01234567
Output c urre nt (A)
Efficiency (% )
Vin=12V
Vin = 1.8V
Vin = 12V
Vout=0.9V
Vcc=5V
Fsw=200KHz
Ch1-> Inductor current
Ch2-> Phase Node
Ch3-> Output voltage
Ch1-> Inductor current
Ch2- > Ph as e Nod e
Ch3-> Ou tp ut voltage
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Figure 32. Normal functionality in PWM mode.
Figure 33. Normal functionality in PFM mode.
Figure 34. Start up waveform with 0A load.
Figure 35. Start up waveform with 5A load..
Ch1-> Inductor current
Ch2-> Phase Node
Ch3-> Output voltage
Ch1-> Inductor current
Ch2-> Phase Node
Ch3-> Output voltage
Ch1-> Inductor current
Ch2-> Soft start Voltage
Ch3-> Output voltage
Ch1-> Inductor current
Ch2-> Soft start Voltage
Ch3-> Output voltage
L6997S
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Figure 36. TSSOP20 Mechanical Data & Package Dimensions
OUTLINE AN D
M E CHAN ICA L DA TA
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.20 0.047
A1 0.050 0.150 0.002 0.006
A2 0.800 1.000 1.050 0.031 0.039 0.041
b 0.190 0.300 0.007 0.012
c 0.090 0.200 0.004 0.008
D (1) 6.400 6.500 6.600 0.252 0.256 0.260
E 6.200 6.400 6.600 0.244 0.252 0.260
E1 (1) 4.300 4.400 4.500 0.170 0.173 0.177
e 0.650 0.026
L 0.450 0.600 0.750 0.018 0.024 0.030
L1 1.000 0.039
k 0˚ (min.) 8˚ (max.)
aaa 0.100 0.004
Not e: 1. D and E 1 does no t inclu de mo ld fla sh or prot rusi ons .
Mold flash or potrusions shall not exceed 0.15mm
(.006inch) per side.
TSSOP20
0087225 (Jedec MO-153-AC)
Thin Shrink Small Outline Package
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L6997S
Table 15. Revision History
Date Revision Descrip tio n of Ch anges
June 2004 1 First Issue.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such inf ormation nor for any infri ngement of patents or othe r rights of third parties which may result fr om its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. T his publication supersedes and replaces all information previo usly supplied. STMicroelectr onics product s are not
authorized for use as critical components in life support devices or systems without express written app roval of STMicroelectronics.
The ST logo is a registered trademark of STMicr oelectronics.
All other names ar e the property of their respective owners
© 2004 STMicroele ctronics - All rights reserved
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