AT28C010-12JU SL076 - ATMEL

Features

•Fast Read Access Time - 120 ns

•Automatic Page Write Operation

– Internal Address and Data Latches for 128-Bytes

– Internal Control Timer

•Fast Write Cycle Time

– Page Write Cycle Time - 10 ms Maximum

– 1 to 128-Byte Page Write Operation

•Low Power Dissipation

– 80 mA Active Current

– 300µA CMOS Standby Current

•Hardware and Software Data Protection

•DATA Polling for End of Write Detection

•High Reliability CMOS Technology

– Endurance: 104or 105Cycles

– Data Retention: 10 Years

•Single 5V 10% Supply

•CMOS and TTL Compatible Inputs and Outputs

•JEDEC Approved Byte-Wide Pinout

Pin Configuration

Pin Name Function

A0 - A16 Addresses

CE Chip Enable

OE Output Enable

WE Write Enable

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

0010F–PEEPR–062014

AT28C010 Mil

1-Megabit

(128K x 8)

Paged Parallel

EEPROMs

AT28C010

Military

CERDIP, FLATPACK

Top View

A16

A15

A12

I/O0

I/O1

I/O2

GND

VCC

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

PGA

Top View

44 LCC

Top View

A12

A13

A11

A10

I/O0

I/O1

I/O2

VSS

I/O3

I/O4

I/O5

I/O6

I/O7

A15

A16

VCC

A14

32 LCC

Top View

I/O0

A14

A13

A11

A10

I/O7

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O6

A12

A15

A16

VCC

(continued)

0010F–PEEPR–062014

AT28C010 Military

Description

The AT28C010 is a high-performance Electrically Erasable and Programmable Read Only Mem-

ory. Its one megabit of memory is organized as 131,072 words by 8 bits. Manufactured with

Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with

power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is

less than 300A.

The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for

external components. The device contains a 128-byte page register to allow writing of up to 128-

bytes simultaneously. During a write cycle, the address and 1 to 128-bytes of data are internally

latched, freeing the address and data bus for other operations. Following the initiation of a write

cycle, the device will automatically write the latched data using an internal control timer. The end

of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has

been detected a new access for a read or write can begin.

Atmel's 28C010 has additional features to ensure high quality and manufacturability. The device

utilizes internal error correction for extended endurance and improved data retention character-

istics. An optional software data protection mechanism is available to guard against inadvertent

writes. The device also includes an extra 128-bytes of EEPROM for device identification or

tracking.

Block Diagram

Absolute Maximum Ratings*

Temperature Under Bias ............................... -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to VCC + 0.6V

Voltage on OE and A9

with Respect to Ground ...................................-0.6V to +13.5V

0010F–PEEPR–062014

AT28C010 Military

Device Operation

READ: The AT28C010 is accessed like a Static RAM. When CE and OE are low and WEis

high, the data stored at the memory location determined by the address pins is asserted on the

outputs. The outputs are put in the high impedance state when either CEorOE is high. This

dual-line control gives designers flexibility in preventing bus contention in their system.

BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high

initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs

last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started

it will automatically time itself to completion. Once a programming operation has been initiated

and for the duration of tWC, a read operation will effectively be a polling operation.

PAGE WRITE: The page write operation of the AT28C010 allows 1 to 128-bytes of data to be

written into the device during a single internal programming period. A page write operation is ini-

tiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127

additional bytes. Each successive byte must be written within 150s(t

BLC) of the previous byte.

If the tBLC limit is exceeded the AT28C010 will cease accepting data and commence the internal

programming operation. All bytes during a page write operation must reside on the same page

as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the

page write operation, A7 - A16 must be the same.

The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes

may be loaded in any order and may be altered within the same load period. Only bytes which

are specified for writing will be written; unnecessary cycling of other bytes within the page does

not occur.

DATA POLLING: The AT28C010 features DATA Polling to indicate the end of a write cycle.

During a byte or page write cycle an attempted read of the last byte written will result in the com-

plement of the written data to be presented on I/O7. Once the write cycle has been completed,

true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at

anytime during the write cycle.

TOGGLE BIT: In addition to DATA Polling the AT28C010 provides another method for determin-

ing the end of a write cycle. During the write operation, successive attempts to read data from

the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6

will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during

the write cycle.

DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transi-

tions of the host system power supply. Atmel has incorporated both hardware and software fea-

tures that will protect the memory against inadvertent writes.

HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the

AT28C010 in the following ways: (a) VCC sense - if VCC is below 3.8V (typical) the write function

is inhibited; (b) VCC power-on delay - once VCC has reached 3.8V the device will automatically

time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of OElow,CE

high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the

WE or CE inputs will not initiate a write cycle.

SOFTWARE DATA PROTECTION: A software controlled data protection feature has been

implemented on the AT28C010. When enabled, the software data protection (SDP), will prevent

inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010 is

shipped from Atmel with SDP disabled.

SDP is enabled by the host system issuing a series of three write commands; three specific

bytes of data are written to three specific addresses (refer to Software Data Protection Algo-

rithm). After writing the 3-byte command sequence and after tWC the entire AT28C010 will be

protected against inadvertent write operations. It should be noted, that once protected the host

may still perform a byte or page write to the AT28C010. This is done by preceding the data to be

written by the same 3-byte command sequence used to enable SDP.

0010F–PEEPR–062014

AT28C010 Military

Once set, SDP will remain active unless the disable command sequence is issued. Power transi-

tions do not disable SDP and SDP will protect the AT28C010 during power-up and power-down

conditions. All command sequences must conform to the page write timing specifications. The

data in the enable and disable command sequences is not written to the device and the memory

addresses used in the sequence may be written with data in either a byte or page write opera-

tion.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will

start the internal write timers. No data will be written to the device; however, for the duration of

tWC, read operations will effectively be polling operations.

DEVICE IDENTIFICATION: An extra 128-bytes of EEPROM memory are available to the user

for device identification. By raising A9 to 12V 0.5V and using address locations 1FF80H to

1FFFFH the bytes may be written to or read from in the same manner as the regular memory

array.

OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software

code. Please see Software Chip Erase application note for details.

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms

DC and AC Operating Range

AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25

Operating

Temperature (Case) Mil. -55°C - 125°C -55°C - 125°C -55°C - 125°C -55°C - 125°C

VCC Power Supply 5V 10% 5V 10% 5V 10% 5V 10%

Operating Modes

Mode CE OE WE I/O

Read VIL VIL VIH DOUT

Write (2) VIL VIH VIL DIN

Standby/Write Inhibit VIH X(1) XHighZ

Write Inhibit X X VIH

Write Inhibit X VIL X

Output Disable X VIH XHighZ

DC Characteristics

Symbol Parameter Condition Min Max Units

ILI Input Load Current VIN =0VtoV

CC +1V 10 A

ILO Output Leakage Current VI/O =0VtoV

CC 10 A

ISB1 VCC Standby Current CMOS CE = VCC -0.3VtoV

CC + 1V 300 A

ISB2 VCC Standby Current TTL CE = 2.0V to VCC +1V 3 mA

ICC VCC Active Current f = 5 MHz; IOUT =0mA 80 mA

VIL Input Low Voltage 0.8 V

0010F–PEEPR–062014

AT28C010 Military

AC Read Waveforms(1)(2)(3)(4)

Notes: 1. CE may be delayed up to tACC -t

CE after the address transition without impact on tACC.

2. OE may be delayed up to tCE -t

OE after the falling edge of CE without impact on tCE or by tACC -

tOE after an address change without impact in tACC.

3. tDF is specified from OE or CE wichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

5. If CE is de-asserted, it must remain de-asserted for at least 50ns during read operations other-

wise incorrect data may be read.

VIH Input High Voltage 2.0 V

VOL Output Low Voltage IOL = 2.1 mA 0.45 V

VOH1 Output High Voltage IOH = -400 A 2.4 V

VOH2 Output High Voltage CMOS IOH = -100 A; VCC = 4.5V 4,2 V

DC Characteristics (Continued)

Symbol Parameter Condition Min Max Units

AC Read Characteristics

Symbol Parameter

AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25

UnitsMin Max Min Max Min Max Min Max

tACC Address to Output Delay 120 150 200 250 ns

tCE (1) CE to Output Delay 120 150 200 250 ns

tOE (2) OE to Output Delay 0 50 0 55 0 55 0 55 ns

tDF (3, 4) CE or OE to Output Float 0 50 0 55 0 55 0 55 ns

tOH Output Hold from OE, CE or

Address, whichever occurred first

0000ns

tCEPH(5) CE Pulse High Time 50 50 50 50 ns

0010F–PEEPR–062014

AT28C010 Military

Input Test Waveforms and

Measurement Level

Output Test Load

Note: 1. This parameter is 100% characterized and is not 100% tested.

Pin Capacitance

f = 1 MHz, T = 25°C(1)

Symbol Typ Max Units Conditions

CIN 410pFV

IN =0V

COUT 812pFV

OUT =0V

AC Write Characteristics

Symbol Parameter Min Max Units

tWC Write Cycle Time 10 ms

tAS Address Set-up Time 0 ns

tAH Address Hold Time 50 ns

tDS Data Set-up Time 50 ns

tDH Data Hold Time 0 ns

tWP Write Pulse Width 100 ns

tBLC Byte Load Cycle Time 150 s

tWPH Write Pulse Width High 50 ns

0010F–PEEPR–062014

AT28C010 Military

AC Write Waveforms

WE Controlled

CE Controlled

Page Mode Characteristics

Symbol Parameter Min Max Units

tAS,t

OES Address, OE Set-up Time 0 ns

tAH Address Hold Time 50 ns

tCS Chip Select Set-up Time 0 ns

tCH Chip Select Hold Time 0 ns

tWP Write Pulse Width (WE or CE) 100 ns

tDS Data Set-up Time 50 ns

tDH,t

OEH Data, OE Hold Time 0 ns

0010F–PEEPR–062014

AT28C010 Military

Page Mode Write Waveforms (1)(2)

Notes: 1. A7 through A16 must specify the page address during each high to low transition of WE (or

CE).

2. OE must be high only when WE and CE are both low.

0010F–PEEPR–062014

AT28C010 Military

Chip Erase Waveforms

Software Data

Protection Enable Algorithm(1)

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. Write Protect state will be activated at end of write even if no other data is loaded.

3. Write Protect state will be deactivated at end of write period even if no other data if loaded.

4. 1 to 128 bytes of data are loaded.

tS= 5 msec (min.)

tW=t

H= 10 msec (min.)

VH= 12.0V ± 0.5V

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA A0

ADDRESS 5555

LOAD DATA XX

ANY ADDRESS

(4)

LOAD LAST BYTE

LAST ADDRESS ENTER DATA

PROTECT STATE

WRITES ENABLED

(2)

0010F–PEEPR–062014

AT28C010 Military

Software Data

Protection Disable Algorithm(1)

Software Protected Program Cycle Waveform(1)(2)(3)

Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above.

2. After the command sequence has been issued and a page write operation follows, the page

address inputs (A7 - A16) must be the same for each high to low transition of WE (or CE).

3. OE must be high only when WE and CE are both low.

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 80

ADDRESS 5555

LOAD DATA AA

ADDRESS 5555

LOAD DATA 20

ADDRESS 5555

LOAD DATA XX

ANY ADDRESS

(4)

LOAD LAST BYTE

LAST ADDRESS

LOAD DATA 55

ADDRESS 2AAA

EXIT DATA

PROTECT STATE

(3)

0010F–PEEPR–062014

AT28C010 Military

Notes: 1. These parameters are characterized and not 100% tested.

2. See AC Read Characteristics.

Data Polling Waveforms

Notes: 1. These parameters are characterized and not 100% tested.

2. See AC Read Characteristics.

Toggle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

2. Beginning and ending state of I/O6 will vary.

3. Any addres location may be used but the address should not vary.

Data Polling Characterstics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay (2) ns

tWR Write Recovery Time 0 ns

Toggle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay (2) ns

tOEHP OE High Pulse 150 ns

tWR Write Recovery Time 0 ns

0010F–PEEPR–062014

AT28C010 Military

Note: 1. See Valid Part Number table below.

AT28C010 Ordering Information(1)

tACC

(ns)

ICC (mA)

Ordering Code Package Operation RangeActive Standby

120 80 0.3 AT28C010(E)-12DM/883

AT28C010(E)-12EM/883

AT28C010-12FM/883

AT28C010(E)-12LM/883

AT28C010(E)-12UM/883

32D6

32L

32F

44L

30U

Military/883C

Class B, Fully Compliant

(-55C to 125C)

150 80 0.3 AT28C010(E)-15DM/883

AT28C010(E)-15EM/883

AT28C010-15FM/883

AT28C010(E)-15LM/883

AT28C010(E)-15UM/883

32D6

32L

32F

44L

30U

Military/883C

Class B, Fully Compliant

(-55C to 125C)

200 80 0.3 AT28C010-20DM/883

AT28C010-20EM/883

AT28C010-20FM/883

AT28C010-20LM/883

AT28C010-20UM/883

32D6

32L

32F

44L

30U

Military/883C

Class B, Fully Compliant

(-55C to 125C)

250 80 0.3 AT28C010-25DM/883

AT28C010-25EM/883

AT28C010-25FM/883

AT28C010-25LM/883

AT28C010-25UM/883

32D6

32L

32F

44L

30U

Military/883C

Class B, Fully Compliant

(-55C to 125C)

Package Type

32D6 32-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline (Cerdip)

32F 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)

32L 32-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)

44L 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)

30U 30-Pin, Ceramic Pin Grid Array (PGA)

WDie

Options

Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms

EHigh Endurance Option: Endurance = 100K Write Cycles

0010F–PEEPR–062014

AT28C010 Military

Note: 1. See Valid Part Number table below.

5962-38267 Ordering Information(1)

tACC

(ns)

ICC (mA)

Ordering Code Package Operation RangeActive Standby

120 80 0.3 5962-38267 07 MXX

5962-38267 07 MUX

5962-38267 07 MZX

5962-38267 07 MYX

5962-38267 07 MTX

32D6

32L

32F

44L

30U

Military/883C

Class B, Fully Compliant

(-55C to 125C)

150 80 0.3 5962-38267 05 MXX

5962-38267 05 MUX

5962-38267 05 MZX

5962-38267 05 MYX

5962-38267 05 MTX

32D6

32L

32F

44L

30U

Military/883C

Class B, Fully Compliant

(-55C to 125C)

200 80 0.3 5962-38267 03 MXX

5962-38267 03 MUX

5962-38267 03 MZX

5962-38267 03 MYX

5962-38267 03 MTX

32D6

32L

32F

44L

30U

Military/883C

Class B, Fully Compliant

(-55C to 125C)

250 80 0.3 5962-38267 01 MXX

5962-38267 01 MUX

5962-38267 01 MZX

5962-38267 01 MYX

5962-38267 01 MTX

32D6

32L

32F

44L

30U

Military/883C

Class B, Fully Compliant

(-55C to 125C)

Package Type

32D6 32-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline (Cerdip)

32F 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)

32L 32-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)

44L 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)

30U 30-Pin, Ceramic Pin Grid Array (PGA)

WDie

0010F–PEEPR–062014

AT28C010 Military

Valid Part Numbers

The following table lists standard Atmel products that can be ordered.

Options

Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms

EHigh Endurance Option: Endurance = 100K Write Cycles

Device Numbers Speed Package and Temperature Combinations

AT28C010 12 DM/883, EM/883, FM/883, LM/883, UM/883

AT28C010E 12 DM/883, EM/883, LM/883, UM/883

AT28C010 15 DM/883, EM/883, FM/883, LM/883, UM/883

AT28C010E 15 DM/883, EM/883, LM/883, UM/883

AT28C010 20 DM/883, EM/883, FM/883, LM/883, UM/883

AT28C010 25 DM/883, EM/883, FM/883, LM/883, UM/883

AT28C010 –W

Die Products

Reference Section: Parallel EEPROM Die Products

Packaging Information

0010F–PEEPR–062014

AT28C010 Military

11.63(0.458)

11.23(0.442)

14.22(0.560)

13.72(0.540)

2.54(0.100)

2.16(0.085)

1.91(0.075)

1.40(0.055)

INDEX CORNER

0.635(0.025)

0.381(0.015) X 45°

0.305(0.012)

0.178(0.007)RADIUS

0.737(0.029)

0.533(0.021)

1.02(0.040) X 45°

PIN 1

1.40(0.055)

1.14(0.045)

2.41(0.095)

1.91(0.075)

2.16(0.085)

1.65(0.065)

7.62(0.300) BSC

1.27(0.050) TYP

10.16(0.400) BSC

16.81(0.662)

16.26(0.640)

16.81(0.662)

16.26(0.640)

2.74(0.108)

2.16(0.085)

2.03(0.080)

1.40(0.055)

INDEX CORNER

0.635(0.025)

0.381(0.015) X 45°

0.305(0.012)

0.178(0.007)RADIUS

0.737(0.029)

0.533(0.021)

1.02(0.040) X 45°

PIN 1

1.40(0.055)

1.14(0.045)

2.41(0.095)

1.91(0.075)

2.16(0.085)

1.65(0.065)

12.70(0.500) BSC

1.27(0.050) TYP

12.70(0.500) BSC

PIN #1 ID 9.40(0.370)

6.86(0.270)

0.51(0.020)

0.38(0.015)

1.27(0.050) BSC

1.14(0.045) MAX

3.05(0.120)

2.49(0.098)

1.14(0.045)

0.66(0.026)

1.83(0.072)

0.76(0.030)

10.36(0.408)

9.02(0.355)

0.18(0.007)

0.10(0.004)

12.40(0.488)

11.99(0.472)

21.08(0.830)

20.60(0.811)

42.70(1.68)

41.70(1.64)

15.50(0.610)

13.00(0.510)

2.49(0.098)MAX

0.127(0.005)MIN

1.52(0.060)

0.38(0.015)

0.58(0.023)

0.36(0.014)

1.65(0.065)

1.14(0.045)

15.70(0.620)

15.00(0.590)

17.80(0.700) MAX

0.381(0.015)

0.203(0.008)

2.54(0.100)BSC

5.08(0.200)

3.18(0.125)

SEATING

PLANE

5.72(0.225)

MAX

38.10(1.500) REF

0º~ 15º REF

MIL-STD-1835 C-12

44L, 44-Pad, Non-Windowed, Ceramic Leadless

Chip Carrier (LCC)

Dimensions in Inches and (Millimeters)*

JEDEC OUTLINE MO-115

32L, 32-Pad, Non-Windowed, Ceramic Leadless

Chip Carrier (LCC)

Dimensions in Inches and (Millimeters)*

32D6, 32-Lead, 0.600" Wide, Non-Windowed,

Ceramic Dual inline Package (Cerdip)

Dimensions in Inches and (Millimeters)

MIL-STD-1835 D-16 CONFIG A

32F, 32-Lead, Non-Windowed, Ceramic Bottom

Brazed Flat Package (Flatpack)

Dimensions in Inches and (Millimeters)

MIL-STD-1835 F-18 CONFIG B

*Controlling dimension: millimeters*Controlling dimension: millimeters

Packaging Information

0010F–PEEPR–062014

AT28C010 Military

13.74(0.541)

13.36(0.526)

16.18(0.637)

15.82(0.623)

2.57(0.101)

2.06(0.081)

7.26(0.286)

6.50(0.256)

1.40(0.055)

1.14(0.045)

0.58(0.023)

0.43(0.017)

3.12(0.123)

2.62(0.103)

1.83(0.072)

1.57(0.062)

14.17(0.558)

13.77(0.542)

12.70(0.500) TYP

2.54(0.100) TYP

16.71(0.658)

16.31(0.642)

2.54(0.100) TYP

10.41(0.410)

9.91(0.390)

30U, 30-Pin, Ceramic Pin Grid Array (PGA)

Dimensions in Inches and (Millimeters)

XXX

Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com

Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and

other countries. Other terms and product names may be trademarks of others.

DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right

is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE

ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS

INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT

SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES

FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS

BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this

document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information

contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended,

authorized, or warranted for use as components in applications intended to support or sustain life.

SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where

the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written

consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems.

Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are

not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.