EFM32 Gecko Family EFM32G Data Sheet The EFM32 Gecko MCUs are the world's most energy-friendly microcontrollers. KEY FEATURES The EFM32G offers unmatched performance and ultra low power consumption in both active and sleep modes. EFM32G devices consume as little as 0.6 A in Stop mode and 180 A/MHz in Run mode. It also features autonomous peripherals, high overall chip and analog integration, and the performance of the industry standard 32-bit ARM Cortex-M3 processor, making it perfect for battery-powered systems and systems with high-performance, low-energy requirements. * Alarm and security systems * Industrial and home automation Core / Memory ARM CortexTM M3 processor Flash Program Memory RAM Memory * Ultra low power operation * 0.6 A current in Stop (EM3), with brown-out detection and RAM retention * 45 A/MHz in EM1 * 180 A/MHz in Run mode (EM0) * Fast wake-up time of 2 s EFM32G applications include the following: * Energy, gas, water and smart metering * Health and fitness applications * Smart accessories * ARM Cortex-M3 at 32 MHz Clock Management Memory Protection Unit Debug Interface DMA Controller High Frequency Crystal Oscillator High Frequency RC Oscillator Auxiliary High Freq. RC Osc. Low Frequency RC Oscillator Low Frequency Crystal Oscillator Watchdog Oscillator * Hardware cryptography (AES) * Up to 128 kB of Flash and 16 kB of RAM Energy Management Voltage Regulator Voltage Comparator Power-On Reset Brown-Out Detector Security Hardware AES 32-bit bus Peripheral Reflex System Serial Interfaces USART Low Energy UARTTM UART I2C I/O Ports External Bus Interface External Interrupts Timers and Triggers General Purpose I/O Pin Reset Timer/Counter Pulse Counter Low Energy Timer Watchdog Timer Real Time Counter Analog Interfaces ADC DAC LCD Controller Analog Comparator Lowest power mode with peripheral operational: EM0 - Active EM1 - Sleep silabs.com | Building a more connected world. EM2 - Deep Sleep EM3 - Stop EM4 - Shutoff Rev. 2.10 EFM32G Data Sheet Feature List 1. Feature List * ARM Cortex-M3 CPU platform * High Performance 32-bit processor @ up to 32 MHz * Memory Protection Unit * Wake-up Interrupt Controller * SysTick System Timer * Flexible Energy Management System * 20 nA @ 3 V Shutoff Mode * 0.6 A @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention * 0.9 A @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU retention * 45 A/MHz @ 3 V Sleep Mode * 180 A/MHz @ 3 V Run Mode, with code executed from flash * 128/64/32 KB Flash * 16/8 KB RAM * Up to 90 General Purpose I/O pins * Configurable push-pull, open-drain, pull-up/down, input filter, drive strength * Configurable peripheral I/O locations * 16 asynchronous external interrupts * Output state retention and wake-up from Shutoff Mode * 8 Channel DMA Controller * 8 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling * Hardware AES with 128/256-bit keys in 54/75 cycles * Timers/Counters * 3 x 16-bit Timer/Counter * 3x3 Compare/Capture/PWM channels * Dead-Time Insertion on TIMER0 * 16-bit Low Energy Timer * 1x 24-bit Real-Time Counter * 3x 8-bit Pulse Counter * Watchdog Timer with dedicated RC oscillator @ 50 nA * Integrated LCD Controller for up to 4x40 segments * Voltage boost, adjustable contrast and autonomous animation * External Bus Interface for up to 4x64 MB of external memory mapped space * TFT Controller with Direct Drive * Communication interfaces * Up to 3x Universal Synchronous/Asynchronous Receiver/ Transmitter * UART/SPI/SmartCard (ISO 7816)/IrDA/I2S * Triple buffered full/half-duplex operation * 1x Universal Asynchronous Receiver/Transmitter * 2x Low Energy UART * Autonomous operation with DMA in Deep Sleep Mode 2 * I C Interface with SMBus support * Address recognition in Stop Mode * Ultra low power precision analog peripherals * 12-bit 1 Msamples/s Analog to Digital Converter * 8 single-ended channels/4 differential channels * On-chip temperature sensor * 12-bit 500 ksamples/s Digital to Analog Converter * 2 single-ended channels/1 differential channel * 2x Analog Comparator * Capacitive sensing with up to 16 inputs silabs.com | Building a more connected world. Rev. 2.10 | 2 EFM32G Data Sheet Feature List * * * * * * * Supply Voltage Comparator Ultra efficient Power-on Reset and Brown-Out Detector 2-pin Serial Wire Debug Interface * 1-pin Serial Wire Viewer Pre-Programmed USB/UART Bootloader Temperature range -40 to 85 C Single power supply 1.98 to 3.8 V Packages * BGA112 * LQFP100 * TQFP64 * TQFP48 * QFN64 * QFN32 silabs.com | Building a more connected world. Rev. 2.10 | 3 EFM32G Data Sheet Ordering Information 2. Ordering Information The following table shows the available EFM32G devices. Table 2.1. Ordering Information Flash (kB) RAM (kB) Max Speed (MHz) Supply Voltage (V) Temperature (C) Package EFM32G200F16G-E-QFN32 16 8 32 1.98 - 3.8 -40 - 85 QFN32 EFM32G200F32G-E-QFN32 32 8 32 1.98 - 3.8 -40 - 85 QFN32 EFM32G200F64G-E-QFN32 64 16 32 1.98 - 3.8 -40 - 85 QFN32 EFM32G210F128G-E-QFN32 128 16 32 1.98 - 3.8 -40 - 85 QFN32 EFM32G222F32G-E-QFP48 32 8 32 1.98 - 3.8 -40 - 85 TQFP48 EFM32G222F64G-E-QFP48 64 16 32 1.98 - 3.8 -40 - 85 TQFP48 EFM32G222F128G-E-QFP48 128 16 32 1.98 - 3.8 -40 - 85 TQFP48 EFM32G230F32G-E-QFN64 32 8 32 1.98 - 3.8 -40 - 85 QFN64 EFM32G230F64G-E-QFN64 64 16 32 1.98 - 3.8 -40 - 85 QFN64 EFM32G230F128G-E-QFN64 128 16 32 1.98 - 3.8 -40 - 85 QFN64 EFM32G232F32G-E-QFP64 32 8 32 1.98 - 3.8 -40 - 85 TQFP64 EFM32G232F64G-E-QFP64 64 16 32 1.98 - 3.8 -40 - 85 TQFP64 EFM32G232F128G-E-QFP64 128 16 32 1.98 - 3.8 -40 - 85 TQFP64 EFM32G280F32G-E-QFP100 32 8 32 1.98 - 3.8 -40 - 85 LQFP100 EFM32G280F64G-E-QFP100 64 16 32 1.98 - 3.8 -40 - 85 LQFP100 EFM32G280F128G-E-QFP100 128 16 32 1.98 - 3.8 -40 - 85 LQFP100 EFM32G290F32G-E-BGA112 32 8 32 1.98 - 3.8 -40 - 85 BGA112 EFM32G290F64G-E-BGA112 64 16 32 1.98 - 3.8 -40 - 85 BGA112 EFM32G290F128G-E-BGA112 128 16 32 1.98 - 3.8 -40 - 85 BGA112 EFM32G840F32G-E-QFN64 32 8 32 1.98 - 3.8 -40 - 85 QFN64 EFM32G840F64G-E-QFN64 64 16 32 1.98 - 3.8 -40 - 85 QFN64 EFM32G840F128G-E-QFN64 128 16 32 1.98 - 3.8 -40 - 85 QFN64 EFM32G842F32G-E-QFP64 32 8 32 1.98 - 3.8 -40 - 85 TQFP64 EFM32G842F64G-E-QFP64 64 16 32 1.98 - 3.8 -40 - 85 TQFP64 EFM32G842F128G-E-QFP64 128 16 32 1.98 - 3.8 -40 - 85 TQFP64 EFM32G880F32G-E-QFP100 32 8 32 1.98 - 3.8 -40 - 85 LQFP100 EFM32G880F64G-E-QFP100 64 16 32 1.98 - 3.8 -40 - 85 LQFP100 EFM32G880F128G-E-QFP100 128 16 32 1.98 - 3.8 -40 - 85 LQFP100 EFM32G890F32G-E-BGA112 32 8 32 1.98 - 3.8 -40 - 85 BGA112 EFM32G890F64G-E-BGA112 64 16 32 1.98 - 3.8 -40 - 85 BGA112 EFM32G890F128G-E-BGA112 128 16 32 1.98 - 3.8 -40 - 85 BGA112 Ordering Code silabs.com | Building a more connected world. Rev. 2.10 | 4 EFM32G Data Sheet Ordering Information EFM32 G 890 F 128 G - E - BGA 112 R Tape and Reel (Optional) Pin Count Package Revision Temperature Grade - G (-40 to +85 C) Memory Size in kB Memory Type (Flash) Feature Set Code Gecko Energy Friendly Microcontroller 32-bit Figure 2.1. Ordering Code Decoder Adding the suffix 'R' to the part number (e.g., EFM32G890F128G-E-BGA112R) denotes tape and reel. Visit www.silabs.com for information on global distributors and representatives. silabs.com | Building a more connected world. Rev. 2.10 | 5 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 System Introduction . . . . . . . . . . . . . . . . . . . . 3.1.1 ARM Cortex-M3 Core . . . . . . . . . . . . . . . . . 3.1.2 Debug Interface (DBG) . . . . . . . . . . . . . . . . . 3.1.3 Memory System Controller (MSC) . . . . . . . . . . . . . 3.1.4 Direct Memory Access Controller (DMA) . . . . . . . . . . . 3.1.5 Reset Management Unit (RMU) . . . . . . . . . . . . . . 3.1.6 Energy Management Unit (EMU) . . . . . . . . . . . . . 3.1.7 Clock Management Unit (CMU) . . . . . . . . . . . . . . 3.1.8 Watchdog (WDOG) . . . . . . . . . . . . . . . . . . 3.1.9 Peripheral Reflex System (PRS) . . . . . . . . . . . . . 3.1.10 External Bus Interface (EBI) . . . . . . . . . . . . . . 3.1.11 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . 3.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 3.1.13 Pre-Programmed USB/UART Bootloader . . . . . . . . . . 3.1.14 Universal Asynchronous Receiver/Transmitter (UART) . . . . . 3.1.15 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) 3.1.16 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . 3.1.17 Real Time Counter (RTC) . . . . . . . . . . . . . . . 3.1.18 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . 3.1.19 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . 3.1.20 Analog Comparator (ACMP) . . . . . . . . . . . . . . 3.1.21 Voltage Comparator (VCMP) . . . . . . . . . . . . . . 3.1.22 Analog to Digital Converter (ADC) . . . . . . . . . . . . 3.1.23 Digital to Analog Converter (DAC) . . . . . . . . . . . . 3.1.24 Advanced Encryption Standard Accelerator (AES) . . . . . . . 3.1.25 General Purpose Input/Output (GPIO) . . . . . . . . . . . 3.1.26 Liquid Crystal Display Driver (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 .10 .10 .10 .11 .11 .11 .11 .11 .11 .11 .11 .11 .11 .12 .12 .12 .12 .12 .12 .12 .12 .12 .12 .13 .13 .13 3.2 Configuration Summary 3.2.1 EFM32G200 . . 3.2.2 EFM32G210 . . 3.2.3 EFM32G222 . . 3.2.4 EFM32G230 . . 3.2.5 EFM32G232 . . 3.2.6 EFM32G280 . . 3.2.7 EFM32G290 . . 3.2.8 EFM32G840 . . 3.2.9 EFM32G842 . . 3.2.10 EFM32G880 . . 3.2.11 EFM32G890 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 .14 .15 .16 .17 .18 .19 .20 .21 .22 .23 .25 3.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . .27 . . . 4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 29 silabs.com | Building a more connected world. Rev. 2.10 | 6 4.1 Test Conditions . . . . . . . . 4.1.1 Typical Values . . . . . . 4.1.2 Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 .29 .29 4.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . .29 4.3 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . .29 4.4 Current Consumption . . . . 4.4.1 EM0 Current Consumption 4.4.2 EM1 Current Consumption 4.4.3 EM2 Current Consumption 4.4.4 EM3 Current Consumption 4.4.5 EM4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 .31 .34 .37 .38 .39 4.5 Transition between Energy Modes . . . . . . . . . . . . . . . . . . . . . . .39 4.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.7 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.8 General Purpose Input Output . . . . . . . . . . . . . . . . . . . . . . . .42 4.9 Oscillators . . . 4.9.1 LFXO. . . 4.9.2 HFXO . . 4.9.3 LFRCO . . 4.9.4 HFRCO . . 4.9.5 AUXHFRCO 4.9.6 ULFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 .50 .51 .52 .53 .57 .57 4.10 Analog Digital Converter (ADC) 4.10.1 Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 .67 4.11 Digital Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . .71 4.12 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . .73 4.13 Voltage Comparator (VCMP) . . . . . . . . . . . . . . . . . . . . . . . .75 4.14 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.15 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.16 Digital Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.1 EFM32G200 & EFM32G210 (QFN32) . 5.1.1 Pinout . . . . . . . . . 5.1.2 Alternate Functionality Pinout . 5.1.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 .79 .82 .84 5.2 EFM32G222 (TQFP48). . . . . 5.2.1 Pinout . . . . . . . . 5.2.2 Alternate Functionality Pinout 5.2.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 .85 .88 .90 5.3 EFM32G230 (QFN64) . . . . . 5.3.1 Pinout . . . . . . . . 5.3.2 Alternate Functionality Pinout 5.3.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 .91 .94 .97 silabs.com | Building a more connected world. Rev. 2.10 | 7 5.4 EFM32G232 (TQFP64). . . . . . . . . . . . . . . . . . . . . . . . . . .98 5.4.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 5.4.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . 101 . 5.4.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 103 5.5 EFM32G280 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . .104 5.5.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 04 5.5.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . 109 . 5.5.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 113 5.6 EFM32G290 (BGA112). . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.6.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 14 5.6.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . 119 . 5.6.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 123 5.7 EFM32G840 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.7.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 24 5.7.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . 127 . 5.7.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 131 5.8 EFM32G842 (TQFP64). . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.8.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 32 5.8.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . 135 . 5.8.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 139 5.9 EFM32G880 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . .140 5.9.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 40 5.9.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . 146 . 5.9.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 152 5.10 EFM32G890 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . .153 5.10.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 5.10.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . .159 5.10.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . 1 . 65 6. BGA112 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .166 6.1 BGA112 Package Dimensions 6.2 BGA112 PCB Layout . . 6.3 BGA112 Package Marking . . . . . . . . . . . . . . . . . . . . . . .166 . . . . . . . . . . . . . . . . . . . . . . . .167 . . . . . . . . . . . . . . . . . . . . . . . 169 . 7. LQFP100 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 170 7.1 LQFP100 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . 170 7.2 LQFP100 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.3 LQFP100 Package Marking . . . . . . . . . . . . . . . . . . . . . . . .174 8. TQFP64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .175 8.1 TQFP64 Package Dimensions 8.2 TQFP64 PCB Layout . . 8.3 TQFP64 Package Marking 9. TQFP48 Package Specifications 9.1 TQFP48 Package Dimensions silabs.com | Building a more connected world. . . . . . . . . . . . . . . . . . . . . . . .175 . . . . . . . . . . . . . . . . . . . . . . . .177 . . . . . . . . . . . . . . . . . . . . . . . 179 . . . . . . . . . . . . . . . . . . . . . . . .180 . . . . . . . . . . . . . . . . . . . . . . .180 Rev. 2.10 | 8 9.2 TQFP48 PCB Layout . . 9.3 TQFP48 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 . 10. QFN64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .185 10.1 QFN64 Package Dimensions 10.2 QFN64 PCB Layout . . 10.3 QFN64 Package Marking . . . . . . . . . . . . . . . . . . . . . . .185 . . . . . . . . . . . . . . . . . . . . . . . .187 . . . . . . . . . . . . . . . . . . . . . . . 189 . 11. QFN32 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .190 11.1 QFN32 Package Dimensions 11.2 QFN32 PCB Layout . . 11.3 QFN32 Package Marking . . . . . . . . . . . . . . . . . . . . . . .190 . . . . . . . . . . . . . . . . . . . . . . . .191 . . . . . . . . . . . . . . . . . . . . . . . 193 . 12. Chip Revision, Solder Information, Errata 12.1 Chip Revision . . . 12.2 Soldering Information . 12.3 Errata . . . . . . . . . . . .182 . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 94 . . . 194 . .194 13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 13.1 Revision 2.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 . 13.2 Revision 2.00 . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 . 13.3 Revision 1.90 . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 . 13.4 Revision 1.80 . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 . 13.5 Revision 1.71 . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 . 13.6 Revision 1.70 . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 . 13.7 Revision 1.60 . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 . 13.8 Revision 1.50 . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 . 13.9 Revision 1.40 . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 . 13.10 Revision 1.30 . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 13.11 Revision 1.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 13.12 Revision 1.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 13.13 Revision 1.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 13.14 Revision 1.00 . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 13.15 Revision 0.90 . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 13.16 Revision 0.85 . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 13.17 Revision 0.84 . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 13.18 Revision 0.83 . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 13.19 Revision 0.82 . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 13.20 Revision 0.81 . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 13.21 Revision 0.80 . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 silabs.com | Building a more connected world. Rev. 2.10 | 9 EFM32G Data Sheet System Overview 3. System Overview 3.1 System Introduction The EFM32 MCUs are the world's most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM CortexM3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32G microcontroller is well suited for any battery operated application as well as other systems requiring high performance and low-energy consumption. This section gives a short introduction to each of the modules in general terms and also shows a summary of the configuration for the EFM32G devices. For a complete feature set and in-depth information on the modules, the reader is referred to the EFM32G Reference Manual. The diagram shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult Ordering Information. Core / Memory ARM CortexTM M3 processor Memory Protection Unit Flash Program Memory Debug Interface RAM Memory DMA Controller Clock Management High Frequency Crystal Oscillator High Frequency RC Oscillator Auxiliary High Freq. RC Osc. Low Frequency RC Oscillator Low Frequency Crystal Oscillator Watchdog Oscillator Energy Management Voltage Regulator Voltage Comparator Power-On Reset Brown-Out Detector Security Hardware AES 32-bit bus Peripheral Reflex System Serial Interfaces USART Low Energy UARTTM UART I2C I/O Ports External Bus Interface External Interrupts Timers and Triggers General Purpose I/O Pin Reset Timer/Counter Pulse Counter Low Energy Timer Watchdog Timer Real Time Counter Analog Interfaces ADC DAC LCD Controller Analog Comparator Lowest power mode with peripheral operational: EM0 - Active EM1 - Sleep EM2 - Deep Sleep EM3 - Stop EM4 - Shutoff Figure 3.1. Block Diagram 3.1.1 ARM Cortex-M3 Core The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection Unit with support for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep. The EFM32 implementation of the Cortex-M3 is described in detail in EFM32G Reference Manual. 3.1.2 Debug Interface (DBG) This device includes hardware debug support through a 2-pin serial-wire debug interface . In addition there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data trace and software-generated messages. 3.1.3 Memory System Controller (MSC) The Memory System Controller (MSC) is the program memory unit of the EFM32G microcontroller. The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in the energy modes EM0 and EM1. silabs.com | Building a more connected world. Rev. 2.10 | 10 EFM32G Data Sheet System Overview 3.1.4 Direct Memory Access Controller (DMA) The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 DMA controller licensed from ARM. 3.1.5 Reset Management Unit (RMU) The RMU is responsible for handling the reset functionality of the EFM32G. 3.1.6 Energy Management Unit (EMU) The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32G microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks. 3.1.7 Clock Management Unit (CMU) The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32G. The CMU provides the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that are inactive. 3.1.8 Watchdog (WDOG) The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a software failure. 3.1.9 Peripheral Reflex System (PRS) The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but edge triggers and other functionality can be applied by the PRS. 3.1.10 External Bus Interface (EBI) The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH, ADCs and LCDs. The interface is memory mapped into the address bus of the Cortex-M3. This enables seamless access from software without manually manipulating the IO settings each time a read or write is performed. The data and address lines are multiplexed in order to reduce the number of pins required to interface the external devices. The timing is adjustable to meet specifications of the external devices. The interface is limited to asynchronous devices. 3.1.11 Inter-Integrated Circuit Interface (I2C) The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system. The interface provided to software by the I2C module, allows both fine-grained control of the transmission process and close to automatic transfers. Automatic recognition of slave addresses is provided in all energy modes. 3.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, and IrDA devices. 3.1.13 Pre-Programmed USB/UART Bootloader The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Autobaud and destructive write are supported. The autobaud feature, interface and commands are described further in the application note. silabs.com | Building a more connected world. Rev. 2.10 | 11 EFM32G Data Sheet System Overview 3.1.14 Universal Asynchronous Receiver/Transmitter (UART) The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module. It supports full- and half-duplex asynchronous UART communication. 3.1.15 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/ s. The LEUART includes all necessary hardware support to make asynchronous serial communication possible with minimum of software intervention and energy consumption. 3.1.16 Timer/Counter (TIMER) The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor control applications. 3.1.17 Real Time Counter (RTC) The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where most of the device is powered down. 3.1.18 Low Energy Timer (LETIMER) The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2 in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be configured to start counting on compare matches from the RTC. 3.1.19 Pulse Counter (PCNT) The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source. The module may operate in energy mode EM0 - EM3. 3.1.20 Analog Comparator (ACMP) The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs can either be one of the selectable internal references or from external pins. Response time and thereby also the current consumption can be configured by altering the current supply to the comparator. 3.1.21 Voltage Comparator (VCMP) The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can be generated when the supply falls below or rises above a programmable threshold. Response time and thereby also the current consumption can be configured by altering the current supply to the comparator. 3.1.22 Analog to Digital Converter (ADC) The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per second. The integrated input mux can select inputs from 8 external pins and 6 internal signals. 3.1.23 Digital to Analog Converter (DAC) The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC is fully differential rail-to-rail, with 12-bit resolution. It has two single-ended output buffers which can be combined into one differential output. The DAC may be used for a number of different applications such as sensor interfaces or sound output. silabs.com | Building a more connected world. Rev. 2.10 | 12 EFM32G Data Sheet System Overview 3.1.24 Advanced Encryption Standard Accelerator (AES) The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit operations are not supported. 3.1.25 General Purpose Input/Output (GPIO) General Purpose Input/Output (GPIO) pins are organized into ports with up to 16 pins each. These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive strength can also be configured individually for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM outputs or USART communication, which can be routed to several locations on the device. The GPIO supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other peripherals. 3.1.26 Liquid Crystal Display Driver (LCD) The LCD driver is capable of driving a segmented LCD display with up to 4x40 segments. A voltage boost function enables it to provide the LCD display with higher voltage than the supply voltage for the device. In addition, an animation feature can run custom animations on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame Counter interrupt that can wake-up the device on a regular basis for updating data. silabs.com | Building a more connected world. Rev. 2.10 | 13 EFM32G Data Sheet System Overview 3.2 Configuration Summary 3.2.1 EFM32G200 The features of the EFM32G200 is a subset of the feature set described in the EFM32G Reference Manual. The following table describes device specific implementation of the features. Table 3.1. EFM32G200 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[1:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:5], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:4] DAC0 Full configuration DAC0_OUT[0] GPIO 24 pins Available pins are shown in Table 4.3 (p. 57) silabs.com | Building a more connected world. Rev. 2.10 | 14 EFM32G Data Sheet System Overview 3.2.2 EFM32G210 The features of the EFM32G210 is a subset of the feature set described in the EFM32G Reference Manual. The following table describes device specific implementation of the features. Table 3.2. EFM32G210 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0] ACMP0 Full configuration ACMP0_CH[1:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:5], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:4] DAC0 Full configuration DAC0_OUT[0] AES Full configuration NA GPIO 24 pins Available pins are shown in Table 4.3 (p. 57) silabs.com | Building a more connected world. Rev. 2.10 | 15 EFM32G Data Sheet System Overview 3.2.3 EFM32G222 The features of the EFM32G222 is a subset of the feature set described in the EFM32G Reference Manual. The following table describes device specific implementation of the features. Table 3.3. EFM32G222 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS LEUART0 Full configuration LEU0_TX, LEU0_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] ACMP0 Full configuration ACMP0_CH[4:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:4] DAC0 Full configuration DAC0_OUT[1] AES Full configuration NA GPIO 37 pins Available pins are shown in Table 4.3 (p. 57) silabs.com | Building a more connected world. Rev. 2.10 | 16 EFM32G Data Sheet System Overview 3.2.4 EFM32G230 The features of the EFM32G230 is a subset of the feature set described in the EFM32G Reference Manual. The following table describes device specific implementation of the features. Table 3.4. EFM32G230 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0] AES Full configuration NA GPIO 56 pins Available pins are shown in Table 4.3 (p. 57) silabs.com | Building a more connected world. Rev. 2.10 | 17 EFM32G Data Sheet System Overview 3.2.5 EFM32G232 The features of the EFM32G232 is a subset of the feature set described in the EFM32G Reference Manual. The following table describes device specific implementation of the features. Table 3.5. EFM32G232 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[15:8], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[0] AES Full configuration NA GPIO 53 pins Available pins are shown in Table 4.3 (p. 57) silabs.com | Building a more connected world. Rev. 2.10 | 18 EFM32G Data Sheet System Overview 3.2.6 EFM32G280 The features of the EFM32G280 is a subset of the feature set described in the EFM32G Reference Manual. The following table describes device specific implementation of the features. Table 3.6. EFM32G280 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA EBI Full configuration EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn, EBI_CS[3:0], EBI_AD[15:0] I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0] AES Full configuration NA GPIO 86 pins Available pins are shown in Table 4.3 (p. 57) silabs.com | Building a more connected world. Rev. 2.10 | 19 EFM32G Data Sheet System Overview 3.2.7 EFM32G290 The features of the EFM32G290 is a subset of the feature set described in the EFM32G Reference Manual. The following table describes device specific implementation of the features. Table 3.7. EFM32G290 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA EBI Full configuration EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn, EBI_CS[3:0], EBI_AD[15:0] I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0] AES Full configuration NA GPIO 90 pins Available pins are shown in Table 4.3 (p. 57) silabs.com | Building a more connected world. Rev. 2.10 | 20 EFM32G Data Sheet System Overview 3.2.8 EFM32G840 The features of the EFM32G840 is a subset of the feature set described in the EFM32G Reference Manual. The following table describes device specific implementation of the features. Table 3.8. EFM32G840 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:4], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:4], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0] AES Full configuration NA GPIO 56 pins Available pins are shown in Table 4.3 (p. 57) LCD Full configuration LCD_SEG[23:0], LCD_COM[3:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.10 | 21 EFM32G Data Sheet System Overview 3.2.9 EFM32G842 The features of the EFM32G842 is a subset of the feature set described in the EFM32G Reference Manual. The following table describes device specific implementation of the features. Table 3.9. EFM32G842 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[3:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:4], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[0] AES Full configuration NA GPIO 53 pins Available pins are shown in Table 4.3 (p. 57) silabs.com | Building a more connected world. Rev. 2.10 | 22 EFM32G Data Sheet System Overview 3.2.10 EFM32G880 The features of the EFM32G880 is a subset of the feature set described in the EFM32G Reference Manual. The following table describes device specific implementation of the features. Table 3.10. EFM32G880 Configuration Summary Module Module Module Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA EBI Full configuration EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn, EBI_CS[3:0], EBI_AD[15:0] I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0] AES Full configuration NA GPIO 86 pins Available pins are shown in Table 4.3 (p. 57) silabs.com | Building a more connected world. Rev. 2.10 | 23 EFM32G Data Sheet System Overview Module Module Module LCD Full configuration LCD_SEG[39:0], LCD_COM[3:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.10 | 24 EFM32G Data Sheet System Overview 3.2.11 EFM32G890 The features of the EFM32G890 is a subset of the feature set described in the EFM32G Reference Manual. The following table describes device specific implementation of the features. Table 3.11. EFM32G890 Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA EBI Full configuration EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn, EBI_CS[3:0], EBI_AD[15:0] I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] RTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0] AES Full configuration NA GPIO 90 pins Available pins are shown in Table 4.3 (p. 57) silabs.com | Building a more connected world. Rev. 2.10 | 25 EFM32G Data Sheet System Overview Module Configuration Pin Connections LCD Full configuration LCD_SEG[39:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT silabs.com | Building a more connected world. Rev. 2.10 | 26 EFM32G Data Sheet System Overview 3.3 Memory Map The EFM32G memory map is shown in the figure below. RAM and Flash sizes are for the largest memory configuration. Figure 3.2. System Address Space with Core and Code Space Listing silabs.com | Building a more connected world. Rev. 2.10 | 27 EFM32G Data Sheet System Overview Figure 3.3. System Address Space with Peripheral Listing silabs.com | Building a more connected world. Rev. 2.10 | 28 EFM32G Data Sheet Electrical Characteristics 4. Electrical Characteristics 4.1 Test Conditions 4.1.1 Typical Values The typical data are based on TAMB=25C and VDD=3.0 V, as defined in Table 4.2 General Operating Conditions on page 29, unless otherwise specified. 4.1.2 Minimum and Maximum Values The minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined in Table 4.2 General Operating Conditions on page 29, unless otherwise specified. 4.2 Absolute Maximum Ratings The absolute maximum ratings are stress ratings, and functional operation under such conditions are not guaranteed. Stress beyond the limits specified in the following table may affect the device reliability or cause permanent damage to the device. Functional operating conditions are given in Table 4.2 General Operating Conditions on page 29. Table 4.1. Absolute Maximum Ratings Parameter Symbol Storage temperature range TSTG Maximum soldering temperature TS External main supply voltage VDDMAX Voltage on any I/O pin VIOPIN Current per I/O pin (sink) Current per I/O pin (source) Test Condition Min Typ Max Unit -40 -- 150 C -- -- 260 C 0 -- 3.8 V -0.3 -- VDD+0.3 V IIOMAX_SINK -- -- 100 mA IIOMAX_SOURCE -- -- -100 mA Latest IPC/JEDEC JSTD-020 Standard 4.3 General Operating Conditions Table 4.2. General Operating Conditions Parameter Symbol Min Typ Max Unit Ambient temperature range TAMB -40 -- 85 C Operating supply voltage VDDOP 1.98 -- 3.8 V Internal APB clock frequency fAPB -- -- 32 MHz Internal AHB clock frequency fAHB -- -- 32 MHz silabs.com | Building a more connected world. Rev. 2.10 | 29 EFM32G Data Sheet Electrical Characteristics 4.4 Current Consumption Table 4.3. Current Consumption Parameter EM0 current. No prescaling. Running prime number calculation code from Flash. (Production test condition = 14 MHz) Symbol IEM0 EM1 current (Production test IEM1 condition = 14 MHz) EM2 current IEM2 EM3 current IEM3 EM4 current IEM4 silabs.com | Building a more connected world. Test Condition Min Typ Max Unit 32 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V -- 180 -- A/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V -- 181 206 A/MHz 21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V -- 183 207 A/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V -- 185 211 A/MHz 11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V -- 186 215 A/MHz 6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V -- 191 218 A/MHz 1.2 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V -- 220 -- A/MHz 32 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V -- 45 -- A/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V -- 47 62 A/MHz 21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V -- 48 64 A/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V -- 50 69 A/MHz 11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V -- 51 72 A/MHz 6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V -- 56 83 A/MHz 1.2 MHz HFRCO. all peripheral clocks disabled, VDD= 3.0 V -- 103 -- A/MHz EM2 current with RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=25 C -- 0.9 1.5 A EM2 current with RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=85 C -- 3.0 6.0 A VDD= 3.0 V, TAMB=25 C -- 0.59 1.0 A VDD= 3.0 V, TAMB=85 C -- 2.75 5.8 A VDD= 3.0 V, TAMB=25 C -- 0.02 0.045 A VDD= 3.0 V, TAMB=85 C -- 0.25 0.7 A Rev. 2.10 | 30 EFM32G Data Sheet Electrical Characteristics 4.4.1 EM0 Current Consumption 5.3 5.3 85.0C 65.0C 5.2 5.2 45.0C 5.1 5.1 25.0C Idd [mA] 5.0C -15.0C 4.9 4.9 -40.0C 4.8 4.7 4.6 2.0 5.0 Idd [mA] 5.0 Vdd=2.0V Vdd=2.2V Vdd=2.4V Vdd=2.6V Vdd=2.8V Vdd=3.0V Vdd=3.2V Vdd=3.4V Vdd=3.6V Vdd=3.8V 4.8 4.7 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 3.8 4.6 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.1. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 28 MHz silabs.com | Building a more connected world. Rev. 2.10 | 31 EFM32G Data Sheet Electrical Characteristics 4.0 4.0 85.0C 65.0C 3.9 3.9 45.0C 25.0C 5.0C Idd [mA] 3.8 Idd [mA] 3.8 -15.0C 3.7 Vdd=2.0V Vdd=2.2V Vdd=2.4V Vdd=2.6V Vdd=2.8V Vdd=3.0V Vdd=3.2V Vdd=3.4V Vdd=3.6V Vdd=3.8V 3.7 -40.0C 3.6 3.5 2.0 3.6 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 3.5 -40 3.8 -15 5 25 Temperature [C] 45 65 85 Figure 4.2. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 21 MHz 2.75 2.75 85.0C 2.70 2.70 65.0C 2.65 2.65 45.0C 2.60 2.60 Vdd=2.0V Vdd=2.2V Vdd=2.4V Vdd=2.6V Vdd=2.8V Vdd=3.0V Vdd=3.2V Vdd=3.4V Vdd=3.6V Vdd=3.8V Idd [mA] Idd [mA] 25.0C 2.55 5.0C 2.50 -15.0C 2.50 2.45 -40.0C 2.45 2.40 2.35 2.0 2.55 2.40 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 3.8 2.35 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.3. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 14 MHz silabs.com | Building a more connected world. Rev. 2.10 | 32 EFM32G Data Sheet Electrical Characteristics 2.20 2.20 85.0C 2.15 2.15 65.0C 2.10 2.10 45.0C 25.0C 5.0C 2.05 Idd [mA] Idd [mA] 2.05 Vdd=2.0V Vdd=2.2V Vdd=2.4V Vdd=2.6V Vdd=2.8V Vdd=3.0V Vdd=3.2V Vdd=3.4V Vdd=3.6V Vdd=3.8V 2.00 2.00 -15.0C 1.95 1.95 -40.0C 1.90 1.85 2.0 1.90 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 1.85 -40 3.8 -15 5 25 Temperature [C] 45 65 85 Figure 4.4. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 11 MHz 1.45 1.45 85.0C 1.40 1.40 65.0C 45.0C 1.35 1.35 Vdd=2.0V Vdd=2.2V Vdd=2.4V Vdd=2.6V Vdd=2.8V Vdd=3.0V Vdd=3.2V Vdd=3.4V Vdd=3.6V Vdd=3.8V 5.0C -15.0C 1.30 Idd [mA] Idd [mA] 25.0C 1.30 -40.0C 1.25 1.20 2.0 1.25 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 3.8 1.20 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.5. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 7 MHz silabs.com | Building a more connected world. Rev. 2.10 | 33 EFM32G Data Sheet Electrical Characteristics 4.4.2 EM1 Current Consumption 1.40 1.40 85.0C 65.0C 1.35 1.35 Vdd=2.0V Vdd=2.4V Vdd=2.8V Vdd=3.0V Vdd=3.4V Vdd=3.8V 45.0C 25.0C 1.30 1.30 -15.0C Idd [mA] Idd [mA] 5.0C -40.0C 1.25 1.25 1.20 1.15 2.0 1.20 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 1.15 -40 3.8 -15 5 25 Temperature [C] 45 65 85 Figure 4.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 28 MHz 1.08 1.08 85.0C 1.06 1.04 65.0C 1.04 1.02 45.0C 1.02 25.0C 1.00 5.0C Idd [mA] Idd [mA] 1.06 1.00 0.98 -15.0C 0.98 0.96 -40.0C 0.96 0.94 0.92 2.0 Vdd=2.0V Vdd=2.4V Vdd=2.8V Vdd=3.0V Vdd=3.4V Vdd=3.8V 0.94 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 3.8 0.92 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21 MHz silabs.com | Building a more connected world. Rev. 2.10 | 34 EFM32G Data Sheet Electrical Characteristics 0.76 0.76 85.0C 0.74 0.74 65.0C 0.72 Vdd=2.0V Vdd=2.4V Vdd=2.8V Vdd=3.0V Vdd=3.4V Vdd=3.8V 0.72 25.0C 0.70 5.0C Idd [mA] Idd [mA] 45.0C 0.70 -15.0C 0.68 0.68 -40.0C 0.66 0.64 2.0 0.66 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 0.64 -40 3.8 -15 5 25 Temperature [C] 45 65 85 Figure 4.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14 MHz 0.62 0.60 65.0C 0.60 0.58 45.0C 0.58 25.0C 5.0C 0.56 -15.0C Vdd=2.0V Vdd=2.4V Vdd=2.8V Vdd=3.0V Vdd=3.4V Vdd=3.8V Idd [mA] 85.0C Idd [mA] 0.62 0.56 -40.0C 0.54 0.52 2.0 0.54 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 3.8 0.52 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11 MHz silabs.com | Building a more connected world. Rev. 2.10 | 35 EFM32G Data Sheet Electrical Characteristics 0.44 0.44 85.0C 0.43 0.43 65.0C 0.42 Vdd=2.0V Vdd=2.4V Vdd=2.8V Vdd=3.0V Vdd=3.4V Vdd=3.8V 0.42 0.41 0.41 25.0C 0.40 5.0C -15.0C 0.39 Idd [mA] Idd [mA] 45.0C 0.40 0.39 -40.0C 0.38 0.38 0.37 0.37 0.36 2.0 2.2 2.4 2.6 2.8 3.0 Vdd [V] 3.2 3.4 3.6 3.8 0.36 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 7 MHz silabs.com | Building a more connected world. Rev. 2.10 | 36 EFM32G Data Sheet Electrical Characteristics 4.4.3 EM2 Current Consumption 3.5 3.5 -40.0C -15.0C 5.0C 25.0C 45.0C 65.0C 85.0C 3.0 3.0 2.5 Idd [uA] Idd [uA] 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.5 1.8 Vdd=1.8V Vdd=2.2V Vdd=2.6V Vdd=3.0V Vdd=3.4V Vdd=3.8V 2.0 2.2 2.4 2.6 2.8 Vdd [V] 3.0 3.2 3.4 3.6 3.8 0.5 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.11. EM2 Current Consumption, RTC prescaled to 1 kHz, 32.768 kHz LFRCO silabs.com | Building a more connected world. Rev. 2.10 | 37 EFM32G Data Sheet Electrical Characteristics 4.4.4 EM3 Current Consumption 3.0 3.0 -40.0C -15.0C 5.0C 25.0C 45.0C 65.0C 85.0C 2.5 2.5 2.0 Idd [uA] Idd [uA] 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0.0 1.8 Vdd=1.8V Vdd=2.2V Vdd=2.6V Vdd=3.0V Vdd=3.4V Vdd=3.8V 2.0 2.2 2.4 2.6 2.8 Vdd [V] 3.0 3.2 3.4 3.6 3.8 0.0 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.12. EM3 Current Consumption silabs.com | Building a more connected world. Rev. 2.10 | 38 EFM32G Data Sheet Electrical Characteristics 4.4.5 EM4 Current Consumption 0.45 0.40 0.35 0.30 0.30 0.25 0.25 0.20 0.20 0.15 0.15 0.10 0.10 0.05 0.05 0.00 1.8 2.0 2.2 Vdd=1.8V Vdd=2.2V Vdd=2.6V Vdd=3.0V Vdd=3.4V Vdd=3.8V 0.40 Idd [uA] Idd [uA] 0.35 0.45 -40.0C -15.0C 5.0C 25.0C 45.0C 65.0C 85.0C 2.4 2.6 2.8 Vdd [V] 3.0 3.2 3.4 3.6 3.8 0.00 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.13. EM4 Current Consumption 4.5 Transition between Energy Modes The transition times are measured from the trigger to the first clock edge in the CPU. Table 4.4. Energy Modes Transitions Parameter Symbol Min Typ Max Unit Transition time from EM1 to EM0 tEM10 -- 0 -- HFCORECLK cycles Transition time from EM2 to EM0 tEM20 -- 2 -- s Transition time from EM3 to EM0 tEM30 -- 2 -- s Transition time from EM4 to EM0 tEM40 -- 163 -- s silabs.com | Building a more connected world. Rev. 2.10 | 39 EFM32G Data Sheet Electrical Characteristics 4.6 Power Management The EFM32G requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with optional filter) at the PCB level. For practical schematic recommendations, please see the application note, "AN0002 EFM32 Hardware Design Considerations". Table 4.5. Power Management Parameter Symbol Test Condition Min Typ Max Unit BOD threshold on falling external supply voltage VBODextthr- EM0 1.74 -- 1.96 V EM1 1.74 -- 1.96 V EM2 1.74 -- 1.96 V EM0 -- 1.85 -- V -- -- 1.98 V -- 163 -- s BOD threshold on rising external supply voltage VBODextthr+ Power-on Reset (POR) threshold on rising external supply voltage VPORthr+ Delay from reset is released until program execution starts tRESETdly negative pulse length to ensure complete reset of device tRESET 50 -- -- ns Voltage regulator decoupling capacitor. CDECOUPLE X5R capacitor recommended. Apply between DECOUPLE pin and GROUND -- 1 -- F silabs.com | Building a more connected world. Applies to Power-on Reset, Brown-out Reset and pin reset. Rev. 2.10 | 40 EFM32G Data Sheet Electrical Characteristics 4.7 Flash Table 4.6. Flash Parameter Symbol Flash erase cycles before failure ECFLASH Flash data retention RETFLASH Test Condition Min Typ Max Unit 20000 -- -- cycles TAMB<150 C 10000 -- -- h TAMB<85 C 10 -- -- years TAMB<70 C 20 -- -- years Word (32-bit) programming time tW_PROG 20 -- -- s Page erase time2 tP_ERASE 20.7 22.0 24.8 ms Device erase time3 tD_ERASE 41.8 45.0 49.2 ms Erase current IERASE -- -- 71 mA Write current IWRITE -- -- 71 mA Supply voltage during flash erase and write VFLASH 1.98 -- 3.8 V Note: 1. Measured at 25 C. 2. From setting ERASEPAGE bit in MSC_WRITECMD to 1 to reading 1 in ERASE bit in MSC_IF. Internal setup and hold times for flash control signals are included. 3. From setting DEVICEERASE bit in AAP_CMD to 1 to reading 0 in ERASEBUSY bit in AAP_STATUS. Internal setup and hold times for flash control signals are included. silabs.com | Building a more connected world. Rev. 2.10 | 41 EFM32G Data Sheet Electrical Characteristics 4.8 General Purpose Input Output Table 4.7. GPIO Parameter Symbol Input low voltage Input high voltage Min Typ Max Unit VIOIL -- -- 0.30xVDD1 V VIOIH 0.70xVDD1 -- -- V Sourcing 0.1 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = LOWEST -- 0.80xVDD -- V Sourcing 0.1 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = LOWEST -- 0.90xVDD -- V Sourcing 1 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = LOW -- 0.85xVDD -- V Sourcing 1 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = LOW -- 0.90xVDD -- V Sourcing 6 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = STANDARD 0.75xVDD -- -- V Sourcing 6 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = STANDARD 0.85xVDD -- -- V Sourcing 20 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = HIGH 0.60xVDD -- -- V Sourcing 20 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = HIGH 0.80xVDD -- -- V Output high voltage (Production test condition = 3.0 V, DRIVE- VIOOH MODE = STANDARD) silabs.com | Building a more connected world. Test Condition Rev. 2.10 | 42 EFM32G Data Sheet Electrical Characteristics Parameter Output low voltage (Production test condition = 3.0 V, DRIVEMODE = STANDARD) Symbol VIOOL Test Condition Min Typ Max Unit Sinking 0.1 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = LOWEST -- 0.20xVDD -- V Sinking 0.1 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = LOWEST -- 0.10xVDD -- V Sinking 1 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = LOW -- 0.10xVDD -- V Sinking 1 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = LOW -- 0.05xVDD -- V Sinking 6 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = STANDARD -- -- 0.30xVDD V Sinking 6 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = STANDARD -- -- 0.20xVDD V Sinking 20 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = HIGH -- -- 0.35xVDD V Sinking 20 mA, VDD=3.0 V, GPIO_Px_CTRL DRIVEMODE = HIGH -- -- 0.25xVDD V High Impedance IO connected to GROUND or VDD -- 0.1 40 nA Input leakage current IIOLEAK I/O pin pull-up resistor RPU -- 40 -- k I/O pin pull-down resistor RPD -- 40 -- k Internal ESD series resistor RIOESD -- 200 -- Pulse width of pulses to be removed by the glitch suppression filter tIOGLITCH 10 -- 50 ns GPIO_Px_CTRL DRIVEMODE = LOWEST and load capacitance CL=12.5-25pF. 20+0.1CL -- 250 ns GPIO_Px_CTRL DRIVEMODE = LOW and load capacitance CL=350-600pF 20+0.1CL -- 250 ns VDD = 1.98 - 3.8 V 0.1xVDD -- -- V Output fall time tIOOF I/O pin hysteresis (VIOTHR+ VIOTHR-) VIOHYST Note: 1. If the GPIO input voltage is between 0.3xVDD and 0.7xVDD, the current consumption will increase. silabs.com | Building a more connected world. Rev. 2.10 | 43 EFM32G Data Sheet Electrical Characteristics GPIO_Px_CTRL DRIVEMODE = LOW 20 0.15 15 Low-Level Output Current [mA] Low-Level Output Current [mA] GPIO_Px_CTRL DRIVEMODE = LOWEST 0.20 0.10 10 5 0.05 -40C 25C 85C 0.00 0.0 0.5 1.0 Low-Level Output Voltage [V] 1.5 -40C 25C 85C 0 0.0 2.0 GPIO_Px_CTRL DRIVEMODE = STANDARD 0.5 1.0 Low-Level Output Voltage [V] 1.5 2.0 GPIO_Px_CTRL DRIVEMODE = HIGH 5 45 40 35 Low-Level Output Current [mA] Low-Level Output Current [mA] 4 3 2 25 20 15 10 1 5 -40C 25C 85C 0 0.0 30 0.5 1.0 Low-Level Output Voltage [V] 1.5 2.0 0 0.0 -40C 25C 85C 0.5 1.0 Low-Level Output Voltage [V] 1.5 2.0 Figure 4.14. Typical Low-Level Output Current, 2V Supply Voltage silabs.com | Building a more connected world. Rev. 2.10 | 44 EFM32G Data Sheet Electrical Characteristics GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW 0.00 0.0 -40C 25C 85C -40C 25C 85C -0.5 High-Level Output Current [mA] High-Level Output Current [mA] -0.05 -0.10 -1.0 -1.5 -0.15 -2.0 -0.20 0.0 0.5 1.0 High-Level Output Voltage [V] 1.5 2.0 -2.5 0.0 GPIO_Px_CTRL DRIVEMODE = STANDARD 0.5 1.0 High-Level Output Voltage [V] 1.5 2.0 GPIO_Px_CTRL DRIVEMODE = HIGH 0 0 -40C 25C 85C -40C 25C 85C -10 High-Level Output Current [mA] High-Level Output Current [mA] -5 -10 -20 -30 -15 -40 -20 0.0 0.5 1.0 High-Level Output Voltage [V] 1.5 2.0 -50 0.0 0.5 1.0 High-Level Output Voltage [V] 1.5 2.0 Figure 4.15. Typical High-Level Output Current, 2V Supply Voltage silabs.com | Building a more connected world. Rev. 2.10 | 45 EFM32G Data Sheet Electrical Characteristics GPIO_Px_CTRL DRIVEMODE = LOW 10 0.4 8 Low-Level Output Current [mA] Low-Level Output Current [mA] GPIO_Px_CTRL DRIVEMODE = LOWEST 0.5 0.3 0.2 0.1 6 4 2 -40C 25C 85C 0.0 0.0 0.5 1.5 1.0 2.0 Low-Level Output Voltage [V] 2.5 -40C 25C 85C 0 0.0 3.0 GPIO_Px_CTRL DRIVEMODE = STANDARD 0.5 1.5 1.0 2.0 Low-Level Output Voltage [V] 2.5 3.0 GPIO_Px_CTRL DRIVEMODE = HIGH 40 50 35 40 Low-Level Output Current [mA] Low-Level Output Current [mA] 30 25 20 15 30 20 10 10 5 0 0.0 -40C 25C 85C 0.5 1.5 1.0 2.0 Low-Level Output Voltage [V] 2.5 -40C 25C 85C 3.0 0 0.0 0.5 1.5 1.0 2.0 Low-Level Output Voltage [V] 2.5 3.0 Figure 4.16. Typical Low-Level Output Current, 3V Supply Voltage silabs.com | Building a more connected world. Rev. 2.10 | 46 EFM32G Data Sheet Electrical Characteristics GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW 0 0.0 -40C 25C 85C -40C 25C 85C -1 High-Level Output Current [mA] High-Level Output Current [mA] -0.1 -0.2 -0.3 -2 -3 -4 -0.4 -5 -0.5 0.0 0.5 1.5 1.0 2.0 High-Level Output Voltage [V] 2.5 -6 0.0 3.0 GPIO_Px_CTRL DRIVEMODE = STANDARD 2.5 3.0 0 -40C 25C 85C -40C 25C 85C -10 High-Level Output Current [mA] -10 High-Level Output Current [mA] 1.5 1.0 2.0 High-Level Output Voltage [V] GPIO_Px_CTRL DRIVEMODE = HIGH 0 -20 -30 -40 -50 0.0 0.5 -20 -30 -40 0.5 1.5 1.0 2.0 High-Level Output Voltage [V] 2.5 3.0 -50 0.0 0.5 1.5 1.0 2.0 High-Level Output Voltage [V] 2.5 3.0 Figure 4.17. Typical High-Level Output Current, 3V Supply Voltage silabs.com | Building a more connected world. Rev. 2.10 | 47 EFM32G Data Sheet Electrical Characteristics GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW 0.8 14 0.7 12 0.6 Low-Level Output Current [mA] Low-Level Output Current [mA] 10 0.5 0.4 0.3 8 6 4 0.2 2 0.1 0.0 0.0 -40C 25C 85C 0.5 1.5 1.0 2.0 2.5 Low-Level Output Voltage [V] 3.0 -40C 25C 85C 0 0.0 3.5 50 40 40 30 20 10 1.5 1.0 2.0 2.5 Low-Level Output Voltage [V] 3.0 30 20 10 -40C 25C 85C 0 0.0 3.5 GPIO_Px_CTRL DRIVEMODE = HIGH 50 Low-Level Output Current [mA] Low-Level Output Current [mA] GPIO_Px_CTRL DRIVEMODE = STANDARD 0.5 0.5 1.5 1.0 2.0 2.5 Low-Level Output Voltage [V] 3.0 3.5 -40C 25C 85C 0 0.0 0.5 1.5 1.0 2.0 2.5 Low-Level Output Voltage [V] 3.0 3.5 Figure 4.18. Typical Low-Level Output Current, 3.8V Supply Voltage silabs.com | Building a more connected world. Rev. 2.10 | 48 EFM32G Data Sheet Electrical Characteristics GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW 0.0 -0.1 0 -40C 25C 85C -1 -40C 25C 85C -2 High-Level Output Current [mA] High-Level Output Current [mA] -0.2 -0.3 -0.4 -0.5 -3 -4 -5 -6 -0.6 -7 -0.7 -0.8 0.0 -8 0.5 1.5 1.0 2.0 2.5 High-Level Output Voltage [V] 3.0 -9 0.0 3.5 GPIO_Px_CTRL DRIVEMODE = STANDARD 3.0 3.5 0 -40C 25C 85C -40C 25C 85C -10 High-Level Output Current [mA] -10 High-Level Output Current [mA] 1.5 1.0 2.0 2.5 High-Level Output Voltage [V] GPIO_Px_CTRL DRIVEMODE = HIGH 0 -20 -30 -40 -50 0.0 0.5 -20 -30 -40 0.5 1.5 1.0 2.0 2.5 High-Level Output Voltage [V] 3.0 3.5 -50 0.0 0.5 1.5 1.0 2.0 2.5 High-Level Output Voltage [V] 3.0 3.5 Figure 4.19. Typical High-Level Output Current, 3.8V Supply Voltage silabs.com | Building a more connected world. Rev. 2.10 | 49 EFM32G Data Sheet Electrical Characteristics 4.9 Oscillators 4.9.1 LFXO Table 4.8. LFXO Parameter Symbol Supported nominal crystal frequency Test Condition Min Typ Max Unit fLFXO -- 32.768 -- kHz Supported crystal equivalent series resistance (ESR) ESRLFXO -- 30 120 kOhm Supported crystal external load range CLFXOL X1 -- 25 pF Current consumption for core and ILFXO buffer after startup ESR=30 k, CL=10 pF, LFXOBOOST in CMU_CTRL is 1 -- 190 -- nA Start-up time ESR=30 k, CL=10 pF, 40% 60% duty cycle has been reached, LFXOBOOST in CMU_CTRL is 1 -- 400 -- ms tLFXO Note: 1. See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in Configurator in Simplicity Studio. For safe startup of a given crystal, the Configurator tool in Simplicity Studio contains a tool to help users configure both load capacitance and software settings for using the LFXO. For details regarding the crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator Design Consideration". silabs.com | Building a more connected world. Rev. 2.10 | 50 EFM32G Data Sheet Electrical Characteristics 4.9.2 HFXO Table 4.9. HFXO Parameter Symbol Supported nominal crystal Frequency fHFXO Supported crystal equivalent series resistance (ESR) ESRHFXO The transconductance of the HFXO input transistor at crystal startup gmHFXO Supported crystal external load range CHFXOL Current consumption for HFXO after startup IHFXO Startup time tHFXO Pulse width removed by glitch detector silabs.com | Building a more connected world. Test Condition Min Typ Max Unit 4 -- 32 MHz Crystal frequency 32 MHz -- 30 60 Crystal frequency 4 MHz -- 400 1500 HFXOBOOST in CMU_CTRL equals 0b11 20 -- -- mS 5 -- 25 pF 4 MHz: ESR=400 , CL=20 pF, HFXOBOOST in CMU_CTRL equals 0b11 -- 85 -- A 32 MHz: ESR=30 , CL=10 pF, HFXOBOOST in CMU_CTRL equals 0b11 -- 165 -- A 32 MHz: ESR=30 , CL=10 pF, HFXOBOOST in CMU_CTRL equals 0b11 -- 400 -- s 1 -- 4 ns Rev. 2.10 | 51 EFM32G Data Sheet Electrical Characteristics 4.9.3 LFRCO Table 4.10. LFRCO Parameter Symbol Oscillation frequency, VDD= 3.0 V, TAMB=25C Min Typ Max Unit fLFRCO 31.29 32.768 34.24 kHz Startup time not including software calibration tLFRCO -- 150 -- s Current consumption ILFRCO -- 190 -- nA Temperature coefficient TCLFRCO -- 0.02 -- %/C Supply voltage coefficient VCLFRCO -- 15 -- %/V -- 1.5 -- % Frequency step for LSB change TUNESTEPLFRCO in TUNING value Test Condition Figure 4.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage silabs.com | Building a more connected world. Rev. 2.10 | 52 EFM32G Data Sheet Electrical Characteristics 4.9.4 HFRCO Table 4.11. HFRCO Parameter Oscillation frequency, VDD= 3.0 V, TAMB=25 C Settling time Current consumption (Production test condition = 14 MHz) Duty cycle Symbol fHFRCO tHFRCO_settling IHFRCO DCHFRCO Frequency step for LSB change TUNESTEPHFRCO in TUNING value Test Condition Min Typ Max Unit 28 MHz frequency band 27.16 28 28.84 MHz 21 MHz frequency band 20.37 21 21.63 MHz 14 MHz frequency band 13.58 14 14.42 MHz 11 MHz frequency band 10.67 11 11.33 MHz 7 MHz frequency band 6.402 6.61 6.798 MHz 1 MHz frequency band 1.164 1.22 1.236 MHz After start-up, fHFRCO = 14 MHz -- 0.6 -- Cycles After band switch -- 25 -- Cycles fHFRCO = 28 MHz -- 158 190 A fHFRCO = 21 MHz -- 125 155 A fHFRCO = 14 MHz -- 99 120 A fHFRCO = 11 MHz -- 88 110 A fHFRCO = 6.6 MHz -- 72 90 A fHFRCO = 1.2 MHz -- 24 32 A fHFRCO = 14 MHz 48.5 50 51 % -- 0.33 -- % Note: 1. For devices with prod. rev. < 19, Typ = 7 MHz and Min/Max values not applicable. 2. For devices with prod. rev. < 19, Typ = 1 MHz and Min/Max values not applicable. 3. The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions. silabs.com | Building a more connected world. Rev. 2.10 | 53 EFM32G Data Sheet Electrical Characteristics Figure 4.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature Figure 4.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature silabs.com | Building a more connected world. Rev. 2.10 | 54 EFM32G Data Sheet Electrical Characteristics Figure 4.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature Figure 4.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature silabs.com | Building a more connected world. Rev. 2.10 | 55 EFM32G Data Sheet Electrical Characteristics Figure 4.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature Figure 4.26. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature silabs.com | Building a more connected world. Rev. 2.10 | 56 EFM32G Data Sheet Electrical Characteristics 4.9.5 AUXHFRCO Table 4.12. AUXHFRCO Parameter Symbol Test Condition Min Typ Max Unit Oscillation frequency, VDD= 3.0 V, TAMB=25 C fAUXHFRCO 14 MHz frequency band 13.580 14.0 14.420 MHz Settling time after start-up tAUXHFRCO_settling fAUXHFRCO = 14 MHz -- 0.6 -- Cycles Duty cycle DCAUXHFRCO fAUXHFRCO = 14 MHz 48.5 50 51 % -- 0.31 -- % Frequency step for LSB change TUNESTEPAUXHFRCO in TUNING value Note: 1. The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the frequency band to maintain the AUXHFRCO frequency at any arbitrary value in the 14 MHz range across operating conditions. 4.9.6 ULFRCO Table 4.13. ULFRCO Parameter Symbol Test Condition Min Typ Max Unit Oscillation frequency fULFRCO 25 C, 3 V 0.7 -- 1.75 kHz Temperature coefficient TCULFRCO -- 0.05 -- %/C Supply voltage coefficient VCULFRCO -- -18.2 -- %/V silabs.com | Building a more connected world. Rev. 2.10 | 57 EFM32G Data Sheet Electrical Characteristics 4.10 Analog Digital Converter (ADC) Table 4.14. ADC Parameter Symbol Input voltage range VADCIN Input range of external reference voltage, single-ended and differential VADCREFIN Test Condition Single-ended Differential Min Typ Max Unit 0 -- VREF V -VREF/2 -- VREF/2 V 1.25 -- VDD V Input range of external negative VADCREFIN_CH7 reference voltage on channel 7 See VADCREFIN 0 -- VDD - 1.1 V Input range of external positive reference voltage on channel 6 VADCREFIN_CH6 See VADCREFIN 0.625 -- VDD V Common mode input range VADCCMIN 0 -- VDD V Input current IADCIN -- <100 -- nA Analog input common mode rejection ratio CMRRADC -- 65 -- dB 1 Msamples/s, 12 bit, external reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 7351 -- A 1 Msamples/s, 12 bit, internal 1.25V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 7601 -- A 500 Ksamples/s, 12 bit, external reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 3461 -- A 500 Ksamples/s, 12 bit, internal 1.25V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 3541 -- A 10 kSamples/s, 12 bit, internal 1.25 V reference, WARMUP = 00b, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 521 -- A 10 kSamples/s, 12 bit, internal 1.25 V reference, WARMUP = 01b, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 501 -- A 10 kSamples/s, 12 bit, internal 1.25 V reference, WARMUP = 10b, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 541 -- A Average active current IADC 2 pF sampling capacitors Input capacitance CADCIN -- 2 -- pF Input ON resistance RADCIN 1 -- -- M Input RC filter resistance RADCFILT -- 10 -- k Input RC filter/decoupling capacitance CADCFILT -- 250 -- fF Input bias current IADCBIASIN -40 -- 40 nA silabs.com | Building a more connected world. VSS < VIN < VDD Rev. 2.10 | 58 EFM32G Data Sheet Electrical Characteristics Parameter Symbol Test Condition Min Typ Max Unit Input offset current IADCOFFSETIN VSS < VIN < VDD -40 -- 40 nA ADC Clock Frequency fADCCLK BIASPROG=0x747 -- -- 7 MHz BIASPROG=0xF4B -- -- 13 MHz 6 bit 7 -- -- ADCCLK Cycles 8 bit 11 -- -- ADCCLK Cycles 12 bit 13 -- -- ADCCLK Cycles Programmable 1 -- 256 ADCCLK Cycles 2 -- -- s NORMAL mode -- 5 -- s KEEPADCWARM mode -- 1 -- s Conversion time tADCCONV Acquisition time tADCACQ Required acquisition time for VDD/3 reference tADCACQVDD3 Startup time of reference gener- tADCSTART ator and ADC core silabs.com | Building a more connected world. Rev. 2.10 | 59 EFM32G Data Sheet Electrical Characteristics Parameter Symbol Test Condition Signal-to-Noise Ratio (SNR) SNRADC silabs.com | Building a more connected world. Min Typ Max Unit 1 MSamples/s, 12 bit, singleended, internal 1.25 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 59 -- dB 1 MSamples/s, 12 bit, singleended, internal 2.5 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 63 -- dB 1 MSamples/s, 12 bit, singleended, VDD reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 67 -- dB 1 MSamples/s, 12 bit, differential, internal 1.25 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 63 -- dB 1 MSamples/s, 12 bit, differential, internal 2.5 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 66 -- dB 1 MSamples/s, 12 bit, differential, 5 V reference, ADC_CLK =13 MHz, BIASPROG = 0xF4B -- 66 -- dB 1 MSamples/s, 12 bit, differential, VDD reference, ADC_CLK= 13 MHz, BIASPROG =0xF4B 63 69 -- dB 1 MSamples/s, 12 bit, differential, 2xVDD reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 70 -- dB 200 kSamples/s, 12 bit, singleended, internal 1.25 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 62 -- dB 200 kSamples/s, 12 bit, singleended, internal 2.5 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 63 -- dB 200 kSamples/s, 12 bit, singleended, VDD reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 67 -- dB 200 kSamples/s, 12 bit, differential, internal 1.25 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 63 -- dB 200 kSamples/s, 12 bit, differential, internal 2.5 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 66 -- dB 200 kSamples/s, 12 bit, differential, 5 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 66 -- dB Rev. 2.10 | 60 EFM32G Data Sheet Electrical Characteristics Parameter Symbol Test Condition Signal-to-Noise Ratio (SNR) SNRADC silabs.com | Building a more connected world. Min Typ Max Unit 200 kSamples/s, 12 bit, differential, VDD reference,ADC_CLK = 7 MHz, BIASPROG = 0x747 63 69 -- dB 200 kSamples/s, 12 bit, differential, 2xVDD reference,ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 70 -- dB Rev. 2.10 | 61 EFM32G Data Sheet Electrical Characteristics Parameter Symbol Test Condition Signal-to-Noise And Distortion Ratio (SINAD) SINADADC silabs.com | Building a more connected world. Min Typ Max Unit 1 MSamples/s, 12 bit, singleended, internal 1.25 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 58 -- dB 1 MSamples/s, 12 bit, singleended, internal 2.5 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 62 -- dB 1 MSamples/s, 12 bit, singleended, VDD reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 66 -- dB 1 MSamples/s, 12 bit, differential, internal 1.25 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 63 -- dB 1 MSamples/s, 12 bit, differential, internal 2.5 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 66 -- dB 1 MSamples/s, 12 bit, differential, 5 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 66 -- dB 1 MSamples/s, 12 bit, differential, VDD reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B 62 68 -- dB 1 MSamples/s, 12 bit, differential, 2xVDD reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 68 -- dB 200 kSamples/s, 12 bit, singleended, internal 1.25 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 61 -- dB 200 kSamples/s, 12 bit, singleended, internal 2.5 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 62 -- dB 200 kSamples/s, 12 bit, singleended, VDD reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 66 -- dB 200 kSamples/s, 12 bit, differential, internal 1.25 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 63 -- dB 200 kSamples/s, 12 bit, differential, internal 2.5 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 66 -- dB 200 kSamples/s, 12 bit, differential, 5V reference, ADC_CLK= 7 MHz, BIASPROG = 0x747 -- 66 -- dB Rev. 2.10 | 62 EFM32G Data Sheet Electrical Characteristics Parameter Symbol Test Condition Signal-to-Noise And Distortion Ratio (SINAD) SINADADC silabs.com | Building a more connected world. Min Typ Max Unit 200 kSamples/s, 12 bit, differential, VDD reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 62 68 -- dB 200 kSamples/s, 12 bit, differential, 2xVDD reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 69 -- dB Rev. 2.10 | 63 EFM32G Data Sheet Electrical Characteristics Parameter Symbol Test Condition Spurious-Free Dynamic Range (SFDR) SFDRADC silabs.com | Building a more connected world. Min Typ Max Unit 1 MSamples/s, 12 bit, singleended, internal 1.25 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 75 -- dBc 1 MSamples/s, 12 bit, singleended, internal 2.5 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 76 -- dBc 1 MSamples/s, 12 bit, singleended, VDD reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 76 -- dBc 1 MSamples/s, 12 bit, differential, internal 1.25 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 78 -- dBc 1 MSamples/s, 12 bit, differential, internal 2.5 V reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B -- 77 -- dBc 1 MSamples/s, 12 bit, differential, VDD reference, ADC_CLK= 13 MHz, BIASPROG = 0xF4B -- 76 -- dBc 1 MSamples/s, 12 bit, differential, 2xVDD reference, ADC_CLK = 13 MHz, BIASPROG = 0xF4B 68 79 -- dBc 1 MSamples/s, 12 bit, differential, 5 V reference, ADC_CLK =13 MHz, BIASPROG = 0xF4B -- 79 -- dBc 200 kSamples/s, 12 bit, singleended, internal 1.25 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 75 -- dBc 200 kSamples/s, 12 bit, singleended, internal 2.5 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 75 -- dBc 200 kSamples/s, 12 bit, singleended, VDD reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 76 -- dBc 200 kSamples/s, 12 bit, differential, internal 1.25 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 79 -- dBc 200 kSamples/s, 12 bit, differential, internal 2.5 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 79 -- dBc 200 kSamples/s, 12 bit, differential, 5 V reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 78 -- dBc Rev. 2.10 | 64 EFM32G Data Sheet Electrical Characteristics Parameter Symbol Test Condition Spurious-Free Dynamic Range (SFDR) SFDRADC Offset voltage Thermometer output gradient VADCOFFSET Min Typ Max Unit 200 kSamples/s, 12 bit, differential, VDD reference, ADC_CLK = 7 MHz, BIASPROG = 0x747 68 79 -- dBc 200 kSamples/s, 12 bit, differential, 2xVDD reference,ADC_CLK = 7 MHz, BIASPROG = 0x747 -- 79 -- dBc After calibration, single-ended -- 0.3 -- mV After calibration, differential -4 0.3 4 mV -- -1.92 -- mV/C -- -6.3 -- ADC Codes/C TGRADADCTH Differential non-linearity (DNL) DNLADC VDD= 3.0 V, external 2.5 V reference -1 0.7 4 LSB Integral non-linearity (INL), End point method INLADC VDD= 3.0 V, external 2.5 V reference -- 1.2 3 LSB Missing codes MCADC -- -- 3 LSB Gain error drift GAINED 1.25 V reference -- 0.012 0.0333 %/C 2.5 V reference -- 0.012 0.033 %/C 1.25 V reference -- 0.002 0.063 LSB/C 2.5 V reference -- 0.002 0.043 LSB/C 1.25 V reference 1.2 1.25 1.3 V 2.5 V reference 2.4 2.5 2.6 V 1.25 V reference -12.4 2.9 18.2 mV/V 2.5 V reference, VDD > 2.5 V -24.6 5.7 35.2 mV/V 1.25 V reference -132 272 677 V/C 2.5 V reference -231 545 1271 V/C 1.25 V reference -- 67 114 A 2.5 V reference -- 55 82 A 1.25 V reference -- 99.85 -- % 2.5 V reference -- 100.01 -- % Offset error drift VREF voltage VREF voltage drift VREF temperature drift VREF current consumption ADC and DAC VREF matching OFFSETED VREF VREF_VDRIFT VREF_TDRIFT IVREF VREF_MATCH Note: 1. Includes required contribution from the voltage reference. 2. Typical numbers given by abs(Mean) / (85 - 25). 3. Max number given by (abs(Mean) + 3x stddev) / (85 - 25). The integral non-linearity (INL) and differential non-linearity parameters are explained in the following figures. silabs.com | Building a more connected world. Rev. 2.10 | 65 EFM32G Data Sheet Electrical Characteristics Digital output code 4095 4094 4093 4092 INL=|[(VD-VSS)/VLSBIDEAL] - D| where 0 < D < 2N- 1 Actual ADC tranfer function before offset and gain correction Actual ADC tranfer function after offset and gain correction INL Error (End Point INL) Ideal transfer curve 3 2 1 VOFFSET 0 Analog Input Figure 4.27. Integral Non-Linearity (INL) Digital output code DNL=|[(VD+1 - VD)/VLSBIDEAL] - 1| where 0 < D < 2N- 2 Full Scale Range 4095 4094 Example: Adjacent input value VD+1 corrresponds to digital output code D+1 4093 4092 Code width =2 LSB DNL=1 LSB Ideal transfer curve 5 Actual transfer function with one missing code. Example: Input value VDcorrresponds to digital output code D 0.5 LSB Ideal spacing between two adjacent codes VLSBIDEAL=1 LSB 4 3 2 1 Ideal 50% Transition Point Ideal Code Center 0 Analog Input Figure 4.28. Differential Non-Linearity (DNL) silabs.com | Building a more connected world. Rev. 2.10 | 66 EFM32G Data Sheet Electrical Characteristics 4.10.1 Typical Performance 1.25V Reference 2.5V Reference 2XVDDVSS Reference 5VDIFF Reference VDD Reference Figure 4.29. ADC Frequency Spectrum, VDD = 3V, Temp = 25C silabs.com | Building a more connected world. Rev. 2.10 | 67 EFM32G Data Sheet Electrical Characteristics 1.25V Reference 2.5V Reference 2XVDDVSS Reference 5VDIFF Reference VDD Reference Figure 4.30. ADC Integral Linearity Error vs Code, VDD = 3V, Temp = 25C silabs.com | Building a more connected world. Rev. 2.10 | 68 EFM32G Data Sheet Electrical Characteristics 1.25V Reference 2.5V Reference 2XVDDVSS Reference 5VDIFF Reference VDD Reference Figure 4.31. ADC Differential Linearity Error vs Code, VDD = 3V, Temp = 25C silabs.com | Building a more connected world. Rev. 2.10 | 69 EFM32G Data Sheet Electrical Characteristics Offset vs Supply Voltage, Temp = 25C 5 2.0 Vref=1V25 Vref=2V5 Vref=2XVDDVSS Vref=5VDIFF Vref=VDD 4 3 VRef=1V25 VRef=2V5 VRef=2XVDDVSS VRef=5VDIFF VRef=VDD 1.5 1.0 Actual Offset [LSB] 2 Actual Offset [LSB] Offset vs Temperature, VDD = 3V 1 0 -1 0.5 0.0 -2 -0.5 -3 -4 2.0 2.2 2.4 2.6 2.8 3.0 Vdd (V) 3.2 3.4 3.6 -1.0 -40 3.8 -15 5 25 Temp (C) 45 65 85 Figure 4.32. ADC Absolute Offset, Common Mode = VDD/2 Signal to Noise Ratio (SNR) 71 79.4 Spurious-Free Dynamic Range (SFDR) 2XVDDVSS 70 1V25 79.2 Vdd 69 79.0 67 5VDIFF 2V5 66 SFDR [dB] SNR [dB] 68 Vdd 2V5 78.8 78.6 2XVDDVSS 78.4 65 78.2 64 63 -40 -15 5 25 Temperature [C] 45 65 1V25 85 5VDIFF 78.0 -40 -15 5 25 Temperature [C] 45 65 85 Figure 4.33. ADC Dynamic Performance vs Temperature for all ADC References, VDD = 3V silabs.com | Building a more connected world. Rev. 2.10 | 70 EFM32G Data Sheet Electrical Characteristics 4.11 Digital Analog Converter (DAC) Table 4.15. DAC Parameter Symbol Output voltage range VDACOUT Output common mode voltage range VDACCM Average active current Sample rate DAC clock frequency IDAC Test Condition Min Typ Max Unit 0 -- VDD V -VDD -- VDD V 0 -- VDD V 500 kSamples/s, 12 bit, internal 1.25 V reference, Continuous Mode -- 4001 6501 A 100 kSamples/s, 12 bit, internal 1.25 V reference, Sample/Hold Mode -- 2001 2501 A 1 kSamples/s 12 bit, internal 1.25 V reference, Sample/Off Mode -- 171 251 A -- -- 500 ksamples/s Continuous Mode -- -- 1000 kHz Sample/Hold Mode -- -- 250 kHz Sample/Off Mode -- -- 250 kHz VDD voltage reference, singleended VDD voltage reference, differential SRDAC fDAC Clock cycles per conversion CYCDACCONV -- 2 -- cycles Conversion time tDACCONV 2 -- -- s Settling time tDACSETTLE -- 5 -- s 500 kSamples/s, 12 bit, singleended, internal 1.25 V reference -- 58 -- dB 500 kSamples/s, 12 bit, singleended, internal 2.5 V reference -- 59 -- dB 500 kSamples/s, 12 bit, differential, internal 1.25 V reference -- 58 -- dB 500 kSamples/s, 12 bit, differential, internal 2.5 V reference -- 58 -- dB 500 kSamples/s, 12 bit, differential, VDD reference -- 59 -- dB Signal-to-Noise Ratio (SNR) SNRDAC silabs.com | Building a more connected world. Rev. 2.10 | 71 EFM32G Data Sheet Electrical Characteristics Parameter Signal-to-Noise plus Distortion Ratio (SNDR) Spurious-Free Dynamic Range (SFDR) Symbol SNDRDAC SFDRDAC Test Condition Min Typ Max Unit 500 kSamples/s, 12 bit, singleended, internal 1.25 V reference -- 57 -- dB 500 kSamples/s, 12 bit, singleended, internal 2.5 V reference -- 54 -- dB 500 kSamples/s, 12 bit, differential, internal 1.25 V reference -- 56 -- dB 500 kSamples/s, 12 bit, differential, internal 2.5 V reference -- 53 -- dB 500 kSamples/s, 12 bit, differential, VDD reference -- 55 -- dB 500 kSamples/s, 12 bit, singleended, internal 1.25V reference -- 62 -- dBc 500 kSamples/s, 12 bit, singleended, internal 2.5 V reference -- 56 -- dBc 500 kSamples/s, 12 bit, differential, internal 1.25 V reference -- 61 -- dBc 500 kSamples/s, 12 bit, differential, internal 2.5 V reference -- 55 -- dBc 500 kSamples/s, 12 bit, differential, VDD reference -- 60 -- dBc After calibration, single-ended -- 2 -- mV After calibration, differential -- 2 -- mV Offset voltage VDACOFFSET Sample-hold mode voltage drift VDACSHMDRIFT -- 540 -- V/ms Differential non-linearity DNLDAC -- 1 -- LSB Integral non-linearity INLDAC -- 5 -- LSB No missing codes MCDAC -- 12 -- bits Load current ILOAD_DC -- -- 11 mA VREF voltage VREF 1.25 V reference 1.2 1.25 1.3 V 2.5 V reference 2.4 2.5 2.6 V 1.25 V reference -12.4 2.9 18.2 mV/V 2.5 V reference, VDD > 2.5 V -24.6 5.7 35.2 mV/V 1.25 V reference -132 272 677 V/C 2.5 V reference -231 545 1271 V/C 1.25 V reference -- 67 114 A 2.5 V reference -- 55 82 A 1.25 V reference -- 99.85 -- % 2.5 V reference -- 100.01 -- % VREF voltage drift VREF temperature drift VREF current consumption ADC and DAC VREF matching VREF_VDRIFT VREF_TDRIFT IVREF VREF_MATCH Note: 1. Measured with a static input code and no loading on the output. Includes required contribution from the voltage reference. silabs.com | Building a more connected world. Rev. 2.10 | 72 EFM32G Data Sheet Electrical Characteristics 4.12 Analog Comparator (ACMP) Table 4.16. ACMP Parameter Symbol Input voltage range ACMP Common Mode voltage range Active current Current consumption of internal voltage reference Min Typ Max Unit VACMPIN 0 -- VDD V VACMPCM 0 -- VDD V BIASPROG=0b0000, FULLBIAS=0 and HALFBIAS=1 in ACMPn_CTRL register -- 55 600 A BIASPROG=0b1111, FULLBIAS=0 and HALFBIAS=0 in ACMPn_CTRL register -- 2.82 12 A BIASPROG=0b1111, FULLBIAS=1 and HALFBIAS=0 in ACMPn_CTRL register -- 250 520 A Internal voltage reference off. Using external voltage reference -- 0 0.5 A Internal voltage reference, LPREF=1 -- 0.050 3 A Internal voltage reference, LPREF=0 -- 6 -- A IACMP IACMPREF Test Condition Offset voltage VACMPOFFSET BIASPROG= 0b1010, FULLBIAS=0 and HALFBIAS=0 in ACMPn_CTRL register -12 0 12 mV ACMP hysteresis VACMPHYST Programmable -- 17 -- mV CSRESSEL=0b00 in ACMPn_INPUTSEL -- 39 -- k CSRESSEL=0b01 in ACMPn_INPUTSEL -- 71 -- k CSRESSEL=0b10 in ACMPn_INPUTSEL -- 104 -- k CSRESSEL=0b11 in ACMPn_INPUTSEL -- 136 -- k -- -- 10 s Capacitive Sense Internal Resistance Startup time RCSRES tACMPSTART The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given in the following equation. IACMPREF is zero if an external voltage reference is used. I ACMPTOTAL = I ACMP + I ACMPREF silabs.com | Building a more connected world. Rev. 2.10 | 73 EFM32G Data Sheet Electrical Characteristics Current Consumption, HYSTSEL = 4 2.5 Response Time 4.5 HYSTSEL=0.0 HYSTSEL=2.0 HYSTSEL=4.0 HYSTSEL=6.0 4.0 3.5 Response Time [us] Current [uA] 2.0 1.5 1.0 3.0 2.5 2.0 1.5 1.0 0.5 0.5 0.0 4 8 ACMP_CTRL_BIASPROG 0 12 0.0 0 2 4 6 8 10 ACMP_CTRL_BIASPROG 12 14 Hysteresis 100 BIASPROG=0.0 BIASPROG=4.0 BIASPROG=8.0 BIASPROG=12.0 Hysteresis [mV] 80 60 40 20 0 0 1 2 4 3 ACMP_CTRL_HYSTSEL 5 6 7 Figure 4.34. ACMP Characteristics, VDD = 3V, Temp = 25C, FULLBIAS = 0, HALFBIAS = 1 silabs.com | Building a more connected world. Rev. 2.10 | 74 EFM32G Data Sheet Electrical Characteristics 4.13 Voltage Comparator (VCMP) Table 4.17. VCMP Parameter Symbol Input voltage range Test Condition Min Typ Max Unit VVCMPIN -- VDD -- V VCMP Common Mode voltage range VVCMPCM -- VDD -- V Active current IVCMP BIASPROG=0b0000 and HALFBIAS=1 in VCMPn_CTRL register -- 0.3 1 A BIASPROG=0b1111 and HALFBIAS=0 in VCMPn_CTRL register. LPREF=0. -- 22 30 A Startup time reference generator tVCMPREF NORMAL -- 10 -- s Offset voltage VVCMPOFFSET Single-ended -- 10 -- mV Differential -- 10 -- mV VCMP hysteresis VVCMPHYST -- 40 -- mV Startup time tVCMPSTART -- -- 10 s The VDD Trigger Level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in accordance with the following equation: V DD Trigger Level = 1.667V + 0.034 x TRIGLEVEL silabs.com | Building a more connected world. Rev. 2.10 | 75 EFM32G Data Sheet Electrical Characteristics 4.14 LCD Table 4.18. LCD Parameter Symbol Frame rate Min Typ Max Unit fLCDFR 30 -- 200 Hz Number of segments supported NUMSEG -- 4x40 -- seg LCD supply voltage range VLCD Internal boost circuit enabled 2.0 -- 3.8 V Display disconnected, static mode, framerate 32 Hz, all segments on. -- 250 -- nA Display disconnected, quadruplex mode, framerate 32 Hz, all segments on, bias mode to ONETHIRD in LCD_DISPCTRL register. -- 550 -- nA Internal voltage boost off -- 0 -- A -- 8.4 -- A VBLEV of LCD_DISPCTRL register to LEVEL0 -- 3.0 -- V VBLEV of LCD_DISPCTRL register to LEVEL1 -- 3.08 -- V VBLEV of LCD_DISPCTRL register to LEVEL2 -- 3.17 -- V VBLEV of LCD_DISPCTRL register to LEVEL3 -- 3.26 -- V VBLEV of LCD_DISPCTRL register to LEVEL4 -- 3.34 -- V VBLEV of LCD_DISPCTRL register to LEVEL5 -- 3.43 -- V VBLEV of LCD_DISPCTRL register to LEVEL6 -- 3.52 -- V VBLEV of LCD_DISPCTRL register to LEVEL7 -- 3.6 -- V Steady state current consumption. Steady state Current contribution of internal boost. Boost Voltage ILCD Test Condition ILCDBOOST Internal voltage boost on, boosting from 2.2 V to 3.0 V. VBOOST The total LCD current is given by the following equation. ILCDBOOST is zero if internal boost is off. I LCDTOTAL = I LCD + I LCDBOOST silabs.com | Building a more connected world. Rev. 2.10 | 76 EFM32G Data Sheet Electrical Characteristics 4.15 I2C Table 4.19. I2C Standard-mode (Sm) Parameter Symbol Min Typ Max Unit SCL clock frequency fSCL 0 -- 1001 kHz SCL clock low time tLOW 4.7 -- -- s SCL clock high time tHIGH 4.0 -- -- s SDA set-up time tSU,DAT 250 -- -- ns SDA hold time tHD,DAT 8 -- 34502,3 ns Repeated START condition set-up time tSU,STA 4.7 -- -- s (Repeated) START condition hold time tHD,STA 4.0 -- -- s STOP condition set-up time tSU,STO 4.0 -- -- s Bus free time between a STOP and a START condition tBUF 4.7 -- -- s Note: 1. For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32G Reference Manual. 2. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW). 3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 4). Table 4.20. I2C Fast-mode (Fm) Parameter Symbol Min Typ Max Unit SCL clock frequency fSCL 0 -- 4001 kHz SCL clock low time tLOW 1.3 -- -- s SCL clock high time tHIGH 0.6 -- -- s SDA set-up time tSU,DAT 100 -- -- ns SDA hold time tHD,DAT 8 -- 9002,3 ns Repeated START condition set-up time tSU,STA 0.6 -- -- s (Repeated) START condition hold time tHD,STA 0.6 -- -- s STOP condition set-up time tSU,STO 0.6 -- -- s Bus free time between a STOP and a START condition tBUF 1.3 -- -- s Note: 1. For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32G Reference Manual. 2. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW). 3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 4). silabs.com | Building a more connected world. Rev. 2.10 | 77 EFM32G Data Sheet Electrical Characteristics Table 4.21. I2C Fast-mode Plus (Fm+) Parameter Symbol Min Typ Max Unit SCL clock frequency fSCL 0 -- 10001 kHz SCL clock low time tLOW 0.5 -- -- s SCL clock high time tHIGH 0.26 -- -- s SDA set-up time tSU,DAT 50 -- -- ns SDA hold time tHD,DAT 8 -- -- ns Repeated START condition set-up time tSU,STA 0.26 -- -- s (Repeated) START condition hold time tHD,STA 0.26 -- -- s STOP condition set-up time tSU,STO 0.26 -- -- s Bus free time between a STOP and a START condition tBUF 0.5 -- -- s Note: 1. For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32G Reference Manual. 4.16 Digital Peripherals Table 4.22. Digital Peripherals Parameter Symbol Test Condition Min Typ Max Unit USART current IUSART USART idle current, clock enabled -- 7.5 -- A/MHz UART current IUART UART idle current, clock enabled -- 5.63 -- A/MHz LEUART current ILEUART LEUART idle current, clock enabled -- 150 -- nA I2C current II2C I2C idle current, clock enabled -- 6.25 -- A/MHz TIMER current ITIMER TIMER_0 idle current, clock enabled -- 8.75 -- A/MHz LETIMER current ILETIMER LETIMER idle current, clock enabled -- 150 -- nA PCNT current IPCNT PCNT idle current, clock enabled -- 100 -- nA RTC current IRTC RTC idle current, clock enabled -- 100 -- nA LCD current ILCD LCD idle current, clock enabled -- 100 -- nA AES current IAES AES idle current, clock enabled -- 2.5 -- A/MHz GPIO current IGPIO GPIO idle current, clock enabled -- 5.31 -- A/MHz EBI current IEBI EBI idle current, clock enabled -- 1.56 -- A/MHz PRS current IPRS PRS idle current -- 2.81 -- A/MHz DMA current IDMA Clock enable -- 8.12 -- A/MHz Note: Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" forguidelines on designing Printed Circuit Boards (PCB's) for the EFM32G. silabs.com | Building a more connected world. Rev. 2.10 | 78 EFM32G Data Sheet Pin Definitions 5. Pin Definitions Note: Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for guidelines on designing Printed Circuit Boards (PCBs) for the EFM32G. 5.1 EFM32G200 & EFM32G210 (QFN32) 5.1.1 Pinout The EFM32G200 and EFM32G210 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.1. EFM32G200 & EFM32G210 Pinout (top view, not to scale) silabs.com | Building a more connected world. Rev. 2.10 | 79 EFM32G Data Sheet Pin Definitions Table 5.1. Device Pinout QFN32 Pin# and Name Pin # Pin Name 0 VSS 1 Pin Alternate Functionality / Description Analog Timers Communication Other PA0 TIM0_CC0 #0/1 I2C0_SDA #0 2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 3 PA2 TIM0_CC2 #0/1 4 IOVDD_1 5 PC0 ACMP0_CH0 PCNT0_S0IN #2 US1_TX #0 6 PC1 ACMP0_CH1 PCNT0_S1IN #2 US1_RX #0 7 PB7 LFXTAL_P US1_CLK #0 8 PB8 LFXTAL_N US1_CS #0 9 RESETn 10 PB11 11 AVDD_2 12 PB13 HFXTAL_P LEU0_TX #1 13 PB14 HFXTAL_N LEU0_RX #1 14 IOVDD_3 Digital IO power supply 3. 15 AVDD_0 Analog power supply 0. 16 PD4 ADC0_CH4 LEU0_TX #0 17 PD5 ADC0_CH5 LEU0_RX #0 18 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1 19 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1 20 VDD_DREG Power supply for on-chip voltage regulator. 21 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 22 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 TIM1_CC0 #0 PCNT0_S0IN #0 23 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 24 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 TIM1_CC2 #0 DBG_SWO #1 25 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1 26 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1 27 PF2 28 IOVDD_5 29 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX 30 PE11 TIM1_CC1 #1 US0_RX #0 BOOT_RX Ground. CMU_CLK1 #0 CMU_CLK0 #0 Digital IO power supply 1. Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. DAC0_OUT0 LETIM0_OUT0 #1 Analog power supply 2. ACMP1_O #0 DBG_SWO #0 Digital IO power supply 5. silabs.com | Building a more connected world. Rev. 2.10 | 80 EFM32G Data Sheet Pin Definitions QFN32 Pin# and Name Pin # Pin Name 31 PE12 32 PE13 Pin Alternate Functionality / Description Analog silabs.com | Building a more connected world. Timers Communication TIM1_CC2 #1 US0_CLK #0 US0_CS #0 Other ACMP0_O #0 Rev. 2.10 | 81 EFM32G Data Sheet Pin Definitions 5.1.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.2. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 3 Description ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_O PE13 Analog comparator ACMP0, digital output. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 Analog comparator ACMP1, digital output. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. CMU_CLK0 PA2 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 Clock Management Unit, clock output number 1. DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 I2C0 Serial Data input / output. LETIM0_OUT0 PD6 PB11 silabs.com | Building a more connected world. Note that this function is not enabled after reset, and must be enabled by software to be used. PF0 Low Energy Timer LETIM0, output channel 0. Rev. 2.10 | 82 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 PF1 Description LETIM0_OUT1 PD7 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 LEUART0 Receive input. LEU0_TX PD4 PB13 LEUART0 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PCNT0_S0IN PC13 PC0 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PC1 Pulse Counter PCNT0 input number 1. TIM0_CC0 PA0 PA0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PC13 PC13 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PC14 PC14 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PC15 PC15 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2. US0_CLK PE12 USART0 clock input / output. US0_CS PE13 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 US1_CLK PB7 USART1 clock input / output. US1_CS PB8 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX US1_TX PC1 PC0 silabs.com | Building a more connected world. USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. USART1 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.10 | 83 EFM32G Data Sheet Pin Definitions 5.1.3 GPIO Pinout Overview The specific GPIO pins available in EFM32G200 and EFM32G210 is shown in the following table. Each GPIO port is organized as 16bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.3. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Port A -- -- -- -- -- -- -- -- -- -- -- -- -- PA2 PA1 PA0 Port B -- PB14 PB13 -- PB11 -- -- PB8 PB7 -- -- -- -- -- -- -- PC15 PC14 PC13 -- -- -- -- -- -- -- -- -- -- -- PC1 PC0 -- -- -- -- -- PD7 PD6 PD5 PD4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PF2 PF1 PF0 Port C Port D -- -- Port E -- -- Port F -- -- -- PE13 PE12 PE11 PE10 -- -- silabs.com | Building a more connected world. -- -- Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Rev. 2.10 | 84 EFM32G Data Sheet Pin Definitions 5.2 EFM32G222 (TQFP48) 5.2.1 Pinout The EFM32G222 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.2. EFM32G222 Pinout (top view, not to scale) Table 5.4. Device Pinout TQFP48 Pin# and Name Pin # Pin Name 1 Pin Alternate Functionality / Description Analog Timers Communication PA0 TIM0_CC0 #0/1 I2C0_SDA #0 2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 3 PA2 TIM0_CC2 #0/1 4 IOVDD_0 5 VSS Other CMU_CLK1 #0 CMU_CLK0 #0 Digital IO power supply 0. Ground. silabs.com | Building a more connected world. Rev. 2.10 | 85 EFM32G Data Sheet Pin Definitions TQFP48 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 6 PC0 ACMP0_CH0 PCNT0_S0IN #2 US1_TX #0 7 PC1 ACMP0_CH1 PCNT0_S1IN #2 US1_RX #0 8 PC2 ACMP0_CH2 9 PC3 ACMP0_CH3 10 PC4 ACMP0_CH4 11 PB7 LFXTAL_P US1_CLK #0 12 PB8 LFXTAL_N US1_CS #0 13 PA8 TIM2_CC0 #0 14 PA9 TIM2_CC1 #0 15 PA10 TIM2_CC2 #0 16 RESETn 17 PB11 DAC0_OUT0 18 VSS Ground. 19 AVDD_1 20 PB13 HFXTAL_P LEU0_TX #1 21 PB14 HFXTAL_N LEU0_RX #1 22 IOVDD_3 Digital IO power supply 3. 23 AVDD_0 Analog power supply 0. 24 PD4 ADC0_CH4 LEU0_TX #0 25 PD5 ADC0_CH5 LEU0_RX #0 26 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1 27 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1 28 VDD_DREG Power supply for on-chip voltage regulator. 29 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 30 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2 31 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2 32 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 33 PC11 ACMP1_CH3 34 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 TIM1_CC0 #0 PCNT0_S0IN #0 35 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 36 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 TIM1_CC2 #0 DBG_SWO #1 37 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1 LETIM0_OUT0 #3 PCNT1_S0IN #0 Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. LETIM0_OUT0 #1 Analog power supply 1. silabs.com | Building a more connected world. US0_TX #2 Rev. 2.10 | 86 EFM32G Data Sheet Pin Definitions TQFP48 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication 38 PF1 39 PF2 40 PF3 TIM0_CDTI0 #2 41 PF4 TIM0_CDTI1 #2 42 PF5 TIM0_CDTI2 #2 43 IOVDD_5 44 VSS 45 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX 46 PE11 TIM1_CC1 #1 US0_RX #0 BOOT_RX 47 PE12 TIM1_CC2 #1 US0_CLK #0 48 PE13 LETIM0_OUT1 #2 Other DBG_SWDIO #0/1 ACMP1_O #0 DBG_SWO #0 Digital IO power supply 5. Ground. silabs.com | Building a more connected world. US0_CS #0 ACMP0_O #0 Rev. 2.10 | 87 EFM32G Data Sheet Pin Definitions 5.2.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.5. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 3 Description ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_O PE13 Analog comparator ACMP0, digital output. ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 Analog comparator ACMP1, digital output. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. CMU_CLK0 PA2 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 Clock Management Unit, clock output number 1. DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0. DBG_SWCLK PF0 PF0 DBG_SWDIO PF1 PF1 Debug-interface Serial Wire clock input. Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. silabs.com | Building a more connected world. Note that this function is enabled to pin out of reset, and has a built-in pull up. Rev. 2.10 | 88 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 I2C0 Serial Data input / output. LETIM0_OUT0 PD6 PB11 LETIM0_OUT1 PD7 LEU0_RX PD5 PB14 LEUART0 Receive input. LEU0_TX PD4 PB13 LEUART0 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PCNT0_S0IN PC13 PC0 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PC1 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 TIM0_CC0 PA0 PA0 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 Timer 0 Capture Compare input / output channel 2. Note that this function is not enabled after reset, and must be enabled by software to be used. PF0 PC4 PF1 Low Energy Timer LETIM0, output channel 0. Low Energy Timer LETIM0, output channel 1. Pulse Counter PCNT1 input number 0. TIM0_CDTI0 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2. US0_CLK PE12 PC9 USART0 clock input / output. US0_CS PE13 PC8 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 silabs.com | Building a more connected world. PC10 USART0 Synchronous mode Master Input / Slave Output (MISO). Rev. 2.10 | 89 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PC11 US1_CLK PB7 USART1 clock input / output. US1_CS PB8 USART1 chip select input / output. US1_RX PC1 USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_TX USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. PC0 USART1 Synchronous mode Master Output / Slave Input (MOSI). 5.2.3 GPIO Pinout Overview The specific GPIO pins available in EFM32G222 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.6. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Port A -- -- -- -- -- PA10 PA9 PA8 -- -- -- -- -- PA2 PA1 PA0 Port B -- PB14 PB13 -- PB11 -- -- PB8 PB7 -- -- -- -- -- -- -- PC15 PC14 PC13 -- PC11 PC10 PC9 PC8 -- -- -- PC4 PC3 PC2 PC1 PC0 -- -- PD7 PD6 PD5 PD4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0 Port C Port D -- -- Port E -- -- Port F -- -- -- -- -- -- PE13 PE12 PE11 PE10 -- -- silabs.com | Building a more connected world. -- -- Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Rev. 2.10 | 90 EFM32G Data Sheet Pin Definitions 5.3 EFM32G230 (QFN64) 5.3.1 Pinout The EFM32G230 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.3. EFM32G230 Pinout (top view, not to scale) Table 5.7. Device Pinout QFN64 Pin# and Name Pin # Pin Name 0 VSS 1 Pin Alternate Functionality / Description Analog Timers Communication PA0 TIM0_CC0 #0/1 I2C0_SDA #0 2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 3 PA2 TIM0_CC2 #0/1 4 PA3 TIM0_CDTI0 #0 5 PA4 TIM0_CDTI1 #0 Other Ground. silabs.com | Building a more connected world. CMU_CLK1 #0 CMU_CLK0 #0 Rev. 2.10 | 91 EFM32G Data Sheet Pin Definitions QFN64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication 6 PA5 TIM0_CDTI2 #0 LEU1_TX #1 6 PA6 8 IOVDD_0 9 PC0 PCNT0_S0IN #1 US1_TX #0 10 PC1 PCNT0_S1IN #1 US1_RX #0 11 PC2 US2_CLK #0 12 PC3 US2_CS #0 13 PC4 ACMP0_CH4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 14 PC5 ACMP0_CH5 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 15 PB7 LFXTAL_P US1_CLK #0 16 PB8 LFXTAL_N US1_CS #0 17 PA8 TIM2_CC0 #0 18 PA9 TIM2_CC1 #0 19 PA10 TIM2_CC2 #0 20 RESETn 21 PB11 DAC0_OUT0 LETIM0_OUT0 #1 22 PB12 DAC0_OUT1 LETIM0_OUT1 #1 23 AVDD_1 24 PB13 HFXTAL_P LEU0_TX #1 25 PB14 HFXTAL_N LEU0_RX #1 26 IOVDD_3 Digital IO power supply 3. 27 AVDD_0 Analog power supply 0. 28 PD0 ADC0_CH0 PCNT2_S0IN #0 US1_TX #1 29 PD1 ADC0_CH1 TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 31 PD3 ADC0_CH3 TIM0_CC2 #3 US1_CS #1 32 PD4 ADC0_CH4 LEU0_TX #0 33 PD5 ADC0_CH5 LEU0_RX #0 34 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1 35 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1 36 PD8 37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL #2 39 VDD_DREG Other LEU1_RX #1 Digital IO power supply 0. Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. Analog power supply 1. CMU_CLK1 #1 Power supply for on-chip voltage regulator. silabs.com | Building a more connected world. Rev. 2.10 | 92 EFM32G Data Sheet Pin Definitions QFN64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 40 DECOUPLE 41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2 42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2 43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 44 PC11 ACMP1_CH3 45 PC12 ACMP1_CH4 46 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 TIM1_CC0 #0 PCNT0_S0IN #0 47 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 48 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 TIM1_CC2 #0 DBG_SWO #1 49 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1 50 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1 51 PF2 52 PF3 TIM0_CDTI0 #2 53 PF4 TIM0_CDTI1 #2 54 PF5 TIM0_CDTI2 #2 55 IOVDD_5 56 PE8 PCNT2_S0IN #1 57 PE9 PCNT2_S1IN #1 58 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX 59 PE11 TIM1_CC1 #1 US0_RX #0 BOOT_RX 60 PE12 TIM1_CC2 #1 US0_CLK #0 61 PE13 US0_CS #0 62 PE14 LEU0_TX #2 63 PE15 LEU0_RX #2 64 PA15 Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. US0_TX #2 CMU_CLK0 #1 ACMP1_O #0 DBG_SWO #0 Digital IO power supply 5. silabs.com | Building a more connected world. ACMP0_O #0 Rev. 2.10 | 93 EFM32G Data Sheet Pin Definitions 5.3.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.8. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 3 Description ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 Analog comparator ACMP0, digital output. ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP2, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP3, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP4, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 Analog comparator ACMP1, digital output. ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1. silabs.com | Building a more connected world. Rev. 2.10 | 94 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0. DAC0_OUT1 PB12 Digital to Analog Converter DAC0 output channel number 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PCNT0_S0IN PC13 PC0 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PC1 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. TIM0_CC0 PA0 PA0 PD1 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PD2 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PD3 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2. silabs.com | Building a more connected world. Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.10 | 95 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2. US0_CLK PE12 PC9 USART0 clock input / output. US0_CS PE13 PC8 USART0 chip select input / output. US0_RX PE11 PC10 USART0 Asynchronous Receive. PC11 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 US1_CLK PB7 PD2 USART1 clock input / output. US1_CS PB8 PD3 USART1 chip select input / output. US1_RX PC1 PD1 USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. PD0 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 US2_CLK PC4 USART2 clock input / output. US2_CS PC5 USART2 chip select input / output. US2_RX PC3 USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_TX PC2 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.10 | 96 EFM32G Data Sheet Pin Definitions 5.3.3 GPIO Pinout Overview The specific GPIO pins available in EFM32G230 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.9. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Port A PA15 -- -- -- -- PA10 PA8 PA8 -- -- PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B -- -- -- PB8 PB7 -- -- -- -- -- -- -- PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 -- -- -- -- -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0 Port C Port D Port E Port F PB14 PB13 PB12 PB11 PC15 PC14 PC13 PC12 PC11 PC10 -- -- -- -- -- -- PE15 PE14 PE13 PE12 PE11 PE10 -- -- -- -- silabs.com | Building a more connected world. -- -- Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Rev. 2.10 | 97 EFM32G Data Sheet Pin Definitions 5.4 EFM32G232 (TQFP64) 5.4.1 Pinout The EFM32G232 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.4. EFM32G232 Pinout (top view, not to scale) Table 5.10. Device Pinout TQFP64 Pin# and Name Pin # Pin Name 1 Pin Alternate Functionality / Description Analog Timers Communication PA0 TIM0_CC0 #0/1 I2C0_SDA #0 2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 3 PA2 TIM0_CC2 #0/1 4 PA3 TIM0_CDTI0 #0 5 PA4 TIM0_CDTI1 #0 silabs.com | Building a more connected world. Other CMU_CLK1 #0 CMU_CLK0 #0 Rev. 2.10 | 98 EFM32G Data Sheet Pin Definitions TQFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication 6 PA5 TIM0_CDTI2 #0 LEU1_TX #1 7 IOVDD_0 8 VSS Ground. 9 PC0 ACMP0_CH0 PCNT0_S0IN #1 US1_TX #1 10 PC1 ACMP0_CH1 PCNT0_S1IN #1 US1_RX #1 11 PC2 ACMP0_CH2 US1_CLK #1 12 PC3 ACMP0_CH3 US1_CS #1 13 PC4 ACMP0_CH4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 14 PC5 ACMP0_CH5 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 15 PB7 LFXTAL_P US1_CLK #0 16 PB8 LFXTAL_N US1_CS #0 17 PA8 TIM2_CC0 #0 18 PA9 TIM2_CC1 #0 19 PA10 TIM2_CC2 #0 20 RESETn 21 PB11 DAC0_OUT0 22 VSS Ground. 23 AVDD_1 24 PB13 HFXTAL_P LEU0_TX #1 25 PB14 HFXTAL_N LEU0_RX #1 26 IOVDD_3 Digital IO power supply 3. 27 AVDD_0 Analog power supply 0. 28 PD0 ADC0_CH0 PCNT2_S0IN #0 US1_TX #1 29 PD1 ADC0_CH1 TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 31 PD3 ADC0_CH3 TIM0_CC2 #3 US1_CS #1 32 PD4 ADC0_CH4 LEU0_TX #0 33 PD5 ADC0_CH5 LEU0_RX #0 34 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1 35 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1 36 PD8 37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2 38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL #2 Other Digital IO power supply 0. Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. LETIM0_OUT0 #1 Analog power supply 1. CMU_CLK1 #1 silabs.com | Building a more connected world. Rev. 2.10 | 99 EFM32G Data Sheet Pin Definitions TQFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 39 VDD_DREG Power supply for on-chip voltage regulator. 40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2 42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2 43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 44 PC11 ACMP1_CH3 45 PC12 ACMP1_CH4 46 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 TIM1_CC0 #0 PCNT0_S0IN #0 47 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 48 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 TIM1_CC2 #0 DBG_SWO #1 49 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1 50 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1 51 PF2 52 PF3 TIM0_CDTI0 #2 53 PF4 TIM0_CDTI1 #2 54 PF5 TIM0_CDTI2 #2 55 IOVDD_5 56 VSS 57 PE8 PCNT2_S0IN #1 58 PE9 PCNT2_S1IN #1 59 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX 60 PE11 TIM1_CC1 #1 US0_RX #0 BOOT_RX 61 PE12 TIM1_CC2 #1 US0_CLK #0 62 PE13 US0_CS #0 63 PE14 LEU0_TX #2 64 PE15 LEU0_RX #2 US0_TX #2 CMU_CLK0 #1 ACMP1_O #0 DBG_SWO #0 Digital IO power supply 5. Ground. silabs.com | Building a more connected world. ACMP0_O #0 Rev. 2.10 | 100 EFM32G Data Sheet Pin Definitions 5.4.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.11. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 3 Description ACMP0_CH4 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH5 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH6 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH7 PC3 Analog comparator ACMP0, channel 3. ACMP0_O PE13 Analog comparator ACMP0, digital output. ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_O PF2 Analog comparator ACMP1, digital output. ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1. DAC0_OUT0 PB11 DBG_SWCLK PF0 PF0 DBG_SWDIO PF1 PF1 Digital to Analog Converter DAC0 output channel number 0. Debug-interface Serial Wire clock input. Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. silabs.com | Building a more connected world. Note that this function is enabled to pin out of reset, and has a built-in pull up. Rev. 2.10 | 101 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 LEU1_TX PC6 LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PCNT0_S0IN PC13 PC0 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PC1 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. TIM0_CC0 PA0 PA0 PD1 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PD2 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PD3 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2. US0_CLK PE12 PC9 USART0 clock input / output. Note that this function is not enabled after reset, and must be enabled by software to be used. LEUART1 Receive input. LEUART1 Transmit output. Also used as receive input in half duplex communication. PA5 silabs.com | Building a more connected world. Rev. 2.10 | 102 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 US0_CS 1 PE13 2 3 PC8 Description USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PC10 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PC11 US1_CLK PB7 PD2 USART1 clock input / output. US1_CS PB8 PD3 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 USART2 clock input / output. US2_CS PC5 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX PC3 US2_TX USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. PC2 USART2 Synchronous mode Master Output / Slave Input (MOSI). 5.4.3 GPIO Pinout Overview The specific GPIO pins available in EFM32G2322 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.12. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Port A -- -- -- -- -- PA10 PA9 PA8 -- -- PA5 PA4 PA3 PA2 PA1 PA0 Port B -- -- PB11 -- -- PB8 PB7 -- -- -- -- -- -- -- PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 -- -- -- -- -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0 Port C Port D Port E Port F PB14 PB13 PC15 PC14 PC13 PC12 PC11 PC10 -- -- -- -- -- -- PE15 PE14 PE13 PE12 PE11 PE10 -- -- -- -- silabs.com | Building a more connected world. -- -- Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Rev. 2.10 | 103 EFM32G Data Sheet Pin Definitions 5.5 EFM32G280 (LQFP100) 5.5.1 Pinout The EFM32G280 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.5. EFM32G280 Pinout (top view, not to scale) Table 5.13. Device Pinout LQFP100 Pin# and Name Pin # Pin Name 1 Pin Alternate Functionality / Description Analog EBI Timers Communication PA0 EBI_AD09 #0 TIM0_CC0 #0/1 I2C0_SDA #0 2 PA1 EBI_AD10 #0 TIM0_CC1 #0/1 I2C0_SCL #0 3 PA2 EBI_AD11 #0 TIM0_CC2 #0/1 4 PA3 EBI_AD12 #0 TIM0_CDTI0 #0 U0_TX #2 5 PA4 EBI_AD13 #0 TIM0_CDTI1 #0 U0_RX #2 silabs.com | Building a more connected world. Other CMU_CLK1 #0 CMU_CLK0 #0 Rev. 2.10 | 104 EFM32G Data Sheet Pin Definitions LQFP100 Pin# and Name Pin # Pin Name 6 Pin Alternate Functionality / Description Analog EBI Timers Communication PA5 EBI_AD14 #0 TIM0_CDTI2 #0 LEU1_TX #1 7 PA6 EBI_AD15 #0 8 IOVDD_0 9 PB0 TIM1_CC0 #2 10 PB1 TIM1_CC1 #2 11 PB2 TIM1_CC2 #2 12 PB3 PCNT1_S0IN #1 US2_TX #1 13 PB4 PCNT1_S1IN #1 US2_RX #1 14 PB5 US2_CLK #1 15 PB6 US2_CS #1 16 VSS 17 IOVDD_1 18 PC0 ACMP0_C H0 PCNT0_S0IN #2 US1_TX #0 19 PC1 ACMP0_C H1 PCNT0_S1IN #2 US1_RX #0 20 PC2 ACMP0_C H2 US2_TX #0 21 PC3 ACMP0_C H3 US2_RX #0 22 PC4 ACMP0_C H4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 23 PC5 ACMP0_C H5 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 24 PB7 LFXTAL_P US1_CLK #0 25 PB8 LFXTAL_N US1_CS #0 26 PA7 27 PA8 TIM2_CC0 #0 28 PA9 TIM2_CC1 #0 29 PA10 TIM2_CC2 #0 30 PA11 31 IOVDD_2 32 VSS 33 PA12 TIM2_CC0 #1 34 PA13 TIM2_CC1 #1 35 PA14 TIM2_CC2 #1 36 RESETn Other LEU1_RX #1 Digital IO power supply 0. Ground. Digital IO power supply 1. Digital IO power supply 2. Ground. Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. silabs.com | Building a more connected world. Rev. 2.10 | 105 EFM32G Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name 37 PB9 38 PB10 39 PB11 DAC0_OU T0 LETIM0_OUT0 #1 40 PB12 DAC0_OU T1 LETIM0_OUT1 #1 41 AVDD_1 42 PB13 HFXTAL_ P LEU0_TX #1 43 PB14 HFXTAL_ N LEU0_RX #1 44 IOVDD_3 Digital IO power supply 3. 45 AVDD_0 Analog power supply 0. 46 PD0 ADC0_CH 0 PCNT2_S0IN #0 US1_TX #1 47 PD1 ADC0_CH 1 TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 48 PD2 ADC0_CH 2 TIM0_CC1 #3 US1_CLK #1 49 PD3 ADC0_CH 3 TIM0_CC2 #3 US1_CS #1 50 PD4 ADC0_CH 4 LEU0_TX #0 51 PD5 ADC0_CH 5 LEU0_RX #0 52 PD6 ADC0_CH 6 LETIM0_OUT0 #0 I2C0_SDA #1 53 PD7 ADC0_CH 7 LETIM0_OUT1 #0 I2C0_SCL #1 54 PD8 55 PC6 ACMP0_C H6 LEU1_TX #0 I2C0_SDA #2 56 PC7 ACMP0_C H7 LEU1_RX #0 I2C0_SCL #2 57 Analog EBI Timers Communication Other Analog power supply 1. CMU_CLK1 #1 VDD_DRE Power supply for on-chip voltage regulator. G 58 VSS Ground. 59 DECOUPLE 60 PE0 PCNT0_S0IN #1 U0_TX #1 61 PE1 PCNT0_S1IN #1 U0_RX #1 62 PE2 Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. silabs.com | Building a more connected world. ACMP0_O #1 Rev. 2.10 | 106 EFM32G Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other 63 PE3 64 PE4 US0_CS #1 65 PE5 US0_CLK #1 66 PE6 US0_RX #1 67 PE7 US0_TX #1 68 PC8 ACMP1_C H0 TIM2_CC0 #2 US0_CS #2 69 PC9 ACMP1_C H1 TIM2_CC1 #2 US0_CLK #2 70 PC10 ACMP1_C H2 TIM2_CC2 #2 US0_RX #2 71 PC11 ACMP1_C H3 72 PC12 ACMP1_C H4 73 PC13 ACMP1_C H5 TIM0_CDTI0 #1/3 TIM1_CC0 #0 PCNT0_S0IN #0 74 PC14 ACMP1_C H6 TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 U0_TX #3 75 PC15 ACMP1_C H7 TIM0_CDTI2 #1/3 TIM1_CC2 #0 U0_RX #3 76 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1 77 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1 78 PF2 EBI_ARDY #0 79 PF3 EBI_ALE #0 TIM0_CDTI0 #2 80 PF4 EBI_WEn #0 TIM0_CDTI1 #2 81 PF5 EBI_REn #0 TIM0_CDTI2 #2 82 IOVDD_5 83 VSS 84 PF6 TIM0_CC0 #2 U0_TX #0 85 PF7 TIM0_CC1 #2 U0_RX #0 86 PF8 TIM0_CC2 #2 87 PF9 88 PD9 EBI_CS0 #0 89 PD10 EBI_CS1 #0 90 PD11 EBI_CS2 #0 91 PD12 EBI_CS3 #0 ACMP1_O #1 US0_TX #2 CMU_CLK0 #1 DBG_SWO #1 ACMP1_O #0 DBG_SWO #0 Digital IO power supply 5. Ground. silabs.com | Building a more connected world. Rev. 2.10 | 107 EFM32G Data Sheet Pin Definitions LQFP100 Pin# and Name Pin # Pin Name 92 Pin Alternate Functionality / Description Analog EBI Timers Communication Other PE8 EBI_AD00 #0 PCNT2_S0IN #1 93 PE9 EBI_AD01 #0 PCNT2_S1IN #1 94 PE10 EBI_AD02 #0 TIM1_CC0 #1 US0_TX #0 BOOT_TX 95 PE11 EBI_AD03 #0 TIM1_CC1 #1 US0_RX #0 BOOT_RX 96 PE12 EBI_AD04 #0 TIM1_CC2 #1 US0_CLK #0 97 PE13 EBI_AD05 #0 US0_CS #0 98 PE14 EBI_AD06 #0 LEU0_TX #2 99 PE15 EBI_AD07 #0 LEU0_RX #2 100 PA15 EBI_AD08 #0 silabs.com | Building a more connected world. ACMP0_O #0 Rev. 2.10 | 108 EFM32G Data Sheet Pin Definitions 5.5.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.14. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 3 Description ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1. PE2 PE3 silabs.com | Building a more connected world. Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.10 | 109 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0. DAC0_OUT1 PB12 Digital to Analog Converter DAC0 output channel number 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 EBI_AD00 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 External Bus Interface (EBI) Address Latch Enable output. silabs.com | Building a more connected world. Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.10 | 110 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description EBI_ARDY PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_CS0 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_REn PF5 External Bus Interface (EBI) Read Enable output. EBI_WEn PF4 External Bus Interface (EBI) Write Enable output. HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PCNT0_S0IN PC13 PE0 PC0 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. TIM0_CC0 PA0 PA0 PF6 PD1 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB1 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 Timer 1 Capture Compare input / output channel 2. silabs.com | Building a more connected world. Rev. 2.10 | 111 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 USART0 clock input / output. US0_CS PE13 PE4 PC8 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PC11 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 US1_CLK PB7 PD2 USART1 clock input / output. US1_CS PB8 PD3 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX US2_TX PC3 PC2 PB4 PB3 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.10 | 112 EFM32G Data Sheet Pin Definitions 5.5.3 GPIO Pinout Overview The specific GPIO pins available in EFM32G280 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.15. GPIO Pinout Port Port A Port B Port C Port D Port E Port F Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 PA15 PA14 PA13 PA12 PA11 PA10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 -- -- -- -- -- -- -- -- silabs.com | Building a more connected world. -- -- Rev. 2.10 | 113 EFM32G Data Sheet Pin Definitions 5.6 EFM32G290 (BGA112) 5.6.1 Pinout The EFM32G290 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.6. EFM32G280 Pinout (top view, not to scale) Table 5.16. Device Pinout BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI A1 PE15 EBI_AD07 #0 LEU0_RX #2 A2 PE14 EBI_AD06 #0 LEU0_TX #2 A3 PE12 EBI_AD04 #0 TIM1_CC2 #1 A4 PE9 EBI_AD01 #0 PCNT2_S1IN #1 A5 PD10 EBI_CS1 #0 silabs.com | Building a more connected world. Timers Communication Other US0_CLK #0 Rev. 2.10 | 114 EFM32G Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication TIM0_CC1 #2 U0_RX #0 Other A6 PF7 A7 PF5 EBI_REn #0 TIM0_CDTI2 #2 A8 PF4 EBI_WEn #0 TIM0_CDTI1 #2 A9 PE4 A10 PC14 ACMP1_C H6 TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 U0_TX #3 A11 PC15 ACMP1_C H7 TIM0_CDTI2 #1/3 TIM1_CC2 #0 U0_RX #3 DBG_SWO #1 B1 PA15 EBI_AD08 #0 B2 PE13 EBI_AD05 #0 US0_CS #0 ACMP0_O #0 B3 PE11 EBI_AD03 #0 TIM1_CC1 #1 US0_RX #0 BOOT_RX B4 PE8 EBI_AD00 #0 PCNT2_S0IN #1 B5 PD11 EBI_CS2 #0 B6 PF8 TIM0_CC2 #2 B7 PF6 TIM0_CC0 #2 B8 PF3 B9 PE5 B10 PC12 ACMP1_C H4 B11 PC13 ACMP1_C H5 C1 PA1 EBI_AD10 #0 TIM0_CC1 #0/1 I2C0_SCL #0 C2 PA0 EBI_AD09 #0 TIM0_CC0 #0/1 I2C0_SDA #0 C3 PE10 EBI_AD02 #0 TIM1_CC0 #1 US0_TX #0 C4 PD13 C5 PD12 C6 PF9 C7 VSS C8 PF2 C9 PE6 C10 PC10 ACMP1_C H2 C11 PC11 ACMP1_C H3 D1 PA3 EBI_AD12 #0 TIM0_CDTI0 #0 D2 PA2 EBI_AD11 #0 TIM0_CC2 #0/1 US0_CS #1 EBI_ALE #0 U0_TX #0 TIM0_CDTI0 #2 US0_CLK #1 CMU_CLK0 #1 TIM0_CDTI0 #1/3 TIM1_CC0 #0 PCNT0_S0IN #0 CMU_CLK1 #0 BOOT_TX EBI_CS3 #0 Ground. ACMP1_O #0 DBG_SWO #0 EBI_ARDY #0 US0_RX #1 TIM2_CC2 #2 US0_RX #2 US0_TX #2 silabs.com | Building a more connected world. U0_TX #2 CMU_CLK0 #0 Rev. 2.10 | 115 EFM32G Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication D3 PB15 D4 VSS D5 IOVDD_6 D6 PD9 D7 IOVDD_5 D8 PF1 D9 PE7 D10 PC8 ACMP1_C H0 TIM2_CC0 #2 US0_CS #2 D11 PC9 ACMP1_C H1 TIM2_CC1 #2 US0_CLK #2 E1 PA6 EBI_AD15 #0 E2 PA5 EBI_AD14 #0 TIM0_CDTI2 #0 LEU1_TX #1 E3 PA4 EBI_AD13 #0 TIM0_CDTI1 #0 U0_RX #2 E4 PB0 TIM1_CC0 #2 E8 PF0 LETIM0_OUT0 #2 E9 PE0 PCNT0_S0IN #1 U0_TX #1 E10 PE1 PCNT0_S1IN #1 U0_RX #1 E11 PE3 F1 PB1 TIM1_CC1 #2 F2 PB2 TIM1_CC2 #2 F3 PB3 PCNT1_S0IN #1 US2_TX #1 F4 PB4 PCNT1_S1IN #1 US2_RX #1 Other Ground. Digital IO power supply 6. LCD_SEG 28 EBI_CS0 #0 Digital IO power supply 5. LETIM0_OUT1 #2 DBG_SWDIO #0/1 US0_TX #1 LEU1_RX #1 DBG_SWCLK #0/1 ACMP1_O #1 F8 VDD_DRE Power supply for on-chip voltage regulator. G F9 VSS_DRE Ground for on-chip voltage regulator. G F10 PE2 ACMP0_O #1 F11 DECOUPLE G1 PB5 US2_CLK #1 G2 PB6 US2_CS #1 G3 VSS G4 IOVDD_0 Digital IO power supply 0. G8 IOVDD_4 Digital IO power supply 4. G9 VSS Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. Ground. Ground. silabs.com | Building a more connected world. Rev. 2.10 | 116 EFM32G Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers G10 PC6 ACMP0_C H6 LEU1_TX #0 I2C0_SDA #2 G11 PC7 ACMP0_C H7 LEU1_RX #0 I2C0_SCL #2 H1 PC0 ACMP0_C H0 H2 PC2 ACMP0_C H2 H3 PD14 H4 PA7 H5 PA8 H6 VSS H7 IOVDD_3 H8 PD8 H9 PD5 ADC0_CH 5 H10 PD6 ADC0_CH 6 LETIM0_OUT0 #0 I2C0_SDA #1 H11 PD7 ADC0_CH 7 LETIM0_OUT1 #0 I2C0_SCL #1 J1 PC1 ACMP0_C H1 PCNT0_S1IN #2 US1_RX #0 J2 PC3 ACMP0_C H3 J3 PD15 J4 PA12 TIM2_CC0 #1 J5 PA9 TIM2_CC1 #0 J6 PA10 TIM2_CC2 #0 J7 PB9 J8 PB10 J9 PD2 ADC0_CH 2 TIM0_CC1 #3 US1_CLK #1 J10 PD3 ADC0_CH 3 TIM0_CC2 #3 US1_CS #1 J11 PD4 ADC0_CH 4 LEU0_TX #0 K1 PB7 LFXTAL_P US1_CLK #0 K2 PC4 ACMP0_C H4 K3 PA13 K4 VSS PCNT0_S0IN #2 Communication Other US1_TX #0 US2_TX #0 I2C0_SDA #3 TIM2_CC0 #0 Ground. Digital IO power supply 3. CMU_CLK1 #1 LEU0_RX #0 US2_RX #0 I2C0_SCL #3 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 TIM2_CC1 #1 Ground. silabs.com | Building a more connected world. Rev. 2.10 | 117 EFM32G Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers K5 PA11 K6 RESETn Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. K7 AVSS_1 Analog ground 1. K8 AVDD_2 Analog power supply 2. K9 AVDD_1 Analog power supply 1. K10 AVSS_0 Analog ground 0. K11 PD1 ADC0_CH 1 L1 PB8 LFXTAL_N L2 PC5 ACMP0_C H5 L3 PA14 L4 IOVDD_1 L5 PB11 DAC0_OU T0 LETIM0_OUT0 #1 L6 PB12 DAC0_OU T1 LETIM0_OUT1 #1 L7 AVSS_2 L8 PB13 HFXTAL_ P LEU0_TX #1 L9 PB14 HFXTAL_ N LEU0_RX #1 L10 AVDD_0 L11 PD0 TIM0_CC0 #3 PCNT2_S1IN #0 Communication Other US1_RX #1 US1_CS #0 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 TIM2_CC2 #1 Digital IO power supply 1. Analog ground 2. Analog power supply 0. ADC0_CH 0 silabs.com | Building a more connected world. PCNT2_S0IN #0 US1_TX #1 Rev. 2.10 | 118 EFM32G Data Sheet Pin Definitions 5.6.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.17. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 3 Description ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1. PE2 PE3 silabs.com | Building a more connected world. Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.10 | 119 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0. DAC0_OUT1 PB12 Digital to Analog Converter DAC0 output channel number 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 EBI_AD00 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 External Bus Interface (EBI) Address Latch Enable output. silabs.com | Building a more connected world. Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.10 | 120 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description EBI_ARDY PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_CS0 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_REn PF5 External Bus Interface (EBI) Read Enable output. EBI_WEn PF4 External Bus Interface (EBI) Write Enable output. HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PD15 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PD14 I2C0 Serial Data input / output. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PCNT0_S0IN PC13 PE0 PC0 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. TIM0_CC0 PA0 PA0 PF6 PD1 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB1 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 Timer 1 Capture Compare input / output channel 2. silabs.com | Building a more connected world. Rev. 2.10 | 121 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 USART0 clock input / output. US0_CS PE13 PE4 PC8 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PC11 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 US1_CLK PB7 PD2 USART1 clock input / output. US1_CS PB8 PD3 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX US2_TX PC3 PC2 PB4 PB3 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.10 | 122 EFM32G Data Sheet Pin Definitions 5.6.3 GPIO Pinout Overview The specific GPIO pins available in EFM32G290 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.18. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Port F -- -- -- -- silabs.com | Building a more connected world. -- -- Rev. 2.10 | 123 EFM32G Data Sheet Pin Definitions 5.7 EFM32G840 (QFN64) 5.7.1 Pinout The EFM32G840 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.7. EFM32G840 Pinout (top view, not to scale) Table 5.19. Device Pinout QFN64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication 0 VSS Ground. 1 PA0 LCD_SEG13 TIM0_CC0 #0/1 I2C0_SDA #0 2 PA1 LCD_SEG14 TIM0_CC1 #0/1 I2C0_SCL #0 3 PA2 LCD_SEG15 TIM0_CC2 #0/1 4 PA3 LCD_SEG16 TIM0_CDTI0 #0 5 PA4 LCD_SEG17 TIM0_CDTI1 #0 silabs.com | Building a more connected world. Other CMU_CLK1 #0 CMU_CLK0 #0 Rev. 2.10 | 124 EFM32G Data Sheet Pin Definitions QFN64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication 6 PA5 LCD_SEG18 TIM0_CDTI2 #0 LEU1_TX #1 6 PA6 LCD_SEG19 8 IOVDD_0 9 PB3 LCD_SEG20 PCNT1_S0IN #1 US2_TX #1 10 PB4 LCD_SEG21 PCNT1_S1IN #1 US2_RX #1 11 PB5 LCD_SEG22 US2_CLK #1 12 PB6 LCD_SEG23 US2_CS #1 13 PC4 ACMP0_CH4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 14 PC5 ACMP0_CH5 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 15 PB7 LFXTAL_P US1_CLK #0 16 PB8 LFXTAL_N US1_CS #0 17 PA12 LCD_BCAP_ P TIM2_CC0 #1 18 PA13 LCD_BCAP_ N TIM2_CC1 #1 19 PA14 LCD_BEXT TIM2_CC2 #1 20 RESETn 21 PB11 DAC0_OUT0 LETIM0_OUT0 #1 22 PB12 DAC0_OUT1 LETIM0_OUT1 #1 23 AVDD_1 24 PB13 HFXTAL_P LEU0_TX #1 25 PB14 HFXTAL_N LEU0_RX #1 26 IOVDD_3 Digital IO power supply 3. 27 AVDD_0 Analog power supply 0. 28 PD0 ADC0_CH0 PCNT2_S0IN #0 US1_TX #1 29 PD1 ADC0_CH1 TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 31 PD3 ADC0_CH3 TIM0_CC2 #3 US1_CS #1 32 PD4 ADC0_CH4 LEU0_TX #0 33 PD5 ADC0_CH5 LEU0_RX #0 34 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1 35 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1 36 PD8 37 PC6 Other LEU1_RX #1 Digital IO power supply 0. Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. Analog power supply 1. CMU_CLK1 #1 ACMP0_CH6 silabs.com | Building a more connected world. LEU1_TX #0 I2C0_SDA #2 Rev. 2.10 | 125 EFM32G Data Sheet Pin Definitions QFN64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 38 PC7 ACMP0_CH7 39 VDD_DREG Power supply for on-chip voltage regulator. 40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 41 PE4 LCD_COM0 US0_CS #1 42 PE5 LCD_COM1 US0_CLK #1 43 PE6 LCD_COM2 US0_RX #1 44 PE7 LCD_COM3 US0_TX #1 45 PC12 ACMP1_CH4 46 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 TIM1_CC0 #0 PCNT0_S0IN #0 47 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 48 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 TIM1_CC2 #0 DBG_SWO #1 49 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1 50 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1 51 PF2 LCD_SEG0 52 PF3 LCD_SEG1 TIM0_CDTI0 #2 53 PF4 LCD_SEG2 TIM0_CDTI1 #2 54 PF5 LCD_SEG3 TIM0_CDTI2 #2 55 IOVDD_5 56 PE8 LCD_SEG4 PCNT2_S0IN #1 57 PE9 LCD_SEG5 PCNT2_S1IN #1 58 PE10 LCD_SEG6 TIM1_CC0 #1 US0_TX #0 BOOT_TX 59 PE11 LCD_SEG7 TIM1_CC1 #1 US0_RX #0 BOOT_RX 60 PE12 LCD_SEG8 TIM1_CC2 #1 US0_CLK #0 61 PE13 LCD_SEG9 US0_CS #0 62 PE14 LCD_SEG10 LEU0_TX #2 63 PE15 LCD_SEG11 LEU0_RX #2 64 PA15 LCD_SEG12 LEU1_RX #0 I2C0_SCL #2 CMU_CLK0 #1 ACMP1_O #0 DBG_SWO #0 Digital IO power supply 5. silabs.com | Building a more connected world. ACMP0_O #0 Rev. 2.10 | 126 EFM32G Data Sheet Pin Definitions 5.7.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.20. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 3 Description ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 Analog comparator ACMP0, digital output. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 Analog comparator ACMP1, digital output. ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1. DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0. DAC0_OUT1 PB12 Digital to Analog Converter DAC0 output channel number 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 silabs.com | Building a more connected world. Note that this function is enabled to pin out of reset, and has a built-in pull up. Rev. 2.10 | 127 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output. LCD_BCAP_N PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD_BCAP_P PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. Note that this function is not enabled after reset, and must be enabled by software to be used. LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. silabs.com | Building a more connected world. Rev. 2.10 | 128 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG21 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG22 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG23 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PCNT0_S0IN PC13 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 Pulse Counter PCNT0 input number 1. silabs.com | Building a more connected world. Rev. 2.10 | 129 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. TIM0_CC0 PA0 PA0 PD1 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PD2 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PD3 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA12 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA13 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA14 Timer 2 Capture Compare input / output channel 2. US0_CLK PE12 PE5 USART0 clock input / output. US0_CS PE13 PE4 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 US1_CLK PB7 PD2 USART1 clock input / output. US1_CS PB8 PD3 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PD1 US1_TX PD0 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. USART1 Synchronous mode Master Output / Slave Input (MOSI). US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART2 Asynchronous Receive. US2_RX PB4 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). Rev. 2.10 | 130 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 US2_TX 2 3 Description USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. PB3 USART2 Synchronous mode Master Output / Slave Input (MOSI). 5.7.3 GPIO Pinout Overview The specific GPIO pins available in EFM32G840 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.21. GPIO Pinout Port Port A Port B Port C Port D Port E Port F Pin 15 Pin 14 Pin 13 Pin 12 PA15 PA14 PA13 PA12 -- Pin 10 -- -- -- -- -- PA6 PA5 PA4 PA3 PA2 PA1 PA0 -- -- PB8 PB7 PB6 PB5 PB4 PB3 -- -- -- -- -- -- -- PC7 PC6 PC5 PC4 -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 PE7 PE6 PE5 PE4 -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0 PB14 PB13 PB12 PB11 PC15 PC14 PC13 PC12 -- Pin 11 -- -- -- PE15 PE14 PE13 PE12 PE11 PE10 -- -- -- -- silabs.com | Building a more connected world. -- -- Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Rev. 2.10 | 131 EFM32G Data Sheet Pin Definitions 5.8 EFM32G842 (TQFP64) 5.8.1 Pinout The EFM32G842 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.8. EFM32G842 Pinout (top view, not to scale) Table 5.22. Device Pinout TQFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication 1 PA0 LCD_SEG13 TIM0_CC0 #0/1 I2C0_SDA #0 2 PA1 LCD_SEG14 TIM0_CC1 #0/1 I2C0_SCL #0 3 PA2 LCD_SEG15 TIM0_CC2 #0/1 4 PA3 LCD_SEG16 TIM0_CDTI0 #0 5 PA4 LCD_SEG17 TIM0_CDTI1 #0 silabs.com | Building a more connected world. Other CMU_CLK1 #0 CMU_CLK0 #0 Rev. 2.10 | 132 EFM32G Data Sheet Pin Definitions TQFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication 6 PA5 LCD_SEG18 TIM0_CDTI2 #0 LEU1_TX #1 7 IOVDD_0 8 VSS Ground. 9 PB3 LCD_SEG20 PCNT1_S0IN #1 US2_TX #1 10 PB4 LCD_SEG21 PCNT1_S1IN #1 US2_RX #1 11 PB5 LCD_SEG22 US2_CLK #1 12 PB6 LCD_SEG23 US2_CS #1 13 PC4 ACMP0_CH4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 14 PC5 ACMP0_CH5 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 15 PB7 LFXTAL_P US1_CLK #0 16 PB8 LFXTAL_N US1_CS #0 17 PA12 LCD_BCAP_ P TIM2_CC0 #1 18 PA13 LCD_BCAP_ N TIM2_CC1 #1 19 PA14 LCD_BEXT TIM2_CC2 #1 20 RESETn 21 PB11 DAC0_OUT0 22 VSS Ground. 23 AVDD_1 24 PB13 HFXTAL_P LEU0_TX #1 25 PB14 HFXTAL_N LEU0_RX #1 26 IOVDD_3 Digital IO power supply 3. 27 AVDD_0 Analog power supply 0. 28 PD0 ADC0_CH0 PCNT2_S0IN #0 US1_TX #1 29 PD1 ADC0_CH1 TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 31 PD3 ADC0_CH3 TIM0_CC2 #3 US1_CS #1 32 PD4 ADC0_CH4 LEU0_TX #0 33 PD5 ADC0_CH5 LEU0_RX #0 34 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1 35 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1 36 PD8 37 PC6 Other Digital IO power supply 0. Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. LETIM0_OUT0 #1 Analog power supply 1. CMU_CLK1 #1 ACMP0_CH6 silabs.com | Building a more connected world. LEU1_TX #0 I2C0_SDA #2 Rev. 2.10 | 133 EFM32G Data Sheet Pin Definitions TQFP64 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog Timers Communication Other 38 PC7 ACMP0_CH7 39 VDD_DREG Power supply for on-chip voltage regulator. 40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. 41 PE4 LCD_COM0 US0_CS #1 42 PE5 LCD_COM1 US0_CLK #1 43 PE6 LCD_COM2 US0_RX #1 44 PE7 LCD_COM3 US0_TX #1 45 PC12 ACMP1_CH4 46 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 TIM1_CC0 #0 PCNT0_S0IN #0 47 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 48 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 TIM1_CC2 #0 DBG_SWO #1 49 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1 50 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1 51 PF2 LCD_SEG0 52 PF3 LCD_SEG1 TIM0_CDTI0 #2 53 PF4 LCD_SEG2 TIM0_CDTI1 #2 54 PF5 LCD_SEG3 TIM0_CDTI2 #2 55 IOVDD_5 56 VSS 57 PE8 LCD_SEG4 PCNT2_S0IN #1 58 PE9 LCD_SEG5 PCNT2_S1IN #1 59 PE10 LCD_SEG6 TIM1_CC0 #1 US0_TX #0 BOOT_TX 60 PE11 LCD_SEG7 TIM1_CC1 #1 US0_RX #0 BOOT_RX 61 PE12 LCD_SEG8 TIM1_CC2 #1 US0_CLK #0 62 PE13 LCD_SEG9 US0_CS #0 63 PE14 LCD_SEG10 LEU0_TX #2 64 PE15 LCD_SEG11 LEU0_RX #2 LEU1_RX #0 I2C0_SCL #2 CMU_CLK0 #1 ACMP1_O #0 DBG_SWO #0 Digital IO power supply 5. Ground. silabs.com | Building a more connected world. ACMP0_O #0 Rev. 2.10 | 134 EFM32G Data Sheet Pin Definitions 5.8.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.23. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 3 Description ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 Analog comparator ACMP0, digital output. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 Analog comparator ACMP1, digital output. ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1. DAC0_OUT0 PB11 DBG_SWCLK PF0 PF0 DBG_SWDIO PF1 PF1 Digital to Analog Converter DAC0 output channel number 0. Debug-interface Serial Wire clock input. Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. silabs.com | Building a more connected world. Note that this function is enabled to pin out of reset, and has a built-in pull up. Rev. 2.10 | 135 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output. LCD_BCAP_N PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD_BCAP_P PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. Note that this function is not enabled after reset, and must be enabled by software to be used. LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. silabs.com | Building a more connected world. Rev. 2.10 | 136 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG21 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG22 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG23 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LETIM0_OUT0 PD6 LETIM0_OUT1 PD7 LEU0_RX PD5 PB14 PE15 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 LEU1_TX PC6 LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PCNT0_S0IN PC13 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEUART1 Receive input. PA5 silabs.com | Building a more connected world. LEUART1 Transmit output. Also used as receive input in half duplex communication. Rev. 2.10 | 137 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description TIM0_CC0 PA0 PA0 PD1 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PD2 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PD3 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0. TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA12 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA13 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA14 Timer 2 Capture Compare input / output channel 2. US0_CLK PE12 PE5 USART0 clock input / output. US0_CS PE13 PE4 USART0 chip select input / output. US0_RX PE11 PE6 USART0 Asynchronous Receive. USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 US1_CLK PB7 PD2 USART1 clock input / output. US1_CS PB8 PD3 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PD1 US1_TX PD0 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. USART1 Synchronous mode Master Output / Slave Input (MOSI). US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART2 Asynchronous Receive. US2_RX US2_TX PB4 PB3 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.10 | 138 EFM32G Data Sheet Pin Definitions 5.8.3 GPIO Pinout Overview The specific GPIO pins available in EFM32G842 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.24. GPIO Pinout Port Pin 15 Port A -- PA14 PA13 PA12 Port B -- PB14 PB13 Port C Port D Port E Port F Pin 14 Pin 13 Pin 12 -- PC15 PC14 PC13 PC12 -- -- -- -- Pin 11 Pin 10 -- -- -- -- -- -- PA5 PA4 PA3 PA2 PA1 PA0 PB11 -- -- PB8 PB7 PB6 PB5 PB4 PB3 -- -- -- -- -- -- -- PC7 PC6 PC5 PC4 -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE9 PE8 PE7 PE6 PE5 PE4 -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0 PE15 PE14 PE13 PE12 PE11 PE10 -- -- -- -- silabs.com | Building a more connected world. -- -- Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Rev. 2.10 | 139 EFM32G Data Sheet Pin Definitions 5.9 EFM32G880 (LQFP100) 5.9.1 Pinout The EFM32G880 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.9. EFM32G880 Pinout (top view, not to scale) Table 5.25. Device Pinout LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication 1 PA0 LCD_SEG 13 EBI_AD09 #0 TIM0_CC0 #0/1 I2C0_SDA #0 2 PA1 LCD_SEG 14 EBI_AD10 #0 TIM0_CC1 #0/1 I2C0_SCL #0 3 PA2 LCD_SEG 15 EBI_AD11 #0 TIM0_CC2 #0/1 silabs.com | Building a more connected world. Other CMU_CLK1 #0 CMU_CLK0 #0 Rev. 2.10 | 140 EFM32G Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication 4 PA3 LCD_SEG 16 EBI_AD12 #0 TIM0_CDTI0 #0 U0_TX #2 5 PA4 LCD_SEG 17 EBI_AD13 #0 TIM0_CDTI1 #0 U0_RX #2 6 PA5 LCD_SEG 18 EBI_AD14 #0 TIM0_CDTI2 #0 LEU1_TX #1 7 PA6 LCD_SEG 19 EBI_AD15 #0 8 IOVDD_0 9 PB0 LCD_SEG 32 TIM1_CC0 #2 10 PB1 LCD_SEG 33 TIM1_CC1 #2 11 PB2 LCD_SEG 34 TIM1_CC2 #2 12 PB3 LCD_SEG 20 PCNT1_S0IN #1 US2_TX #1 13 PB4 LCD_SEG 21 PCNT1_S1IN #1 US2_RX #1 14 PB5 LCD_SEG 22 US2_CLK #1 15 PB6 LCD_SEG 23 US2_CS #1 16 VSS Ground. 17 IOVDD_1 18 PC0 ACMP0_C H0 PCNT0_S0IN #2 US1_TX #0 19 PC1 ACMP0_C H1 PCNT0_S1IN #2 US1_RX #0 20 PC2 ACMP0_C H2 US2_TX #0 21 PC3 ACMP0_C H3 US2_RX #0 22 PC4 ACMP0_C H4 LETIM0_OUT0 #3 PCNT1_S0IN #0 US2_CLK #0 23 PC5 ACMP0_C H5 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 24 PB7 LFXTAL_P US1_CLK #0 25 PB8 LFXTAL_N US1_CS #0 26 PA7 LCD_SEG 35 27 PA8 LCD_SEG 36 Other LEU1_RX #1 Digital IO power supply 0. Digital IO power supply 1. silabs.com | Building a more connected world. TIM2_CC0 #0 Rev. 2.10 | 141 EFM32G Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication 28 PA9 LCD_SEG 37 TIM2_CC1 #0 29 PA10 LCD_SEG 38 TIM2_CC2 #0 30 PA11 LCD_SEG 39 31 IOVDD_2 32 VSS Ground. 33 PA12 LCD_BCA P_P TIM2_CC0 #1 34 PA13 LCD_BCA P_N TIM2_CC1 #1 35 PA14 LCD_BEX T TIM2_CC2 #1 36 RESETn 37 PB9 38 PB10 39 PB11 DAC0_OU T0 LETIM0_OUT0 #1 40 PB12 DAC0_OU T1 LETIM0_OUT1 #1 41 AVDD_1 42 PB13 HFXTAL_ P LEU0_TX #1 43 PB14 HFXTAL_ N LEU0_RX #1 44 IOVDD_3 Digital IO power supply 3. 45 AVDD_0 Analog power supply 0. 46 PD0 ADC0_CH 0 PCNT2_S0IN #0 US1_TX #1 47 PD1 ADC0_CH 1 TIM0_CC0 #3 PCNT2_S1IN #0 US1_RX #1 48 PD2 ADC0_CH 2 TIM0_CC1 #3 US1_CLK #1 49 PD3 ADC0_CH 3 TIM0_CC2 #3 US1_CS #1 50 PD4 ADC0_CH 4 LEU0_TX #0 51 PD5 ADC0_CH 5 LEU0_RX #0 52 PD6 ADC0_CH 6 Other Digital IO power supply 2. Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. Analog power supply 1. silabs.com | Building a more connected world. LETIM0_OUT0 #0 I2C0_SDA #1 Rev. 2.10 | 142 EFM32G Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog 53 PD7 ADC0_CH 7 54 PD8 55 PC6 ACMP0_C H6 LEU1_TX #0 I2C0_SDA #2 56 PC7 ACMP0_C H7 LEU1_RX #0 I2C0_SCL #2 57 EBI Timers Communication LETIM0_OUT1 #0 I2C0_SCL #1 Other CMU_CLK1 #1 VDD_DRE Power supply for on-chip voltage regulator. G 58 VSS Ground. 59 DECOUPLE 60 PE0 PCNT0_S0IN #1 U0_TX #1 61 PE1 PCNT0_S1IN #1 U0_RX #1 62 PE2 ACMP0_O #1 63 PE3 ACMP1_O #1 64 PE4 LCD_COM 0 US0_CS #1 65 PE5 LCD_COM 1 US0_CLK #1 66 PE6 LCD_COM 2 US0_RX #1 67 PE7 LCD_COM 3 US0_TX #1 68 PC8 ACMP1_C H0 TIM2_CC0 #2 US0_CS #2 69 PC9 ACMP1_C H1 TIM2_CC1 #2 US0_CLK #2 70 PC10 ACMP1_C H2 TIM2_CC2 #2 US0_RX #2 71 PC11 ACMP1_C H3 72 PC12 ACMP1_C H4 73 PC13 ACMP1_C H5 TIM0_CDTI0 #1/3 TIM1_CC0 #0 PCNT0_S0IN #0 74 PC14 ACMP1_C H6 TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 U0_TX #3 75 PC15 ACMP1_C H7 TIM0_CDTI2 #1/3 TIM1_CC2 #0 U0_RX #3 76 PF0 Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. silabs.com | Building a more connected world. US0_TX #2 CMU_CLK0 #1 LETIM0_OUT0 #2 DBG_SWO #1 DBG_SWCLK #0/1 Rev. 2.10 | 143 EFM32G Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication 77 PF1 78 PF2 LCD_SEG 0 EBI_ARDY #0 79 PF3 LCD_SEG 1 EBI_ALE #0 TIM0_CDTI0 #2 80 PF4 LCD_SEG 2 EBI_WEn #0 TIM0_CDTI1 #2 81 PF5 LCD_SEG 3 EBI_REn #0 TIM0_CDTI2 #2 82 IOVDD_5 83 VSS Ground. 84 PF6 LCD_SEG 24 TIM0_CC0 #2 U0_TX #0 85 PF7 LCD_SEG 25 TIM0_CC1 #2 U0_RX #0 86 PF8 LCD_SEG 26 TIM0_CC2 #2 87 PF9 LCD_SEG 27 88 PD9 LCD_SEG 28 EBI_CS0 #0 89 PD10 LCD_SEG 29 EBI_CS1 #0 90 PD11 LCD_SEG 30 EBI_CS2 #0 91 PD12 LCD_SEG 31 EBI_CS3 #0 92 PE8 LCD_SEG 4 EBI_AD00 #0 PCNT2_S0IN #1 93 PE9 LCD_SEG 5 EBI_AD01 #0 PCNT2_S1IN #1 94 PE10 LCD_SEG 6 EBI_AD02 #0 TIM1_CC0 #1 US0_TX #0 BOOT_TX 95 PE11 LCD_SEG 7 EBI_AD03 #0 TIM1_CC1 #1 US0_RX #0 BOOT_RX 96 PE12 LCD_SEG 8 EBI_AD04 #0 TIM1_CC2 #1 US0_CLK #0 97 PE13 LCD_SEG 9 EBI_AD05 #0 US0_CS #0 98 PE14 LCD_SEG 10 EBI_AD06 #0 LEU0_TX #2 99 PE15 LCD_SEG 11 EBI_AD07 #0 LEU0_RX #2 LETIM0_OUT1 #2 Other DBG_SWDIO #0/1 ACMP1_O #0 DBG_SWO #0 Digital IO power supply 5. silabs.com | Building a more connected world. ACMP0_O #0 Rev. 2.10 | 144 EFM32G Data Sheet Pin Definitions LQFP100 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI 100 PA15 LCD_SEG 12 EBI_AD08 #0 silabs.com | Building a more connected world. Timers Communication Other Rev. 2.10 | 145 EFM32G Data Sheet Pin Definitions 5.9.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.26. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 3 Description ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1. PE2 PE3 silabs.com | Building a more connected world. Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.10 | 146 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0. DAC0_OUT1 PB12 Digital to Analog Converter DAC0 output channel number 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 EBI_AD00 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 External Bus Interface (EBI) Address Latch Enable output. silabs.com | Building a more connected world. Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.10 | 147 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description EBI_ARDY PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_CS0 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_REn PF5 External Bus Interface (EBI) Read Enable output. EBI_WEn PF4 External Bus Interface (EBI) Write Enable output. HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output. LCD_BCAP_N PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD_BCAP_P PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. silabs.com | Building a more connected world. Rev. 2.10 | 148 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG21 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG22 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG23 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG24 PF6 LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG25 PF7 LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG26 PF8 LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG27 PF9 LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG28 PD9 LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG29 PD10 LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7. silabs.com | Building a more connected world. Rev. 2.10 | 149 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description LCD_SEG30 PD11 LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG31 PD12 LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG32 PB0 LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG33 PB1 LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG34 PB2 LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG35 PA7 LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG36 PA8 LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG37 PA9 LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG38 PA10 LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG39 PA11 LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PCNT0_S0IN PC13 PE0 PC0 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. TIM0_CC0 PA0 PA0 PF6 PD1 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0. silabs.com | Building a more connected world. Rev. 2.10 | 150 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB1 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 USART0 clock input / output. US0_CS PE13 PE4 PC8 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PC11 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 US1_CLK PB7 PD2 USART1 clock input / output. US1_CS PB8 PD3 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX US2_TX PC3 PC2 PB4 PB3 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.10 | 151 EFM32G Data Sheet Pin Definitions 5.9.3 GPIO Pinout Overview The specific GPIO pins available in EFM32G880 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.27. GPIO Pinout Port Port A Port B Port C Port D Port E Port F Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 PA15 PA14 PA13 PA12 PA11 PA10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 -- -- -- -- -- -- -- -- silabs.com | Building a more connected world. -- -- Rev. 2.10 | 152 EFM32G Data Sheet Pin Definitions 5.10 EFM32G890 (BGA112) 5.10.1 Pinout The EFM32G890 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question. Figure 5.10. EFM32G890 Pinout (top view, not to scale) Table 5.28. Device Pinout BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI A1 PE15 LCD_SEG 11 EBI_AD07 #0 LEU0_RX #2 A2 PE14 LCD_SEG 10 EBI_AD06 #0 LEU0_TX #2 A3 PE12 LCD_SEG 8 EBI_AD04 #0 silabs.com | Building a more connected world. Timers TIM1_CC2 #1 Communication Other US0_CLK #0 Rev. 2.10 | 153 EFM32G Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers A4 PE9 LCD_SEG 5 EBI_AD01 #0 PCNT2_S1IN #1 A5 PD10 LCD_SEG 29 EBI_CS1 #0 A6 PF7 LCD_SEG 25 A7 PF5 LCD_SEG 3 EBI_REn #0 TIM0_CDTI2 #2 A8 PF4 LCD_SEG 2 EBI_WEn #0 TIM0_CDTI1 #2 A9 PE4 LCD_COM 0 A10 PC14 ACMP1_C H6 TIM0_CDTI1 #1/3 TIM1_CC1 #0 PCNT0_S1IN #0 U0_TX #3 A11 PC15 ACMP1_C H7 TIM0_CDTI2 #1/3 TIM1_CC2 #0 U0_RX #3 DBG_SWO #1 B1 PA15 LCD_SEG 12 EBI_AD08 #0 B2 PE13 LCD_SEG 9 EBI_AD05 #0 US0_CS #0 ACMP0_O #0 B3 PE11 LCD_SEG 7 EBI_AD03 #0 TIM1_CC1 #1 US0_RX #0 BOOT_RX B4 PE8 LCD_SEG 4 EBI_AD00 #0 PCNT2_S0IN #1 B5 PD11 LCD_SEG 30 EBI_CS2 #0 B6 PF8 LCD_SEG 26 TIM0_CC2 #2 B7 PF6 LCD_SEG 24 TIM0_CC0 #2 B8 PF3 LCD_SEG 1 B9 PE5 LCD_COM 1 B10 PC12 ACMP1_C H4 B11 PC13 ACMP1_C H5 C1 PA1 LCD_SEG 14 EBI_AD10 #0 TIM0_CC1 #0/1 I2C0_SCL #0 C2 PA0 LCD_SEG 13 EBI_AD09 #0 TIM0_CC0 #0/1 I2C0_SDA #0 TIM0_CC1 #2 Communication Other U0_RX #0 US0_CS #1 EBI_ALE #0 U0_TX #0 TIM0_CDTI0 #2 US0_CLK #1 CMU_CLK0 #1 TIM0_CDTI0 #1/3 TIM1_CC0 #0 PCNT0_S0IN #0 silabs.com | Building a more connected world. CMU_CLK1 #0 Rev. 2.10 | 154 EFM32G Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other C3 PE10 LCD_SEG 6 EBI_AD02 #0 TIM1_CC0 #1 US0_TX #0 BOOT_TX C4 PD13 C5 PD12 LCD_SEG 31 EBI_CS3 #0 C6 PF9 LCD_SEG 27 C7 VSS Ground. C8 PF2 LCD_SEG 0 C9 PE6 LCD_COM 2 C10 PC10 ACMP1_C H2 C11 PC11 ACMP1_C H3 D1 PA3 LCD_SEG 16 EBI_AD12 #0 TIM0_CDTI0 #0 D2 PA2 LCD_SEG 15 EBI_AD11 #0 TIM0_CC2 #0/1 CMU_CLK0 #0 D3 PB15 D4 VSS D5 IOVDD_6 D6 PD9 D7 IOVDD_5 D8 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1 D9 PE7 LCD_COM 3 D10 PC8 ACMP1_C H0 TIM2_CC0 #2 US0_CS #2 D11 PC9 ACMP1_C H1 TIM2_CC1 #2 US0_CLK #2 E1 PA6 LCD_SEG 19 EBI_AD15 #0 E2 PA5 LCD_SEG 18 EBI_AD14 #0 TIM0_CDTI2 #0 LEU1_TX #1 E3 PA4 LCD_SEG 17 EBI_AD13 #0 TIM0_CDTI1 #0 U0_RX #2 E4 PB0 LCD_SEG 32 E8 PF0 ACMP1_O #0 DBG_SWO #0 EBI_ARDY #0 US0_RX #1 TIM2_CC2 #2 US0_RX #2 US0_TX #2 U0_TX #2 Ground. Digital IO power supply 6. LCD_SEG 28 EBI_CS0 #0 Digital IO power supply 5. US0_TX #1 silabs.com | Building a more connected world. LEU1_RX #1 TIM1_CC0 #2 LETIM0_OUT0 #2 DBG_SWCLK #0/1 Rev. 2.10 | 155 EFM32G Data Sheet Pin Definitions BGA112 Pin# and Name Pin # Pin Name E9 Pin Alternate Functionality / Description Analog EBI Timers Communication PE0 PCNT0_S0IN #1 U0_TX #1 E10 PE1 PCNT0_S1IN #1 U0_RX #1 E11 PE3 F1 PB1 LCD_SEG 33 TIM1_CC1 #2 F2 PB2 LCD_SEG 34 TIM1_CC2 #2 F3 PB3 LCD_SEG 20 PCNT1_S0IN #1 US2_TX #1 F4 PB4 LCD_SEG 21 PCNT1_S1IN #1 US2_RX #1 Other ACMP1_O #1 F8 VDD_DRE Power supply for on-chip voltage regulator. G F9 VSS_DRE Ground for on-chip voltage regulator. G F10 PE2 ACMP0_O #1 F11 DECOUPLE G1 PB5 LCD_SEG 22 US2_CLK #1 G2 PB6 LCD_SEG 23 US2_CS #1 G3 VSS Ground. G4 IOVDD_0 Digital IO power supply 0. G8 IOVDD_4 Digital IO power supply 4. G9 VSS Ground. G10 PC6 ACMP0_C H6 LEU1_TX #0 I2C0_SDA #2 G11 PC7 ACMP0_C H7 LEU1_RX #0 I2C0_SCL #2 H1 PC0 ACMP0_C H0 H2 PC2 ACMP0_C H2 H3 PD14 H4 PA7 LCD_SEG 35 H5 PA8 LCD_SEG 36 H6 VSS Ground. H7 IOVDD_3 H8 PD8 Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin. PCNT0_S0IN #2 US1_TX #0 US2_TX #0 I2C0_SDA #3 TIM2_CC0 #0 Digital IO power supply 3. silabs.com | Building a more connected world. CMU_CLK1 #1 Rev. 2.10 | 156 EFM32G Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication Other H9 PD5 ADC0_CH 5 H10 PD6 ADC0_CH 6 LETIM0_OUT0 #0 I2C0_SDA #1 H11 PD7 ADC0_CH 7 LETIM0_OUT1 #0 I2C0_SCL #1 J1 PC1 ACMP0_C H1 PCNT0_S1IN #2 US1_RX #0 J2 PC3 ACMP0_C H3 J3 PD15 J4 PA12 LCD_BCA P_P TIM2_CC0 #1 J5 PA9 LCD_SEG 37 TIM2_CC1 #0 J6 PA10 LCD_SEG 38 TIM2_CC2 #0 J7 PB9 J8 PB10 J9 PD2 ADC0_CH 2 TIM0_CC1 #3 US1_CLK #1 J10 PD3 ADC0_CH 3 TIM0_CC2 #3 US1_CS #1 J11 PD4 ADC0_CH 4 LEU0_TX #0 K1 PB7 LFXTAL_P US1_CLK #0 K2 PC4 ACMP0_C H4 LETIM0_OUT0 #3 PCNT1_S0IN #0 K3 PA13 LCD_BCA P_N TIM2_CC1 #1 K4 VSS Ground. K5 PA11 LCD_SEG 39 K6 RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. K7 AVSS_1 Analog ground 1. K8 AVDD_2 Analog power supply 2. K9 AVDD_1 Analog power supply 1. K10 AVSS_0 Analog ground 0. K11 PD1 ADC0_CH 1 L1 PB8 LFXTAL_N LEU0_RX #0 US2_RX #0 I2C0_SCL #3 silabs.com | Building a more connected world. TIM0_CC0 #3 PCNT2_S1IN #0 US2_CLK #0 US1_RX #1 US1_CS #0 Rev. 2.10 | 157 EFM32G Data Sheet Pin Definitions BGA112 Pin# and Name Pin Alternate Functionality / Description Pin # Pin Name Analog EBI Timers Communication L2 PC5 ACMP0_C H5 LETIM0_OUT1 #3 PCNT1_S1IN #0 US2_CS #0 L3 PA14 LCD_BEX T TIM2_CC2 #1 L4 IOVDD_1 L5 PB11 DAC0_OU T0 LETIM0_OUT0 #1 L6 PB12 DAC0_OU T1 LETIM0_OUT1 #1 L7 AVSS_2 L8 PB13 HFXTAL_ P LEU0_TX #1 L9 PB14 HFXTAL_ N LEU0_RX #1 L10 AVDD_0 L11 PD0 Other Digital IO power supply 1. Analog ground 2. Analog power supply 0. ADC0_CH 0 silabs.com | Building a more connected world. PCNT2_S0IN #0 US1_TX #1 Rev. 2.10 | 158 EFM32G Data Sheet Pin Definitions 5.10.2 Alternate Functionality Pinout A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 5.29. Alternate functionality overview Alternate LOCATION Functionality 0 1 2 3 Description ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0. ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1. ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2. ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3. ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4. ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5. ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6. ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7. ACMP0_O PE13 ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0. ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1. ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2. ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3. ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4. ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5. ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6. ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7. ACMP1_O PF2 ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0. ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1. ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2. ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3. ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4. ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5. ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6. ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7. BOOT_RX PE11 Bootloader RX. BOOT_TX PE10 Bootloader TX. CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0. CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1. PE2 PE3 silabs.com | Building a more connected world. Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Rev. 2.10 | 159 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0. DAC0_OUT1 PB12 Digital to Analog Converter DAC0 output channel number 1. Debug-interface Serial Wire clock input. DBG_SWCLK PF0 PF0 Note that this function is enabled to pin out of reset, and has a built-in pull down. Debug-interface Serial Wire data input / output. DBG_SWDIO PF1 PF1 Note that this function is enabled to pin out of reset, and has a built-in pull up. Debug-interface Serial Wire viewer Output. DBG_SWO PF2 PC15 EBI_AD00 PE8 External Bus Interface (EBI) address and data input / output pin 00. EBI_AD01 PE9 External Bus Interface (EBI) address and data input / output pin 01. EBI_AD02 PE10 External Bus Interface (EBI) address and data input / output pin 02. EBI_AD03 PE11 External Bus Interface (EBI) address and data input / output pin 03. EBI_AD04 PE12 External Bus Interface (EBI) address and data input / output pin 04. EBI_AD05 PE13 External Bus Interface (EBI) address and data input / output pin 05. EBI_AD06 PE14 External Bus Interface (EBI) address and data input / output pin 06. EBI_AD07 PE15 External Bus Interface (EBI) address and data input / output pin 07. EBI_AD08 PA15 External Bus Interface (EBI) address and data input / output pin 08. EBI_AD09 PA0 External Bus Interface (EBI) address and data input / output pin 09. EBI_AD10 PA1 External Bus Interface (EBI) address and data input / output pin 10. EBI_AD11 PA2 External Bus Interface (EBI) address and data input / output pin 11. EBI_AD12 PA3 External Bus Interface (EBI) address and data input / output pin 12. EBI_AD13 PA4 External Bus Interface (EBI) address and data input / output pin 13. EBI_AD14 PA5 External Bus Interface (EBI) address and data input / output pin 14. EBI_AD15 PA6 External Bus Interface (EBI) address and data input / output pin 15. EBI_ALE PF3 External Bus Interface (EBI) Address Latch Enable output. silabs.com | Building a more connected world. Note that this function is not enabled after reset, and must be enabled by software to be used. Rev. 2.10 | 160 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description EBI_ARDY PF2 External Bus Interface (EBI) Hardware Ready Control input. EBI_CS0 PD9 External Bus Interface (EBI) Chip Select output 0. EBI_CS1 PD10 External Bus Interface (EBI) Chip Select output 1. EBI_CS2 PD11 External Bus Interface (EBI) Chip Select output 2. EBI_CS3 PD12 External Bus Interface (EBI) Chip Select output 3. EBI_REn PF5 External Bus Interface (EBI) Read Enable output. EBI_WEn PF4 External Bus Interface (EBI) Write Enable output. HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external optional clock input pin. HFXTAL_P PB13 High Frequency Crystal positive pin. I2C0_SCL PA1 PD7 PC7 PD15 I2C0 Serial Clock Line input / output. I2C0_SDA PA0 PD6 PC6 PD14 I2C0 Serial Data input / output. LCD_BCAP_N PA13 LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD_BCAP_P PA12 LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P. LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS. LCD_BEXT PA14 An external LCD voltage may also be applied to this pin if the booster is not enabled. If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO. LCD_COM0 PE4 LCD driver common line number 0. LCD_COM1 PE5 LCD driver common line number 1. LCD_COM2 PE6 LCD driver common line number 2. LCD_COM3 PE7 LCD driver common line number 3. LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0. LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1. silabs.com | Building a more connected world. Rev. 2.10 | 161 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1. LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2. LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3. LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4. LCD_SEG20 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG21 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG22 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG23 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. LCD_SEG24 PF6 LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG25 PF7 LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG26 PF8 LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG27 PF9 LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6. LCD_SEG28 PD9 LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG29 PD10 LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7. silabs.com | Building a more connected world. Rev. 2.10 | 162 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description LCD_SEG30 PD11 LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG31 PD12 LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7. LCD_SEG32 PB0 LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG33 PB1 LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG34 PB2 LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG35 PA7 LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8. LCD_SEG36 PA8 LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG37 PA9 LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG38 PA10 LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LCD_SEG39 PA11 LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9. LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0. LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1. LEU0_RX PD5 PB14 PE15 LEUART0 Receive input. LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half duplex communication. LEU1_RX PC7 PA6 LEUART1 Receive input. LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half duplex communication. LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin. LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin. PCNT0_S0IN PC13 PE0 PC0 Pulse Counter PCNT0 input number 0. PCNT0_S1IN PC14 PE1 PC1 Pulse Counter PCNT0 input number 1. PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0. PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1. PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0. PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1. TIM0_CC0 PA0 PA0 PF6 PD1 Timer 0 Capture Compare input / output channel 0. TIM0_CC1 PA1 PA1 PF7 PD2 Timer 0 Capture Compare input / output channel 1. TIM0_CC2 PA2 PA2 PF8 PD3 Timer 0 Capture Compare input / output channel 2. TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0. silabs.com | Building a more connected world. Rev. 2.10 | 163 EFM32G Data Sheet Pin Definitions Alternate LOCATION Functionality 0 1 2 3 Description TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1. TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2. TIM1_CC0 PC13 PE10 PB0 Timer 1 Capture Compare input / output channel 0. TIM1_CC1 PC14 PE11 PB1 Timer 1 Capture Compare input / output channel 1. TIM1_CC2 PC15 PE12 PB2 Timer 1 Capture Compare input / output channel 2. TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0. TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1. TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2. U0_RX PF7 PE1 PA4 PC15 UART0 Receive input. U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half duplex communication. US0_CLK PE12 PE5 PC9 USART0 clock input / output. US0_CS PE13 PE4 PC8 USART0 chip select input / output. USART0 Asynchronous Receive. US0_RX PE11 PE6 PC10 PC11 USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit.Also used as receive input in half duplex communication. US0_TX PE10 PE7 US1_CLK PB7 PD2 USART1 clock input / output. US1_CS PB8 PD3 USART1 chip select input / output. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 Asynchronous Receive. US1_RX PC1 PD1 USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit.Also used as receive input in half duplex communication. US1_TX PC0 PD0 US2_CLK PC4 PB5 USART2 clock input / output. US2_CS PC5 PB6 USART2 chip select input / output. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 Asynchronous Receive. US2_RX US2_TX PC3 PC2 PB4 PB3 silabs.com | Building a more connected world. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit.Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). Rev. 2.10 | 164 EFM32G Data Sheet Pin Definitions 5.10.3 GPIO Pinout Overview The specific GPIO pins available in EFM32G890 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0. Table 5.30. GPIO Pinout Port Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Pin 10 Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Port F -- -- -- -- silabs.com | Building a more connected world. -- -- Rev. 2.10 | 165 EFM32G Data Sheet BGA112 Package Specifications 6. BGA112 Package Specifications Rev: 97SPP01315A_X03_06Jun11 6.1 BGA112 Package Dimensions BOTTOM VIEW TOP VIEW SIDE VIEW Figure 6.1. BGA112 Note: 1. The dimensions in parenthesis are reference. 2. Datum 'C' and seating plane are defined by the crown of the solder balls. 3. All dimensions are in millimeters. The BGA112 Package uses SAC105 solderballs. All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb). For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx. silabs.com | Building a more connected world. Rev. 2.10 | 166 EFM32G Data Sheet BGA112 Package Specifications 6.2 BGA112 PCB Layout b a e d Figure 6.2. BGA112 PCB Land Pattern Table 6.1. BGA112 PCB Land Pattern Dimensions (Dimensions in mm) Symbol Dim. (mm) a 0.35 b 0.80 d 8.00 e 8.00 b a e d Figure 6.3. BGA112 PCB Solder Mask Table 6.2. BGA112 PCB Solder Mask Dimensions (Dimensions in mm) Symbol Dim. (mm) a 0.48 b 0.80 d 8.00 e 8.00 silabs.com | Building a more connected world. Rev. 2.10 | 167 EFM32G Data Sheet BGA112 Package Specifications b a e d Figure 6.4. BGA112 PCB Stencil Design Table 6.3. BGA112 PCB Stencil Design Dimensions (Dimensions in mm) Symbol Dim. (mm) a 0.33 b 0.80 d 8.00 e 8.00 Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions. silabs.com | Building a more connected world. Rev. 2.10 | 168 EFM32G Data Sheet BGA112 Package Specifications 6.3 BGA112 Package Marking In the illustration below package fields and position are shown. Figure 6.5. Example Chip Marking (Top View) silabs.com | Building a more connected world. Rev. 2.10 | 169 EFM32G Data Sheet LQFP100 Package Specifications 7. LQFP100 Package Specifications Rev: 98A0100QP043_03MAY2007 7.1 LQFP100 Package Dimensions Figure 7.1. LQFP100 Note: 1. Datum 'T', 'U' and 'Z' to be determined at datum plane 'H' 2. Datum 'D' and 'E' to be determined at seating plane datum 'Y'. 3. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25 per side. Dimensions 'D1' and 'E1' do include mold mismatch and are determined at datum plane datum 'H'. 4. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause thelead width to exceed the maximum 'b' dimension by more than 0.08 mm. Dambar can not be locatedon the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm. 5. Exact shape of each corner is optional. Table 7.1. LQFP100 (Dimensions in mm) SYMBOL MIN NOM MAX total thickness A -- -- 1.6 stand off A1 0.05 -- 0.15 mold thickness A2 1.35 1.4 1.45 lead width (plating) b 0.17 0.2 0.27 lead width b1 0.17 -- 0.23 L/F thickness (plating) c 0.09 -- 0.2 lead thickness c1 0.09 -- 0.16 silabs.com | Building a more connected world. Rev. 2.10 | 170 EFM32G Data Sheet LQFP100 Package Specifications SYMBOL body size MIN NOM x D 16 BSC y E 16 BSC x D1 14 BSC y E1 14 BSC e 0.5 BSC lead pitch L footprint 0.45 L1 0.6 MAX 0.75 1 REF 0 3.5 7 1 0 -- -- 2 11 12 13 3 11 12 13 R1 0.08 -- -- R1 0.08 -- 0.2 S 0.2 -- -- package edge tolerance aaa 0.2 lead edge tolerance bbb 0.2 coplanarity ccc 0.08 lead offset ddd 0.08 mold flatness eee 0.05 The LQFP100 Package uses Nickel-Palladium-Gold preplated leadframe. All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb). For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx silabs.com | Building a more connected world. Rev. 2.10 | 171 EFM32G Data Sheet LQFP100 Package Specifications 7.2 LQFP100 PCB Layout a p8 b p7 p6 p1 e c p2 p5 p3 p4 d Figure 7.2. LQFP100 PCB Land Pattern Table 7.2. LQFP100 PCB Land Pattern Dimensions (Dimensions in mm) Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number a 1.45 P1 1 P6 75 b 0.30 P2 25 P7 76 c 0.50 P3 26 P8 100 d 15.40 P4 50 e 15.40 P5 51 a b e c d Figure 7.3. LQFP100 PCB Solder Mask Table 7.3. LQFP100 PCB Solder Mask Dimensions (Dimensions in mm) Symbol Dim. (mm) a 1.57 b 0.42 c 0.50 d 15.40 e 15.40 silabs.com | Building a more connected world. Rev. 2.10 | 172 EFM32G Data Sheet LQFP100 Package Specifications a b e c d Figure 7.4. LQFP100 PCB Stencil Design Table 7.4. LQFP100 PCB Stencil Design Dimensions (Dimensions in mm) Symbol Dim. (mm) a 1.35 b 0.20 c 0.50 d 15.40 e 15.40 Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions. silabs.com | Building a more connected world. Rev. 2.10 | 173 EFM32G Data Sheet LQFP100 Package Specifications 7.3 LQFP100 Package Marking In the illustration below package fields and position are shown. Figure 7.5. Example Chip Marking (Top View) silabs.com | Building a more connected world. Rev. 2.10 | 174 EFM32G Data Sheet TQFP64 Package Specifications 8. TQFP64 Package Specifications Rev: 98SPP64023A_XO1_17MAR2011 8.1 TQFP64 Package Dimensions F CL Figure 8.1. TQFP64 Note: 1. All dimensions & tolerancing confirm to ASME Y14.5M-1994. 2. The top package body size may be smaller than the bottom package body size. 3. Datum 'A,B', and 'B' to be determined at datum plane 'H'. 4. To be determined at seating place 'C'. 5. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25mm per side.'D1' and 'E1' are maximum plastic body size dimension including mold mismatch. Dimension 'D1' and'E1' shall be determined at datum plane 'H'. 6. Detail of Pin 1 indicatifier are option all but must be located within the zone indicated. 7. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause thelead width to exceed the maximum 'b' dimension by more than 0.08 mm. Dambar can not be locatedon the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm. 8. Exact shape of each corner is optional. 9. These dimension apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 10. All dimensions are in millimeters. Table 8.1. QFP64 (Dimensions in mm) DIM MIN NOM MAX DIM A -- 1.10 1.20 L1 A1 0.05 -- 0.15 R1 0.08 -- -- A2 0.95 1.00 1.05 R2 0.08 -- 0.20 silabs.com | Building a more connected world. MIN NOM MAX -- Rev. 2.10 | 175 EFM32G Data Sheet TQFP64 Package Specifications DIM MIN NOM MAX DIM MIN NOM MAX b 0.17 0.22 0.27 S 0.20 -- -- b1 0.17 0.20 0.23 0 3.5 7 c 0.09 -- 0.20 1 0 -- -- C1 0.09 -- 0.16 2 11 12 13 3 11 12 13 D 12.0 BSC D1 10.0 BSC e 0.50 BSC E 12.0 BSC E1 10.0 BSC L 0.45 0.60 0.75 The TQFP64 Package is 10 by 10 mm in size and has a 0.5 mm pin pitch. The TQFP64 Package uses Nickel-Palladium-Gold preplated leadframe. All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb). For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx. silabs.com | Building a more connected world. Rev. 2.10 | 176 EFM32G Data Sheet TQFP64 Package Specifications 8.2 TQFP64 PCB Layout a p8 b p7 p6 p1 e c p2 p5 p3 p4 d Figure 8.2. TQFP64 PCB Land Pattern Table 8.2. TQFP64 PCB Land Pattern Dimensions (Dimensions in mm) Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number a 1.60 P1 1 P6 48 b 0.30 P2 16 P7 49 c 0.50 P3 17 P8 64 d 11.50 P4 32 e 11.50 P5 33 a b e c d Figure 8.3. TQFP64 PCB Solder Mask Table 8.3. TQFP64 PCB Solder Mask Dimensions (Dimensions in mm) Symbol Dim. (mm) a 1.72 b 0.42 c 0.50 d 11.50 e 11.50 silabs.com | Building a more connected world. Rev. 2.10 | 177 EFM32G Data Sheet TQFP64 Package Specifications a b e c d Figure 8.4. TQFP64 PCB Stencil Design Table 8.4. TQFP64 PCB Stencil Design Dimensions (Dimensions in mm) Symbol Dim. (mm) a 1.50 b 0.20 c 0.50 d 11.50 e 11.50 Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions. silabs.com | Building a more connected world. Rev. 2.10 | 178 EFM32G Data Sheet TQFP64 Package Specifications 8.3 TQFP64 Package Marking In the illustration below package fields and position are shown. Figure 8.5. Example Chip Marking (Top View) silabs.com | Building a more connected world. Rev. 2.10 | 179 EFM32G Data Sheet TQFP48 Package Specifications 9. TQFP48 Package Specifications Rev: 98SPP48097A_XO_30Mar11 9.1 TQFP48 Package Dimensions Figure 9.1. TQFP48 Note: 1. Dimensions and tolerance per ASME Y14.5M-1994 2. Control dimension: Millimeter 3. Datum plane AB is located at bottom of lead and is coincident with the lead where the lead existsfrom the plastic body at the bottom of the parting line. 4. Datums T, U and Z to be determined at datum plane AB. 5. Dimensions S and V to be determined at seating plane AC. 6. Dimensions A and B do not include mold protrusion. Allowable protrusion is 0.250 per side. Dimensions A and B do include mold mismatch and are determined at datum AB. 7. Dimension D does not include dambar protrusion. Dambar protrusion shall not cause the D dimensionto exceed 0.350. 8. Minimum solder plate thickness shall be 0.0076. 9. Exact shape of each corner is optional. Table 9.1. QFP48 (Dimensions in mm) DIM MIN NOM MAX DIM MIN NOM A -- 7.000 BSC -- M -- 12DEG REF A1 -- 3.500 BSC -- N 0.090 -- 0.160 B -- 7.000 BSC -- P -- 0.250 BSC -- B1 -- 3.500 BSC -- R 0.150 -- 0.250 C 1.000 -- 1.200 S -- 9.000 BSC -- silabs.com | Building a more connected world. MAX Rev. 2.10 | 180 EFM32G Data Sheet TQFP48 Package Specifications DIM MIN NOM MAX DIM MIN NOM MAX D 0.170 -- 0.270 S1 -- 4.500 BSC -- E 0.950 -- 1.050 V -- 9.000 BSC -- F 0.170 -- 0.230 V1 -- 4.5000 BSC -- G -- 0.500 BSC -- W -- 0.200 BSC -- H 0.050 -- 0.150 AA -- 1.000BSC -- J 0.090 -- 0.200 K 0.500 -- 0.700 L 0DE G -- 7DEG The TQFP48 Package is 7 by 7 mm in size and has a 0.5 mm pin pitch. The TQFP48 Package uses Nickel-Palladium-Gold preplated leadframe. All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb). For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx silabs.com | Building a more connected world. Rev. 2.10 | 181 EFM32G Data Sheet TQFP48 Package Specifications 9.2 TQFP48 PCB Layout a p8 b p7 p6 p1 e c p2 p5 p3 p4 d Figure 9.2. TQFP48 PCB Land Pattern Table 9.2. TQFP48 PCB Land Pattern Dimensions (Dimensions in mm) Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number a 1.60 P1 1 P6 36 b 0.30 P2 12 P7 37 c 0.50 P3 13 P8 48 d 8.50 P4 24 e 8.50 P5 25 a b e c d Figure 9.3. TQFP48 PCB Solder Mask Table 9.3. TQFP48 PCB Solder Mask Dimensions (Dimensions in mm) Symbol Dim. (mm) a 1.72 b 0.42 c 0.50 d 8.50 e 8.50 silabs.com | Building a more connected world. Rev. 2.10 | 182 EFM32G Data Sheet TQFP48 Package Specifications a b e c d Figure 9.4. TQFP48 PCB Stencil Design Table 9.4. TQFP48 PCB Stencil Design Dimensions (Dimensions in mm) Symbol Dim. (mm) a 1.50 b 0.20 c 0.50 d 8.50 e 8.50 Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see 5. Pin Definitions. silabs.com | Building a more connected world. Rev. 2.10 | 183 EFM32G Data Sheet TQFP48 Package Specifications 9.3 TQFP48 Package Marking In the illustration below package fields and position are shown. Figure 9.5. Example Chip Marking (Top View) silabs.com | Building a more connected world. Rev. 2.10 | 184 EFM32G Data Sheet QFN64 Package Specifications 10. QFN64 Package Specifications 10.1 QFN64 Package Dimensions 49 64 48 33 16 32 17 m m Rev: 98SPP64048A_XO1_08MAR2011 1 Figure 10.1. QFN64 Note: 1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. 3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm fromthe terminal tip. Dimension L1 represents terminal full back from package edge up to 0.1 mm isacceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional. Table 10.1. QFN64 (Dimensions in mm) Symbol Min Nom Max A 0.80 0.85 0.90 A1 0.00 -- 0.05 A3 b 0.203 REF 0.25 0.30 D 9.00 BSC E 9.00 BSC 0.35 D2 7.10 7.20 7.30 E2 7.10 7.20 7.30 silabs.com | Building a more connected world. Rev. 2.10 | 185 EFM32G Data Sheet QFN64 Package Specifications Symbol Min e Nom Max 0.50 BSC L 0.40 0.45 0.50 L1 0.00 -- 0.10 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 The QFN64 Package uses Nickel-Palladium-Gold preplated leadframe. All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb). For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx. silabs.com | Building a more connected world. Rev. 2.10 | 186 EFM32G Data Sheet QFN64 Package Specifications 10.2 QFN64 PCB Layout a p8 b p7 p1 p6 e g p9 c p2 p5 p3 p4 f d Figure 10.2. QFN64 PCB Land Pattern Table 10.2. QFN64 PCB Land Pattern Dimensions (Dimensions in mm) Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number a 0.85 P1 1 P8 64 b 0.30 P2 16 P9 65 c 0.50 P3 17 d 8.90 P4 32 e 8.90 P5 33 f 7.20 P6 48 g 7.20 P7 49 a b e g c f d Figure 10.3. QFN64 PCB Solder Mask Table 10.3. QFN64 PCB Solder Mask Dimensions (Dimensions in mm) Symbol Dim. (mm) Symbol Dim. (mm) a 0.97 e 8.90 b 0.42 f 7.32 c 0.50 g 7.32 silabs.com | Building a more connected world. Rev. 2.10 | 187 EFM32G Data Sheet QFN64 Package Specifications Symbol Dim. (mm) Symbol Dim. (mm) d 8.90 - - a b x y e z c d Figure 10.4. QFN64 PCB Stencil Design Table 10.4. QFN64 PCB Stencil Design Dimensions (Dimensions in mm) Symbol Dim. (mm) Symbol Dim. (mm) a 0.75 e 8.90 b 0.22 x 2.70 c 0.50 y 2.70 d 8.90 z 0.80 Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions. silabs.com | Building a more connected world. Rev. 2.10 | 188 EFM32G Data Sheet QFN64 Package Specifications 10.3 QFN64 Package Marking In the illustration below package fields and position are shown. Figure 10.5. Example Chip Marking (Top View) silabs.com | Building a more connected world. Rev. 2.10 | 189 EFM32G Data Sheet QFN32 Package Specifications 11. QFN32 Package Specifications 11.1 QFN32 Package Dimensions D2 D 25 26 27 28 29 30 31 32 24 1 23 2 3 21 4 20 5 19 6 18 7 17 8 32xL 16 15 14 13 12 11 10 Rev: 98SPP32088A_XO1_10MAR2011 E E2 e 22 9 32xb m m G L1 SEATING PLANE A1 A3 L A M DETAIL G VIEW ROTATED 90 CLOCKWISE e EVEN / ODD TERMINL SIDE M Figure 11.1. QFN32 Note: 1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. 3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm fromthe terminal tip. Dimension L1 represents terminal full back from package edge up to 0.1 mm isacceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional. Table 11.1. QFN32 (Dimensions in mm) Symbol A A1 Min 0.80 0.00 Nom 0.85 -- Max 0.90 0.05 A3 b D E 6.00 BSC 6.00 BSC 0.25 0.203 REF 0.30 0.35 D2 E2 4.30 4.30 4.40 4.40 4.50 4.50 e 0.65 BSC L L1 0.30 0.00 0.35 0.40 aaa bbb ccc ddd eee 0.10 0.10 0.10 0.05 0.08 0.10 The QFN32 Package uses Nickel-Palladium-Gold preplated leadframe. All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb). For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx silabs.com | Building a more connected world. Rev. 2.10 | 190 EFM32G Data Sheet QFN32 Package Specifications 11.2 QFN32 PCB Layout a p8 b p7 p1 p6 g p9 e c p2 p5 p3 p4 f d Figure 11.2. QFN32 PCB Land Pattern Table 11.2. QFN32 PCB Land Pattern Dimensions (Dimensions in mm) Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number a 0.80 P1 1 P6 24 b 0.35 P2 8 P7 25 c 0.65 P3 9 P8 32 d 6.00 P4 16 P9 33 e 6.00 P5 17 f 4.40 g 4.40 a b g e c f d Figure 11.3. QFN32 PCB Solder Mask Table 11.3. QFN32 PCB Solder Mask Dimensions (Dimensions in mm) Symbol Dim. (mm) a 0.92 b 0.47 c 0.65 silabs.com | Building a more connected world. Rev. 2.10 | 191 EFM32G Data Sheet QFN32 Package Specifications Symbol Dim. (mm) d 6.00 e 6.00 f 4.52 g 4.52 a b x y e z c d Figure 11.4. QFN32 PCB Stencil Design Table 11.4. QFN32 PCB Stencil Design Dimensions (Dimensions in mm) Symbol Dim. (mm) a 0.70 b 0.25 c 0.65 d 6.00 e 6.00 x 1.30 y 1.30 z 0.50 Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see 5. Pin Definitions. silabs.com | Building a more connected world. Rev. 2.10 | 192 EFM32G Data Sheet QFN32 Package Specifications 11.3 QFN32 Package Marking In the illustration below package fields and position are shown. Figure 11.5. Example Chip Marking (Top View) silabs.com | Building a more connected world. Rev. 2.10 | 193 EFM32G Data Sheet Chip Revision, Solder Information, Errata 12. Chip Revision, Solder Information, Errata 12.1 Chip Revision The revision of a chip can be determined from the "Revision" field in the package marking. 12.2 Soldering Information The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed. 12.3 Errata Please see the errata document for description and resolution of device errata. This document is available in Simplicity Studio and online at: http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit silabs.com | Building a more connected world. Rev. 2.10 | 194 EFM32G Data Sheet Revision History 13. Revision History 13.1 Revision 2.10 July 19, 2017 In 4.8 General Purpose Input Output: * Added missing multiply symbols. In 4.10 Analog Digital Converter (ADC): * Updated average active current. * Updated SNR. * Updated SINAD. * Updated SFDR. * Renamed VREF Output Voltage to VREF Voltage. In 4.11 Digital Analog Converter (DAC): * Renamed VREF Output Voltage to VREF Voltage. silabs.com | Building a more connected world. Rev. 2.10 | 195 EFM32G Data Sheet Revision History 13.2 Revision 2.00 May 10th, 2017 Consolidated all EFM32G data sheets: * EFM32G200 * EFM32G210 * EFM32G222 * EFM32G230 * EFM32G232 * EFM32G280 * EFM32G290 * EFM32G840 * EFM32G842 * EFM32G880 * EFM32G890 New formatting throughout. Added 1. Feature List. Updated ordering codes in 2. Ordering Information for Revision E and tape and reel. Added Figure 2.1 Ordering Code Decoder on page 5. Separated Memory Map figure into Figure 3.2 System Address Space with Core and Code Space Listing on page 27 and Figure 3.3 System Address Space with Peripheral Listing on page 28 for readability. Removed footnote for storage temperature range in 4.2 Absolute Maximum Ratings. In 4.6 Power Management: * Updated EM0 condition for VBODextthr- specification. * Added VBODextthr- in EM1 and EM2 specifications. * Updated EM0 condition for VBODextthr+ specification. Updated Flash page erase time and device erase time in 4.7 Flash and added footnotes. Updated figures in 4.9.3 LFRCO. Updated figures and HFRCO current consumption typical values in 4.9.4 HFRCO. In 4.10 Analog Digital Converter (ADC): * Updated test conditions, updated specifications, and added footnote for average active current. * Added input bias current. * Added input offset current. * Updated ADC clock frequency. * Updated SNR, SINAD and SFDR. * Updated offset voltage. * Updated missing codes. * Added gain error drift and offset error drift. * Added VREF output voltage, VREF voltage drift, VREF temperature drift, VREF current consumption, and ADC and DAC VREF matching. In 4.11 Digital Analog Converter (DAC): * Updated IDAC parameter, test conditions, and footnote. * Added DAC load current specification to 4.11 Digital Analog Converter (DAC). * Added VREF output voltage, VREF voltage drift, VREF temperature drift, VREF current consumption, and ADC and DAC VREF matching. Updated ACMP active current (BIASPROG=0b1111, FULLBIAS=1 and HALFBIAS=0 in ACMPn_CTRL register) typical value in 4.12 Analog Comparator (ACMP). Updated VCMP hysteresis typical value in 4.13 Voltage Comparator (VCMP). silabs.com | Building a more connected world. Rev. 2.10 | 196 EFM32G Data Sheet Revision History Corrected pin number for symbol P3 in Table 11.2 QFN32 PCB Land Pattern Dimensions (Dimensions in mm) on page 191. Updated package marking figures to include temperature grade. 13.3 Revision 1.90 May 22nd, 2015 For devices with an ADC, Added clarification on conditions for INLADC and DNLADC parameters. Corrected EM2 current consumption condition in Electrical Characteristics section. Added AUXHFRCO to block diagram and Electrical Characteristics. Updated HFRCO table in the Electrical Characteristics section. Updated EM0, EM2, EM3, and EM4 maximum current specifications in the Electrical Characteristics section. Updated the Output Low Voltage maximum for sinking 20 mA with VDD = 3.0 V in the Electrical Characteristics section. Updated the Input Leakage Current maximum in the Electrical Characteristics section. Updated the minimum and maximum frequency specifications for the LFRCO, HFRCO, and AUXHFRCO in the Electrical Characteristics section. Updated the maximum current consumption of the HFRCO in the Electrical Characteristics section. Updated the maximum current consumption of the HFRCO in the Electrical Characteristics section. Added some minimum ADC SNR, SNDR, and SFDR specifications in the Electrical Characteristics section. Added some minimum and maximum ADC offset voltage, DNL, and INL specifications in the Electrical Characteristics section. Added maximum DAC current specifications in the Electrical Characteristics section. Added maximum ACMP current and maximum and minimum offset voltage specifications in the Electrical Characteristics section. Added maximum VCMP current and updated typical VCMP current specifications in the Electrical Characteristics section. Updated references to energyAware Designer to Configurator. 13.4 Revision 1.80 July 2nd, 2014 Corrected single power supply voltage minimum value from 1.85V to 1.98V. Updated current consumption. Updated transition between energy modes. Updated power management data. Updated GPIO data. Updated LFXO, HFXO, HFRCO and ULFRCO data. Updated LFRCO and HFRCO plots. For devices with an ACMP, updated ACMP data. silabs.com | Building a more connected world. Rev. 2.10 | 197 EFM32G Data Sheet Revision History 13.5 Revision 1.71 November 21st, 2013 Updated figures. Updated errata-link. Updated chip marking. Added link to Environmental and Quality information. For devices with a DAC, re-added missing DAC-data. 13.6 Revision 1.70 September 30th, 2013 For devices with an I2C, added I2C characterization data. Corrected GPIO operating voltage from 1.8 V to 1.85 V. For devices with an ADC, corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit. For QFN64 devices, updated the Max VESDCDM value to 750 V. Updated Environmental information. Updated trademark, disclaimer and contact information. Other minor corrections. 13.7 Revision 1.60 June 28th, 2013 For BGA devices, updated PCB Land Pattern, PCB Solder Mask and PCB Stencil Design figures. Updated power requirements in the Power Management section. Removed minimum load capacitance figure and table. Added reference to application note. Other minor corrections. 13.8 Revision 1.50 September 11th, 2012 Updated the HFRCO 1 MHz band typical value to 1.2 MHz. Updated the HFRCO 7 MHz band typical value to 6.6 MHz. For BGA devices, corrected BGA solder balls material from Sn96.5/Ag3/Cu0.5 to SAC105. Other minor corrections. silabs.com | Building a more connected world. Rev. 2.10 | 198 EFM32G Data Sheet Revision History 13.9 Revision 1.40 February 27th, 2012 Updated Power Management section. Corrected operating voltage from 1.8 V to 1.85 V. Corrected TGRADADCTH parameter. Corrected package drawing. Updated PCB land pattern, solder mask and stencil design. For LQFP48 devices, corrected available Pulse Counters from 3 to 2. For LQFP48 devices, corrected available LEUARTs from 2 to 1. For LQFP64 devices, corrected ordering codes in the ordering information table. 13.10 Revision 1.30 May 20th, 2011 This revision applies the following devices: * EFM32G200 * EFM32G210 * EFM32G230 * EFM32G280 * EFM32G290 * EFM32G840 * EFM32G880 * EFM32G890 Updated LFXO load capacitance section. silabs.com | Building a more connected world. Rev. 2.10 | 199 EFM32G Data Sheet Revision History 13.11 Revision 1.20 December 17th, 2010 This revision applies the following devices: * EFM32G200 * EFM32G210 * EFM32G230 * EFM32G280 * EFM32G290 * EFM32G840 * EFM32G880 * EFM32G890 Increased max storage temperature. Added data for <150C and <70C on Flash data retention. Changed latch-up sensitivity test description. Added IO leakage current. For LQFP100 devices, updated ESD CDM value. Added Flash current consumption. Updated HFRCO data. Updated LFRCO data. Added graph for ADC Absolute Offset over temperature. Added graph for ADC Temperature sensor readout. 13.12 Revision 1.11 November 17th, 2010 This revision applies the following devices: * EFM32G200 * EFM32G210 * EFM32G230 * EFM32G280 * EFM32G290 * EFM32G840 * EFM32G880 * EFM32G890 Corrected maximum DAC clock speed for continuous mode. Added DAC sample-hold mode voltage drift rate. Added pulse widths detected by the HFXO glitch detector. Added power sequencing information to Power Management section. silabs.com | Building a more connected world. Rev. 2.10 | 200 EFM32G Data Sheet Revision History 13.13 Revision 1.10 September 13th, 2010 This revision applies the following devices: * EFM32G200 * EFM32G210 * EFM32G230 * EFM32G280 * EFM32G290 * EFM32G840 * EFM32G880 * EFM32G890 For LQFP100 devices, corrected number of GPIO pins. Added typical values for RADCFILT and CADCFILT. Added two conditions for DAC clock frequency; one for sample/hold and one for sample/off. Added RoHS information and specified leadframe/solderballs material. Added Serial Bootloader to feature list and system summary. Updated ADC characterization data. Updated DAC characterization data. Updated RCO characterization data. Updated ACMP characterization data. Updated VCMP characterization data. 13.14 Revision 1.00 April 23rd, 2010 This revision applies the following devices: * EFM32G200 * EFM32G210 * EFM32G230 * EFM32G280 * EFM32G290 * EFM32G840 * EFM32G880 * EFM32G890 ADC_VCM line removed. Added pinout illustration and additional pinout table. Changed "Errata" chapter. Errata description moved to separate document. Document changed status from "Preliminary". Updated "Electrical Characteristics" chapter. For EFM32G222 May 20th, 2011 Updated LFXO load capacitance section. silabs.com | Building a more connected world. Rev. 2.10 | 201 EFM32G Data Sheet Revision History 13.15 Revision 0.90 This revision applies the following devices: * EFM32G222 Initial preliminary revision, April 14th, 2011 This revision applies the following devices: * EFM32G232 * EFM32G842 Initial preliminary revision, June 30th, 2011 13.16 Revision 0.85 February 19th, 2010 This revision applies the following devices: * EFM32G200 * EFM32G210 * EFM32G230 * EFM32G280 * EFM32G290 * EFM32G840 * EFM32G880 * EFM32G890 Renamed DBG_SWV pin to DBG_SWO. 13.17 Revision 0.84 February 11th, 2010 This revision applies the following devices: * EFM32G230 * EFM32G840 Corrected pinout tables. 13.18 Revision 0.83 January 25th, 2010 This revision applies the following devices: * EFM32G200 * EFM32G210 * EFM32G230 * EFM32G280 * EFM32G290 * EFM32G840 * EFM32G880 * EFM32G890 Updated errata section. Specified flash word width in Flash Electrical Characteristics. Added Capacitive Sense Internal Resistor values in ACMP Electrical Characteristics. silabs.com | Building a more connected world. Rev. 2.10 | 202 EFM32G Data Sheet Revision History 13.19 Revision 0.82 December 9th, 2009 This revision applies the following devices: * EFM32G200 * EFM32G210 * EFM32G230 * EFM32G280 * EFM32G290 * EFM32G840 * EFM32G880 * EFM32G890 For LQFP100 devices, incorrect pin 0 removed from pinout table. Updated contact information. ADC current consumption numbers updated in ADC Electrical Characteristics. For devices with LCD, updated LCD supply voltage range in LCD Electrical Characteristics. 13.20 Revision 0.81 November 20th, 2009 This revision applies the following devices: * EFM32G200 * EFM32G210 * EFM32G230 * EFM32G280 * EFM32G290 * EFM32G840 * EFM32G880 * EFM32G890 For devices without a differential DAC, System Summary updated. Electrical Characteristics updated. Storage temperature in Electrical Characteristics updated. Temperature coefficient of band-gap reference in Electrical Characteristics added. Erase times in Flash Electrical Characteristics updated. Definitions of DNL and INL added in ADC section. For devices with and LCD, LCD Electrical Characteristics added. Current consumption of digital peripherals added in Electrical Characteristics. For LQFP100 devices, package information in Pinout and Package corrected. For BGA112 devices, pinout information in Pinout table corrected. Updated errata section. silabs.com | Building a more connected world. Rev. 2.10 | 203 EFM32G Data Sheet Revision History 13.21 Revision 0.80 October 19th, 2009 This revision applies the following devices: * EFM32G200 * EFM32G210 * EFM32G230 * EFM32G280 * EFM32G290 * EFM32G840 * EFM32G880 * EFM32G890 Initial preliminary revision silabs.com | Building a more connected world. Rev. 2.10 | 204 Simplicity Studio One-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux! IoT Portfolio www.silabs.com/IoT SW/HW www.silabs.com/simplicity Quality www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. Trademark Information Silicon Laboratories Inc.(R) , Silicon Laboratories(R), Silicon Labs(R), SiLabs(R) and the Silicon Labs logo(R), Bluegiga(R), Bluegiga Logo(R), Clockbuilder(R), CMEMS(R), DSPLL(R), EFM(R), EFM32(R), EFR, Ember(R), Energy Micro, Energy Micro logo and combinations thereof, "the world's most energy friendly microcontrollers", Ember(R), EZLink(R), EZRadio(R), EZRadioPRO(R), Gecko(R), ISOmodem(R), Micrium, Precision32(R), ProSLIC(R), Simplicity Studio(R), SiPHY(R), Telegesis, the Telegesis Logo(R), USBXpress(R), Zentri and others are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders. Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 USA http://www.silabs.com