EFM32 Gecko Family
EFM32G Data Sheet
The EFM32 Gecko MCUs are the world’s most energy-friendly mi-
crocontrollers.
The EFM32G offers unmatched performance and ultra low power consumption in both
active and sleep modes. EFM32G devices consume as little as 0.6 μA in Stop mode and
180 μA/MHz in Run mode. It also features autonomous peripherals, high overall chip and
analog integration, and the performance of the industry standard 32-bit ARM Cortex-M3
processor, making it perfect for battery-powered systems and systems with high-per-
formance, low-energy requirements.
EFM32G applications include the following:
KEY FEATURES
• ARM Cortex-M3 at 32 MHz
• Ultra low power operation
• 0.6 μA current in Stop (EM3), with
brown-out detection and RAM retention
• 45 μA/MHz in EM1
• 180 μA/MHz in Run mode (EM0)
• Fast wake-up time of 2 µs
• Hardware cryptography (AES)
• Up to 128 kB of Flash and 16 kB of RAM
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
32-bit bus
Lowest power mode with peripheral operational:
EM2 – Deep Sleep
EM1 - Sleep EM4 - Shutoff
EM0 - Active EM3 - Stop
Core / Memory
Flash Program
Memory
RAM Memory
ARM CortexTM
M3 processor
Debug Interface
DMA Controller
Memory
Protection Unit
Security
Hardware AES
Energy Management
Brown-Out
Detector
Voltage
Regulator
Voltage
Comparator
Power-On Reset
Clock Management
High Frequency
RC Oscillator
Low Frequency
RC Oscillator
Low Frequency
Crystal
Oscillator
Watchdog
Oscillator
Auxiliary High
Freq. RC Osc.
High Frequency
Crystal Oscillator
Analog Interfaces
DACADC
LCD Controller Analog
Comparator
Peripheral Reflex System
Serial Interfaces
UART
I2C
I/O Ports Timers and Triggers
Timer/Counter
Low Energy Timer Watchdog Timer
External
Interrupts Pin Reset
External Bus
Interface
General
Purpose I/O
Pulse Counter
Real Time
Counter
USART
Low Energy
UARTTM
silabs.com | Building a more connected world. Rev. 2.10
1. Feature List
• ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 32 MHz
• Memory Protection Unit
• Wake-up Interrupt Controller
• SysTick System Timer
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention
• 0.9 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 45 µA/MHz @ 3 V Sleep Mode
• 180 µA/MHz @ 3 V Run Mode, with code executed from flash
• 128/64/32 KB Flash
• 16/8 KB RAM
• Up to 90 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 8 Channel DMA Controller
• 8 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• 3 × 16-bit Timer/Counter
• 3×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter
• 3× 8-bit Pulse Counter
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Integrated LCD Controller for up to 4×40 segments
• Voltage boost, adjustable contrast and autonomous animation
• External Bus Interface for up to 4x64 MB of external memory mapped space
• TFT Controller with Direct Drive
• Communication interfaces
• Up to 3× Universal Synchronous/Asynchronous Receiver/ Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• Triple buffered full/half-duplex operation
• 1× Universal Asynchronous Receiver/Transmitter
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
•I2C Interface with SMBus support
• Address recognition in Stop Mode
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single-ended channels/4 differential channels
• On-chip temperature sensor
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2 single-ended channels/1 differential channel
• 2× Analog Comparator
• Capacitive sensing with up to 16 inputs
EFM32G Data Sheet
Feature List
silabs.com | Building a more connected world. Rev. 2.10 | 2
• Supply Voltage Comparator
• Ultra efficient Power-on Reset and Brown-Out Detector
• 2-pin Serial Wire Debug Interface
• 1-pin Serial Wire Viewer
• Pre-Programmed USB/UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• Packages
• BGA112
• LQFP100
• TQFP64
• TQFP48
• QFN64
• QFN32
EFM32G Data Sheet
Feature List
silabs.com | Building a more connected world. Rev. 2.10 | 3
2. Ordering Information
The following table shows the available EFM32G devices.
Table 2.1. Ordering Information
Ordering Code Flash (kB) RAM (kB)
Max Speed
(MHz)
Supply Volt-
age (V)
Tempera-
ture (ºC) Package
EFM32G200F16G-E-QFN32 16 8 32 1.98 - 3.8 -40 - 85 QFN32
EFM32G200F32G-E-QFN32 32 8 32 1.98 - 3.8 -40 - 85 QFN32
EFM32G200F64G-E-QFN32 64 16 32 1.98 - 3.8 -40 - 85 QFN32
EFM32G210F128G-E-QFN32 128 16 32 1.98 - 3.8 -40 - 85 QFN32
EFM32G222F32G-E-QFP48 32 8 32 1.98 - 3.8 -40 - 85 TQFP48
EFM32G222F64G-E-QFP48 64 16 32 1.98 - 3.8 -40 - 85 TQFP48
EFM32G222F128G-E-QFP48 128 16 32 1.98 - 3.8 -40 - 85 TQFP48
EFM32G230F32G-E-QFN64 32 8 32 1.98 - 3.8 -40 - 85 QFN64
EFM32G230F64G-E-QFN64 64 16 32 1.98 - 3.8 -40 - 85 QFN64
EFM32G230F128G-E-QFN64 128 16 32 1.98 - 3.8 -40 - 85 QFN64
EFM32G232F32G-E-QFP64 32 8 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G232F64G-E-QFP64 64 16 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G232F128G-E-QFP64 128 16 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G280F32G-E-QFP100 32 8 32 1.98 - 3.8 -40 - 85 LQFP100
EFM32G280F64G-E-QFP100 64 16 32 1.98 - 3.8 -40 - 85 LQFP100
EFM32G280F128G-E-QFP100 128 16 32 1.98 - 3.8 -40 - 85 LQFP100
EFM32G290F32G-E-BGA112 32 8 32 1.98 - 3.8 -40 - 85 BGA112
EFM32G290F64G-E-BGA112 64 16 32 1.98 - 3.8 -40 - 85 BGA112
EFM32G290F128G-E-BGA112 128 16 32 1.98 - 3.8 -40 - 85 BGA112
EFM32G840F32G-E-QFN64 32 8 32 1.98 - 3.8 -40 - 85 QFN64
EFM32G840F64G-E-QFN64 64 16 32 1.98 - 3.8 -40 - 85 QFN64
EFM32G840F128G-E-QFN64 128 16 32 1.98 - 3.8 -40 - 85 QFN64
EFM32G842F32G-E-QFP64 32 8 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G842F64G-E-QFP64 64 16 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G842F128G-E-QFP64 128 16 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G880F32G-E-QFP100 32 8 32 1.98 - 3.8 -40 - 85 LQFP100
EFM32G880F64G-E-QFP100 64 16 32 1.98 - 3.8 -40 - 85 LQFP100
EFM32G880F128G-E-QFP100 128 16 32 1.98 - 3.8 -40 - 85 LQFP100
EFM32G890F32G-E-BGA112 32 8 32 1.98 - 3.8 -40 - 85 BGA112
EFM32G890F64G-E-BGA112 64 16 32 1.98 - 3.8 -40 - 85 BGA112
EFM32G890F128G-E-BGA112 128 16 32 1.98 - 3.8 -40 - 85 BGA112
EFM32G Data Sheet
Ordering Information
silabs.com | Building a more connected world. Rev. 2.10 | 4
EFM32 890 128F –BGA 112 R
Tape and Reel (Optional)
Pin Count
Package
Memory Size in kB
Memory Type (Flash)
Feature Set Code
Gecko
Energy Friendly Microcontroller 32-bit
G–E
Revision
Temperature Grade – G (-40 to +85 °C)
G
Figure 2.1. Ordering Code Decoder
Adding the suffix 'R' to the part number (e.g., EFM32G890F128G-E-BGA112R) denotes tape and reel.
Visit www.silabs.com for information on global distributors and representatives.
EFM32G Data Sheet
Ordering Information
silabs.com | Building a more connected world. Rev. 2.10 | 5
Table of Contents
1. Feature List ................................2
2. Ordering Information ............................4
3. System Overview .............................10
3.1 System Introduction ............................10
3.1.1 ARM Cortex-M3 Core .........................10
3.1.2 Debug Interface (DBG) .........................10
3.1.3 Memory System Controller (MSC) .....................10
3.1.4 Direct Memory Access Controller (DMA) ...................11
3.1.5 Reset Management Unit (RMU) ......................11
3.1.6 Energy Management Unit (EMU) .....................11
3.1.7 Clock Management Unit (CMU) ......................11
3.1.8 Watchdog (WDOG) ..........................11
3.1.9 Peripheral Reflex System (PRS) .....................11
3.1.10 External Bus Interface (EBI) ......................11
3.1.11 Inter-Integrated Circuit Interface (I2C) ...................11
3.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) ........11
3.1.13 Pre-Programmed USB/UART Bootloader ..................11
3.1.14 Universal Asynchronous Receiver/Transmitter (UART) .............12
3.1.15 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) ........12
3.1.16 Timer/Counter (TIMER) ........................12
3.1.17 Real Time Counter (RTC) .......................12
3.1.18 Low Energy Timer (LETIMER) ......................12
3.1.19 Pulse Counter (PCNT) ........................12
3.1.20 Analog Comparator (ACMP) ......................12
3.1.21 Voltage Comparator (VCMP) ......................12
3.1.22 Analog to Digital Converter (ADC) ....................12
3.1.23 Digital to Analog Converter (DAC) ....................12
3.1.24 Advanced Encryption Standard Accelerator (AES) ...............13
3.1.25 General Purpose Input/Output (GPIO) ...................13
3.1.26 Liquid Crystal Display Driver (LCD) ....................13
3.2 Configuration Summary ..........................14
3.2.1 EFM32G200 ............................14
3.2.2 EFM32G210 ............................15
3.2.3 EFM32G222 ............................16
3.2.4 EFM32G230 ............................17
3.2.5 EFM32G232 ............................18
3.2.6 EFM32G280 ............................19
3.2.7 EFM32G290 ............................20
3.2.8 EFM32G840 ............................21
3.2.9 EFM32G842 ............................22
3.2.10 EFM32G880 ............................23
3.2.11 EFM32G890 ............................25
3.3 Memory Map ..............................27
4. Electrical Characteristics ..........................29
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4.1 Test Conditions .............................29
4.1.1 Typical Values ...........................29
4.1.2 Minimum and Maximum Values ......................29
4.2 Absolute Maximum Ratings .........................29
4.3 General Operating Conditions ........................29
4.4 Current Consumption ...........................30
4.4.1 EM0 Current Consumption .......................31
4.4.2 EM1 Current Consumption .......................34
4.4.3 EM2 Current Consumption .......................37
4.4.4 EM3 Current Consumption .......................38
4.4.5 EM4 Current Consumption .......................39
4.5 Transition between Energy Modes .......................39
4.6 Power Management ............................40
4.7 Flash .................................41
4.8 General Purpose Input Output ........................42
4.9 Oscillators ...............................50
4.9.1 LFXO...............................50
4.9.2 HFXO ..............................51
4.9.3 LFRCO ..............................52
4.9.4 HFRCO ..............................53
4.9.5 AUXHFRCO ............................57
4.9.6 ULFRCO .............................57
4.10 Analog Digital Converter (ADC) .......................58
4.10.1 Typical Performance .........................67
4.11 Digital Analog Converter (DAC) .......................71
4.12 Analog Comparator (ACMP) ........................73
4.13 Voltage Comparator (VCMP) ........................75
4.14 LCD .................................76
4.15 I2C .................................77
4.16 Digital Peripherals ............................78
5. Pin Definitions ..............................79
5.1 EFM32G200 & EFM32G210 (QFN32) ......................79
5.1.1 Pinout ..............................79
5.1.2 Alternate Functionality Pinout ......................82
5.1.3 GPIO Pinout Overview .........................84
5.2 EFM32G222 (TQFP48)...........................85
5.2.1 Pinout ..............................85
5.2.2 Alternate Functionality Pinout ......................88
5.2.3 GPIO Pinout Overview .........................90
5.3 EFM32G230 (QFN64) ...........................91
5.3.1 Pinout ..............................91
5.3.2 Alternate Functionality Pinout ......................94
5.3.3 GPIO Pinout Overview .........................97
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5.4 EFM32G232 (TQFP64)...........................98
5.4.1 Pinout ..............................98
5.4.2 Alternate Functionality Pinout .....................101
5.4.3 GPIO Pinout Overview ........................103
5.5 EFM32G280 (LQFP100) .........................104
5.5.1 Pinout .............................104
5.5.2 Alternate Functionality Pinout .....................109
5.5.3 GPIO Pinout Overview ........................113
5.6 EFM32G290 (BGA112)..........................114
5.6.1 Pinout .............................114
5.6.2 Alternate Functionality Pinout .....................119
5.6.3 GPIO Pinout Overview ........................123
5.7 EFM32G840 (QFN64) ..........................124
5.7.1 Pinout .............................124
5.7.2 Alternate Functionality Pinout .....................127
5.7.3 GPIO Pinout Overview ........................131
5.8 EFM32G842 (TQFP64)..........................132
5.8.1 Pinout .............................132
5.8.2 Alternate Functionality Pinout .....................135
5.8.3 GPIO Pinout Overview ........................139
5.9 EFM32G880 (LQFP100) .........................140
5.9.1 Pinout .............................140
5.9.2 Alternate Functionality Pinout .....................146
5.9.3 GPIO Pinout Overview ........................152
5.10 EFM32G890 (BGA112) .........................153
5.10.1 Pinout .............................153
5.10.2 Alternate Functionality Pinout .....................159
5.10.3 GPIO Pinout Overview .......................165
6. BGA112 Package Specifications .......................166
6.1 BGA112 Package Dimensions .......................166
6.2 BGA112 PCB Layout ..........................167
6.3 BGA112 Package Marking ........................169
7. LQFP100 Package Specifications .......................170
7.1 LQFP100 Package Dimensions .......................170
7.2 LQFP100 PCB Layout ..........................172
7.3 LQFP100 Package Marking ........................174
8. TQFP64 Package Specifications .......................175
8.1 TQFP64 Package Dimensions .......................175
8.2 TQFP64 PCB Layout ..........................177
8.3 TQFP64 Package Marking ........................179
9. TQFP48 Package Specifications .......................180
9.1 TQFP48 Package Dimensions .......................180
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9.2 TQFP48 PCB Layout ..........................182
9.3 TQFP48 Package Marking ........................184
10. QFN64 Package Specifications .......................185
10.1 QFN64 Package Dimensions .......................185
10.2 QFN64 PCB Layout ..........................187
10.3 QFN64 Package Marking ........................189
11. QFN32 Package Specifications .......................190
11.1 QFN32 Package Dimensions .......................190
11.2 QFN32 PCB Layout ..........................191
11.3 QFN32 Package Marking ........................193
12. Chip Revision, Solder Information, Errata ...................194
12.1 Chip Revision ............................194
12.2 Soldering Information ..........................194
12.3 Errata ...............................194
13. Revision History.............................195
13.1 Revision 2.10 ............................195
13.2 Revision 2.00 ............................196
13.3 Revision 1.90 ............................197
13.4 Revision 1.80 ............................197
13.5 Revision 1.71 ............................198
13.6 Revision 1.70 ............................198
13.7 Revision 1.60 ............................198
13.8 Revision 1.50 ............................198
13.9 Revision 1.40 ............................199
13.10 Revision 1.30 ............................199
13.11 Revision 1.20 ............................200
13.12 Revision 1.11 ............................200
13.13 Revision 1.10 ............................201
13.14 Revision 1.00 ............................201
13.15 Revision 0.90 ............................202
13.16 Revision 0.85 ............................202
13.17 Revision 0.84 ............................202
13.18 Revision 0.83 ............................202
13.19 Revision 0.82 ............................203
13.20 Revision 0.81 ............................203
13.21 Revision 0.80 ............................204
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3. System Overview
3.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-
M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32G
microcontroller is well suited for any battery operated application as well as other systems requiring high performance and low-energy
consumption. This section gives a short introduction to each of the modules in general terms and also shows a summary of the configu-
ration for the EFM32G devices. For a complete feature set and in-depth information on the modules, the reader is referred to the
EFM32G Reference Manual.
The diagram shows a superset of features available on the family, which vary by OPN. For more information about specific device fea-
tures, consult Ordering Information.
32-bit bus
Lowest power mode with peripheral operational:
EM2 – Deep Sleep
EM1 - Sleep EM4 - Shutoff
EM0 - Active EM3 - Stop
Core / Memory
Flash Program
Memory
RAM Memory
ARM CortexTM
M3 processor
Debug Interface
DMA Controller
Memory
Protection Unit
Security
Hardware AES
Energy Management
Brown-Out
Detector
Voltage
Regulator
Voltage
Comparator
Power-On Reset
Clock Management
High Frequency
RC Oscillator
Low Frequency
RC Oscillator
Low Frequency
Crystal
Oscillator
Watchdog
Oscillator
Auxiliary High
Freq. RC Osc.
High Frequency
Crystal Oscillator
Analog Interfaces
DACADC
LCD Controller Analog
Comparator
Peripheral Reflex System
Serial Interfaces
UART
I2C
I/O Ports Timers and Triggers
Timer/Counter
Low Energy Timer Watchdog Timer
External
Interrupts Pin Reset
External Bus
Interface
General
Purpose I/O
Pulse Counter
Real Time
Counter
USART
Low Energy
UARTTM
Figure 3.1. Block Diagram
3.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection
Unit with support for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts triggered while
the CPU is asleep. The EFM32 implementation of the Cortex-M3 is described in detail in EFM32G Reference Manual.
3.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface . In addition there is also a 1-wire Serial Wire
Viewer pin which can be used to output profiling information, data trace and software-generated messages.
3.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32G microcontroller. The flash memory is readable and
writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block.
Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock
bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations
are supported in the energy modes EM0 and EM1.
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 10
3.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing
the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance
data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230
µDMA controller licensed from ARM.
3.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32G.
3.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32G microcontrollers. Each energy mode man-
ages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks.
3.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32G. The CMU provides
the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the
available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not
wasting power on peripherals and oscillators that are inactive.
3.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may
e.g. be caused by an external event, such as an ESD pulse, or by a software failure.
3.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each
other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex
signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but
edge triggers and other functionality can be applied by the PRS.
3.1.10 External Bus Interface (EBI)
The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH, ADCs and LCDs. The inter-
face is memory mapped into the address bus of the Cortex-M3. This enables seamless access from software without manually manipu-
lating the IO settings each time a read or write is performed. The data and address lines are multiplexed in order to reduce the number
of pins required to interface the external devices. The timing is adjustable to meet specifications of the external devices. The interface is
limited to asynchronous devices.
3.1.11 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as both a master and a slave, and
supports multi-master buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all
the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant
system. The interface provided to software by the I2C module, allows both fine-grained control of the transmission process and close to
automatic transfers. Automatic recognition of slave addresses is provided in all energy modes.
3.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full
duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 Smart-
Cards, and IrDA devices.
3.1.13 Pre-Programmed USB/UART Bootloader
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Autobaud and destructive write are
supported. The autobaud feature, interface and commands are described further in the application note.
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 11
3.1.14 Universal Asynchronous Receiver/Transmitter (UART)
The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module. It supports full- and half-du-
plex asynchronous UART communication.
3.1.15 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on a strict power budget. Only a
32.768 kHz clock is needed to allow UART communication up to 9600 baud/ s. The LEUART includes all necessary hardware support
to make asynchronous serial communication possible with minimum of software intervention and energy consumption.
3.1.16 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-Width Modulation (PWM) out-
put. TIMER0 also includes a Dead-Time Insertion module suitable for motor control applications.
3.1.17 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal oscillator, or a 32.768 kHz RC
oscillator. In addition to energy modes EM0 and EM1, the RTC is also available in EM2. This makes it ideal for keeping track of time
since the RTC is enabled in EM2 where most of the device is powered down.
3.1.18 Low Energy Timer (LETIMER)
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2 in addition to EM1 and EM0.
Because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks to be
performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of
waveforms with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be configured to start
counting on compare matches from the RTC.
3.1.19 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature encoded inputs. It runs off either
the internal LFACLK or the PCNTn_S0IN pin as external clock source. The module may operate in energy mode EM0 - EM3.
3.1.20 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs can either be one of the selectable internal references or from external pins. Response time and thereby also the current
consumption can be configured by altering the current supply to the comparator.
3.1.21 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can be generated when the supply
falls below or rises above a programmable threshold. Response time and thereby also the current consumption can be configured by
altering the current supply to the comparator.
3.1.22 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per
second. The integrated input mux can select inputs from 8 external pins and 6 internal signals.
3.1.23 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC is fully differential rail-to-rail,
with 12-bit resolution. It has two single-ended output buffers which can be combined into one differential output. The DAC may be used
for a number of different applications such as sensor interfaces or sound output.
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 12
3.1.24 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data
block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave
which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or
16-bit operations are not supported.
3.1.25 General Purpose Input/Output (GPIO)
General Purpose Input/Output (GPIO) pins are organized into ports with up to 16 pins each. These pins can individually be configured
as either an output or input. More advanced configurations like open-drain, filtering and drive strength can also be configured individual-
ly for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM outputs or USART communica-
tion, which can be routed to several locations on the device. The GPIO supports up to 16 asynchronous external pin interrupts, which
enables interrupts from any pin on the device. Also, the input value of a pin can be routed through the Peripheral Reflex System to
other peripherals.
3.1.26 Liquid Crystal Display Driver (LCD)
The LCD driver is capable of driving a segmented LCD display with up to 4x40 segments. A voltage boost function enables it to provide
the LCD display with higher voltage than the supply voltage for the device. In addition, an animation feature can run custom animations
on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame
Counter interrupt that can wake-up the device on a regular basis for updating data.
EFM32G Data Sheet
System Overview
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3.2 Configuration Summary
3.2.1 EFM32G200
The features of the EFM32G200 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.1. EFM32G200 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
ACMP0 Full configuration ACMP0_CH[1:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:5], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:4]
DAC0 Full configuration DAC0_OUT[0]
GPIO 24 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
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3.2.2 EFM32G210
The features of the EFM32G210 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.2. EFM32G210 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
ACMP0 Full configuration ACMP0_CH[1:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:5], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:4]
DAC0 Full configuration DAC0_OUT[0]
AES Full configuration NA
GPIO 24 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 15
3.2.3 EFM32G222
The features of the EFM32G222 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.3. EFM32G222 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
ACMP0 Full configuration ACMP0_CH[4:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:4]
DAC0 Full configuration DAC0_OUT[1]
AES Full configuration NA
GPIO 37 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 16
3.2.4 EFM32G230
The features of the EFM32G230 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.4. EFM32G230 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[1:0]
AES Full configuration NA
GPIO 56 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 17
3.2.5 EFM32G232
The features of the EFM32G232 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.5. EFM32G232 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[15:8], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[0]
AES Full configuration NA
GPIO 53 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 18
3.2.6 EFM32G280
The features of the EFM32G280 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.6. EFM32G280 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
EBI Full configuration EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn,
EBI_CS[3:0], EBI_AD[15:0]
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
UART0 Full configuration U0_TX, U0_RX
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[1:0]
AES Full configuration NA
GPIO 86 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 19
3.2.7 EFM32G290
The features of the EFM32G290 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.7. EFM32G290 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
EBI Full configuration EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn,
EBI_CS[3:0], EBI_AD[15:0]
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
UART0 Full configuration U0_TX, U0_RX
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[1:0]
AES Full configuration NA
GPIO 90 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 20
3.2.8 EFM32G840
The features of the EFM32G840 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.8. EFM32G840 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:4], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:4], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[1:0]
AES Full configuration NA
GPIO 56 pins Available pins are shown in Table 4.3 (p. 57)
LCD Full configuration LCD_SEG[23:0], LCD_COM[3:0], LCD_BCAP_P,
LCD_BCAP_N, LCD_BEXT
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 21
3.2.9 EFM32G842
The features of the EFM32G842 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.9. EFM32G842 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[3:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:4], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[0]
AES Full configuration NA
GPIO 53 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 22
3.2.10 EFM32G880
The features of the EFM32G880 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.10. EFM32G880 Configuration Summary
Module Module Module
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
EBI Full configuration EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn,
EBI_CS[3:0], EBI_AD[15:0]
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
UART0 Full configuration U0_TX, U0_RX
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[1:0]
AES Full configuration NA
GPIO 86 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 23
Module Module Module
LCD Full configuration LCD_SEG[39:0], LCD_COM[3:0], LCD_BCAP_P,
LCD_BCAP_N, LCD_BEXT
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 24
3.2.11 EFM32G890
The features of the EFM32G890 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.11. EFM32G890 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
EBI Full configuration EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn,
EBI_CS[3:0], EBI_AD[15:0]
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
UART0 Full configuration U0_TX, U0_RX
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[1:0]
AES Full configuration NA
GPIO 90 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 25
Module Configuration Pin Connections
LCD Full configuration LCD_SEG[39:0], LCD_COM[7:0], LCD_BCAP_P,
LCD_BCAP_N, LCD_BEXT
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 26
3.3 Memory Map
The EFM32G memory map is shown in the figure below. RAM and Flash sizes are for the largest memory configuration.
Figure 3.2. System Address Space with Core and Code Space Listing
EFM32G Data Sheet
System Overview
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Figure 3.3. System Address Space with Peripheral Listing
EFM32G Data Sheet
System Overview
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4. Electrical Characteristics
4.1 Test Conditions
4.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 4.2 General Operating Conditions on page 29, unless
otherwise specified.
4.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined
in Table 4.2 General Operating Conditions on page 29, unless otherwise specified.
4.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are not guaranteed. Stress beyond
the limits specified in the following table may affect the device reliability or cause permanent damage to the device. Functional operat-
ing conditions are given in Table 4.2 General Operating Conditions on page 29.
Table 4.1. Absolute Maximum Ratings
Parameter Symbol Test Condition Min Typ Max Unit
Storage temperature range TSTG -40 — 150 °C
Maximum soldering temperature TSLatest IPC/JEDEC J-
STD-020 Standard
— — 260 °C
External main supply voltage VDDMAX 0 — 3.8 V
Voltage on any I/O pin VIOPIN -0.3 — VDD+0.3 V
Current per I/O pin (sink) IIOMAX_SINK — — 100 mA
Current per I/O pin (source) IIOMAX_SOURCE — — -100 mA
4.3 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter Symbol Min Typ Max Unit
Ambient temperature range TAMB -40 — 85 °C
Operating supply voltage VDDOP 1.98 — 3.8 V
Internal APB clock frequency fAPB — — 32 MHz
Internal AHB clock frequency fAHB — — 32 MHz
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 29
4.4 Current Consumption
Table 4.3. Current Consumption
Parameter Symbol Test Condition Min Typ Max Unit
EM0 current. No prescaling.
Running prime number cal-
culation code from Flash.
(Production test condition =
14 MHz)
IEM0
32 MHz HFXO, all peripheral clocks disabled,
VDD= 3.0 V
— 180 — µA/MHz
28 MHz HFRCO, all peripheral clocks disabled,
VDD= 3.0 V
— 181 206 µA/MHz
21 MHz HFRCO, all peripheral clocks disabled,
VDD= 3.0 V
— 183 207 µA/MHz
14 MHz HFRCO, all peripheral clocks disabled,
VDD= 3.0 V
— 185 211 µA/MHz
11 MHz HFRCO, all peripheral clocks disabled,
VDD= 3.0 V
— 186 215 µA/MHz
6.6 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
— 191 218 µA/MHz
1.2 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
— 220 — µA/MHz
EM1 current (Production test
condition = 14 MHz) IEM1
32 MHz HFXO, all peripheral clocks disabled,
VDD= 3.0 V
— 45 — µA/MHz
28 MHz HFRCO, all peripheral clocks disabled,
VDD= 3.0 V
— 47 62 µA/MHz
21 MHz HFRCO, all peripheral clocks disabled,
VDD= 3.0 V
— 48 64 µA/MHz
14 MHz HFRCO, all peripheral clocks disabled,
VDD= 3.0 V
— 50 69 µA/MHz
11 MHz HFRCO, all peripheral clocks disabled,
VDD= 3.0 V
— 51 72 µA/MHz
6.6 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
— 56 83 µA/MHz
1.2 MHz HFRCO. all peripheral clocks disa-
bled, VDD= 3.0 V
— 103 — µA/MHz
EM2 current IEM2
EM2 current with RTC prescaled to 1 Hz,
32.768 kHz LFRCO, VDD= 3.0 V, TAMB=25 ºC
— 0.9 1.5 μA
EM2 current with RTC prescaled to 1 Hz,
32.768 kHz LFRCO, VDD= 3.0 V, TAMB=85 ºC
— 3.0 6.0 µA
EM3 current IEM3
VDD= 3.0 V, TAMB=25 ºC — 0.59 1.0 µA
VDD= 3.0 V, TAMB=85 ºC — 2.75 5.8 µA
EM4 current IEM4
VDD= 3.0 V, TAMB=25 ºC — 0.02 0.045 µA
VDD= 3.0 V, TAMB=85 ºC — 0.25 0.7 µA
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 30
4.4.1 EM0 Current Consumption
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Idd [mA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Idd [mA]
Vdd=2.0V
Vdd=2.2V
Vdd=2.4V
Vdd=2.6V
Vdd=2.8V
Vdd=3.0V
Vdd=3.2V
Vdd=3.4V
Vdd=3.6V
Vdd=3.8V
Figure 4.1. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 28
MHz
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 31
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
3.5
3.6
3.7
3.8
3.9
4.0
Idd [mA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
3.5
3.6
3.7
3.8
3.9
4.0
Idd [mA]
Vdd=2.0V
Vdd=2.2V
Vdd=2.4V
Vdd=2.6V
Vdd=2.8V
Vdd=3.0V
Vdd=3.2V
Vdd=3.4V
Vdd=3.6V
Vdd=3.8V
Figure 4.2. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 21
MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
Idd [mA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
Idd [mA]
Vdd=2.0V
Vdd=2.2V
Vdd=2.4V
Vdd=2.6V
Vdd=2.8V
Vdd=3.0V
Vdd=3.2V
Vdd=3.4V
Vdd=3.6V
Vdd=3.8V
Figure 4.3. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 14
MHz
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 32
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
Idd [mA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
Idd [mA]
Vdd=2.0V
Vdd=2.2V
Vdd=2.4V
Vdd=2.6V
Vdd=2.8V
Vdd=3.0V
Vdd=3.2V
Vdd=3.4V
Vdd=3.6V
Vdd=3.8V
Figure 4.4. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 11
MHz
–40 –15 5 25 45 65 85
Temperature [°C]
1.20
1.25
1.30
1.35
1.40
1.45
Idd [mA]
Vdd=2.0V
Vdd=2.2V
Vdd=2.4V
Vdd=2.6V
Vdd=2.8V
Vdd=3.0V
Vdd=3.2V
Vdd=3.4V
Vdd=3.6V
Vdd=3.8V
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
1.20
1.25
1.30
1.35
1.40
1.45
Idd [mA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
Figure 4.5. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 7
MHz
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 33
4.4.2 EM1 Current Consumption
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
1.15
1.20
1.25
1.30
1.35
1.40
Idd [mA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
1.15
1.20
1.25
1.30
1.35
1.40
Idd [mA]
Vdd=2.0V
Vdd=2.4V
Vdd=2.8V
Vdd=3.0V
Vdd=3.4V
Vdd=3.8V
Figure 4.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 28 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
Idd [mA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
Idd [mA]
Vdd=2.0V
Vdd=2.4V
Vdd=2.8V
Vdd=3.0V
Vdd=3.4V
Vdd=3.8V
Figure 4.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21 MHz
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 34
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.64
0.66
0.68
0.70
0.72
0.74
0.76
Idd [mA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.64
0.66
0.68
0.70
0.72
0.74
0.76
Idd [mA]
Vdd=2.0V
Vdd=2.4V
Vdd=2.8V
Vdd=3.0V
Vdd=3.4V
Vdd=3.8V
Figure 4.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.52
0.54
0.56
0.58
0.60
0.62
Idd [mA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.52
0.54
0.56
0.58
0.60
0.62
Idd [mA]
Vdd=2.0V
Vdd=2.4V
Vdd=2.8V
Vdd=3.0V
Vdd=3.4V
Vdd=3.8V
Figure 4.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11 MHz
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 35
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.36
0.37
0.38
0.39
0.40
0.41
0.42
0.43
0.44
Idd [mA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.36
0.37
0.38
0.39
0.40
0.41
0.42
0.43
0.44
Idd [mA]
Vdd=2.0V
Vdd=2.4V
Vdd=2.8V
Vdd=3.0V
Vdd=3.4V
Vdd=3.8V
Figure 4.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 7 MHz
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 36
4.4.3 EM2 Current Consumption
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Idd [uA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Idd [uA]
Vdd=1.8V
Vdd=2.2V
Vdd=2.6V
Vdd=3.0V
Vdd=3.4V
Vdd=3.8V
Figure 4.11. EM2 Current Consumption, RTC prescaled to 1 kHz, 32.768 kHz LFRCO
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 37
4.4.4 EM3 Current Consumption
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Idd [uA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Idd [uA]
Vdd=1.8V
Vdd=2.2V
Vdd=2.6V
Vdd=3.0V
Vdd=3.4V
Vdd=3.8V
Figure 4.12. EM3 Current Consumption
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 38
4.4.5 EM4 Current Consumption
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd [V]
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
Idd [uA]
-40.0°C
-15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85
Temperature [°C]
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
Idd [uA]
Vdd=1.8V
Vdd=2.2V
Vdd=2.6V
Vdd=3.0V
Vdd=3.4V
Vdd=3.8V
Figure 4.13. EM4 Current Consumption
4.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
Table 4.4. Energy Modes Transitions
Parameter Symbol Min Typ Max Unit
Transition time from EM1 to EM0 tEM10 — 0 — HFCORECLK
cycles
Transition time from EM2 to EM0 tEM20 — 2 — µs
Transition time from EM3 to EM0 tEM30 — 2 — µs
Transition time from EM4 to EM0 tEM40 — 163 — µs
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 39
4.6 Power Management
The EFM32G requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with optional filter) at the PCB level. For
practical schematic recommendations, please see the application note, "AN0002 EFM32 Hardware Design Considerations".
Table 4.5. Power Management
Parameter Symbol Test Condition Min Typ Max Unit
BOD threshold on falling external sup-
ply voltage
VBODextthr- EM0 1.74 — 1.96 V
EM1 1.74 — 1.96 V
EM2 1.74 — 1.96 V
BOD threshold on rising external sup-
ply voltage
VBODextthr+ EM0 — 1.85 — V
Power-on Reset (POR) threshold on
rising external supply voltage
VPORthr+ — — 1.98 V
Delay from reset is released until pro-
gram execution starts
tRESETdly Applies to Power-on Re-
set, Brown-out Reset and
pin reset.
— 163 — µs
negative pulse length to ensure com-
plete reset of device
tRESET 50 — — ns
Voltage regulator decoupling capaci-
tor.
CDECOUPLE X5R capacitor recom-
mended. Apply between
DECOUPLE pin and
GROUND
— 1 — µF
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 40
4.7 Flash
Table 4.6. Flash
Parameter Symbol Test Condition Min Typ Max Unit
Flash erase cycles before failure ECFLASH 20000 — — cycles
Flash data retention RETFLASH
TAMB<150 ºC 10000 — — h
TAMB<85 ºC 10 — — years
TAMB<70 ºC 20 — — years
Word (32-bit) programming time tW_PROG 20 — — µs
Page erase time2tP_ERASE 20.7 22.0 24.8 ms
Device erase time3tD_ERASE 41.8 45.0 49.2 ms
Erase current IERASE — — 71mA
Write current IWRITE — — 71mA
Supply voltage during flash erase and
write
VFLASH 1.98 — 3.8 V
Note:
1. Measured at 25 °C.
2. From setting ERASEPAGE bit in MSC_WRITECMD to 1 to reading 1 in ERASE bit in MSC_IF. Internal setup and hold times for
flash control signals are included.
3. From setting DEVICEERASE bit in AAP_CMD to 1 to reading 0 in ERASEBUSY bit in AAP_STATUS. Internal setup and hold
times for flash control signals are included.
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 41
4.8 General Purpose Input Output
Table 4.7. GPIO
Parameter Symbol Test Condition Min Typ Max Unit
Input low voltage VIOIL — — 0.30×VDD1V
Input high voltage VIOIH 0.70×VDD1— — V
Output high voltage (Production
test condition = 3.0 V, DRIVE-
MODE = STANDARD)
VIOOH
Sourcing 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
— 0.80×VDD — V
Sourcing 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
— 0.90×VDD — V
Sourcing 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
— 0.85×VDD — V
Sourcing 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
— 0.90×VDD — V
Sourcing 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.75×VDD — — V
Sourcing 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.85×VDD — — V
Sourcing 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.60×VDD — — V
Sourcing 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.80×VDD — — V
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 42
Parameter Symbol Test Condition Min Typ Max Unit
Output low voltage (Production
test condition = 3.0 V, DRIVE-
MODE = STANDARD)
VIOOL
Sinking 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
— 0.20×VDD — V
Sinking 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
— 0.10×VDD — V
Sinking 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
— 0.10×VDD — V
Sinking 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
— 0.05×VDD — V
Sinking 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
— — 0.30×VDD V
Sinking 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
— — 0.20×VDD V
Sinking 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
— — 0.35×VDD V
Sinking 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
— — 0.25×VDD V
Input leakage current IIOLEAK High Impedance IO connected
to GROUND or VDD
— ±0.1 ±40 nA
I/O pin pull-up resistor RPU — 40 — kΩ
I/O pin pull-down resistor RPD — 40 — kΩ
Internal ESD series resistor RIOESD — 200 — Ω
Pulse width of pulses to be re-
moved by the glitch suppres-
sion filter
tIOGLITCH 10 — 50 ns
Output fall time tIOOF
GPIO_Px_CTRL DRIVEMODE
= LOWEST and load capaci-
tance CL=12.5-25pF.
20+0.1CL— 250 ns
GPIO_Px_CTRL DRIVEMODE
= LOW and load capacitance
CL=350-600pF
20+0.1CL— 250 ns
I/O pin hysteresis (VIOTHR+ -
VIOTHR-)
VIOHYST VDD = 1.98 - 3.8 V 0.1×VDD — — V
Note:
1. If the GPIO input voltage is between 0.3×VDD and 0.7×VDD, the current consumption will increase.
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 43
0.0 0.5 1.0 1.5 2.0
Low-Level Output Voltage [V]
0.00
0.05
0.10
0.15
0.20
Low-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0
Low-Level Output Voltage [V]
0
5
10
15
20
25
30
35
40
45
Low-Level Output Current [mA]
-40°C
25°C
85°C
0.0 0.5 1.0 1.5 2.0
Low-Level Output Voltage [V]
0
5
10
15
20
Low-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0
Low-Level Output Voltage [V]
0
1
2
3
4
5
Low-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD GPIO_Px_CTRL DRIVEMODE = HIGH
Figure 4.14. Typical Low-Level Output Current, 2V Supply Voltage
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 44
0.0 0.5 1.0 1.5 2.0
High-Level Output Voltage [V]
–0.20
–0.15
–0.10
–0.05
0.00
High-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0
High-Level Output Voltage [V]
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
High-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0
High-Level Output Voltage [V]
–20
–15
–10
–5
0
High-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0
High-Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
Figure 4.15. Typical High-Level Output Current, 2V Supply Voltage
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 45
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low-Level Output Voltage [V]
0
2
4
6
8
10
Low-Level Output Current [mA]
-40°C
25°C
85°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low-Level Output Voltage [V]
0.0
0.1
0.2
0.3
0.4
0.5
Low-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low-Level Output Voltage [V]
0
10
20
30
40
50
Low-Level Output Current [mA]
-40°C
25°C
85°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low-Level Output Voltage [V]
0
5
10
15
20
25
30
35
40
Low-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD GPIO_Px_CTRL DRIVEMODE = HIGH
Figure 4.16. Typical Low-Level Output Current, 3V Supply Voltage
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 46
0.0 0.5 1.0 1.5 2.0 2.5 3.0
High-Level Output Voltage [V]
–6
–5
–4
–3
–2
–1
0
High-Level Output Current [mA]
-40°C
25°C
85°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0
High-Level Output Voltage [V]
–0.5
–0.4
–0.3
–0.2
–0.1
0.0
High-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0
High-Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High-Level Output Current [mA]
-40°C
25°C
85°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0
High-Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD GPIO_Px_CTRL DRIVEMODE = HIGH
Figure 4.17. Typical High-Level Output Current, 3V Supply Voltage
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 47
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low-Level Output Voltage [V]
0
10
20
30
40
50
Low-Level Output Current [mA]
-40°C
25°C
85°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low-Level Output Voltage [V]
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Low-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low-Level Output Voltage [V]
0
10
20
30
40
50
Low-Level Output Current [mA]
-40°C
25°C
85°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low-Level Output Voltage [V]
0
2
4
6
8
10
12
14
Low-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
GPIO_Px_CTRL DRIVEMODE = STANDARD GPIO_Px_CTRL DRIVEMODE = HIGH
Figure 4.18. Typical Low-Level Output Current, 3.8V Supply Voltage
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 48
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High-Level Output Voltage [V]
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0.0
High-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High-Level Output Voltage [V]
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
High-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High-Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High-Level Output Voltage [V]
–50
–40
–30
–20
–10
0
High-Level Output Current [mA]
-40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
Figure 4.19. Typical High-Level Output Current, 3.8V Supply Voltage
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 49
4.9 Oscillators
4.9.1 LFXO
Table 4.8. LFXO
Parameter Symbol Test Condition Min Typ Max Unit
Supported nominal crystal fre-
quency
fLFXO — 32.768 — kHz
Supported crystal equivalent ser-
ies resistance (ESR)
ESRLFXO — 30 120 kOhm
Supported crystal external load
range
CLFXOL X1— 25 pF
Current consumption for core and
buffer after startup
ILFXO ESR=30 kΩ, CL=10 pF, LFXO-
BOOST in CMU_CTRL is 1
— 190 — nA
Start-up time tLFXO ESR=30 kΩ, CL=10 pF, 40% -
60% duty cycle has been
reached, LFXOBOOST in
CMU_CTRL is 1
— 400 — ms
Note:
1. See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in Configurator in Simplicity Studio.
For safe startup of a given crystal, the Configurator tool in Simplicity Studio contains a tool to help users configure both load capaci-
tance and software settings for using the LFXO. For details regarding the crystal configuration, the reader is referred to application note
"AN0016 EFM32 Oscillator Design Consideration".
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 50
4.9.2 HFXO
Table 4.9. HFXO
Parameter Symbol Test Condition Min Typ Max Unit
Supported nominal crystal Fre-
quency
fHFXO 4 — 32 MHz
Supported crystal equivalent ser-
ies resistance (ESR) ESRHFXO
Crystal frequency 32 MHz — 30 60 Ω
Crystal frequency 4 MHz — 400 1500 Ω
The transconductance of the
HFXO input transistor at crystal
startup
gmHFXO HFXOBOOST in CMU_CTRL
equals 0b11
20 — — mS
Supported crystal external load
range
CHFXOL 5 — 25 pF
Current consumption for HFXO
after startup IHFXO
4 MHz: ESR=400 Ω, CL=20 pF,
HFXOBOOST in CMU_CTRL
equals 0b11
— 85 — µA
32 MHz: ESR=30 Ω, CL=10 pF,
HFXOBOOST in CMU_CTRL
equals 0b11
— 165 — µA
Startup time
tHFXO
32 MHz: ESR=30 Ω, CL=10 pF,
HFXOBOOST in CMU_CTRL
equals 0b11
— 400 — µs
Pulse width removed by glitch de-
tector
1 — 4 ns
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 51
4.9.3 LFRCO
Table 4.10. LFRCO
Parameter Symbol Test Condition Min Typ Max Unit
Oscillation frequency, VDD= 3.0
V, TAMB=25°C
fLFRCO 31.29 32.768 34.24 kHz
Startup time not including soft-
ware calibration
tLFRCO — 150 — µs
Current consumption ILFRCO — 190 — nA
Temperature coefficient TCLFRCO — ±0.02 — %/°C
Supply voltage coefficient VCLFRCO — ±15 — %/V
Frequency step for LSB change
in TUNING value
TUNESTEPLFRCO — 1.5 — %
Figure 4.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 52
4.9.4 HFRCO
Table 4.11. HFRCO
Parameter Symbol Test Condition Min Typ Max Unit
Oscillation frequency, VDD= 3.0
V, TAMB=25 ºC fHFRCO
28 MHz frequency band 27.16 28 28.84 MHz
21 MHz frequency band 20.37 21 21.63 MHz
14 MHz frequency band 13.58 14 14.42 MHz
11 MHz frequency band 10.67 11 11.33 MHz
7 MHz frequency band 6.402 6.616.798 MHz
1 MHz frequency band 1.164 1.221.236 MHz
Settling time tHFRCO_settling
After start-up, fHFRCO = 14 MHz — 0.6 — Cycles
After band switch — 25 — Cycles
Current consumption (Produc-
tion test condition = 14 MHz) IHFRCO
fHFRCO = 28 MHz — 158 190 µA
fHFRCO = 21 MHz — 125 155 µA
fHFRCO = 14 MHz — 99 120 µA
fHFRCO = 11 MHz — 88 110 µA
fHFRCO = 6.6 MHz — 72 90 µA
fHFRCO = 1.2 MHz — 24 32 µA
Duty cycle DCHFRCO fHFRCO = 14 MHz 48.5 50 51 %
Frequency step for LSB change
in TUNING value
TUNESTEPHFRCO —0.33— %
Note:
1. For devices with prod. rev. < 19, Typ = 7 MHz and Min/Max values not applicable.
2. For devices with prod. rev. < 19, Typ = 1 MHz and Min/Max values not applicable.
3. The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment
range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature.
By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and
the frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating condi-
tions.
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 53
Figure 4.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
Figure 4.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 54
Figure 4.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
Figure 4.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 55
Figure 4.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
Figure 4.26. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 56
4.9.5 AUXHFRCO
Table 4.12. AUXHFRCO
Parameter Symbol Test Condition Min Typ Max Unit
Oscillation frequency, VDD= 3.0
V, TAMB=25 ºC
fAUXHFRCO 14 MHz frequency band 13.580 14.0 14.420 MHz
Settling time after start-up tAUXHFRCO_settling fAUXHFRCO = 14 MHz — 0.6 — Cycles
Duty cycle DCAUXHFRCO fAUXHFRCO = 14 MHz 48.5 50 51 %
Frequency step for LSB change
in TUNING value
TUNESTEPAUXHFRCO —0.31— %
Note:
1. The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. By using a stable
frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the frequency band
to maintain the AUXHFRCO frequency at any arbitrary value in the 14 MHz range across operating conditions.
4.9.6 ULFRCO
Table 4.13. ULFRCO
Parameter Symbol Test Condition Min Typ Max Unit
Oscillation frequency fULFRCO 25 °C, 3 V 0.7 — 1.75 kHz
Temperature coefficient TCULFRCO — 0.05 — %/°C
Supply voltage coefficient VCULFRCO — -18.2 — %/V
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 57
4.10 Analog Digital Converter (ADC)
Table 4.14. ADC
Parameter Symbol Test Condition Min Typ Max Unit
Input voltage range VADCIN
Single-ended 0 — VREF V
Differential -VREF/2 — VREF/2 V
Input range of external refer-
ence voltage, single-ended and
differential
VADCREFIN 1.25 — VDD V
Input range of external negative
reference voltage on channel 7
VADCREFIN_CH7 See VADCREFIN 0 — VDD - 1.1 V
Input range of external positive
reference voltage on channel 6
VADCREFIN_CH6 See VADCREFIN 0.625 — VDD V
Common mode input range VADCCMIN 0 — VDD V
Input current IADCIN 2 pF sampling capacitors — <100 — nA
Analog input common mode re-
jection ratio
CMRRADC — 65 — dB
Average active current IADC
1 Msamples/s, 12 bit, external
reference, ADC_CLK = 13 MHz,
BIASPROG = 0xF4B
—7351— µA
1 Msamples/s, 12 bit, internal
1.25V reference, ADC_CLK =
13 MHz, BIASPROG = 0xF4B
—7601— µA
500 Ksamples/s, 12 bit, external
reference, ADC_CLK = 7 MHz,
BIASPROG = 0x747
—3461— µA
500 Ksamples/s, 12 bit, internal
1.25V reference, ADC_CLK = 7
MHz, BIASPROG = 0x747
—3541— µA
10 kSamples/s, 12 bit, internal
1.25 V reference, WARMUP =
00b, ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
—521— µA
10 kSamples/s, 12 bit, internal
1.25 V reference, WARMUP =
01b, ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
—501— µA
10 kSamples/s, 12 bit, internal
1.25 V reference, WARMUP =
10b, ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
—541— µA
Input capacitance CADCIN — 2 — pF
Input ON resistance RADCIN 1 — — MΩ
Input RC filter resistance RADCFILT — 10 — kΩ
Input RC filter/decoupling ca-
pacitance
CADCFILT — 250 — fF
Input bias current IADCBIASIN VSS < VIN < VDD -40 — 40 nA
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 58
Parameter Symbol Test Condition Min Typ Max Unit
Input offset current IADCOFFSETIN VSS < VIN < VDD -40 — 40 nA
ADC Clock Frequency fADCCLK BIASPROG=0x747 — — 7 MHz
BIASPROG=0xF4B — — 13 MHz
Conversion time tADCCONV
6 bit 7 — — ADCCLK
Cycles
8 bit 11 — — ADCCLK
Cycles
12 bit 13 — — ADCCLK
Cycles
Acquisition time tADCACQ Programmable 1 — 256 ADCCLK
Cycles
Required acquisition time for
VDD/3 reference
tADCACQVDD3 2 — — µs
Startup time of reference gener-
ator and ADC core
tADCSTART NORMAL mode — 5 — µs
KEEPADCWARM mode — 1 — µs
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 59
Parameter Symbol Test Condition Min Typ Max Unit
Signal-to-Noise Ratio (SNR) SNRADC 1 MSamples/s, 12 bit, single-
ended, internal 1.25 V refer-
ence, ADC_CLK = 13 MHz,
BIASPROG = 0xF4B
— 59 — dB
1 MSamples/s, 12 bit, single-
ended, internal 2.5 V reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 63 — dB
1 MSamples/s, 12 bit, single-
ended, VDD reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 67 — dB
1 MSamples/s, 12 bit, differen-
tial, internal 1.25 V reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 63 — dB
1 MSamples/s, 12 bit, differen-
tial, internal 2.5 V reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 66 — dB
1 MSamples/s, 12 bit, differen-
tial, 5 V reference, ADC_CLK
=13 MHz, BIASPROG = 0xF4B
— 66 — dB
1 MSamples/s, 12 bit, differen-
tial, VDD reference, ADC_CLK=
13 MHz, BIASPROG =0xF4B
63 69 — dB
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 70 — dB
200 kSamples/s, 12 bit, single-
ended, internal 1.25 V refer-
ence, ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 62 — dB
200 kSamples/s, 12 bit, single-
ended, internal 2.5 V reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 63 — dB
200 kSamples/s, 12 bit, single-
ended, VDD reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 67 — dB
200 kSamples/s, 12 bit, differen-
tial, internal 1.25 V reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 63 — dB
200 kSamples/s, 12 bit, differen-
tial, internal 2.5 V reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 66 — dB
200 kSamples/s, 12 bit, differen-
tial, 5 V reference, ADC_CLK =
7 MHz, BIASPROG = 0x747
— 66 — dB
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 60
Parameter Symbol Test Condition Min Typ Max Unit
Signal-to-Noise Ratio (SNR) SNRADC 200 kSamples/s, 12 bit, differen-
tial, VDD reference,ADC_CLK =
7 MHz, BIASPROG = 0x747
63 69 — dB
200 kSamples/s, 12 bit, differen-
tial, 2xVDD reference,ADC_CLK
= 7 MHz, BIASPROG = 0x747
— 70 — dB
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 61
Parameter Symbol Test Condition Min Typ Max Unit
Signal-to-Noise And Distortion
Ratio (SINAD)
SINADADC 1 MSamples/s, 12 bit, single-
ended, internal 1.25 V refer-
ence, ADC_CLK = 13 MHz,
BIASPROG = 0xF4B
— 58 — dB
1 MSamples/s, 12 bit, single-
ended, internal 2.5 V reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 62 — dB
1 MSamples/s, 12 bit, single-
ended, VDD reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 66 — dB
1 MSamples/s, 12 bit, differen-
tial, internal 1.25 V reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 63 — dB
1 MSamples/s, 12 bit, differen-
tial, internal 2.5 V reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 66 — dB
1 MSamples/s, 12 bit, differen-
tial, 5 V reference, ADC_CLK =
13 MHz, BIASPROG = 0xF4B
— 66 — dB
1 MSamples/s, 12 bit, differen-
tial, VDD reference, ADC_CLK =
13 MHz, BIASPROG = 0xF4B
62 68 — dB
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 68 — dB
200 kSamples/s, 12 bit, single-
ended, internal 1.25 V refer-
ence, ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 61 — dB
200 kSamples/s, 12 bit, single-
ended, internal 2.5 V reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 62 — dB
200 kSamples/s, 12 bit, single-
ended, VDD reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 66 — dB
200 kSamples/s, 12 bit, differen-
tial, internal 1.25 V reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 63 — dB
200 kSamples/s, 12 bit, differen-
tial, internal 2.5 V reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 66 — dB
200 kSamples/s, 12 bit, differen-
tial, 5V reference, ADC_CLK= 7
MHz, BIASPROG = 0x747
— 66 — dB
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 62
Parameter Symbol Test Condition Min Typ Max Unit
Signal-to-Noise And Distortion
Ratio (SINAD)
SINADADC 200 kSamples/s, 12 bit, differen-
tial, VDD reference, ADC_CLK =
7 MHz, BIASPROG = 0x747
62 68 — dB
200 kSamples/s, 12 bit, differen-
tial, 2xVDD reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 69 — dB
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 63
Parameter Symbol Test Condition Min Typ Max Unit
Spurious-Free Dynamic Range
(SFDR)
SFDRADC 1 MSamples/s, 12 bit, single-
ended, internal 1.25 V refer-
ence, ADC_CLK = 13 MHz,
BIASPROG = 0xF4B
— 75 — dBc
1 MSamples/s, 12 bit, single-
ended, internal 2.5 V reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 76 — dBc
1 MSamples/s, 12 bit, single-
ended, VDD reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 76 — dBc
1 MSamples/s, 12 bit, differen-
tial, internal 1.25 V reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 78 — dBc
1 MSamples/s, 12 bit, differen-
tial, internal 2.5 V reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
— 77 — dBc
1 MSamples/s, 12 bit, differen-
tial, VDD reference, ADC_CLK=
13 MHz, BIASPROG = 0xF4B
— 76 — dBc
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference,
ADC_CLK = 13 MHz, BIA-
SPROG = 0xF4B
68 79 — dBc
1 MSamples/s, 12 bit, differen-
tial, 5 V reference, ADC_CLK
=13 MHz, BIASPROG = 0xF4B
— 79 — dBc
200 kSamples/s, 12 bit, single-
ended, internal 1.25 V refer-
ence, ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 75 — dBc
200 kSamples/s, 12 bit, single-
ended, internal 2.5 V reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 75 — dBc
200 kSamples/s, 12 bit, single-
ended, VDD reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 76 — dBc
200 kSamples/s, 12 bit, differen-
tial, internal 1.25 V reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 79 — dBc
200 kSamples/s, 12 bit, differen-
tial, internal 2.5 V reference,
ADC_CLK = 7 MHz, BIA-
SPROG = 0x747
— 79 — dBc
200 kSamples/s, 12 bit, differen-
tial, 5 V reference, ADC_CLK =
7 MHz, BIASPROG = 0x747
— 78 — dBc
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 64
Parameter Symbol Test Condition Min Typ Max Unit
Spurious-Free Dynamic Range
(SFDR)
SFDRADC 200 kSamples/s, 12 bit, differen-
tial, VDD reference, ADC_CLK =
7 MHz, BIASPROG = 0x747
68 79 — dBc
200 kSamples/s, 12 bit, differen-
tial, 2xVDD reference,ADC_CLK
= 7 MHz, BIASPROG = 0x747
— 79 — dBc
Offset voltage VADCOFFSET After calibration, single-ended — 0.3 — mV
After calibration, differential -4 0.3 4 mV
Thermometer output gradient TGRADADCTH — -1.92 — mV/°C
— -6.3 — ADC Co-
des/°C
Differential non-linearity (DNL) DNLADC VDD= 3.0 V, external 2.5 V ref-
erence
-1 ±0.7 4 LSB
Integral non-linearity (INL), End
point method
INLADC VDD= 3.0 V, external 2.5 V ref-
erence
— ±1.2 ±3 LSB
Missing codes MCADC — — 3 LSB
Gain error drift GAINED 1.25 V reference — 0.0120.0333%/°C
2.5 V reference — 0.0120.033%/°C
Offset error drift OFFSETED 1.25 V reference — 0.0020.063LSB/°C
2.5 V reference — 0.0020.043LSB/°C
VREF voltage VREF 1.25 V reference 1.2 1.25 1.3 V
2.5 V reference 2.4 2.5 2.6 V
VREF voltage drift VREF_VDRIFT 1.25 V reference -12.4 2.9 18.2 mV/V
2.5 V reference, VDD > 2.5 V -24.6 5.7 35.2 mV/V
VREF temperature drift VREF_TDRIFT 1.25 V reference -132 272 677 µV/°C
2.5 V reference -231 545 1271 µV/°C
VREF current consumption IVREF 1.25 V reference — 67 114 µA
2.5 V reference — 55 82 µA
ADC and DAC VREF matching VREF_MATCH 1.25 V reference — 99.85 — %
2.5 V reference — 100.01 — %
Note:
1. Includes required contribution from the voltage reference.
2. Typical numbers given by abs(Mean) / (85 - 25).
3. Max number given by (abs(Mean) + 3x stddev) / (85 - 25).
The integral non-linearity (INL) and differential non-linearity parameters are explained in the following figures.
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 65
Ideal transfer
curve
Digital output code
Analog Input
INL=|[(VD-VSS)/VLSBIDEAL] - D| where 0 < D < 2N- 1
0
1
2
3
4092
4093
4094
4095
VOFFSET
Actual ADC
tranfer function
before offset and
gain correction Actual ADC
tranfer function
after offset and
gain correction
INL Error
(End Point INL)
Figure 4.27. Integral Non-Linearity (INL)
Ideal transfer
curve
Digital
output
code
Analog Input
DNL=|[(VD+1 - VD)/VLSBIDEAL] - 1| where 0 < D < 2N- 2
0
1
2
3
4092
4093
4094
4095
Actual transfer
function with one
missing code.
4
5
Full Scale Range
0.5
LSB
Ideal Code Center
Ideal 50%
Transition Point
Ideal spacing
between two
adjacent codes
VLSBIDEAL=1 LSB
Code width =2 LSB
DNL=1 LSB
Example: Adjacent
input value VD+1
corrresponds to digital
output code D+1
Example: Input value
VDcorrresponds to
digital output code D
Figure 4.28. Differential Non-Linearity (DNL)
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 66
4.10.1 Typical Performance
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
Figure 4.29. ADC Frequency Spectrum, VDD = 3V, Temp = 25°C
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 67
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
Figure 4.30. ADC Integral Linearity Error vs Code, VDD = 3V, Temp = 25°C
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 68
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
Figure 4.31. ADC Differential Linearity Error vs Code, VDD = 3V, Temp = 25°C
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 69
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd (V)
–4
–3
–2
–1
0
1
2
3
4
5
Actual Offset [LSB]
Vref=1V25
Vref=2V5
Vref=2XVDDVSS
Vref=5VDIFF
Vref=VDD
Offset vs Supply Voltage, Temp = 25°C
–40 –15 5 25 45 65 85
Temp (C)
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
Actual Offset [LSB]
VRef=1V25
VRef=2V5
VRef=2XVDDVSS
VRef=5VDIFF
VRef=VDD
Offset vs Temperature, VDD = 3V
Figure 4.32. ADC Absolute Offset, Common Mode = VDD/2
–40 –15 5 25 45 65 85
Temperature [°C]
78.0
78.2
78.4
78.6
78.8
79.0
79.2
79.4
SFDR [dB]
1V25
2V5
Vdd
5VDIFF
2XVDDVSS
–40 –15 5 25 45 65 85
Temperature [°C]
63
64
65
66
67
68
69
70
71
SNR [dB]
1V25
2V5
Vdd
5VDIFF
2XVDDVSS
Signal to Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR)
Figure 4.33. ADC Dynamic Performance vs Temperature for all ADC References, VDD = 3V
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 70
4.11 Digital Analog Converter (DAC)
Table 4.15. DAC
Parameter Symbol Test Condition Min Typ Max Unit
Output voltage range VDACOUT
VDD voltage reference, single-
ended
0 — VDD V
VDD voltage reference, differen-
tial
-VDD — VDD V
Output common mode voltage
range
VDACCM 0 — VDD V
Average active current IDAC
500 kSamples/s, 12 bit, internal
1.25 V reference, Continuous
Mode
—40016501µA
100 kSamples/s, 12 bit, internal
1.25 V reference, Sample/Hold
Mode
—20012501µA
1 kSamples/s 12 bit, internal
1.25 V reference, Sample/Off
Mode
—171251µA
Sample rate SRDAC — — 500 ksamples/s
DAC clock frequency fDAC
Continuous Mode — — 1000 kHz
Sample/Hold Mode — — 250 kHz
Sample/Off Mode — — 250 kHz
Clock cycles per conversion CYCDACCONV — 2 — cycles
Conversion time tDACCONV 2 — — µs
Settling time tDACSETTLE — 5 — µs
Signal-to-Noise Ratio (SNR) SNRDAC
500 kSamples/s, 12 bit, single-
ended, internal 1.25 V reference
— 58 — dB
500 kSamples/s, 12 bit, single-
ended, internal 2.5 V reference
— 59 — dB
500 kSamples/s, 12 bit, differen-
tial, internal 1.25 V reference
— 58 — dB
500 kSamples/s, 12 bit, differen-
tial, internal 2.5 V reference
— 58 — dB
500 kSamples/s, 12 bit, differen-
tial, VDD reference
— 59 — dB
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 71
Parameter Symbol Test Condition Min Typ Max Unit
Signal-to-Noise plus Distortion
Ratio (SNDR) SNDRDAC
500 kSamples/s, 12 bit, single-
ended, internal 1.25 V reference
— 57 — dB
500 kSamples/s, 12 bit, single-
ended, internal 2.5 V reference
— 54 — dB
500 kSamples/s, 12 bit, differen-
tial, internal 1.25 V reference
— 56 — dB
500 kSamples/s, 12 bit, differen-
tial, internal 2.5 V reference
— 53 — dB
500 kSamples/s, 12 bit, differen-
tial, VDD reference
— 55 — dB
Spurious-Free Dynamic Range
(SFDR) SFDRDAC
500 kSamples/s, 12 bit, single-
ended, internal 1.25V reference
— 62 — dBc
500 kSamples/s, 12 bit, single-
ended, internal 2.5 V reference
— 56 — dBc
500 kSamples/s, 12 bit, differen-
tial, internal 1.25 V reference
— 61 — dBc
500 kSamples/s, 12 bit, differen-
tial, internal 2.5 V reference
— 55 — dBc
500 kSamples/s, 12 bit, differen-
tial, VDD reference
— 60 — dBc
Offset voltage VDACOFFSET
After calibration, single-ended — 2 — mV
After calibration, differential — 2 — mV
Sample-hold mode voltage drift VDACSHMDRIFT — 540 — µV/ms
Differential non-linearity DNLDAC — ±1 — LSB
Integral non-linearity INLDAC — ±5 — LSB
No missing codes MCDAC — 12 — bits
Load current ILOAD_DC — — 11 mA
VREF voltage VREF 1.25 V reference 1.2 1.25 1.3 V
2.5 V reference 2.4 2.5 2.6 V
VREF voltage drift VREF_VDRIFT 1.25 V reference -12.4 2.9 18.2 mV/V
2.5 V reference, VDD > 2.5 V -24.6 5.7 35.2 mV/V
VREF temperature drift VREF_TDRIFT 1.25 V reference -132 272 677 µV/°C
2.5 V reference -231 545 1271 µV/°C
VREF current consumption IVREF 1.25 V reference — 67 114 µA
2.5 V reference — 55 82 µA
ADC and DAC VREF matching VREF_MATCH 1.25 V reference — 99.85 — %
2.5 V reference — 100.01 — %
Note:
1. Measured with a static input code and no loading on the output. Includes required contribution from the voltage reference.
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 72
4.12 Analog Comparator (ACMP)
Table 4.16. ACMP
Parameter Symbol Test Condition Min Typ Max Unit
Input voltage range VACMPIN 0 — VDD V
ACMP Common Mode voltage
range
VACMPCM 0 — VDD V
Active current IACMP
BIASPROG=0b0000, FULL-
BIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
— 55 600 µA
BIASPROG=0b1111, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
— 2.82 12 µA
BIASPROG=0b1111, FULL-
BIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
— 250 520 µA
Current consumption of internal
voltage reference IACMPREF
Internal voltage reference off.
Using external voltage refer-
ence
— 0 0.5 µA
Internal voltage reference,
LPREF=1
— 0.050 3 µA
Internal voltage reference,
LPREF=0
— 6 — µA
Offset voltage VACMPOFFSET BIASPROG= 0b1010, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
-12 0 12 mV
ACMP hysteresis VACMPHYST Programmable — 17 — mV
Capacitive Sense Internal Re-
sistance RCSRES
CSRESSEL=0b00 in
ACMPn_INPUTSEL
— 39 — kΩ
CSRESSEL=0b01 in
ACMPn_INPUTSEL
— 71 — kΩ
CSRESSEL=0b10 in
ACMPn_INPUTSEL
— 104 — kΩ
CSRESSEL=0b11 in
ACMPn_INPUTSEL
— 136 — kΩ
Startup time tACMPSTART — — 10 µs
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given in the following equa-
tion. IACMPREF is zero if an external voltage reference is used.
IACMPTOTAL =IACMP +IACMPREF
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 73
0 2 46 8 10 12 14
ACMP_CTRL_BIASPROG
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Response Time [us]
HYSTSEL=0.0
HYSTSEL=2.0
HYSTSEL=4.0
HYSTSEL=6.0
012 3 4 5 67
ACMP_CTRL_HYSTSEL
0
20
40
60
80
100
Hysteresis [mV]
BIASPROG=0.0
BIASPROG=4.0
BIASPROG=8.0
BIASPROG=12.0
048 12
ACMP_CTRL_BIASPROG
0.0
0.5
1.0
1.5
2.0
2.5
Current [uA]
Current Consumption, HYSTSEL = 4 Response Time
Hysteresis
Figure 4.34. ACMP Characteristics, VDD = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 74
4.13 Voltage Comparator (VCMP)
Table 4.17. VCMP
Parameter Symbol Test Condition Min Typ Max Unit
Input voltage range VVCMPIN — VDD — V
VCMP Common Mode voltage
range
VVCMPCM — VDD — V
Active current IVCMP BIASPROG=0b0000 and HALF-
BIAS=1 in VCMPn_CTRL regis-
ter
— 0.3 1 µA
BIASPROG=0b1111 and HALF-
BIAS=0 in VCMPn_CTRL regis-
ter. LPREF=0.
— 22 30 µA
Startup time reference genera-
tor
tVCMPREF NORMAL — 10 — µs
Offset voltage VVCMPOFFSET Single-ended — 10 — mV
Differential — 10 — mV
VCMP hysteresis VVCMPHYST — 40 — mV
Startup time tVCMPSTART — — 10 µs
The VDD Trigger Level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in accordance with the following
equation:
VDD Trigger Level = 1.667V+ 0.034 × TRIGLEVEL
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 75
4.14 LCD
Table 4.18. LCD
Parameter Symbol Test Condition Min Typ Max Unit
Frame rate fLCDFR 30 — 200 Hz
Number of segments supported NUMSEG — 4×40 — seg
LCD supply voltage range VLCD Internal boost circuit enabled 2.0 — 3.8 V
Steady state current consumption. ILCD
Display disconnected, static mode,
framerate 32 Hz, all segments on.
— 250 — nA
Display disconnected, quadruplex
mode, framerate 32 Hz, all seg-
ments on, bias mode to ONE-
THIRD in LCD_DISPCTRL regis-
ter.
— 550 — nA
Steady state Current contribution
of internal boost. ILCDBOOST
Internal voltage boost off — 0 — µA
Internal voltage boost on, boosting
from 2.2 V to 3.0 V.
— 8.4 — µA
Boost Voltage VBOOST
VBLEV of LCD_DISPCTRL regis-
ter to LEVEL0
— 3.0 — V
VBLEV of LCD_DISPCTRL regis-
ter to LEVEL1
— 3.08 — V
VBLEV of LCD_DISPCTRL regis-
ter to LEVEL2
— 3.17 — V
VBLEV of LCD_DISPCTRL regis-
ter to LEVEL3
— 3.26 — V
VBLEV of LCD_DISPCTRL regis-
ter to LEVEL4
— 3.34 — V
VBLEV of LCD_DISPCTRL regis-
ter to LEVEL5
— 3.43 — V
VBLEV of LCD_DISPCTRL regis-
ter to LEVEL6
— 3.52 — V
VBLEV of LCD_DISPCTRL regis-
ter to LEVEL7
— 3.6 — V
The total LCD current is given by the following equation. ILCDBOOST is zero if internal boost is off.
ILCDTOTAL =ILCD +ILCDBOOST
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 76
4.15 I2C
Table 4.19. I2C Standard-mode (Sm)
Parameter Symbol Min Typ Max Unit
SCL clock frequency fSCL 0 — 1001kHz
SCL clock low time tLOW 4.7 — — µs
SCL clock high time tHIGH 4.0 — — µs
SDA set-up time tSU,DAT 250 — — ns
SDA hold time tHD,DAT 8 — 34502,3 ns
Repeated START condition set-up time tSU,STA 4.7 — — µs
(Repeated) START condition hold time tHD,STA 4.0 — — µs
STOP condition set-up time tSU,STO 4.0 — — µs
Bus free time between a STOP and a START
condition
tBUF 4.7 — — µs
Note:
1. For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32G Reference Manual.
2. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 4).
Table 4.20. I2C Fast-mode (Fm)
Parameter Symbol Min Typ Max Unit
SCL clock frequency fSCL 0 — 4001kHz
SCL clock low time tLOW 1.3 — — µs
SCL clock high time tHIGH 0.6 — — µs
SDA set-up time tSU,DAT 100 — — ns
SDA hold time tHD,DAT 8 — 9002,3 ns
Repeated START condition set-up time tSU,STA 0.6 — — µs
(Repeated) START condition hold time tHD,STA 0.6 — — µs
STOP condition set-up time tSU,STO 0.6 — — µs
Bus free time between a STOP and a START
condition
tBUF 1.3 — — µs
Note:
1. For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32G Reference Manual.
2. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 4).
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 77
Table 4.21. I2C Fast-mode Plus (Fm+)
Parameter Symbol Min Typ Max Unit
SCL clock frequency fSCL 0 — 10001kHz
SCL clock low time tLOW 0.5 — — µs
SCL clock high time tHIGH 0.26 — — µs
SDA set-up time tSU,DAT 50 — — ns
SDA hold time tHD,DAT 8 — — ns
Repeated START condition set-up time tSU,STA 0.26 — — µs
(Repeated) START condition hold time tHD,STA 0.26 — — µs
STOP condition set-up time tSU,STO 0.26 — — µs
Bus free time between a STOP and a START
condition
tBUF 0.5 — — µs
Note:
1. For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32G Reference Manual.
4.16 Digital Peripherals
Table 4.22. Digital Peripherals
Parameter Symbol Test Condition Min Typ Max Unit
USART current IUSART USART idle current, clock enabled — 7.5 — µA/MHz
UART current IUART UART idle current, clock enabled — 5.63 — µA/MHz
LEUART current ILEUART LEUART idle current, clock enabled — 150 — nA
I2C current II2C I2C idle current, clock enabled — 6.25 — µA/MHz
TIMER current ITIMER TIMER_0 idle current, clock enabled — 8.75 — µA/MHz
LETIMER current ILETIMER LETIMER idle current, clock enabled — 150 — nA
PCNT current IPCNT PCNT idle current, clock enabled — 100 — nA
RTC current IRTC RTC idle current, clock enabled — 100 — nA
LCD current ILCD LCD idle current, clock enabled — 100 — nA
AES current IAES AES idle current, clock enabled — 2.5 — µA/MHz
GPIO current IGPIO GPIO idle current, clock enabled — 5.31 — µA/MHz
EBI current IEBI EBI idle current, clock enabled — 1.56 — µA/MHz
PRS current IPRS PRS idle current — 2.81 — µA/MHz
DMA current IDMA Clock enable — 8.12 — µA/MHz
Note: Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" forguidelines on designing Printed Circuit
Boards (PCB's) for the EFM32G.
EFM32G Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world. Rev. 2.10 | 78
5. Pin Definitions
Note: Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for guidelines on designing Printed Cir-
cuit Boards (PCBs) for the EFM32G.
5.1 EFM32G200 & EFM32G210 (QFN32)
5.1.1 Pinout
The EFM32G200 and EFM32G210 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by
the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bit-
field in the *_ROUTE register in the module in question.
Figure 5.1. EFM32G200 & EFM32G210 Pinout (top view, not to scale)
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 79
Table 5.1. Device Pinout
QFN32 Pin# and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
0 VSS Ground.
1 PA0 TIM0_CC0 #0/1 I2C0_SDA #0
2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
3 PA2 TIM0_CC2 #0/1 CMU_CLK0 #0
4 IOVDD_1 Digital IO power supply 1.
5 PC0 ACMP0_CH0 PCNT0_S0IN #2 US1_TX #0
6 PC1 ACMP0_CH1 PCNT0_S1IN #2 US1_RX #0
7 PB7 LFXTAL_P US1_CLK #0
8 PB8 LFXTAL_N US1_CS #0
9 RESETn Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
10 PB11 DAC0_OUT0 LETIM0_OUT0 #1
11 AVDD_2 Analog power supply 2.
12 PB13 HFXTAL_P LEU0_TX #1
13 PB14 HFXTAL_N LEU0_RX #1
14 IOVDD_3 Digital IO power supply 3.
15 AVDD_0 Analog power supply 0.
16 PD4 ADC0_CH4 LEU0_TX #0
17 PD5 ADC0_CH5 LEU0_RX #0
18 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1
19 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1
20 VDD_DREG Power supply for on-chip voltage regulator.
21 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
pin.
22 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 TIM1_CC0
#0 PCNT0_S0IN #0
23 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 TIM1_CC1
#0 PCNT0_S1IN #0
24 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 TIM1_CC2
#0 DBG_SWO #1
25 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1
26 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1
27 PF2 ACMP1_O #0 DBG_SWO #0
28 IOVDD_5 Digital IO power supply 5.
29 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX
30 PE11 TIM1_CC1 #1 US0_RX #0 BOOT_RX
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 80
QFN32 Pin# and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
31 PE12 TIM1_CC2 #1 US0_CLK #0
32 PE13 US0_CS #0 ACMP0_O #0
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 81
5.1.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.2. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 Description
ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.
ACMP0_O PE13 Analog comparator ACMP0, digital output.
ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.
ACMP1_O PF2 Analog comparator ACMP1, digital output.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PE11 Bootloader RX.
BOOT_TX PE10 Bootloader TX.
CMU_CLK0 PA2 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 Clock Management Unit, clock output number 1.
DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0.
DBG_SWCLK PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a
built-in pull down.
DBG_SWDIO PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a
built-in pull up.
DBG_SWO PF2 PC15
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be
enabled by software to be used.
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 I2C0 Serial Data input / output.
LETIM0_OUT0 PD6 PB11 PF0 Low Energy Timer LETIM0, output channel 0.
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 82
Alternate LOCATION
Functionality 0 1 2 3 Description
LETIM0_OUT1 PD7 PF1 Low Energy Timer LETIM0, output channel 1.
LEU0_RX PD5 PB14 LEUART0 Receive input.
LEU0_TX PD4 PB13 LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-
so used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC13 PC0 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PC1 Pulse Counter PCNT0 input number 1.
TIM0_CC0 PA0 PA0 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PC13 PC13 Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1 PC14 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PC15 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2.
US0_CLK PE12 USART0 clock input / output.
US0_CS PE13 USART0 chip select input / output.
US0_RX PE11
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MI-
SO).
US0_TX PE10
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 USART1 clock input / output.
US1_CS PB8 USART1 chip select input / output.
US1_RX PC1
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MI-
SO).
US1_TX PC0
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 83
5.1.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32G200 and EFM32G210 is shown in the following table. Each GPIO port is organized as 16-
bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.3. GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
Port A — — — — — — — — — — — — — PA2 PA1 PA0
Port B — PB14 PB13 — PB11 — — PB8 PB7 — — — — — — —
Port C PC15 PC14 PC13 — — — — — — — — — — — PC1 PC0
Port D — — — — — — — — PD7 PD6 PD5 PD4 — — — —
Port E — — PE13 PE12 PE11 PE10 — — — — — — — — — —
Port F — — — — — — — — — — — — — PF2 PF1 PF0
EFM32G Data Sheet
Pin Definitions
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5.2 EFM32G222 (TQFP48)
5.2.1 Pinout
The EFM32G222 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.2. EFM32G222 Pinout (top view, not to scale)
Table 5.4. Device Pinout
TQFP48 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
1 PA0 TIM0_CC0 #0/1 I2C0_SDA #0
2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
3 PA2 TIM0_CC2 #0/1 CMU_CLK0 #0
4 IOVDD_0 Digital IO power supply 0.
5 VSS Ground.
EFM32G Data Sheet
Pin Definitions
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TQFP48 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
6 PC0 ACMP0_CH0 PCNT0_S0IN #2 US1_TX #0
7 PC1 ACMP0_CH1 PCNT0_S1IN #2 US1_RX #0
8 PC2 ACMP0_CH2
9 PC3 ACMP0_CH3
10 PC4 ACMP0_CH4 LETIM0_OUT0 #3
PCNT1_S0IN #0
11 PB7 LFXTAL_P US1_CLK #0
12 PB8 LFXTAL_N US1_CS #0
13 PA8 TIM2_CC0 #0
14 PA9 TIM2_CC1 #0
15 PA10 TIM2_CC2 #0
16 RESETn Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
17 PB11 DAC0_OUT0 LETIM0_OUT0 #1
18 VSS Ground.
19 AVDD_1 Analog power supply 1.
20 PB13 HFXTAL_P LEU0_TX #1
21 PB14 HFXTAL_N LEU0_RX #1
22 IOVDD_3 Digital IO power supply 3.
23 AVDD_0 Analog power supply 0.
24 PD4 ADC0_CH4 LEU0_TX #0
25 PD5 ADC0_CH5 LEU0_RX #0
26 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1
27 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1
28 VDD_DREG Power supply for on-chip voltage regulator.
29 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
pin.
30 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2
31 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2
32 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2
33 PC11 ACMP1_CH3 US0_TX #2
34 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 TIM1_CC0
#0 PCNT0_S0IN #0
35 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 TIM1_CC1
#0 PCNT0_S1IN #0
36 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 TIM1_CC2
#0 DBG_SWO #1
37 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1
EFM32G Data Sheet
Pin Definitions
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TQFP48 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
38 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1
39 PF2 ACMP1_O #0 DBG_SWO #0
40 PF3 TIM0_CDTI0 #2
41 PF4 TIM0_CDTI1 #2
42 PF5 TIM0_CDTI2 #2
43 IOVDD_5 Digital IO power supply 5.
44 VSS Ground.
45 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX
46 PE11 TIM1_CC1 #1 US0_RX #0 BOOT_RX
47 PE12 TIM1_CC2 #1 US0_CLK #0
48 PE13 US0_CS #0 ACMP0_O #0
EFM32G Data Sheet
Pin Definitions
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5.2.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.5. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 Description
ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.
ACMP0_O PE13 Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.
ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.
ACMP1_O PF2 Analog comparator ACMP1, digital output.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PE11 Bootloader RX.
BOOT_TX PE10 Bootloader TX.
CMU_CLK0 PA2 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 Clock Management Unit, clock output number 1.
DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0.
DBG_SWCLK PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a
built-in pull down.
DBG_SWDIO PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a
built-in pull up.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
DBG_SWO PF2 PC15
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be
enabled by software to be used.
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 I2C0 Serial Data input / output.
LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PF1 Low Energy Timer LETIM0, output channel 1.
LEU0_RX PD5 PB14 LEUART0 Receive input.
LEU0_TX PD4 PB13 LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-
so used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC13 PC0 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PC1 Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0.
TIM0_CC0 PA0 PA0 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2.
TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2.
US0_CLK PE12 PC9 USART0 clock input / output.
US0_CS PE13 PC8 USART0 chip select input / output.
US0_RX PE11 PC10
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MI-
SO).
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
US0_TX PE10 PC11
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 USART1 clock input / output.
US1_CS PB8 USART1 chip select input / output.
US1_RX PC1
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MI-
SO).
US1_TX PC0
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
5.2.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32G222 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.6. GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
Port A — — — — — PA10 PA9 PA8 — — — — — PA2 PA1 PA0
Port B — PB14 PB13 — PB11 — — PB8 PB7 — — — — — — —
Port C PC15 PC14 PC13 — PC11 PC10 PC9 PC8 — — — PC4 PC3 PC2 PC1 PC0
Port D — — — — — — — — PD7 PD6 PD5 PD4 — — — —
Port E — — PE13 PE12 PE11 PE10 — — — — — — — — — —
Port F — — — — — — — — — — PF5 PF4 PF3 PF2 PF1 PF0
EFM32G Data Sheet
Pin Definitions
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5.3 EFM32G230 (QFN64)
5.3.1 Pinout
The EFM32G230 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.3. EFM32G230 Pinout (top view, not to scale)
Table 5.7. Device Pinout
QFN64 Pin# and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
0 VSS Ground.
1 PA0 TIM0_CC0 #0/1 I2C0_SDA #0
2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
3 PA2 TIM0_CC2 #0/1 CMU_CLK0 #0
4 PA3 TIM0_CDTI0 #0
5 PA4 TIM0_CDTI1 #0
EFM32G Data Sheet
Pin Definitions
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QFN64 Pin# and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
6 PA5 TIM0_CDTI2 #0 LEU1_TX #1
6 PA6 LEU1_RX #1
8 IOVDD_0 Digital IO power supply 0.
9 PC0 PCNT0_S0IN #1 US1_TX #0
10 PC1 PCNT0_S1IN #1 US1_RX #0
11 PC2 US2_CLK #0
12 PC3 US2_CS #0
13 PC4 ACMP0_CH4 LETIM0_OUT0 #3
PCNT1_S0IN #0 US2_CLK #0
14 PC5 ACMP0_CH5 LETIM0_OUT1 #3
PCNT1_S1IN #0 US2_CS #0
15 PB7 LFXTAL_P US1_CLK #0
16 PB8 LFXTAL_N US1_CS #0
17 PA8 TIM2_CC0 #0
18 PA9 TIM2_CC1 #0
19 PA10 TIM2_CC2 #0
20 RESETn Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
21 PB11 DAC0_OUT0 LETIM0_OUT0 #1
22 PB12 DAC0_OUT1 LETIM0_OUT1 #1
23 AVDD_1 Analog power supply 1.
24 PB13 HFXTAL_P LEU0_TX #1
25 PB14 HFXTAL_N LEU0_RX #1
26 IOVDD_3 Digital IO power supply 3.
27 AVDD_0 Analog power supply 0.
28 PD0 ADC0_CH0 PCNT2_S0IN #0 US1_TX #1
29 PD1 ADC0_CH1 TIM0_CC0 #3 PCNT2_S1IN
#0 US1_RX #1
30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1
31 PD3 ADC0_CH3 TIM0_CC2 #3 US1_CS #1
32 PD4 ADC0_CH4 LEU0_TX #0
33 PD5 ADC0_CH5 LEU0_RX #0
34 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1
35 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1
36 PD8 CMU_CLK1 #1
37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2
38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL #2
39 VDD_DREG Power supply for on-chip voltage regulator.
EFM32G Data Sheet
Pin Definitions
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QFN64 Pin# and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
pin.
41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2
42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2
43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2
44 PC11 ACMP1_CH3 US0_TX #2
45 PC12 ACMP1_CH4 CMU_CLK0 #1
46 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 TIM1_CC0
#0 PCNT0_S0IN #0
47 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 TIM1_CC1
#0 PCNT0_S1IN #0
48 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 TIM1_CC2
#0 DBG_SWO #1
49 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1
50 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1
51 PF2 ACMP1_O #0 DBG_SWO #0
52 PF3 TIM0_CDTI0 #2
53 PF4 TIM0_CDTI1 #2
54 PF5 TIM0_CDTI2 #2
55 IOVDD_5 Digital IO power supply 5.
56 PE8 PCNT2_S0IN #1
57 PE9 PCNT2_S1IN #1
58 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX
59 PE11 TIM1_CC1 #1 US0_RX #0 BOOT_RX
60 PE12 TIM1_CC2 #1 US0_CLK #0
61 PE13 US0_CS #0 ACMP0_O #0
62 PE14 LEU0_TX #2
63 PE15 LEU0_RX #2
64 PA15
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Pin Definitions
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5.3.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.8. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 Description
ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.
ACMP0_O PE13 Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9 Analog comparator ACMP2, channel 1.
ACMP1_CH2 PC10 Analog comparator ACMP3, channel 2.
ACMP1_CH3 PC11 Analog comparator ACMP4, channel 3.
ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.
ACMP1_O PF2 Analog comparator ACMP1, digital output.
ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0.
ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1.
ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2.
ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PE11 Bootloader RX.
BOOT_TX PE10 Bootloader TX.
CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1.
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Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0.
DAC0_OUT1 PB12 Digital to Analog Converter DAC0 output channel number 1.
DBG_SWCLK PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a
built-in pull down.
DBG_SWDIO PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a
built-in pull up.
DBG_SWO PF2 PC15
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be
enabled by software to be used.
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output.
LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.
LEU0_RX PD5 PB14 PE15 LEUART0 Receive input.
LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LEU1_RX PC7 PA6 LEUART1 Receive input.
LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half
duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-
so used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC13 PC0 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PC1 Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1.
PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.
PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.
TIM0_CC0 PA0 PA0 PD1 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 PD2 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 PD3 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2.
TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2.
US0_CLK PE12 PC9 USART0 clock input / output.
US0_CS PE13 PC8 USART0 chip select input / output.
US0_RX PE11 PC10
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MI-
SO).
US0_TX PE10 PC11
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 PD2 USART1 clock input / output.
US1_CS PB8 PD3 USART1 chip select input / output.
US1_RX PC1 PD1
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MI-
SO).
US1_TX PC0 PD0
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK PC4 USART2 clock input / output.
US2_CS PC5 USART2 chip select input / output.
US2_RX PC3
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MI-
SO).
US2_TX PC2
USART2 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
EFM32G Data Sheet
Pin Definitions
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5.3.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32G230 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.9. GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
Port A PA15 — — — — PA10 PA8 PA8
—— PA6 PA5 PA4 PA3 PA2 PA1 PA0
Port B — PB14 PB13 PB12 PB11 — — PB8 PB7 — — — — — — —
Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Port D — — — — — — — PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 — — — — — — — —
Port F — — — — — — — — — — PF5 PF4 PF3 PF2 PF1 PF0
EFM32G Data Sheet
Pin Definitions
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5.4 EFM32G232 (TQFP64)
5.4.1 Pinout
The EFM32G232 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.4. EFM32G232 Pinout (top view, not to scale)
Table 5.10. Device Pinout
TQFP64 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
1 PA0 TIM0_CC0 #0/1 I2C0_SDA #0
2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
3 PA2 TIM0_CC2 #0/1 CMU_CLK0 #0
4 PA3 TIM0_CDTI0 #0
5 PA4 TIM0_CDTI1 #0
EFM32G Data Sheet
Pin Definitions
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TQFP64 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
6 PA5 TIM0_CDTI2 #0 LEU1_TX #1
7 IOVDD_0 Digital IO power supply 0.
8 VSS Ground.
9 PC0 ACMP0_CH0 PCNT0_S0IN #1 US1_TX #1
10 PC1 ACMP0_CH1 PCNT0_S1IN #1 US1_RX #1
11 PC2 ACMP0_CH2 US1_CLK #1
12 PC3 ACMP0_CH3 US1_CS #1
13 PC4 ACMP0_CH4 LETIM0_OUT0 #3
PCNT1_S0IN #0 US2_CLK #0
14 PC5 ACMP0_CH5 LETIM0_OUT1 #3
PCNT1_S1IN #0 US2_CS #0
15 PB7 LFXTAL_P US1_CLK #0
16 PB8 LFXTAL_N US1_CS #0
17 PA8 TIM2_CC0 #0
18 PA9 TIM2_CC1 #0
19 PA10 TIM2_CC2 #0
20 RESETn Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
21 PB11 DAC0_OUT0 LETIM0_OUT0 #1
22 VSS Ground.
23 AVDD_1 Analog power supply 1.
24 PB13 HFXTAL_P LEU0_TX #1
25 PB14 HFXTAL_N LEU0_RX #1
26 IOVDD_3 Digital IO power supply 3.
27 AVDD_0 Analog power supply 0.
28 PD0 ADC0_CH0 PCNT2_S0IN #0 US1_TX #1
29 PD1 ADC0_CH1 TIM0_CC0 #3 PCNT2_S1IN
#0 US1_RX #1
30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1
31 PD3 ADC0_CH3 TIM0_CC2 #3 US1_CS #1
32 PD4 ADC0_CH4 LEU0_TX #0
33 PD5 ADC0_CH5 LEU0_RX #0
34 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1
35 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1
36 PD8 CMU_CLK1 #1
37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2
38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL #2
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 99
TQFP64 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
39 VDD_DREG Power supply for on-chip voltage regulator.
40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
pin.
41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2
42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2
43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2
44 PC11 ACMP1_CH3 US0_TX #2
45 PC12 ACMP1_CH4 CMU_CLK0 #1
46 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 TIM1_CC0
#0 PCNT0_S0IN #0
47 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 TIM1_CC1
#0 PCNT0_S1IN #0
48 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 TIM1_CC2
#0 DBG_SWO #1
49 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1
50 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1
51 PF2 ACMP1_O #0 DBG_SWO #0
52 PF3 TIM0_CDTI0 #2
53 PF4 TIM0_CDTI1 #2
54 PF5 TIM0_CDTI2 #2
55 IOVDD_5 Digital IO power supply 5.
56 VSS Ground.
57 PE8 PCNT2_S0IN #1
58 PE9 PCNT2_S1IN #1
59 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX
60 PE11 TIM1_CC1 #1 US0_RX #0 BOOT_RX
61 PE12 TIM1_CC2 #1 US0_CLK #0
62 PE13 US0_CS #0 ACMP0_O #0
63 PE14 LEU0_TX #2
64 PE15 LEU0_RX #2
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 100
5.4.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.11. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 Description
ACMP0_CH4 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH5 PC1 Analog comparator ACMP0, channel 1.
ACMP0_CH6 PC2 Analog comparator ACMP0, channel 2.
ACMP0_CH7 PC3 Analog comparator ACMP0, channel 3.
ACMP0_O PE13 Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.
ACMP1_O PF2 Analog comparator ACMP1, digital output.
ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0.
ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1.
ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2.
ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PE11 Bootloader RX.
BOOT_TX PE10 Bootloader TX.
CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1.
DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0.
DBG_SWCLK PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a
built-in pull down.
DBG_SWDIO PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a
built-in pull up.
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 101
Alternate LOCATION
Functionality 0 1 2 3 Description
DBG_SWO PF2 PC15
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be
enabled by software to be used.
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output.
LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PF1 PC5 Low Energy Timer LETIM0, output channel 1.
LEU0_RX PD5 PB14 PE15 LEUART0 Receive input.
LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LEU1_RX PC7 LEUART1 Receive input.
LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half
duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-
so used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC13 PC0 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PC1 Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1.
PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.
PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.
TIM0_CC0 PA0 PA0 PD1 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 PD2 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 PD3 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2.
TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2.
US0_CLK PE12 PC9 USART0 clock input / output.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
US0_CS PE13 PC8 USART0 chip select input / output.
US0_RX PE11 PC10
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MI-
SO).
US0_TX PE10 PC11
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 PD2 USART1 clock input / output.
US1_CS PB8 PD3 USART1 chip select input / output.
US1_RX PC1 PD1
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MI-
SO).
US1_TX PC0 PD0
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK PC4 USART2 clock input / output.
US2_CS PC5 USART2 chip select input / output.
US2_RX PC3
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MI-
SO).
US2_TX PC2
USART2 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
5.4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32G2322 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.12. GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
Port A — — — — — PA10 PA9 PA8 — — PA5 PA4 PA3 PA2 PA1 PA0
Port B — PB14 PB13 — PB11 — — PB8 PB7 — — — — — — —
Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Port D — — — — — — — PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 — — — — — — — —
Port F — — — — — — — — — — PF5 PF4 PF3 PF2 PF1 PF0
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 103
5.5 EFM32G280 (LQFP100)
5.5.1 Pinout
The EFM32G280 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.5. EFM32G280 Pinout (top view, not to scale)
Table 5.13. Device Pinout
LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
1 PA0 EBI_AD09 #0 TIM0_CC0 #0/1 I2C0_SDA #0
2 PA1 EBI_AD10 #0 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
3 PA2 EBI_AD11 #0 TIM0_CC2 #0/1 CMU_CLK0 #0
4 PA3 EBI_AD12 #0 TIM0_CDTI0 #0 U0_TX #2
5 PA4 EBI_AD13 #0 TIM0_CDTI1 #0 U0_RX #2
EFM32G Data Sheet
Pin Definitions
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LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
6 PA5 EBI_AD14 #0 TIM0_CDTI2 #0 LEU1_TX #1
7 PA6 EBI_AD15 #0 LEU1_RX #1
8 IOVDD_0 Digital IO power supply 0.
9 PB0 TIM1_CC0 #2
10 PB1 TIM1_CC1 #2
11 PB2 TIM1_CC2 #2
12 PB3 PCNT1_S0IN #1 US2_TX #1
13 PB4 PCNT1_S1IN #1 US2_RX #1
14 PB5 US2_CLK #1
15 PB6 US2_CS #1
16 VSS Ground.
17 IOVDD_1 Digital IO power supply 1.
18 PC0 ACMP0_C
H0 PCNT0_S0IN #2 US1_TX #0
19 PC1 ACMP0_C
H1 PCNT0_S1IN #2 US1_RX #0
20 PC2 ACMP0_C
H2 US2_TX #0
21 PC3 ACMP0_C
H3 US2_RX #0
22 PC4 ACMP0_C
H4
LETIM0_OUT0 #3
PCNT1_S0IN #0 US2_CLK #0
23 PC5 ACMP0_C
H5
LETIM0_OUT1 #3
PCNT1_S1IN #0 US2_CS #0
24 PB7 LFXTAL_P US1_CLK #0
25 PB8 LFXTAL_N US1_CS #0
26 PA7
27 PA8 TIM2_CC0 #0
28 PA9 TIM2_CC1 #0
29 PA10 TIM2_CC2 #0
30 PA11
31 IOVDD_2 Digital IO power supply 2.
32 VSS Ground.
33 PA12 TIM2_CC0 #1
34 PA13 TIM2_CC1 #1
35 PA14 TIM2_CC2 #1
36 RESETn Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure that reset is released.
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 105
LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
37 PB9
38 PB10
39 PB11 DAC0_OU
T0 LETIM0_OUT0 #1
40 PB12 DAC0_OU
T1 LETIM0_OUT1 #1
41 AVDD_1 Analog power supply 1.
42 PB13 HFXTAL_
PLEU0_TX #1
43 PB14 HFXTAL_
NLEU0_RX #1
44 IOVDD_3 Digital IO power supply 3.
45 AVDD_0 Analog power supply 0.
46 PD0 ADC0_CH
0PCNT2_S0IN #0 US1_TX #1
47 PD1 ADC0_CH
1
TIM0_CC0 #3
PCNT2_S1IN #0 US1_RX #1
48 PD2 ADC0_CH
2TIM0_CC1 #3 US1_CLK #1
49 PD3 ADC0_CH
3TIM0_CC2 #3 US1_CS #1
50 PD4 ADC0_CH
4LEU0_TX #0
51 PD5 ADC0_CH
5LEU0_RX #0
52 PD6 ADC0_CH
6LETIM0_OUT0 #0 I2C0_SDA #1
53 PD7 ADC0_CH
7LETIM0_OUT1 #0 I2C0_SCL #1
54 PD8 CMU_CLK1 #1
55 PC6 ACMP0_C
H6
LEU1_TX #0
I2C0_SDA #2
56 PC7 ACMP0_C
H7
LEU1_RX #0
I2C0_SCL #2
57 VDD_DRE
GPower supply for on-chip voltage regulator.
58 VSS Ground.
59 DECOU-
PLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
60 PE0 PCNT0_S0IN #1 U0_TX #1
61 PE1 PCNT0_S1IN #1 U0_RX #1
62 PE2 ACMP0_O #1
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 106
LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
63 PE3 ACMP1_O #1
64 PE4 US0_CS #1
65 PE5 US0_CLK #1
66 PE6 US0_RX #1
67 PE7 US0_TX #1
68 PC8 ACMP1_C
H0 TIM2_CC0 #2 US0_CS #2
69 PC9 ACMP1_C
H1 TIM2_CC1 #2 US0_CLK #2
70 PC10 ACMP1_C
H2 TIM2_CC2 #2 US0_RX #2
71 PC11 ACMP1_C
H3 US0_TX #2
72 PC12 ACMP1_C
H4 CMU_CLK0 #1
73 PC13 ACMP1_C
H5
TIM0_CDTI0 #1/3
TIM1_CC0 #0
PCNT0_S0IN #0
74 PC14 ACMP1_C
H6
TIM0_CDTI1 #1/3
TIM1_CC1 #0
PCNT0_S1IN #0
U0_TX #3
75 PC15 ACMP1_C
H7
TIM0_CDTI2 #1/3
TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
76 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1
77 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1
78 PF2 EBI_ARDY #0 ACMP1_O #0
DBG_SWO #0
79 PF3 EBI_ALE #0 TIM0_CDTI0 #2
80 PF4 EBI_WEn #0 TIM0_CDTI1 #2
81 PF5 EBI_REn #0 TIM0_CDTI2 #2
82 IOVDD_5 Digital IO power supply 5.
83 VSS Ground.
84 PF6 TIM0_CC0 #2 U0_TX #0
85 PF7 TIM0_CC1 #2 U0_RX #0
86 PF8 TIM0_CC2 #2
87 PF9
88 PD9 EBI_CS0 #0
89 PD10 EBI_CS1 #0
90 PD11 EBI_CS2 #0
91 PD12 EBI_CS3 #0
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 107
LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
92 PE8 EBI_AD00 #0 PCNT2_S0IN #1
93 PE9 EBI_AD01 #0 PCNT2_S1IN #1
94 PE10 EBI_AD02 #0 TIM1_CC0 #1 US0_TX #0 BOOT_TX
95 PE11 EBI_AD03 #0 TIM1_CC1 #1 US0_RX #0 BOOT_RX
96 PE12 EBI_AD04 #0 TIM1_CC2 #1 US0_CLK #0
97 PE13 EBI_AD05 #0 US0_CS #0 ACMP0_O #0
98 PE14 EBI_AD06 #0 LEU0_TX #2
99 PE15 EBI_AD07 #0 LEU0_RX #2
100 PA15 EBI_AD08 #0
EFM32G Data Sheet
Pin Definitions
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5.5.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.14. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 Description
ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.
ACMP0_O PE13 PE2 Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.
ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.
ACMP1_O PF2 PE3 Analog comparator ACMP1, digital output.
ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0.
ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1.
ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2.
ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PE11 Bootloader RX.
BOOT_TX PE10 Bootloader TX.
CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0.
DAC0_OUT1 PB12 Digital to Analog Converter DAC0 output channel number 1.
DBG_SWCLK PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a
built-in pull down.
DBG_SWDIO PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a
built-in pull up.
DBG_SWO PF2 PC15
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be
enabled by software to be used.
EBI_AD00 PE8 External Bus Interface (EBI) address and data input / output
pin 00.
EBI_AD01 PE9 External Bus Interface (EBI) address and data input / output
pin 01.
EBI_AD02 PE10 External Bus Interface (EBI) address and data input / output
pin 02.
EBI_AD03 PE11 External Bus Interface (EBI) address and data input / output
pin 03.
EBI_AD04 PE12 External Bus Interface (EBI) address and data input / output
pin 04.
EBI_AD05 PE13 External Bus Interface (EBI) address and data input / output
pin 05.
EBI_AD06 PE14 External Bus Interface (EBI) address and data input / output
pin 06.
EBI_AD07 PE15 External Bus Interface (EBI) address and data input / output
pin 07.
EBI_AD08 PA15 External Bus Interface (EBI) address and data input / output
pin 08.
EBI_AD09 PA0 External Bus Interface (EBI) address and data input / output
pin 09.
EBI_AD10 PA1 External Bus Interface (EBI) address and data input / output
pin 10.
EBI_AD11 PA2 External Bus Interface (EBI) address and data input / output
pin 11.
EBI_AD12 PA3 External Bus Interface (EBI) address and data input / output
pin 12.
EBI_AD13 PA4 External Bus Interface (EBI) address and data input / output
pin 13.
EBI_AD14 PA5 External Bus Interface (EBI) address and data input / output
pin 14.
EBI_AD15 PA6 External Bus Interface (EBI) address and data input / output
pin 15.
EBI_ALE PF3 External Bus Interface (EBI) Address Latch Enable output.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
EBI_ARDY PF2 External Bus Interface (EBI) Hardware Ready Control input.
EBI_CS0 PD9 External Bus Interface (EBI) Chip Select output 0.
EBI_CS1 PD10 External Bus Interface (EBI) Chip Select output 1.
EBI_CS2 PD11 External Bus Interface (EBI) Chip Select output 2.
EBI_CS3 PD12 External Bus Interface (EBI) Chip Select output 3.
EBI_REn PF5 External Bus Interface (EBI) Read Enable output.
EBI_WEn PF4 External Bus Interface (EBI) Write Enable output.
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output.
LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.
LEU0_RX PD5 PB14 PE15 LEUART0 Receive input.
LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LEU1_RX PC7 PA6 LEUART1 Receive input.
LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half
duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-
so used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC13 PE0 PC0 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PE1 PC1 Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.
PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.
PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.
TIM0_CC0 PA0 PA0 PF6 PD1 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 PF7 PD2 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 PF8 PD3 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PC13 PE10 PB0 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 PB1 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 PB2 Timer 1 Capture Compare input / output channel 2.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.
U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.
U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half du-
plex communication.
US0_CLK PE12 PE5 PC9 USART0 clock input / output.
US0_CS PE13 PE4 PC8 USART0 chip select input / output.
US0_RX PE11 PE6 PC10
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MI-
SO).
US0_TX PE10 PE7 PC11
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 PD2 USART1 clock input / output.
US1_CS PB8 PD3 USART1 chip select input / output.
US1_RX PC1 PD1
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MI-
SO).
US1_TX PC0 PD0
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK PC4 PB5 USART2 clock input / output.
US2_CS PC5 PB6 USART2 chip select input / output.
US2_RX PC3 PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MI-
SO).
US2_TX PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
EFM32G Data Sheet
Pin Definitions
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5.5.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32G280 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.15. GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Port B — PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Port D — — — PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
Port F — — — — — — PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
EFM32G Data Sheet
Pin Definitions
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5.6 EFM32G290 (BGA112)
5.6.1 Pinout
The EFM32G290 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.6. EFM32G280 Pinout (top view, not to scale)
Table 5.16. Device Pinout
BGA112 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
A1 PE15 EBI_AD07 #0 LEU0_RX #2
A2 PE14 EBI_AD06 #0 LEU0_TX #2
A3 PE12 EBI_AD04 #0 TIM1_CC2 #1 US0_CLK #0
A4 PE9 EBI_AD01 #0 PCNT2_S1IN #1
A5 PD10 EBI_CS1 #0
EFM32G Data Sheet
Pin Definitions
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BGA112 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
A6 PF7 TIM0_CC1 #2 U0_RX #0
A7 PF5 EBI_REn #0 TIM0_CDTI2 #2
A8 PF4 EBI_WEn #0 TIM0_CDTI1 #2
A9 PE4 US0_CS #1
A10 PC14 ACMP1_C
H6
TIM0_CDTI1 #1/3
TIM1_CC1 #0
PCNT0_S1IN #0
U0_TX #3
A11 PC15 ACMP1_C
H7
TIM0_CDTI2 #1/3
TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
B1 PA15 EBI_AD08 #0
B2 PE13 EBI_AD05 #0 US0_CS #0 ACMP0_O #0
B3 PE11 EBI_AD03 #0 TIM1_CC1 #1 US0_RX #0 BOOT_RX
B4 PE8 EBI_AD00 #0 PCNT2_S0IN #1
B5 PD11 EBI_CS2 #0
B6 PF8 TIM0_CC2 #2
B7 PF6 TIM0_CC0 #2 U0_TX #0
B8 PF3 EBI_ALE #0 TIM0_CDTI0 #2
B9 PE5 US0_CLK #1
B10 PC12 ACMP1_C
H4 CMU_CLK0 #1
B11 PC13 ACMP1_C
H5
TIM0_CDTI0 #1/3
TIM1_CC0 #0
PCNT0_S0IN #0
C1 PA1 EBI_AD10 #0 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
C2 PA0 EBI_AD09 #0 TIM0_CC0 #0/1 I2C0_SDA #0
C3 PE10 EBI_AD02 #0 TIM1_CC0 #1 US0_TX #0 BOOT_TX
C4 PD13
C5 PD12 EBI_CS3 #0
C6 PF9
C7 VSS Ground.
C8 PF2 EBI_ARDY #0 ACMP1_O #0
DBG_SWO #0
C9 PE6 US0_RX #1
C10 PC10 ACMP1_C
H2 TIM2_CC2 #2 US0_RX #2
C11 PC11 ACMP1_C
H3 US0_TX #2
D1 PA3 EBI_AD12 #0 TIM0_CDTI0 #0 U0_TX #2
D2 PA2 EBI_AD11 #0 TIM0_CC2 #0/1 CMU_CLK0 #0
EFM32G Data Sheet
Pin Definitions
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BGA112 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
D3 PB15
D4 VSS Ground.
D5 IOVDD_6 Digital IO power supply 6.
D6 PD9 LCD_SEG
28 EBI_CS0 #0
D7 IOVDD_5 Digital IO power supply 5.
D8 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1
D9 PE7 US0_TX #1
D10 PC8 ACMP1_C
H0 TIM2_CC0 #2 US0_CS #2
D11 PC9 ACMP1_C
H1 TIM2_CC1 #2 US0_CLK #2
E1 PA6 EBI_AD15 #0 LEU1_RX #1
E2 PA5 EBI_AD14 #0 TIM0_CDTI2 #0 LEU1_TX #1
E3 PA4 EBI_AD13 #0 TIM0_CDTI1 #0 U0_RX #2
E4 PB0 TIM1_CC0 #2
E8 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1
E9 PE0 PCNT0_S0IN #1 U0_TX #1
E10 PE1 PCNT0_S1IN #1 U0_RX #1
E11 PE3 ACMP1_O #1
F1 PB1 TIM1_CC1 #2
F2 PB2 TIM1_CC2 #2
F3 PB3 PCNT1_S0IN #1 US2_TX #1
F4 PB4 PCNT1_S1IN #1 US2_RX #1
F8 VDD_DRE
GPower supply for on-chip voltage regulator.
F9 VSS_DRE
GGround for on-chip voltage regulator.
F10 PE2 ACMP0_O #1
F11 DECOU-
PLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
G1 PB5 US2_CLK #1
G2 PB6 US2_CS #1
G3 VSS Ground.
G4 IOVDD_0 Digital IO power supply 0.
G8 IOVDD_4 Digital IO power supply 4.
G9 VSS Ground.
EFM32G Data Sheet
Pin Definitions
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BGA112 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
G10 PC6 ACMP0_C
H6
LEU1_TX #0
I2C0_SDA #2
G11 PC7 ACMP0_C
H7
LEU1_RX #0
I2C0_SCL #2
H1 PC0 ACMP0_C
H0 PCNT0_S0IN #2 US1_TX #0
H2 PC2 ACMP0_C
H2 US2_TX #0
H3 PD14 I2C0_SDA #3
H4 PA7
H5 PA8 TIM2_CC0 #0
H6 VSS Ground.
H7 IOVDD_3 Digital IO power supply 3.
H8 PD8 CMU_CLK1 #1
H9 PD5 ADC0_CH
5LEU0_RX #0
H10 PD6 ADC0_CH
6LETIM0_OUT0 #0 I2C0_SDA #1
H11 PD7 ADC0_CH
7LETIM0_OUT1 #0 I2C0_SCL #1
J1 PC1 ACMP0_C
H1 PCNT0_S1IN #2 US1_RX #0
J2 PC3 ACMP0_C
H3 US2_RX #0
J3 PD15 I2C0_SCL #3
J4 PA12 TIM2_CC0 #1
J5 PA9 TIM2_CC1 #0
J6 PA10 TIM2_CC2 #0
J7 PB9
J8 PB10
J9 PD2 ADC0_CH
2TIM0_CC1 #3 US1_CLK #1
J10 PD3 ADC0_CH
3TIM0_CC2 #3 US1_CS #1
J11 PD4 ADC0_CH
4LEU0_TX #0
K1 PB7 LFXTAL_P US1_CLK #0
K2 PC4 ACMP0_C
H4
LETIM0_OUT0 #3
PCNT1_S0IN #0 US2_CLK #0
K3 PA13 TIM2_CC1 #1
K4 VSS Ground.
EFM32G Data Sheet
Pin Definitions
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BGA112 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
K5 PA11
K6 RESETn Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure that reset is released.
K7 AVSS_1 Analog ground 1.
K8 AVDD_2 Analog power supply 2.
K9 AVDD_1 Analog power supply 1.
K10 AVSS_0 Analog ground 0.
K11 PD1 ADC0_CH
1
TIM0_CC0 #3
PCNT2_S1IN #0 US1_RX #1
L1 PB8 LFXTAL_N US1_CS #0
L2 PC5 ACMP0_C
H5
LETIM0_OUT1 #3
PCNT1_S1IN #0 US2_CS #0
L3 PA14 TIM2_CC2 #1
L4 IOVDD_1 Digital IO power supply 1.
L5 PB11 DAC0_OU
T0 LETIM0_OUT0 #1
L6 PB12 DAC0_OU
T1 LETIM0_OUT1 #1
L7 AVSS_2 Analog ground 2.
L8 PB13 HFXTAL_
PLEU0_TX #1
L9 PB14 HFXTAL_
NLEU0_RX #1
L10 AVDD_0 Analog power supply 0.
L11 PD0 ADC0_CH
0PCNT2_S0IN #0 US1_TX #1
EFM32G Data Sheet
Pin Definitions
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5.6.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.17. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 Description
ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.
ACMP0_O PE13 PE2 Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.
ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.
ACMP1_O PF2 PE3 Analog comparator ACMP1, digital output.
ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0.
ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1.
ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2.
ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PE11 Bootloader RX.
BOOT_TX PE10 Bootloader TX.
CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0.
DAC0_OUT1 PB12 Digital to Analog Converter DAC0 output channel number 1.
DBG_SWCLK PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a
built-in pull down.
DBG_SWDIO PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a
built-in pull up.
DBG_SWO PF2 PC15
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be
enabled by software to be used.
EBI_AD00 PE8 External Bus Interface (EBI) address and data input / output
pin 00.
EBI_AD01 PE9 External Bus Interface (EBI) address and data input / output
pin 01.
EBI_AD02 PE10 External Bus Interface (EBI) address and data input / output
pin 02.
EBI_AD03 PE11 External Bus Interface (EBI) address and data input / output
pin 03.
EBI_AD04 PE12 External Bus Interface (EBI) address and data input / output
pin 04.
EBI_AD05 PE13 External Bus Interface (EBI) address and data input / output
pin 05.
EBI_AD06 PE14 External Bus Interface (EBI) address and data input / output
pin 06.
EBI_AD07 PE15 External Bus Interface (EBI) address and data input / output
pin 07.
EBI_AD08 PA15 External Bus Interface (EBI) address and data input / output
pin 08.
EBI_AD09 PA0 External Bus Interface (EBI) address and data input / output
pin 09.
EBI_AD10 PA1 External Bus Interface (EBI) address and data input / output
pin 10.
EBI_AD11 PA2 External Bus Interface (EBI) address and data input / output
pin 11.
EBI_AD12 PA3 External Bus Interface (EBI) address and data input / output
pin 12.
EBI_AD13 PA4 External Bus Interface (EBI) address and data input / output
pin 13.
EBI_AD14 PA5 External Bus Interface (EBI) address and data input / output
pin 14.
EBI_AD15 PA6 External Bus Interface (EBI) address and data input / output
pin 15.
EBI_ALE PF3 External Bus Interface (EBI) Address Latch Enable output.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
EBI_ARDY PF2 External Bus Interface (EBI) Hardware Ready Control input.
EBI_CS0 PD9 External Bus Interface (EBI) Chip Select output 0.
EBI_CS1 PD10 External Bus Interface (EBI) Chip Select output 1.
EBI_CS2 PD11 External Bus Interface (EBI) Chip Select output 2.
EBI_CS3 PD12 External Bus Interface (EBI) Chip Select output 3.
EBI_REn PF5 External Bus Interface (EBI) Read Enable output.
EBI_WEn PF4 External Bus Interface (EBI) Write Enable output.
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 PC7 PD15 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 PC6 PD14 I2C0 Serial Data input / output.
LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.
LEU0_RX PD5 PB14 PE15 LEUART0 Receive input.
LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LEU1_RX PC7 PA6 LEUART1 Receive input.
LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half
duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-
so used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC13 PE0 PC0 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PE1 PC1 Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.
PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.
PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.
TIM0_CC0 PA0 PA0 PF6 PD1 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 PF7 PD2 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 PF8 PD3 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PC13 PE10 PB0 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 PB1 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 PB2 Timer 1 Capture Compare input / output channel 2.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.
U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.
U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half du-
plex communication.
US0_CLK PE12 PE5 PC9 USART0 clock input / output.
US0_CS PE13 PE4 PC8 USART0 chip select input / output.
US0_RX PE11 PE6 PC10
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MI-
SO).
US0_TX PE10 PE7 PC11
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 PD2 USART1 clock input / output.
US1_CS PB8 PD3 USART1 chip select input / output.
US1_RX PC1 PD1
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MI-
SO).
US1_TX PC0 PD0
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK PC4 PB5 USART2 clock input / output.
US2_CS PC5 PB6 USART2 chip select input / output.
US2_RX PC3 PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MI-
SO).
US2_TX PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
EFM32G Data Sheet
Pin Definitions
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5.6.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32G290 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.18. GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
Port F — — — — — — PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
EFM32G Data Sheet
Pin Definitions
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5.7 EFM32G840 (QFN64)
5.7.1 Pinout
The EFM32G840 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.7. EFM32G840 Pinout (top view, not to scale)
Table 5.19. Device Pinout
QFN64 Pin# and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
0 VSS Ground.
1 PA0 LCD_SEG13 TIM0_CC0 #0/1 I2C0_SDA #0
2 PA1 LCD_SEG14 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
3 PA2 LCD_SEG15 TIM0_CC2 #0/1 CMU_CLK0 #0
4 PA3 LCD_SEG16 TIM0_CDTI0 #0
5 PA4 LCD_SEG17 TIM0_CDTI1 #0
EFM32G Data Sheet
Pin Definitions
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QFN64 Pin# and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
6 PA5 LCD_SEG18 TIM0_CDTI2 #0 LEU1_TX #1
6 PA6 LCD_SEG19 LEU1_RX #1
8 IOVDD_0 Digital IO power supply 0.
9 PB3 LCD_SEG20 PCNT1_S0IN #1 US2_TX #1
10 PB4 LCD_SEG21 PCNT1_S1IN #1 US2_RX #1
11 PB5 LCD_SEG22 US2_CLK #1
12 PB6 LCD_SEG23 US2_CS #1
13 PC4 ACMP0_CH4 LETIM0_OUT0 #3
PCNT1_S0IN #0 US2_CLK #0
14 PC5 ACMP0_CH5 LETIM0_OUT1 #3
PCNT1_S1IN #0 US2_CS #0
15 PB7 LFXTAL_P US1_CLK #0
16 PB8 LFXTAL_N US1_CS #0
17 PA12 LCD_BCAP_
PTIM2_CC0 #1
18 PA13 LCD_BCAP_
NTIM2_CC1 #1
19 PA14 LCD_BEXT TIM2_CC2 #1
20 RESETn Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
21 PB11 DAC0_OUT0 LETIM0_OUT0 #1
22 PB12 DAC0_OUT1 LETIM0_OUT1 #1
23 AVDD_1 Analog power supply 1.
24 PB13 HFXTAL_P LEU0_TX #1
25 PB14 HFXTAL_N LEU0_RX #1
26 IOVDD_3 Digital IO power supply 3.
27 AVDD_0 Analog power supply 0.
28 PD0 ADC0_CH0 PCNT2_S0IN #0 US1_TX #1
29 PD1 ADC0_CH1 TIM0_CC0 #3 PCNT2_S1IN
#0 US1_RX #1
30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1
31 PD3 ADC0_CH3 TIM0_CC2 #3 US1_CS #1
32 PD4 ADC0_CH4 LEU0_TX #0
33 PD5 ADC0_CH5 LEU0_RX #0
34 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1
35 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1
36 PD8 CMU_CLK1 #1
37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2
EFM32G Data Sheet
Pin Definitions
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QFN64 Pin# and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL #2
39 VDD_DREG Power supply for on-chip voltage regulator.
40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
pin.
41 PE4 LCD_COM0 US0_CS #1
42 PE5 LCD_COM1 US0_CLK #1
43 PE6 LCD_COM2 US0_RX #1
44 PE7 LCD_COM3 US0_TX #1
45 PC12 ACMP1_CH4 CMU_CLK0 #1
46 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 TIM1_CC0
#0 PCNT0_S0IN #0
47 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 TIM1_CC1
#0 PCNT0_S1IN #0
48 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 TIM1_CC2
#0 DBG_SWO #1
49 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1
50 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1
51 PF2 LCD_SEG0 ACMP1_O #0 DBG_SWO #0
52 PF3 LCD_SEG1 TIM0_CDTI0 #2
53 PF4 LCD_SEG2 TIM0_CDTI1 #2
54 PF5 LCD_SEG3 TIM0_CDTI2 #2
55 IOVDD_5 Digital IO power supply 5.
56 PE8 LCD_SEG4 PCNT2_S0IN #1
57 PE9 LCD_SEG5 PCNT2_S1IN #1
58 PE10 LCD_SEG6 TIM1_CC0 #1 US0_TX #0 BOOT_TX
59 PE11 LCD_SEG7 TIM1_CC1 #1 US0_RX #0 BOOT_RX
60 PE12 LCD_SEG8 TIM1_CC2 #1 US0_CLK #0
61 PE13 LCD_SEG9 US0_CS #0 ACMP0_O #0
62 PE14 LCD_SEG10 LEU0_TX #2
63 PE15 LCD_SEG11 LEU0_RX #2
64 PA15 LCD_SEG12
EFM32G Data Sheet
Pin Definitions
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5.7.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.20. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 Description
ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.
ACMP0_O PE13 Analog comparator ACMP0, digital output.
ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.
ACMP1_O PF2 Analog comparator ACMP1, digital output.
ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0.
ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1.
ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2.
ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PE11 Bootloader RX.
BOOT_TX PE10 Bootloader TX.
CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1.
DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0.
DAC0_OUT1 PB12 Digital to Analog Converter DAC0 output channel number 1.
DBG_SWCLK PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a
built-in pull down.
DBG_SWDIO PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a
built-in pull up.
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Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
DBG_SWO PF2 PC15
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be
enabled by software to be used.
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output.
LCD_BCAP_N PA13
LCD voltage booster (optional), boost capacitor, negative pin.
If using the LCD voltage booster, connect a 22 nF capacitor
between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor, positive pin.
If using the LCD voltage booster, connect a 22 nF capacitor
between LCD_BCAP_N and LCD_BCAP_P.
LCD_BEXT PA14
LCD voltage booster (optional), boost output. If using the LCD
voltage booster, connect a 1 uF capacitor between this pin
and VSS.
An external LCD voltage may also be applied to this pin if the
booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin
may be left unconnected or used as a GPIO.
LCD_COM0 PE4 LCD driver common line number 0.
LCD_COM1 PE5 LCD driver common line number 1.
LCD_COM2 PE6 LCD driver common line number 2.
LCD_COM3 PE7 LCD driver common line number 3.
LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled
by SEGEN2.
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Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled
by SEGEN2.
LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are control-
led by SEGEN2.
LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are control-
led by SEGEN2.
LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG20 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG21 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG22 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG23 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.
LEU0_RX PD5 PB14 PE15 LEUART0 Receive input.
LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LEU1_RX PC7 PA6 LEUART1 Receive input.
LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half
duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-
so used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC13 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 Pulse Counter PCNT0 input number 1.
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Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.
PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.
PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.
TIM0_CC0 PA0 PA0 PD1 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 PD2 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 PD3 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2.
TIM2_CC0 PA12 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA13 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA14 Timer 2 Capture Compare input / output channel 2.
US0_CLK PE12 PE5 USART0 clock input / output.
US0_CS PE13 PE4 USART0 chip select input / output.
US0_RX PE11 PE6
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MI-
SO).
US0_TX PE10 PE7
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 PD2 USART1 clock input / output.
US1_CS PB8 PD3 USART1 chip select input / output.
US1_RX PD1
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MI-
SO).
US1_TX PD0
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK PC4 PB5 USART2 clock input / output.
US2_CS PC5 PB6 USART2 chip select input / output.
US2_RX PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MI-
SO).
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
US2_TX PB3
USART2 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
5.7.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32G840 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.21. GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
Port A PA15 PA14 PA13 PA12 — — — — — PA6 PA5 PA4 PA3 PA2 PA1 PA0
Port B — PB14 PB13 PB12 PB11 — — PB8 PB7 PB6 PB5 PB4 PB3 — — —
Port C PC15 PC14 PC13 PC12 — — — — PC7 PC6 PC5 PC4 — — — —
Port D — — — — — — — PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 — — — —
Port F — — — — — — — — — — PF5 PF4 PF3 PF2 PF1 PF0
EFM32G Data Sheet
Pin Definitions
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5.8 EFM32G842 (TQFP64)
5.8.1 Pinout
The EFM32G842 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.8. EFM32G842 Pinout (top view, not to scale)
Table 5.22. Device Pinout
TQFP64 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
1 PA0 LCD_SEG13 TIM0_CC0 #0/1 I2C0_SDA #0
2 PA1 LCD_SEG14 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
3 PA2 LCD_SEG15 TIM0_CC2 #0/1 CMU_CLK0 #0
4 PA3 LCD_SEG16 TIM0_CDTI0 #0
5 PA4 LCD_SEG17 TIM0_CDTI1 #0
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Pin Definitions
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TQFP64 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
6 PA5 LCD_SEG18 TIM0_CDTI2 #0 LEU1_TX #1
7 IOVDD_0 Digital IO power supply 0.
8 VSS Ground.
9 PB3 LCD_SEG20 PCNT1_S0IN #1 US2_TX #1
10 PB4 LCD_SEG21 PCNT1_S1IN #1 US2_RX #1
11 PB5 LCD_SEG22 US2_CLK #1
12 PB6 LCD_SEG23 US2_CS #1
13 PC4 ACMP0_CH4 LETIM0_OUT0 #3
PCNT1_S0IN #0 US2_CLK #0
14 PC5 ACMP0_CH5 LETIM0_OUT1 #3
PCNT1_S1IN #0 US2_CS #0
15 PB7 LFXTAL_P US1_CLK #0
16 PB8 LFXTAL_N US1_CS #0
17 PA12 LCD_BCAP_
PTIM2_CC0 #1
18 PA13 LCD_BCAP_
NTIM2_CC1 #1
19 PA14 LCD_BEXT TIM2_CC2 #1
20 RESETn Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
21 PB11 DAC0_OUT0 LETIM0_OUT0 #1
22 VSS Ground.
23 AVDD_1 Analog power supply 1.
24 PB13 HFXTAL_P LEU0_TX #1
25 PB14 HFXTAL_N LEU0_RX #1
26 IOVDD_3 Digital IO power supply 3.
27 AVDD_0 Analog power supply 0.
28 PD0 ADC0_CH0 PCNT2_S0IN #0 US1_TX #1
29 PD1 ADC0_CH1 TIM0_CC0 #3 PCNT2_S1IN
#0 US1_RX #1
30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1
31 PD3 ADC0_CH3 TIM0_CC2 #3 US1_CS #1
32 PD4 ADC0_CH4 LEU0_TX #0
33 PD5 ADC0_CH5 LEU0_RX #0
34 PD6 ADC0_CH6 LETIM0_OUT0 #0 I2C0_SDA #1
35 PD7 ADC0_CH7 LETIM0_OUT1 #0 I2C0_SCL #1
36 PD8 CMU_CLK1 #1
37 PC6 ACMP0_CH6 LEU1_TX #0 I2C0_SDA #2
EFM32G Data Sheet
Pin Definitions
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TQFP64 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog Timers Communication Other
38 PC7 ACMP0_CH7 LEU1_RX #0 I2C0_SCL #2
39 VDD_DREG Power supply for on-chip voltage regulator.
40 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
pin.
41 PE4 LCD_COM0 US0_CS #1
42 PE5 LCD_COM1 US0_CLK #1
43 PE6 LCD_COM2 US0_RX #1
44 PE7 LCD_COM3 US0_TX #1
45 PC12 ACMP1_CH4 CMU_CLK0 #1
46 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 TIM1_CC0
#0 PCNT0_S0IN #0
47 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 TIM1_CC1
#0 PCNT0_S1IN #0
48 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 TIM1_CC2
#0 DBG_SWO #1
49 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1
50 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1
51 PF2 LCD_SEG0 ACMP1_O #0 DBG_SWO #0
52 PF3 LCD_SEG1 TIM0_CDTI0 #2
53 PF4 LCD_SEG2 TIM0_CDTI1 #2
54 PF5 LCD_SEG3 TIM0_CDTI2 #2
55 IOVDD_5 Digital IO power supply 5.
56 VSS Ground.
57 PE8 LCD_SEG4 PCNT2_S0IN #1
58 PE9 LCD_SEG5 PCNT2_S1IN #1
59 PE10 LCD_SEG6 TIM1_CC0 #1 US0_TX #0 BOOT_TX
60 PE11 LCD_SEG7 TIM1_CC1 #1 US0_RX #0 BOOT_RX
61 PE12 LCD_SEG8 TIM1_CC2 #1 US0_CLK #0
62 PE13 LCD_SEG9 US0_CS #0 ACMP0_O #0
63 PE14 LCD_SEG10 LEU0_TX #2
64 PE15 LCD_SEG11 LEU0_RX #2
EFM32G Data Sheet
Pin Definitions
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5.8.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.23. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 Description
ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.
ACMP0_O PE13 Analog comparator ACMP0, digital output.
ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.
ACMP1_O PF2 Analog comparator ACMP1, digital output.
ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0.
ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1.
ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2.
ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PE11 Bootloader RX.
BOOT_TX PE10 Bootloader TX.
CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1.
DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0.
DBG_SWCLK PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a
built-in pull down.
DBG_SWDIO PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a
built-in pull up.
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Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
DBG_SWO PF2 PC15
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be
enabled by software to be used.
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output.
LCD_BCAP_N PA13
LCD voltage booster (optional), boost capacitor, negative pin.
If using the LCD voltage booster, connect a 22 nF capacitor
between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor, positive pin.
If using the LCD voltage booster, connect a 22 nF capacitor
between LCD_BCAP_N and LCD_BCAP_P.
LCD_BEXT PA14
LCD voltage booster (optional), boost output. If using the LCD
voltage booster, connect a 1 uF capacitor between this pin
and VSS.
An external LCD voltage may also be applied to this pin if the
booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin
may be left unconnected or used as a GPIO.
LCD_COM0 PE4 LCD driver common line number 0.
LCD_COM1 PE5 LCD driver common line number 1.
LCD_COM2 PE6 LCD driver common line number 2.
LCD_COM3 PE7 LCD driver common line number 3.
LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled
by SEGEN2.
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Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled
by SEGEN2.
LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are control-
led by SEGEN2.
LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are control-
led by SEGEN2.
LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG20 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG21 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG22 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG23 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PF1 PC5 Low Energy Timer LETIM0, output channel 1.
LEU0_RX PD5 PB14 PE15 LEUART0 Receive input.
LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LEU1_RX PC7 LEUART1 Receive input.
LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half
duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-
so used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC13 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.
PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.
PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 137
Alternate LOCATION
Functionality 0 1 2 3 Description
TIM0_CC0 PA0 PA0 PD1 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 PD2 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 PD3 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PC13 PE10 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 Timer 1 Capture Compare input / output channel 2.
TIM2_CC0 PA12 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA13 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA14 Timer 2 Capture Compare input / output channel 2.
US0_CLK PE12 PE5 USART0 clock input / output.
US0_CS PE13 PE4 USART0 chip select input / output.
US0_RX PE11 PE6
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MI-
SO).
US0_TX PE10 PE7
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 PD2 USART1 clock input / output.
US1_CS PB8 PD3 USART1 chip select input / output.
US1_RX PD1
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MI-
SO).
US1_TX PD0
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK PC4 PB5 USART2 clock input / output.
US2_CS PC5 PB6 USART2 chip select input / output.
US2_RX PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MI-
SO).
US2_TX PB3
USART2 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
EFM32G Data Sheet
Pin Definitions
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5.8.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32G842 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.24. GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
Port A — PA14 PA13 PA12 — — — — — — PA5 PA4 PA3 PA2 PA1 PA0
Port B — PB14 PB13 — PB11 — — PB8 PB7 PB6 PB5 PB4 PB3 — — —
Port C PC15 PC14 PC13 PC12 — — — — PC7 PC6 PC5 PC4 — — — —
Port D — — — — — — — PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 — — — —
Port F — — — — — — — — — — PF5 PF4 PF3 PF2 PF1 PF0
EFM32G Data Sheet
Pin Definitions
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5.9 EFM32G880 (LQFP100)
5.9.1 Pinout
The EFM32G880 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.9. EFM32G880 Pinout (top view, not to scale)
Table 5.25. Device Pinout
LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
1 PA0 LCD_SEG
13 EBI_AD09 #0 TIM0_CC0 #0/1 I2C0_SDA #0
2 PA1 LCD_SEG
14 EBI_AD10 #0 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
3 PA2 LCD_SEG
15 EBI_AD11 #0 TIM0_CC2 #0/1 CMU_CLK0 #0
EFM32G Data Sheet
Pin Definitions
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LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
4 PA3 LCD_SEG
16 EBI_AD12 #0 TIM0_CDTI0 #0 U0_TX #2
5 PA4 LCD_SEG
17 EBI_AD13 #0 TIM0_CDTI1 #0 U0_RX #2
6 PA5 LCD_SEG
18 EBI_AD14 #0 TIM0_CDTI2 #0 LEU1_TX #1
7 PA6 LCD_SEG
19 EBI_AD15 #0 LEU1_RX #1
8 IOVDD_0 Digital IO power supply 0.
9 PB0 LCD_SEG
32 TIM1_CC0 #2
10 PB1 LCD_SEG
33 TIM1_CC1 #2
11 PB2 LCD_SEG
34 TIM1_CC2 #2
12 PB3 LCD_SEG
20 PCNT1_S0IN #1 US2_TX #1
13 PB4 LCD_SEG
21 PCNT1_S1IN #1 US2_RX #1
14 PB5 LCD_SEG
22 US2_CLK #1
15 PB6 LCD_SEG
23 US2_CS #1
16 VSS Ground.
17 IOVDD_1 Digital IO power supply 1.
18 PC0 ACMP0_C
H0 PCNT0_S0IN #2 US1_TX #0
19 PC1 ACMP0_C
H1 PCNT0_S1IN #2 US1_RX #0
20 PC2 ACMP0_C
H2 US2_TX #0
21 PC3 ACMP0_C
H3 US2_RX #0
22 PC4 ACMP0_C
H4
LETIM0_OUT0 #3
PCNT1_S0IN #0 US2_CLK #0
23 PC5 ACMP0_C
H5
LETIM0_OUT1 #3
PCNT1_S1IN #0 US2_CS #0
24 PB7 LFXTAL_P US1_CLK #0
25 PB8 LFXTAL_N US1_CS #0
26 PA7 LCD_SEG
35
27 PA8 LCD_SEG
36 TIM2_CC0 #0
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Pin Definitions
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LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
28 PA9 LCD_SEG
37 TIM2_CC1 #0
29 PA10 LCD_SEG
38 TIM2_CC2 #0
30 PA11 LCD_SEG
39
31 IOVDD_2 Digital IO power supply 2.
32 VSS Ground.
33 PA12 LCD_BCA
P_P TIM2_CC0 #1
34 PA13 LCD_BCA
P_N TIM2_CC1 #1
35 PA14 LCD_BEX
TTIM2_CC2 #1
36 RESETn Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure that reset is released.
37 PB9
38 PB10
39 PB11 DAC0_OU
T0 LETIM0_OUT0 #1
40 PB12 DAC0_OU
T1 LETIM0_OUT1 #1
41 AVDD_1 Analog power supply 1.
42 PB13 HFXTAL_
PLEU0_TX #1
43 PB14 HFXTAL_
NLEU0_RX #1
44 IOVDD_3 Digital IO power supply 3.
45 AVDD_0 Analog power supply 0.
46 PD0 ADC0_CH
0PCNT2_S0IN #0 US1_TX #1
47 PD1 ADC0_CH
1
TIM0_CC0 #3
PCNT2_S1IN #0 US1_RX #1
48 PD2 ADC0_CH
2TIM0_CC1 #3 US1_CLK #1
49 PD3 ADC0_CH
3TIM0_CC2 #3 US1_CS #1
50 PD4 ADC0_CH
4LEU0_TX #0
51 PD5 ADC0_CH
5LEU0_RX #0
52 PD6 ADC0_CH
6LETIM0_OUT0 #0 I2C0_SDA #1
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Pin Definitions
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LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
53 PD7 ADC0_CH
7LETIM0_OUT1 #0 I2C0_SCL #1
54 PD8 CMU_CLK1 #1
55 PC6 ACMP0_C
H6
LEU1_TX #0
I2C0_SDA #2
56 PC7 ACMP0_C
H7
LEU1_RX #0
I2C0_SCL #2
57 VDD_DRE
GPower supply for on-chip voltage regulator.
58 VSS Ground.
59 DECOU-
PLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
60 PE0 PCNT0_S0IN #1 U0_TX #1
61 PE1 PCNT0_S1IN #1 U0_RX #1
62 PE2 ACMP0_O #1
63 PE3 ACMP1_O #1
64 PE4 LCD_COM
0US0_CS #1
65 PE5 LCD_COM
1US0_CLK #1
66 PE6 LCD_COM
2US0_RX #1
67 PE7 LCD_COM
3US0_TX #1
68 PC8 ACMP1_C
H0 TIM2_CC0 #2 US0_CS #2
69 PC9 ACMP1_C
H1 TIM2_CC1 #2 US0_CLK #2
70 PC10 ACMP1_C
H2 TIM2_CC2 #2 US0_RX #2
71 PC11 ACMP1_C
H3 US0_TX #2
72 PC12 ACMP1_C
H4 CMU_CLK0 #1
73 PC13 ACMP1_C
H5
TIM0_CDTI0 #1/3
TIM1_CC0 #0
PCNT0_S0IN #0
74 PC14 ACMP1_C
H6
TIM0_CDTI1 #1/3
TIM1_CC1 #0
PCNT0_S1IN #0
U0_TX #3
75 PC15 ACMP1_C
H7
TIM0_CDTI2 #1/3
TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
76 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1
EFM32G Data Sheet
Pin Definitions
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LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
77 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1
78 PF2 LCD_SEG
0EBI_ARDY #0 ACMP1_O #0
DBG_SWO #0
79 PF3 LCD_SEG
1EBI_ALE #0 TIM0_CDTI0 #2
80 PF4 LCD_SEG
2EBI_WEn #0 TIM0_CDTI1 #2
81 PF5 LCD_SEG
3EBI_REn #0 TIM0_CDTI2 #2
82 IOVDD_5 Digital IO power supply 5.
83 VSS Ground.
84 PF6 LCD_SEG
24 TIM0_CC0 #2 U0_TX #0
85 PF7 LCD_SEG
25 TIM0_CC1 #2 U0_RX #0
86 PF8 LCD_SEG
26 TIM0_CC2 #2
87 PF9 LCD_SEG
27
88 PD9 LCD_SEG
28 EBI_CS0 #0
89 PD10 LCD_SEG
29 EBI_CS1 #0
90 PD11 LCD_SEG
30 EBI_CS2 #0
91 PD12 LCD_SEG
31 EBI_CS3 #0
92 PE8 LCD_SEG
4EBI_AD00 #0 PCNT2_S0IN #1
93 PE9 LCD_SEG
5EBI_AD01 #0 PCNT2_S1IN #1
94 PE10 LCD_SEG
6EBI_AD02 #0 TIM1_CC0 #1 US0_TX #0 BOOT_TX
95 PE11 LCD_SEG
7EBI_AD03 #0 TIM1_CC1 #1 US0_RX #0 BOOT_RX
96 PE12 LCD_SEG
8EBI_AD04 #0 TIM1_CC2 #1 US0_CLK #0
97 PE13 LCD_SEG
9EBI_AD05 #0 US0_CS #0 ACMP0_O #0
98 PE14 LCD_SEG
10 EBI_AD06 #0 LEU0_TX #2
99 PE15 LCD_SEG
11 EBI_AD07 #0 LEU0_RX #2
EFM32G Data Sheet
Pin Definitions
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LQFP100 Pin#
and Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
100 PA15 LCD_SEG
12 EBI_AD08 #0
EFM32G Data Sheet
Pin Definitions
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5.9.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.26. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 Description
ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.
ACMP0_O PE13 PE2 Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.
ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.
ACMP1_O PF2 PE3 Analog comparator ACMP1, digital output.
ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0.
ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1.
ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2.
ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PE11 Bootloader RX.
BOOT_TX PE10 Bootloader TX.
CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0.
DAC0_OUT1 PB12 Digital to Analog Converter DAC0 output channel number 1.
DBG_SWCLK PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a
built-in pull down.
DBG_SWDIO PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a
built-in pull up.
DBG_SWO PF2 PC15
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be
enabled by software to be used.
EBI_AD00 PE8 External Bus Interface (EBI) address and data input / output
pin 00.
EBI_AD01 PE9 External Bus Interface (EBI) address and data input / output
pin 01.
EBI_AD02 PE10 External Bus Interface (EBI) address and data input / output
pin 02.
EBI_AD03 PE11 External Bus Interface (EBI) address and data input / output
pin 03.
EBI_AD04 PE12 External Bus Interface (EBI) address and data input / output
pin 04.
EBI_AD05 PE13 External Bus Interface (EBI) address and data input / output
pin 05.
EBI_AD06 PE14 External Bus Interface (EBI) address and data input / output
pin 06.
EBI_AD07 PE15 External Bus Interface (EBI) address and data input / output
pin 07.
EBI_AD08 PA15 External Bus Interface (EBI) address and data input / output
pin 08.
EBI_AD09 PA0 External Bus Interface (EBI) address and data input / output
pin 09.
EBI_AD10 PA1 External Bus Interface (EBI) address and data input / output
pin 10.
EBI_AD11 PA2 External Bus Interface (EBI) address and data input / output
pin 11.
EBI_AD12 PA3 External Bus Interface (EBI) address and data input / output
pin 12.
EBI_AD13 PA4 External Bus Interface (EBI) address and data input / output
pin 13.
EBI_AD14 PA5 External Bus Interface (EBI) address and data input / output
pin 14.
EBI_AD15 PA6 External Bus Interface (EBI) address and data input / output
pin 15.
EBI_ALE PF3 External Bus Interface (EBI) Address Latch Enable output.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
EBI_ARDY PF2 External Bus Interface (EBI) Hardware Ready Control input.
EBI_CS0 PD9 External Bus Interface (EBI) Chip Select output 0.
EBI_CS1 PD10 External Bus Interface (EBI) Chip Select output 1.
EBI_CS2 PD11 External Bus Interface (EBI) Chip Select output 2.
EBI_CS3 PD12 External Bus Interface (EBI) Chip Select output 3.
EBI_REn PF5 External Bus Interface (EBI) Read Enable output.
EBI_WEn PF4 External Bus Interface (EBI) Write Enable output.
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 PC7 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 PC6 I2C0 Serial Data input / output.
LCD_BCAP_N PA13
LCD voltage booster (optional), boost capacitor, negative pin.
If using the LCD voltage booster, connect a 22 nF capacitor
between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor, positive pin.
If using the LCD voltage booster, connect a 22 nF capacitor
between LCD_BCAP_N and LCD_BCAP_P.
LCD_BEXT PA14
LCD voltage booster (optional), boost output. If using the LCD
voltage booster, connect a 1 uF capacitor between this pin
and VSS.
An external LCD voltage may also be applied to this pin if the
booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin
may be left unconnected or used as a GPIO.
LCD_COM0 PE4 LCD driver common line number 0.
LCD_COM1 PE5 LCD driver common line number 1.
LCD_COM2 PE6 LCD driver common line number 2.
LCD_COM3 PE7 LCD driver common line number 3.
LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled
by SEGEN2.
LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled
by SEGEN2.
LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are control-
led by SEGEN2.
LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are control-
led by SEGEN2.
LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG20 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG21 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG22 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG23 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG24 PF6 LCD segment line 24. Segments 24, 25, 26 and 27 are con-
trolled by SEGEN6.
LCD_SEG25 PF7 LCD segment line 25. Segments 24, 25, 26 and 27 are con-
trolled by SEGEN6.
LCD_SEG26 PF8 LCD segment line 26. Segments 24, 25, 26 and 27 are con-
trolled by SEGEN6.
LCD_SEG27 PF9 LCD segment line 27. Segments 24, 25, 26 and 27 are con-
trolled by SEGEN6.
LCD_SEG28 PD9 LCD segment line 28. Segments 28, 29, 30 and 31 are con-
trolled by SEGEN7.
LCD_SEG29 PD10 LCD segment line 29. Segments 28, 29, 30 and 31 are con-
trolled by SEGEN7.
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 149
Alternate LOCATION
Functionality 0 1 2 3 Description
LCD_SEG30 PD11 LCD segment line 30. Segments 28, 29, 30 and 31 are con-
trolled by SEGEN7.
LCD_SEG31 PD12 LCD segment line 31. Segments 28, 29, 30 and 31 are con-
trolled by SEGEN7.
LCD_SEG32 PB0 LCD segment line 32. Segments 32, 33, 34 and 35 are con-
trolled by SEGEN8.
LCD_SEG33 PB1 LCD segment line 33. Segments 32, 33, 34 and 35 are con-
trolled by SEGEN8.
LCD_SEG34 PB2 LCD segment line 34. Segments 32, 33, 34 and 35 are con-
trolled by SEGEN8.
LCD_SEG35 PA7 LCD segment line 35. Segments 32, 33, 34 and 35 are con-
trolled by SEGEN8.
LCD_SEG36 PA8 LCD segment line 36. Segments 36, 37, 38 and 39 are con-
trolled by SEGEN9.
LCD_SEG37 PA9 LCD segment line 37. Segments 36, 37, 38 and 39 are con-
trolled by SEGEN9.
LCD_SEG38 PA10 LCD segment line 38. Segments 36, 37, 38 and 39 are con-
trolled by SEGEN9.
LCD_SEG39 PA11 LCD segment line 39. Segments 36, 37, 38 and 39 are con-
trolled by SEGEN9.
LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.
LEU0_RX PD5 PB14 PE15 LEUART0 Receive input.
LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LEU1_RX PC7 PA6 LEUART1 Receive input.
LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half
duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-
so used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC13 PE0 PC0 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PE1 PC1 Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.
PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.
PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.
TIM0_CC0 PA0 PA0 PF6 PD1 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 PF7 PD2 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 PF8 PD3 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PC13 PE10 PB0 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 PB1 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 PB2 Timer 1 Capture Compare input / output channel 2.
TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.
U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.
U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half du-
plex communication.
US0_CLK PE12 PE5 PC9 USART0 clock input / output.
US0_CS PE13 PE4 PC8 USART0 chip select input / output.
US0_RX PE11 PE6 PC10
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MI-
SO).
US0_TX PE10 PE7 PC11
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 PD2 USART1 clock input / output.
US1_CS PB8 PD3 USART1 chip select input / output.
US1_RX PC1 PD1
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MI-
SO).
US1_TX PC0 PD0
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK PC4 PB5 USART2 clock input / output.
US2_CS PC5 PB6 USART2 chip select input / output.
US2_RX PC3 PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MI-
SO).
US2_TX PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
EFM32G Data Sheet
Pin Definitions
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5.9.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32G880 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.27. GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Port B — PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Port D — — — PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
Port F — — — — — — PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
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5.10 EFM32G890 (BGA112)
5.10.1 Pinout
The EFM32G890 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.10. EFM32G890 Pinout (top view, not to scale)
Table 5.28. Device Pinout
BGA112 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
A1 PE15 LCD_SEG
11 EBI_AD07 #0 LEU0_RX #2
A2 PE14 LCD_SEG
10 EBI_AD06 #0 LEU0_TX #2
A3 PE12 LCD_SEG
8EBI_AD04 #0 TIM1_CC2 #1 US0_CLK #0
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Pin Definitions
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BGA112 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
A4 PE9 LCD_SEG
5EBI_AD01 #0 PCNT2_S1IN #1
A5 PD10 LCD_SEG
29 EBI_CS1 #0
A6 PF7 LCD_SEG
25 TIM0_CC1 #2 U0_RX #0
A7 PF5 LCD_SEG
3EBI_REn #0 TIM0_CDTI2 #2
A8 PF4 LCD_SEG
2EBI_WEn #0 TIM0_CDTI1 #2
A9 PE4 LCD_COM
0US0_CS #1
A10 PC14 ACMP1_C
H6
TIM0_CDTI1 #1/3
TIM1_CC1 #0
PCNT0_S1IN #0
U0_TX #3
A11 PC15 ACMP1_C
H7
TIM0_CDTI2 #1/3
TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
B1 PA15 LCD_SEG
12 EBI_AD08 #0
B2 PE13 LCD_SEG
9EBI_AD05 #0 US0_CS #0 ACMP0_O #0
B3 PE11 LCD_SEG
7EBI_AD03 #0 TIM1_CC1 #1 US0_RX #0 BOOT_RX
B4 PE8 LCD_SEG
4EBI_AD00 #0 PCNT2_S0IN #1
B5 PD11 LCD_SEG
30 EBI_CS2 #0
B6 PF8 LCD_SEG
26 TIM0_CC2 #2
B7 PF6 LCD_SEG
24 TIM0_CC0 #2 U0_TX #0
B8 PF3 LCD_SEG
1EBI_ALE #0 TIM0_CDTI0 #2
B9 PE5 LCD_COM
1US0_CLK #1
B10 PC12 ACMP1_C
H4 CMU_CLK0 #1
B11 PC13 ACMP1_C
H5
TIM0_CDTI0 #1/3
TIM1_CC0 #0
PCNT0_S0IN #0
C1 PA1 LCD_SEG
14 EBI_AD10 #0 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
C2 PA0 LCD_SEG
13 EBI_AD09 #0 TIM0_CC0 #0/1 I2C0_SDA #0
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Pin Definitions
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BGA112 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
C3 PE10 LCD_SEG
6EBI_AD02 #0 TIM1_CC0 #1 US0_TX #0 BOOT_TX
C4 PD13
C5 PD12 LCD_SEG
31 EBI_CS3 #0
C6 PF9 LCD_SEG
27
C7 VSS Ground.
C8 PF2 LCD_SEG
0EBI_ARDY #0 ACMP1_O #0
DBG_SWO #0
C9 PE6 LCD_COM
2US0_RX #1
C10 PC10 ACMP1_C
H2 TIM2_CC2 #2 US0_RX #2
C11 PC11 ACMP1_C
H3 US0_TX #2
D1 PA3 LCD_SEG
16 EBI_AD12 #0 TIM0_CDTI0 #0 U0_TX #2
D2 PA2 LCD_SEG
15 EBI_AD11 #0 TIM0_CC2 #0/1 CMU_CLK0 #0
D3 PB15
D4 VSS Ground.
D5 IOVDD_6 Digital IO power supply 6.
D6 PD9 LCD_SEG
28 EBI_CS0 #0
D7 IOVDD_5 Digital IO power supply 5.
D8 PF1 LETIM0_OUT1 #2 DBG_SWDIO #0/1
D9 PE7 LCD_COM
3US0_TX #1
D10 PC8 ACMP1_C
H0 TIM2_CC0 #2 US0_CS #2
D11 PC9 ACMP1_C
H1 TIM2_CC1 #2 US0_CLK #2
E1 PA6 LCD_SEG
19 EBI_AD15 #0 LEU1_RX #1
E2 PA5 LCD_SEG
18 EBI_AD14 #0 TIM0_CDTI2 #0 LEU1_TX #1
E3 PA4 LCD_SEG
17 EBI_AD13 #0 TIM0_CDTI1 #0 U0_RX #2
E4 PB0 LCD_SEG
32 TIM1_CC0 #2
E8 PF0 LETIM0_OUT0 #2 DBG_SWCLK #0/1
EFM32G Data Sheet
Pin Definitions
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BGA112 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
E9 PE0 PCNT0_S0IN #1 U0_TX #1
E10 PE1 PCNT0_S1IN #1 U0_RX #1
E11 PE3 ACMP1_O #1
F1 PB1 LCD_SEG
33 TIM1_CC1 #2
F2 PB2 LCD_SEG
34 TIM1_CC2 #2
F3 PB3 LCD_SEG
20 PCNT1_S0IN #1 US2_TX #1
F4 PB4 LCD_SEG
21 PCNT1_S1IN #1 US2_RX #1
F8 VDD_DRE
GPower supply for on-chip voltage regulator.
F9 VSS_DRE
GGround for on-chip voltage regulator.
F10 PE2 ACMP0_O #1
F11 DECOU-
PLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
G1 PB5 LCD_SEG
22 US2_CLK #1
G2 PB6 LCD_SEG
23 US2_CS #1
G3 VSS Ground.
G4 IOVDD_0 Digital IO power supply 0.
G8 IOVDD_4 Digital IO power supply 4.
G9 VSS Ground.
G10 PC6 ACMP0_C
H6
LEU1_TX #0
I2C0_SDA #2
G11 PC7 ACMP0_C
H7
LEU1_RX #0
I2C0_SCL #2
H1 PC0 ACMP0_C
H0 PCNT0_S0IN #2 US1_TX #0
H2 PC2 ACMP0_C
H2 US2_TX #0
H3 PD14 I2C0_SDA #3
H4 PA7 LCD_SEG
35
H5 PA8 LCD_SEG
36 TIM2_CC0 #0
H6 VSS Ground.
H7 IOVDD_3 Digital IO power supply 3.
H8 PD8 CMU_CLK1 #1
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Pin Definitions
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BGA112 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
H9 PD5 ADC0_CH
5LEU0_RX #0
H10 PD6 ADC0_CH
6LETIM0_OUT0 #0 I2C0_SDA #1
H11 PD7 ADC0_CH
7LETIM0_OUT1 #0 I2C0_SCL #1
J1 PC1 ACMP0_C
H1 PCNT0_S1IN #2 US1_RX #0
J2 PC3 ACMP0_C
H3 US2_RX #0
J3 PD15 I2C0_SCL #3
J4 PA12 LCD_BCA
P_P TIM2_CC0 #1
J5 PA9 LCD_SEG
37 TIM2_CC1 #0
J6 PA10 LCD_SEG
38 TIM2_CC2 #0
J7 PB9
J8 PB10
J9 PD2 ADC0_CH
2TIM0_CC1 #3 US1_CLK #1
J10 PD3 ADC0_CH
3TIM0_CC2 #3 US1_CS #1
J11 PD4 ADC0_CH
4LEU0_TX #0
K1 PB7 LFXTAL_P US1_CLK #0
K2 PC4 ACMP0_C
H4
LETIM0_OUT0 #3
PCNT1_S0IN #0 US2_CLK #0
K3 PA13 LCD_BCA
P_N TIM2_CC1 #1
K4 VSS Ground.
K5 PA11 LCD_SEG
39
K6 RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure that reset is released.
K7 AVSS_1 Analog ground 1.
K8 AVDD_2 Analog power supply 2.
K9 AVDD_1 Analog power supply 1.
K10 AVSS_0 Analog ground 0.
K11 PD1 ADC0_CH
1
TIM0_CC0 #3
PCNT2_S1IN #0 US1_RX #1
L1 PB8 LFXTAL_N US1_CS #0
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Pin Definitions
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BGA112 Pin# and
Name Pin Alternate Functionality / Description
Pin # Pin Name Analog EBI Timers Communication Other
L2 PC5 ACMP0_C
H5
LETIM0_OUT1 #3
PCNT1_S1IN #0 US2_CS #0
L3 PA14 LCD_BEX
TTIM2_CC2 #1
L4 IOVDD_1 Digital IO power supply 1.
L5 PB11 DAC0_OU
T0 LETIM0_OUT0 #1
L6 PB12 DAC0_OU
T1 LETIM0_OUT1 #1
L7 AVSS_2 Analog ground 2.
L8 PB13 HFXTAL_
PLEU0_TX #1
L9 PB14 HFXTAL_
NLEU0_RX #1
L10 AVDD_0 Analog power supply 0.
L11 PD0 ADC0_CH
0PCNT2_S0IN #0 US1_TX #1
EFM32G Data Sheet
Pin Definitions
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5.10.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.29. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 Description
ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.
ACMP0_O PE13 PE2 Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.
ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.
ACMP1_O PF2 PE3 Analog comparator ACMP1, digital output.
ADC0_CH0 PD0 Analog to digital converter ADC0, input channel number 0.
ADC0_CH1 PD1 Analog to digital converter ADC0, input channel number 1.
ADC0_CH2 PD2 Analog to digital converter ADC0, input channel number 2.
ADC0_CH3 PD3 Analog to digital converter ADC0, input channel number 3.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PE11 Bootloader RX.
BOOT_TX PE10 Bootloader TX.
CMU_CLK0 PA2 PC12 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 PD8 Clock Management Unit, clock output number 1.
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Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
DAC0_OUT0 PB11 Digital to Analog Converter DAC0 output channel number 0.
DAC0_OUT1 PB12 Digital to Analog Converter DAC0 output channel number 1.
DBG_SWCLK PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a
built-in pull down.
DBG_SWDIO PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a
built-in pull up.
DBG_SWO PF2 PC15
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be
enabled by software to be used.
EBI_AD00 PE8 External Bus Interface (EBI) address and data input / output
pin 00.
EBI_AD01 PE9 External Bus Interface (EBI) address and data input / output
pin 01.
EBI_AD02 PE10 External Bus Interface (EBI) address and data input / output
pin 02.
EBI_AD03 PE11 External Bus Interface (EBI) address and data input / output
pin 03.
EBI_AD04 PE12 External Bus Interface (EBI) address and data input / output
pin 04.
EBI_AD05 PE13 External Bus Interface (EBI) address and data input / output
pin 05.
EBI_AD06 PE14 External Bus Interface (EBI) address and data input / output
pin 06.
EBI_AD07 PE15 External Bus Interface (EBI) address and data input / output
pin 07.
EBI_AD08 PA15 External Bus Interface (EBI) address and data input / output
pin 08.
EBI_AD09 PA0 External Bus Interface (EBI) address and data input / output
pin 09.
EBI_AD10 PA1 External Bus Interface (EBI) address and data input / output
pin 10.
EBI_AD11 PA2 External Bus Interface (EBI) address and data input / output
pin 11.
EBI_AD12 PA3 External Bus Interface (EBI) address and data input / output
pin 12.
EBI_AD13 PA4 External Bus Interface (EBI) address and data input / output
pin 13.
EBI_AD14 PA5 External Bus Interface (EBI) address and data input / output
pin 14.
EBI_AD15 PA6 External Bus Interface (EBI) address and data input / output
pin 15.
EBI_ALE PF3 External Bus Interface (EBI) Address Latch Enable output.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
EBI_ARDY PF2 External Bus Interface (EBI) Hardware Ready Control input.
EBI_CS0 PD9 External Bus Interface (EBI) Chip Select output 0.
EBI_CS1 PD10 External Bus Interface (EBI) Chip Select output 1.
EBI_CS2 PD11 External Bus Interface (EBI) Chip Select output 2.
EBI_CS3 PD12 External Bus Interface (EBI) Chip Select output 3.
EBI_REn PF5 External Bus Interface (EBI) Read Enable output.
EBI_WEn PF4 External Bus Interface (EBI) Write Enable output.
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 PC7 PD15 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 PC6 PD14 I2C0 Serial Data input / output.
LCD_BCAP_N PA13
LCD voltage booster (optional), boost capacitor, negative pin.
If using the LCD voltage booster, connect a 22 nF capacitor
between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor, positive pin.
If using the LCD voltage booster, connect a 22 nF capacitor
between LCD_BCAP_N and LCD_BCAP_P.
LCD_BEXT PA14
LCD voltage booster (optional), boost output. If using the LCD
voltage booster, connect a 1 uF capacitor between this pin
and VSS.
An external LCD voltage may also be applied to this pin if the
booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin
may be left unconnected or used as a GPIO.
LCD_COM0 PE4 LCD driver common line number 0.
LCD_COM1 PE5 LCD driver common line number 1.
LCD_COM2 PE6 LCD driver common line number 2.
LCD_COM3 PE7 LCD driver common line number 3.
LCD_SEG0 PF2 LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG3 PF5 LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by
SEGEN0.
LCD_SEG4 PE8 LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG5 PE9 LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG6 PE10 LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
LCD_SEG7 PE11 LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by
SEGEN1.
LCD_SEG8 PE12 LCD segment line 8. Segments 8, 9, 10 and 11 are controlled
by SEGEN2.
LCD_SEG9 PE13 LCD segment line 9. Segments 8, 9, 10 and 11 are controlled
by SEGEN2.
LCD_SEG10 PE14 LCD segment line 10. Segments 8, 9, 10 and 11 are control-
led by SEGEN2.
LCD_SEG11 PE15 LCD segment line 11. Segments 8, 9, 10 and 11 are control-
led by SEGEN2.
LCD_SEG12 PA15 LCD segment line 12. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG13 PA0 LCD segment line 13. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG14 PA1 LCD segment line 14. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG15 PA2 LCD segment line 15. Segments 12, 13, 14 and 15 are con-
trolled by SEGEN3.
LCD_SEG16 PA3 LCD segment line 16. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG17 PA4 LCD segment line 17. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG18 PA5 LCD segment line 18. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG19 PA6 LCD segment line 19. Segments 16, 17, 18 and 19 are con-
trolled by SEGEN4.
LCD_SEG20 PB3 LCD segment line 20. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG21 PB4 LCD segment line 21. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG22 PB5 LCD segment line 22. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG23 PB6 LCD segment line 23. Segments 20, 21, 22 and 23 are con-
trolled by SEGEN5.
LCD_SEG24 PF6 LCD segment line 24. Segments 24, 25, 26 and 27 are con-
trolled by SEGEN6.
LCD_SEG25 PF7 LCD segment line 25. Segments 24, 25, 26 and 27 are con-
trolled by SEGEN6.
LCD_SEG26 PF8 LCD segment line 26. Segments 24, 25, 26 and 27 are con-
trolled by SEGEN6.
LCD_SEG27 PF9 LCD segment line 27. Segments 24, 25, 26 and 27 are con-
trolled by SEGEN6.
LCD_SEG28 PD9 LCD segment line 28. Segments 28, 29, 30 and 31 are con-
trolled by SEGEN7.
LCD_SEG29 PD10 LCD segment line 29. Segments 28, 29, 30 and 31 are con-
trolled by SEGEN7.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
LCD_SEG30 PD11 LCD segment line 30. Segments 28, 29, 30 and 31 are con-
trolled by SEGEN7.
LCD_SEG31 PD12 LCD segment line 31. Segments 28, 29, 30 and 31 are con-
trolled by SEGEN7.
LCD_SEG32 PB0 LCD segment line 32. Segments 32, 33, 34 and 35 are con-
trolled by SEGEN8.
LCD_SEG33 PB1 LCD segment line 33. Segments 32, 33, 34 and 35 are con-
trolled by SEGEN8.
LCD_SEG34 PB2 LCD segment line 34. Segments 32, 33, 34 and 35 are con-
trolled by SEGEN8.
LCD_SEG35 PA7 LCD segment line 35. Segments 32, 33, 34 and 35 are con-
trolled by SEGEN8.
LCD_SEG36 PA8 LCD segment line 36. Segments 36, 37, 38 and 39 are con-
trolled by SEGEN9.
LCD_SEG37 PA9 LCD segment line 37. Segments 36, 37, 38 and 39 are con-
trolled by SEGEN9.
LCD_SEG38 PA10 LCD segment line 38. Segments 36, 37, 38 and 39 are con-
trolled by SEGEN9.
LCD_SEG39 PA11 LCD segment line 39. Segments 36, 37, 38 and 39 are con-
trolled by SEGEN9.
LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.
LEU0_RX PD5 PB14 PE15 LEUART0 Receive input.
LEU0_TX PD4 PB13 PE14 LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LEU1_RX PC7 PA6 LEUART1 Receive input.
LEU1_TX PC6 PA5 LEUART1 Transmit output. Also used as receive input in half
duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-
so used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC13 PE0 PC0 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PE1 PC1 Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.
PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.
PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.
TIM0_CC0 PA0 PA0 PF6 PD1 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 PF7 PD2 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 PF8 PD3 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PA3 PC13 PF3 PC13 Timer 0 Complimentary Deat Time Insertion channel 0.
EFM32G Data Sheet
Pin Definitions
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Alternate LOCATION
Functionality 0 1 2 3 Description
TIM0_CDTI1 PA4 PC14 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PA5 PC15 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PC13 PE10 PB0 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 PB1 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 PB2 Timer 1 Capture Compare input / output channel 2.
TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.
U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.
U0_TX PF6 PE0 PA3 PC14 UART0 Transmit output. Also used as receive input in half du-
plex communication.
US0_CLK PE12 PE5 PC9 USART0 clock input / output.
US0_CS PE13 PE4 PC8 USART0 chip select input / output.
US0_RX PE11 PE6 PC10
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MI-
SO).
US0_TX PE10 PE7 PC11
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 PD2 USART1 clock input / output.
US1_CS PB8 PD3 USART1 chip select input / output.
US1_RX PC1 PD1
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MI-
SO).
US1_TX PC0 PD0
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK PC4 PB5 USART2 clock input / output.
US2_CS PC5 PB6 USART2 chip select input / output.
US2_RX PC3 PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MI-
SO).
US2_TX PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 164
5.10.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32G890 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.30. GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
Port F — — — — — — PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
EFM32G Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 2.10 | 165
6. BGA112 Package Specifications
6.1 BGA112 Package Dimensions
TOP VIEW BOTTOM VIEW
SIDE VIEW
Rev: 97SPP01315A_X03_06Jun11
Figure 6.1. BGA112
Note:
1. The dimensions in parenthesis are reference.
2. Datum 'C' and seating plane are defined by the crown of the solder balls.
3. All dimensions are in millimeters.
The BGA112 Package uses SAC105 solderballs.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx.
EFM32G Data Sheet
BGA112 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 166
6.2 BGA112 PCB Layout
a
b
d
e
Figure 6.2. BGA112 PCB Land Pattern
Table 6.1. BGA112 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 0.35
b 0.80
d 8.00
e 8.00
a
b
d
e
Figure 6.3. BGA112 PCB Solder Mask
Table 6.2. BGA112 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 0.48
b 0.80
d 8.00
e 8.00
EFM32G Data Sheet
BGA112 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 167
a
b
d
e
Figure 6.4. BGA112 PCB Stencil Design
Table 6.3. BGA112 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 0.33
b 0.80
d 8.00
e 8.00
Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.
EFM32G Data Sheet
BGA112 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 168
6.3 BGA112 Package Marking
In the illustration below package fields and position are shown.
Figure 6.5. Example Chip Marking (Top View)
EFM32G Data Sheet
BGA112 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 169
7. LQFP100 Package Specifications
7.1 LQFP100 Package Dimensions
Rev: 98A0100QP043_03MAY2007
Figure 7.1. LQFP100
Note:
1. Datum 'T', 'U' and 'Z' to be determined at datum plane 'H'
2. Datum 'D' and 'E' to be determined at seating plane datum 'Y'.
3. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25 per side. Dimensions 'D1' and 'E1' do include
mold mismatch and are determined at datum plane datum 'H'.
4. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause thelead width to exceed the maxi-
mum 'b' dimension by more than 0.08 mm. Dambar can not be locatedon the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm.
5. Exact shape of each corner is optional.
Table 7.1. LQFP100 (Dimensions in mm)
SYMBOL MIN NOM MAX
total thickness A — — 1.6
stand off A1 0.05 — 0.15
mold thickness A2 1.35 1.4 1.45
lead width (plating) b 0.17 0.2 0.27
lead width b1 0.17 — 0.23
L/F thickness (plating) c 0.09 — 0.2
lead thickness c1 0.09 — 0.16
EFM32G Data Sheet
LQFP100 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 170
SYMBOL MIN NOM MAX
x D 16 BSC
y E 16 BSC
body size
x D1 14 BSC
y E1 14 BSC
lead pitch e 0.5 BSC
L 0.45 0.6 0.75
footprint L1 1 REF
θ 0º 3.5º 7º
θ1 0º — —
θ2 11º 12º 13º
θ3 11º 12º 13º
R1 0.08 — —
R1 0.08 — 0.2
S 0.2 — —
package edge tolerance aaa 0.2
lead edge tolerance bbb 0.2
coplanarity ccc 0.08
lead offset ddd 0.08
mold flatness eee 0.05
The LQFP100 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx
EFM32G Data Sheet
LQFP100 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 171
7.2 LQFP100 PCB Layout
e
a
d
c
b
p1
p2
p3 p4
p5
p6
p7p8
Figure 7.2. LQFP100 PCB Land Pattern
Table 7.2. LQFP100 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number
a 1.45 P1 1 P6 75
b 0.30 P2 25 P7 76
c 0.50 P3 26 P8 100
d 15.40 P4 50
e 15.40 P5 51
e
a
d
c
b
Figure 7.3. LQFP100 PCB Solder Mask
Table 7.3. LQFP100 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.57
b 0.42
c 0.50
d 15.40
e 15.40
EFM32G Data Sheet
LQFP100 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 172
e
a
d
c
b
Figure 7.4. LQFP100 PCB Stencil Design
Table 7.4. LQFP100 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.35
b 0.20
c 0.50
d 15.40
e 15.40
Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.
EFM32G Data Sheet
LQFP100 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 173
7.3 LQFP100 Package Marking
In the illustration below package fields and position are shown.
Figure 7.5. Example Chip Marking (Top View)
EFM32G Data Sheet
LQFP100 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 174
8. TQFP64 Package Specifications
8.1 TQFP64 Package Dimensions
Rev: 98SPP64023A_XO1_17MAR2011
C
L
F
Figure 8.1. TQFP64
Note:
1. All dimensions & tolerancing confirm to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package body size.
3. Datum 'A,B', and 'B' to be determined at datum plane 'H'.
4. To be determined at seating place 'C'.
5. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25mm per side.'D1' and 'E1' are maximum plas-
tic body size dimension including mold mismatch. Dimension 'D1' and'E1' shall be determined at datum plane 'H'.
6. Detail of Pin 1 indicatifier are option all but must be located within the zone indicated.
7. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause thelead width to exceed the maxi-
mum 'b' dimension by more than 0.08 mm. Dambar can not be locatedon the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm.
8. Exact shape of each corner is optional.
9. These dimension apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
10. All dimensions are in millimeters.
Table 8.1. QFP64 (Dimensions in mm)
DIM MIN NOM MAX DIM MIN NOM MAX
A — 1.10 1.20 L1 —
A1 0.05 — 0.15 R1 0.08 — —
A2 0.95 1.00 1.05 R2 0.08 — 0.20
EFM32G Data Sheet
TQFP64 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 175
DIM MIN NOM MAX DIM MIN NOM MAX
b 0.17 0.22 0.27 S 0.20 — —
b1 0.17 0.20 0.23 θ 0° 3.5° 7°
c 0.09 — 0.20 θ1 0° — —
C1 0.09 — 0.16 θ2 11° 12° 13°
D 12.0 BSC θ3 11° 12° 13°
D1 10.0 BSC
e 0.50 BSC
E 12.0 BSC
E1 10.0 BSC
L 0.45 0.60 0.75
The TQFP64 Package is 10 by 10 mm in size and has a 0.5 mm pin pitch.
The TQFP64 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx.
EFM32G Data Sheet
TQFP64 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 176
8.2 TQFP64 PCB Layout
e
a
d
c
b
p1
p2
p3 p4
p5
p6
p7p8
Figure 8.2. TQFP64 PCB Land Pattern
Table 8.2. TQFP64 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number
a 1.60 P1 1 P6 48
b 0.30 P2 16 P7 49
c 0.50 P3 17 P8 64
d 11.50 P4 32
e 11.50 P5 33
e
a
d
c
b
Figure 8.3. TQFP64 PCB Solder Mask
Table 8.3. TQFP64 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.72
b 0.42
c 0.50
d 11.50
e 11.50
EFM32G Data Sheet
TQFP64 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 177
e
a
d
c
b
Figure 8.4. TQFP64 PCB Stencil Design
Table 8.4. TQFP64 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.50
b 0.20
c 0.50
d 11.50
e 11.50
Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.
EFM32G Data Sheet
TQFP64 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 178
8.3 TQFP64 Package Marking
In the illustration below package fields and position are shown.
Figure 8.5. Example Chip Marking (Top View)
EFM32G Data Sheet
TQFP64 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 179
9. TQFP48 Package Specifications
9.1 TQFP48 Package Dimensions
Rev: 98SPP48097A_XO_30Mar11
Figure 9.1. TQFP48
Note:
1. Dimensions and tolerance per ASME Y14.5M-1994
2. Control dimension: Millimeter
3. Datum plane AB is located at bottom of lead and is coincident with the lead where the lead existsfrom the plastic body at the bot-
tom of the parting line.
4. Datums T, U and Z to be determined at datum plane AB.
5. Dimensions S and V to be determined at seating plane AC.
6. Dimensions A and B do not include mold protrusion. Allowable protrusion is 0.250 per side. Dimensions A and B do include mold
mismatch and are determined at datum AB.
7. Dimension D does not include dambar protrusion. Dambar protrusion shall not cause the D dimensionto exceed 0.350.
8. Minimum solder plate thickness shall be 0.0076.
9. Exact shape of each corner is optional.
Table 9.1. QFP48 (Dimensions in mm)
DIM MIN NOM MAX DIM MIN NOM MAX
A — 7.000 BSC — M — 12DEG REF
A1 — 3.500 BSC — N 0.090 — 0.160
B — 7.000 BSC — P — 0.250 BSC —
B1 — 3.500 BSC — R 0.150 — 0.250
C 1.000 — 1.200 S — 9.000 BSC —
EFM32G Data Sheet
TQFP48 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 180
DIM MIN NOM MAX DIM MIN NOM MAX
D 0.170 — 0.270 S1 — 4.500 BSC —
E 0.950 — 1.050 V — 9.000 BSC —
F 0.170 — 0.230 V1 — 4.5000 BSC —
G — 0.500 BSC — W — 0.200 BSC —
H 0.050 — 0.150 AA — 1.000BSC —
J 0.090 — 0.200
K 0.500 — 0.700
L0DE
G— 7DEG
The TQFP48 Package is 7 by 7 mm in size and has a 0.5 mm pin pitch.
The TQFP48 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx
EFM32G Data Sheet
TQFP48 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 181
9.2 TQFP48 PCB Layout
e
a
d
c
b
p1
p2
p3 p4
p5
p6
p7p8
Figure 9.2. TQFP48 PCB Land Pattern
Table 9.2. TQFP48 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number
a 1.60 P1 1 P6 36
b 0.30 P2 12 P7 37
c 0.50 P3 13 P8 48
d 8.50 P4 24
e 8.50 P5 25
e
a
d
c
b
Figure 9.3. TQFP48 PCB Solder Mask
Table 9.3. TQFP48 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.72
b 0.42
c 0.50
d 8.50
e 8.50
EFM32G Data Sheet
TQFP48 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 182
e
a
d
c
b
Figure 9.4. TQFP48 PCB Stencil Design
Table 9.4. TQFP48 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.50
b 0.20
c 0.50
d 8.50
e 8.50
Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see 5. Pin Definitions.
EFM32G Data Sheet
TQFP48 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 183
9.3 TQFP48 Package Marking
In the illustration below package fields and position are shown.
Figure 9.5. Example Chip Marking (Top View)
EFM32G Data Sheet
TQFP48 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 184
10. QFN64 Package Specifications
10.1 QFN64 Package Dimensions
Rev: 98SPP64048A_XO1_08MAR2011
16
1732
33
64
1
49
48
m
m
Figure 10.1. QFN64
Note:
1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm fromthe terminal tip. Dimension L1
represents terminal full back from package edge up to 0.1 mm isacceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional.
Table 10.1. QFN64 (Dimensions in mm)
Symbol Min Nom Max
A 0.80 0.85 0.90
A1 0.00 — 0.05
A3 0.203 REF
b 0.25 0.30 0.35
D 9.00 BSC
E 9.00 BSC
D2 7.10 7.20 7.30
E2 7.10 7.20 7.30
EFM32G Data Sheet
QFN64 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 185
Symbol Min Nom Max
e 0.50 BSC
L 0.40 0.45 0.50
L1 0.00 — 0.10
aaa 0.10
bbb 0.10
ccc 0.10
ddd 0.05
eee 0.08
The QFN64 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx.
EFM32G Data Sheet
QFN64 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 186
10.2 QFN64 PCB Layout
e
a
d
p1
p2
p3 p4
p5
p6
p7
p8
c
b
p9
f
g
Figure 10.2. QFN64 PCB Land Pattern
Table 10.2. QFN64 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number
a 0.85 P1 1 P8 64
b 0.30 P2 16 P9 65
c 0.50 P3 17
d 8.90 P4 32
e 8.90 P5 33
f 7.20 P6 48
g 7.20 P7 49
e
a
d
c
b
f
g
Figure 10.3. QFN64 PCB Solder Mask
Table 10.3. QFN64 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol Dim. (mm) Symbol Dim. (mm)
a 0.97 e 8.90
b 0.42 f 7.32
c 0.50 g 7.32
EFM32G Data Sheet
QFN64 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 187
Symbol Dim. (mm) Symbol Dim. (mm)
d 8.90 - -
e
a
d
c
b
x y
z
Figure 10.4. QFN64 PCB Stencil Design
Table 10.4. QFN64 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol Dim. (mm) Symbol Dim. (mm)
a 0.75 e 8.90
b 0.22 x 2.70
c 0.50 y 2.70
d 8.90 z 0.80
Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.
EFM32G Data Sheet
QFN64 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 188
10.3 QFN64 Package Marking
In the illustration below package fields and position are shown.
Figure 10.5. Example Chip Marking (Top View)
EFM32G Data Sheet
QFN64 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 189
11. QFN32 Package Specifications
11.1 QFN32 Package Dimensions
Rev: 98SPP32088A_XO1_10MAR2011
D
E
D2
32xL
E2
e
32xb
m
m
M
G
M
1
17
32
9
2
3
4
5
6
7
8
31302928272625
18
19
20
21
22
23
24
10111213141516
EVEN / ODD TERMINL SIDE
e
L1
L
DETAIL G
VIEW ROTATED 90° CLOCKWISE
A3
A
A1
SEATING PLANE
Figure 11.1. QFN32
Note:
1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm fromthe terminal tip. Dimension L1
represents terminal full back from package edge up to 0.1 mm isacceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional.
Table 11.1. QFN32 (Dimensions in mm)
Symbol A A1 A3 b D E D2 E2 e L L1 aaa bbb ccc ddd eee
Min 0.80 0.00
0.203
REF
0.25
6.00
BSC
6.00
BSC
4.30 4.30
0.65
BSC
0.30 0.00
0.10 0.10 0.10 0.05 0.08Nom 0.85 — 0.30 4.40 4.40 0.35
Max 0.90 0.05 0.35 4.50 4.50 0.40 0.10
The QFN32 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx
EFM32G Data Sheet
QFN32 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 190
11.2 QFN32 PCB Layout
e
a
d
p1
p2
p3 p4
p5
p6
p7
p8
c
b
p9
f
g
Figure 11.2. QFN32 PCB Land Pattern
Table 11.2. QFN32 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number
a 0.80 P1 1 P6 24
b 0.35 P2 8 P7 25
c 0.65 P3 9 P8 32
d 6.00 P4 16 P9 33
e 6.00 P5 17
f 4.40
g 4.40
e
a
d
c
b
f
g
Figure 11.3. QFN32 PCB Solder Mask
Table 11.3. QFN32 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 0.92
b 0.47
c 0.65
EFM32G Data Sheet
QFN32 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 191
Symbol Dim. (mm)
d 6.00
e 6.00
f 4.52
g 4.52
e
a
d
c
b
x y
z
Figure 11.4. QFN32 PCB Stencil Design
Table 11.4. QFN32 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 0.70
b 0.25
c 0.65
d 6.00
e 6.00
x 1.30
y 1.30
z 0.50
Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see 5. Pin Definitions.
EFM32G Data Sheet
QFN32 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 192
11.3 QFN32 Package Marking
In the illustration below package fields and position are shown.
Figure 11.5. Example Chip Marking (Top View)
EFM32G Data Sheet
QFN32 Package Specifications
silabs.com | Building a more connected world. Rev. 2.10 | 193
12. Chip Revision, Solder Information, Errata
12.1 Chip Revision
The revision of a chip can be determined from the "Revision" field in the package marking.
12.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
12.3 Errata
Please see the errata document for description and resolution of device errata. This document is available in Simplicity Studio and on-
line at: http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
EFM32G Data Sheet
Chip Revision, Solder Information, Errata
silabs.com | Building a more connected world. Rev. 2.10 | 194
13. Revision History
13.1 Revision 2.10
July 19, 2017
In 4.8 General Purpose Input Output:
• Added missing multiply symbols.
In 4.10 Analog Digital Converter (ADC):
• Updated average active current.
• Updated SNR.
• Updated SINAD.
• Updated SFDR.
• Renamed VREF Output Voltage to VREF Voltage.
In 4.11 Digital Analog Converter (DAC):
• Renamed VREF Output Voltage to VREF Voltage.
EFM32G Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 2.10 | 195
13.2 Revision 2.00
May 10th, 2017
Consolidated all EFM32G data sheets:
• EFM32G200
• EFM32G210
• EFM32G222
• EFM32G230
• EFM32G232
• EFM32G280
• EFM32G290
• EFM32G840
• EFM32G842
• EFM32G880
• EFM32G890
New formatting throughout.
Added 1. Feature List.
Updated ordering codes in 2. Ordering Information for Revision E and tape and reel.
Added Figure 2.1 Ordering Code Decoder on page 5.
Separated Memory Map figure into Figure 3.2 System Address Space with Core and Code Space Listing on page 27 and Figure
3.3 System Address Space with Peripheral Listing on page 28 for readability.
Removed footnote for storage temperature range in 4.2 Absolute Maximum Ratings.
In 4.6 Power Management:
• Updated EM0 condition for VBODextthr- specification.
• Added VBODextthr- in EM1 and EM2 specifications.
• Updated EM0 condition for VBODextthr+ specification.
Updated Flash page erase time and device erase time in 4.7 Flash and added footnotes.
Updated figures in 4.9.3 LFRCO.
Updated figures and HFRCO current consumption typical values in 4.9.4 HFRCO.
In 4.10 Analog Digital Converter (ADC):
• Updated test conditions, updated specifications, and added footnote for average active current.
• Added input bias current.
• Added input offset current.
• Updated ADC clock frequency.
• Updated SNR, SINAD and SFDR.
• Updated offset voltage.
• Updated missing codes.
• Added gain error drift and offset error drift.
• Added VREF output voltage, VREF voltage drift, VREF temperature drift, VREF current consumption, and ADC and DAC VREF
matching.
In 4.11 Digital Analog Converter (DAC):
• Updated IDAC parameter, test conditions, and footnote.
• Added DAC load current specification to 4.11 Digital Analog Converter (DAC).
• Added VREF output voltage, VREF voltage drift, VREF temperature drift, VREF current consumption, and ADC and DAC VREF
matching.
Updated ACMP active current (BIASPROG=0b1111, FULLBIAS=1 and HALFBIAS=0 in ACMPn_CTRL register) typical value in
4.12 Analog Comparator (ACMP).
Updated VCMP hysteresis typical value in 4.13 Voltage Comparator (VCMP).
EFM32G Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 2.10 | 196
Corrected pin number for symbol P3 in Table 11.2 QFN32 PCB Land Pattern Dimensions (Dimensions in mm) on page 191.
Updated package marking figures to include temperature grade.
13.3 Revision 1.90
May 22nd, 2015
For devices with an ADC, Added clarification on conditions for INLADC and DNLADC parameters.
Corrected EM2 current consumption condition in Electrical Characteristics section.
Added AUXHFRCO to block diagram and Electrical Characteristics.
Updated HFRCO table in the Electrical Characteristics section.
Updated EM0, EM2, EM3, and EM4 maximum current specifications in the Electrical Characteristics section.
Updated the Output Low Voltage maximum for sinking 20 mA with VDD = 3.0 V in the Electrical Characteristics section.
Updated the Input Leakage Current maximum in the Electrical Characteristics section.
Updated the minimum and maximum frequency specifications for the LFRCO, HFRCO, and AUXHFRCO in the Electrical Characteris-
tics section.
Updated the maximum current consumption of the HFRCO in the Electrical Characteristics section.
Updated the maximum current consumption of the HFRCO in the Electrical Characteristics section.
Added some minimum ADC SNR, SNDR, and SFDR specifications in the Electrical Characteristics section.
Added some minimum and maximum ADC offset voltage, DNL, and INL specifications in the Electrical Characteristics section.
Added maximum DAC current specifications in the Electrical Characteristics section.
Added maximum ACMP current and maximum and minimum offset voltage specifications in the Electrical Characteristics section.
Added maximum VCMP current and updated typical VCMP current specifications in the Electrical Characteristics section.
Updated references to energyAware Designer to Configurator.
13.4 Revision 1.80
July 2nd, 2014
Corrected single power supply voltage minimum value from 1.85V to 1.98V.
Updated current consumption.
Updated transition between energy modes.
Updated power management data.
Updated GPIO data.
Updated LFXO, HFXO, HFRCO and ULFRCO data.
Updated LFRCO and HFRCO plots.
For devices with an ACMP, updated ACMP data.
EFM32G Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 2.10 | 197
13.5 Revision 1.71
November 21st, 2013
Updated figures.
Updated errata-link.
Updated chip marking.
Added link to Environmental and Quality information.
For devices with a DAC, re-added missing DAC-data.
13.6 Revision 1.70
September 30th, 2013
For devices with an I2C, added I2C characterization data.
Corrected GPIO operating voltage from 1.8 V to 1.85 V.
For devices with an ADC, corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit.
For QFN64 devices, updated the Max VESDCDM value to 750 V.
Updated Environmental information.
Updated trademark, disclaimer and contact information.
Other minor corrections.
13.7 Revision 1.60
June 28th, 2013
For BGA devices, updated PCB Land Pattern, PCB Solder Mask and PCB Stencil Design figures.
Updated power requirements in the Power Management section.
Removed minimum load capacitance figure and table. Added reference to application note.
Other minor corrections.
13.8 Revision 1.50
September 11th, 2012
Updated the HFRCO 1 MHz band typical value to 1.2 MHz.
Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
For BGA devices, corrected BGA solder balls material from Sn96.5/Ag3/Cu0.5 to SAC105.
Other minor corrections.
EFM32G Data Sheet
Revision History
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13.9 Revision 1.40
February 27th, 2012
Updated Power Management section.
Corrected operating voltage from 1.8 V to 1.85 V.
Corrected TGRADADCTH parameter.
Corrected package drawing.
Updated PCB land pattern, solder mask and stencil design.
For LQFP48 devices, corrected available Pulse Counters from 3 to 2.
For LQFP48 devices, corrected available LEUARTs from 2 to 1.
For LQFP64 devices, corrected ordering codes in the ordering information table.
13.10 Revision 1.30
May 20th, 2011
This revision applies the following devices:
• EFM32G200
• EFM32G210
• EFM32G230
• EFM32G280
• EFM32G290
• EFM32G840
• EFM32G880
• EFM32G890
Updated LFXO load capacitance section.
EFM32G Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 2.10 | 199
13.11 Revision 1.20
December 17th, 2010
This revision applies the following devices:
• EFM32G200
• EFM32G210
• EFM32G230
• EFM32G280
• EFM32G290
• EFM32G840
• EFM32G880
• EFM32G890
Increased max storage temperature.
Added data for <150°C and <70°C on Flash data retention.
Changed latch-up sensitivity test description.
Added IO leakage current.
For LQFP100 devices, updated ESD CDM value.
Added Flash current consumption.
Updated HFRCO data.
Updated LFRCO data.
Added graph for ADC Absolute Offset over temperature.
Added graph for ADC Temperature sensor readout.
13.12 Revision 1.11
November 17th, 2010
This revision applies the following devices:
• EFM32G200
• EFM32G210
• EFM32G230
• EFM32G280
• EFM32G290
• EFM32G840
• EFM32G880
• EFM32G890
Corrected maximum DAC clock speed for continuous mode.
Added DAC sample-hold mode voltage drift rate.
Added pulse widths detected by the HFXO glitch detector.
Added power sequencing information to Power Management section.
EFM32G Data Sheet
Revision History
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13.13 Revision 1.10
September 13th, 2010
This revision applies the following devices:
• EFM32G200
• EFM32G210
• EFM32G230
• EFM32G280
• EFM32G290
• EFM32G840
• EFM32G880
• EFM32G890
For LQFP100 devices, corrected number of GPIO pins.
Added typical values for RADCFILT and CADCFILT.
Added two conditions for DAC clock frequency; one for sample/hold and one for sample/off.
Added RoHS information and specified leadframe/solderballs material.
Added Serial Bootloader to feature list and system summary.
Updated ADC characterization data.
Updated DAC characterization data.
Updated RCO characterization data.
Updated ACMP characterization data.
Updated VCMP characterization data.
13.14 Revision 1.00
April 23rd, 2010
This revision applies the following devices:
• EFM32G200
• EFM32G210
• EFM32G230
• EFM32G280
• EFM32G290
• EFM32G840
• EFM32G880
• EFM32G890
ADC_VCM line removed.
Added pinout illustration and additional pinout table.
Changed "Errata" chapter. Errata description moved to separate document.
Document changed status from "Preliminary".
Updated "Electrical Characteristics" chapter.
For EFM32G222
May 20th, 2011
Updated LFXO load capacitance section.
EFM32G Data Sheet
Revision History
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13.15 Revision 0.90
This revision applies the following devices:
• EFM32G222
Initial preliminary revision, April 14th, 2011
This revision applies the following devices:
• EFM32G232
• EFM32G842
Initial preliminary revision, June 30th, 2011
13.16 Revision 0.85
February 19th, 2010
This revision applies the following devices:
• EFM32G200
• EFM32G210
• EFM32G230
• EFM32G280
• EFM32G290
• EFM32G840
• EFM32G880
• EFM32G890
Renamed DBG_SWV pin to DBG_SWO.
13.17 Revision 0.84
February 11th, 2010
This revision applies the following devices:
• EFM32G230
• EFM32G840
Corrected pinout tables.
13.18 Revision 0.83
January 25th, 2010
This revision applies the following devices:
• EFM32G200
• EFM32G210
• EFM32G230
• EFM32G280
• EFM32G290
• EFM32G840
• EFM32G880
• EFM32G890
Updated errata section.
Specified flash word width in Flash Electrical Characteristics.
Added Capacitive Sense Internal Resistor values in ACMP Electrical Characteristics.
EFM32G Data Sheet
Revision History
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13.19 Revision 0.82
December 9th, 2009
This revision applies the following devices:
• EFM32G200
• EFM32G210
• EFM32G230
• EFM32G280
• EFM32G290
• EFM32G840
• EFM32G880
• EFM32G890
For LQFP100 devices, incorrect pin 0 removed from pinout table.
Updated contact information.
ADC current consumption numbers updated in ADC Electrical Characteristics.
For devices with LCD, updated LCD supply voltage range in LCD Electrical Characteristics.
13.20 Revision 0.81
November 20th, 2009
This revision applies the following devices:
• EFM32G200
• EFM32G210
• EFM32G230
• EFM32G280
• EFM32G290
• EFM32G840
• EFM32G880
• EFM32G890
For devices without a differential DAC, System Summary updated.
Electrical Characteristics updated.
Storage temperature in Electrical Characteristics updated.
Temperature coefficient of band-gap reference in Electrical Characteristics added.
Erase times in Flash Electrical Characteristics updated.
Definitions of DNL and INL added in ADC section.
For devices with and LCD, LCD Electrical Characteristics added.
Current consumption of digital peripherals added in Electrical Characteristics.
For LQFP100 devices, package information in Pinout and Package corrected.
For BGA112 devices, pinout information in Pinout table corrected.
Updated errata section.
EFM32G Data Sheet
Revision History
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13.21 Revision 0.80
October 19th, 2009
This revision applies the following devices:
• EFM32G200
• EFM32G210
• EFM32G230
• EFM32G280
• EFM32G290
• EFM32G840
• EFM32G880
• EFM32G890
Initial preliminary revision
EFM32G Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 2.10 | 204
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