EFM32 Gecko Family
EFM32G Data Sheet
The EFM32 Gecko MCUs are the world’s most energy-friendly mi-
crocontrollers.
The EFM32G offers unmatched performance and ultra low power consumption in both
active and sleep modes. EFM32G devices consume as little as 0.6 μA in Stop mode and
180 μA/MHz in Run mode. It also features autonomous peripherals, high overall chip and
analog integration, and the performance of the industry standard 32-bit ARM Cortex-M3
processor, making it perfect for battery-powered systems and systems with high-per-
formance, low-energy requirements.
EFM32G applications include the following:
KEY FEATURES
• ARM Cortex-M3 at 32 MHz
• Ultra low power operation
• 0.6 μA current in Stop (EM3), with
brown-out detection and RAM retention
• 45 μA/MHz in EM1
• 180 μA/MHz in Run mode (EM0)
• Fast wake-up time of 2 µs
• Hardware cryptography (AES)
• Up to 128 kB of Flash and 16 kB of RAM
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
32-bit bus
Lowest power mode with peripheral operational:
EM2 – Deep Sleep
EM1 - Sleep EM4 - Shutoff
EM0 - Active EM3 - Stop
Core / Memory
Flash Program
Memory
RAM Memory
ARM CortexTM
M3 processor
Debug Interface
DMA Controller
Memory
Protection Unit
Security
Hardware AES
Energy Management
Brown-Out
Detector
Voltage
Regulator
Voltage
Comparator
Power-On Reset
Clock Management
High Frequency
RC Oscillator
Low Frequency
RC Oscillator
Low Frequency
Crystal
Oscillator
Watchdog
Oscillator
Auxiliary High
Freq. RC Osc.
High Frequency
Crystal Oscillator
Analog Interfaces
DACADC
LCD Controller Analog
Comparator
Peripheral Reflex System
Serial Interfaces
UART
I2C
I/O Ports Timers and Triggers
Timer/Counter
Low Energy Timer Watchdog Timer
External
Interrupts Pin Reset
External Bus
Interface
General
Purpose I/O
Pulse Counter
Real Time
Counter
USART
Low Energy
UARTTM
silabs.com | Building a more connected world. Rev. 2.10
1. Feature List
• ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 32 MHz
• Memory Protection Unit
• Wake-up Interrupt Controller
• SysTick System Timer
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention
• 0.9 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 45 µA/MHz @ 3 V Sleep Mode
• 180 µA/MHz @ 3 V Run Mode, with code executed from flash
• 128/64/32 KB Flash
• 16/8 KB RAM
• Up to 90 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 8 Channel DMA Controller
• 8 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• 3 × 16-bit Timer/Counter
• 3×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter
• 3× 8-bit Pulse Counter
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Integrated LCD Controller for up to 4×40 segments
• Voltage boost, adjustable contrast and autonomous animation
• External Bus Interface for up to 4x64 MB of external memory mapped space
• TFT Controller with Direct Drive
• Communication interfaces
• Up to 3× Universal Synchronous/Asynchronous Receiver/ Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• Triple buffered full/half-duplex operation
• 1× Universal Asynchronous Receiver/Transmitter
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
•I2C Interface with SMBus support
• Address recognition in Stop Mode
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single-ended channels/4 differential channels
• On-chip temperature sensor
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2 single-ended channels/1 differential channel
• 2× Analog Comparator
• Capacitive sensing with up to 16 inputs
EFM32G Data Sheet
Feature List
silabs.com | Building a more connected world. Rev. 2.10 | 2
• Supply Voltage Comparator
• Ultra efficient Power-on Reset and Brown-Out Detector
• 2-pin Serial Wire Debug Interface
• 1-pin Serial Wire Viewer
• Pre-Programmed USB/UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• Packages
• BGA112
• LQFP100
• TQFP64
• TQFP48
• QFN64
• QFN32
EFM32G Data Sheet
Feature List
silabs.com | Building a more connected world. Rev. 2.10 | 3
2. Ordering Information
The following table shows the available EFM32G devices.
Table 2.1. Ordering Information
Ordering Code Flash (kB) RAM (kB)
Max Speed
(MHz)
Supply Volt-
age (V)
Tempera-
ture (ºC) Package
EFM32G200F16G-E-QFN32 16 8 32 1.98 - 3.8 -40 - 85 QFN32
EFM32G200F32G-E-QFN32 32 8 32 1.98 - 3.8 -40 - 85 QFN32
EFM32G200F64G-E-QFN32 64 16 32 1.98 - 3.8 -40 - 85 QFN32
EFM32G210F128G-E-QFN32 128 16 32 1.98 - 3.8 -40 - 85 QFN32
EFM32G222F32G-E-QFP48 32 8 32 1.98 - 3.8 -40 - 85 TQFP48
EFM32G222F64G-E-QFP48 64 16 32 1.98 - 3.8 -40 - 85 TQFP48
EFM32G222F128G-E-QFP48 128 16 32 1.98 - 3.8 -40 - 85 TQFP48
EFM32G230F32G-E-QFN64 32 8 32 1.98 - 3.8 -40 - 85 QFN64
EFM32G230F64G-E-QFN64 64 16 32 1.98 - 3.8 -40 - 85 QFN64
EFM32G230F128G-E-QFN64 128 16 32 1.98 - 3.8 -40 - 85 QFN64
EFM32G232F32G-E-QFP64 32 8 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G232F64G-E-QFP64 64 16 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G232F128G-E-QFP64 128 16 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G280F32G-E-QFP100 32 8 32 1.98 - 3.8 -40 - 85 LQFP100
EFM32G280F64G-E-QFP100 64 16 32 1.98 - 3.8 -40 - 85 LQFP100
EFM32G280F128G-E-QFP100 128 16 32 1.98 - 3.8 -40 - 85 LQFP100
EFM32G290F32G-E-BGA112 32 8 32 1.98 - 3.8 -40 - 85 BGA112
EFM32G290F64G-E-BGA112 64 16 32 1.98 - 3.8 -40 - 85 BGA112
EFM32G290F128G-E-BGA112 128 16 32 1.98 - 3.8 -40 - 85 BGA112
EFM32G840F32G-E-QFN64 32 8 32 1.98 - 3.8 -40 - 85 QFN64
EFM32G840F64G-E-QFN64 64 16 32 1.98 - 3.8 -40 - 85 QFN64
EFM32G840F128G-E-QFN64 128 16 32 1.98 - 3.8 -40 - 85 QFN64
EFM32G842F32G-E-QFP64 32 8 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G842F64G-E-QFP64 64 16 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G842F128G-E-QFP64 128 16 32 1.98 - 3.8 -40 - 85 TQFP64
EFM32G880F32G-E-QFP100 32 8 32 1.98 - 3.8 -40 - 85 LQFP100
EFM32G880F64G-E-QFP100 64 16 32 1.98 - 3.8 -40 - 85 LQFP100
EFM32G880F128G-E-QFP100 128 16 32 1.98 - 3.8 -40 - 85 LQFP100
EFM32G890F32G-E-BGA112 32 8 32 1.98 - 3.8 -40 - 85 BGA112
EFM32G890F64G-E-BGA112 64 16 32 1.98 - 3.8 -40 - 85 BGA112
EFM32G890F128G-E-BGA112 128 16 32 1.98 - 3.8 -40 - 85 BGA112
EFM32G Data Sheet
Ordering Information
silabs.com | Building a more connected world. Rev. 2.10 | 4
EFM32 890 128F –BGA 112 R
Tape and Reel (Optional)
Pin Count
Package
Memory Size in kB
Memory Type (Flash)
Feature Set Code
Gecko
Energy Friendly Microcontroller 32-bit
G–E
Revision
Temperature Grade – G (-40 to +85 °C)
G
Figure 2.1. Ordering Code Decoder
Adding the suffix 'R' to the part number (e.g., EFM32G890F128G-E-BGA112R) denotes tape and reel.
Visit www.silabs.com for information on global distributors and representatives.
EFM32G Data Sheet
Ordering Information
silabs.com | Building a more connected world. Rev. 2.10 | 5
Table of Contents
1. Feature List ................................2
2. Ordering Information ............................4
3. System Overview .............................10
3.1 System Introduction ............................10
3.1.1 ARM Cortex-M3 Core .........................10
3.1.2 Debug Interface (DBG) .........................10
3.1.3 Memory System Controller (MSC) .....................10
3.1.4 Direct Memory Access Controller (DMA) ...................11
3.1.5 Reset Management Unit (RMU) ......................11
3.1.6 Energy Management Unit (EMU) .....................11
3.1.7 Clock Management Unit (CMU) ......................11
3.1.8 Watchdog (WDOG) ..........................11
3.1.9 Peripheral Reflex System (PRS) .....................11
3.1.10 External Bus Interface (EBI) ......................11
3.1.11 Inter-Integrated Circuit Interface (I2C) ...................11
3.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) ........11
3.1.13 Pre-Programmed USB/UART Bootloader ..................11
3.1.14 Universal Asynchronous Receiver/Transmitter (UART) .............12
3.1.15 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) ........12
3.1.16 Timer/Counter (TIMER) ........................12
3.1.17 Real Time Counter (RTC) .......................12
3.1.18 Low Energy Timer (LETIMER) ......................12
3.1.19 Pulse Counter (PCNT) ........................12
3.1.20 Analog Comparator (ACMP) ......................12
3.1.21 Voltage Comparator (VCMP) ......................12
3.1.22 Analog to Digital Converter (ADC) ....................12
3.1.23 Digital to Analog Converter (DAC) ....................12
3.1.24 Advanced Encryption Standard Accelerator (AES) ...............13
3.1.25 General Purpose Input/Output (GPIO) ...................13
3.1.26 Liquid Crystal Display Driver (LCD) ....................13
3.2 Configuration Summary ..........................14
3.2.1 EFM32G200 ............................14
3.2.2 EFM32G210 ............................15
3.2.3 EFM32G222 ............................16
3.2.4 EFM32G230 ............................17
3.2.5 EFM32G232 ............................18
3.2.6 EFM32G280 ............................19
3.2.7 EFM32G290 ............................20
3.2.8 EFM32G840 ............................21
3.2.9 EFM32G842 ............................22
3.2.10 EFM32G880 ............................23
3.2.11 EFM32G890 ............................25
3.3 Memory Map ..............................27
4. Electrical Characteristics ..........................29
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4.1 Test Conditions .............................29
4.1.1 Typical Values ...........................29
4.1.2 Minimum and Maximum Values ......................29
4.2 Absolute Maximum Ratings .........................29
4.3 General Operating Conditions ........................29
4.4 Current Consumption ...........................30
4.4.1 EM0 Current Consumption .......................31
4.4.2 EM1 Current Consumption .......................34
4.4.3 EM2 Current Consumption .......................37
4.4.4 EM3 Current Consumption .......................38
4.4.5 EM4 Current Consumption .......................39
4.5 Transition between Energy Modes .......................39
4.6 Power Management ............................40
4.7 Flash .................................41
4.8 General Purpose Input Output ........................42
4.9 Oscillators ...............................50
4.9.1 LFXO...............................50
4.9.2 HFXO ..............................51
4.9.3 LFRCO ..............................52
4.9.4 HFRCO ..............................53
4.9.5 AUXHFRCO ............................57
4.9.6 ULFRCO .............................57
4.10 Analog Digital Converter (ADC) .......................58
4.10.1 Typical Performance .........................67
4.11 Digital Analog Converter (DAC) .......................71
4.12 Analog Comparator (ACMP) ........................73
4.13 Voltage Comparator (VCMP) ........................75
4.14 LCD .................................76
4.15 I2C .................................77
4.16 Digital Peripherals ............................78
5. Pin Definitions ..............................79
5.1 EFM32G200 & EFM32G210 (QFN32) ......................79
5.1.1 Pinout ..............................79
5.1.2 Alternate Functionality Pinout ......................82
5.1.3 GPIO Pinout Overview .........................84
5.2 EFM32G222 (TQFP48)...........................85
5.2.1 Pinout ..............................85
5.2.2 Alternate Functionality Pinout ......................88
5.2.3 GPIO Pinout Overview .........................90
5.3 EFM32G230 (QFN64) ...........................91
5.3.1 Pinout ..............................91
5.3.2 Alternate Functionality Pinout ......................94
5.3.3 GPIO Pinout Overview .........................97
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5.4 EFM32G232 (TQFP64)...........................98
5.4.1 Pinout ..............................98
5.4.2 Alternate Functionality Pinout .....................101
5.4.3 GPIO Pinout Overview ........................103
5.5 EFM32G280 (LQFP100) .........................104
5.5.1 Pinout .............................104
5.5.2 Alternate Functionality Pinout .....................109
5.5.3 GPIO Pinout Overview ........................113
5.6 EFM32G290 (BGA112)..........................114
5.6.1 Pinout .............................114
5.6.2 Alternate Functionality Pinout .....................119
5.6.3 GPIO Pinout Overview ........................123
5.7 EFM32G840 (QFN64) ..........................124
5.7.1 Pinout .............................124
5.7.2 Alternate Functionality Pinout .....................127
5.7.3 GPIO Pinout Overview ........................131
5.8 EFM32G842 (TQFP64)..........................132
5.8.1 Pinout .............................132
5.8.2 Alternate Functionality Pinout .....................135
5.8.3 GPIO Pinout Overview ........................139
5.9 EFM32G880 (LQFP100) .........................140
5.9.1 Pinout .............................140
5.9.2 Alternate Functionality Pinout .....................146
5.9.3 GPIO Pinout Overview ........................152
5.10 EFM32G890 (BGA112) .........................153
5.10.1 Pinout .............................153
5.10.2 Alternate Functionality Pinout .....................159
5.10.3 GPIO Pinout Overview .......................165
6. BGA112 Package Specifications .......................166
6.1 BGA112 Package Dimensions .......................166
6.2 BGA112 PCB Layout ..........................167
6.3 BGA112 Package Marking ........................169
7. LQFP100 Package Specifications .......................170
7.1 LQFP100 Package Dimensions .......................170
7.2 LQFP100 PCB Layout ..........................172
7.3 LQFP100 Package Marking ........................174
8. TQFP64 Package Specifications .......................175
8.1 TQFP64 Package Dimensions .......................175
8.2 TQFP64 PCB Layout ..........................177
8.3 TQFP64 Package Marking ........................179
9. TQFP48 Package Specifications .......................180
9.1 TQFP48 Package Dimensions .......................180
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9.2 TQFP48 PCB Layout ..........................182
9.3 TQFP48 Package Marking ........................184
10. QFN64 Package Specifications .......................185
10.1 QFN64 Package Dimensions .......................185
10.2 QFN64 PCB Layout ..........................187
10.3 QFN64 Package Marking ........................189
11. QFN32 Package Specifications .......................190
11.1 QFN32 Package Dimensions .......................190
11.2 QFN32 PCB Layout ..........................191
11.3 QFN32 Package Marking ........................193
12. Chip Revision, Solder Information, Errata ...................194
12.1 Chip Revision ............................194
12.2 Soldering Information ..........................194
12.3 Errata ...............................194
13. Revision History.............................195
13.1 Revision 2.10 ............................195
13.2 Revision 2.00 ............................196
13.3 Revision 1.90 ............................197
13.4 Revision 1.80 ............................197
13.5 Revision 1.71 ............................198
13.6 Revision 1.70 ............................198
13.7 Revision 1.60 ............................198
13.8 Revision 1.50 ............................198
13.9 Revision 1.40 ............................199
13.10 Revision 1.30 ............................199
13.11 Revision 1.20 ............................200
13.12 Revision 1.11 ............................200
13.13 Revision 1.10 ............................201
13.14 Revision 1.00 ............................201
13.15 Revision 0.90 ............................202
13.16 Revision 0.85 ............................202
13.17 Revision 0.84 ............................202
13.18 Revision 0.83 ............................202
13.19 Revision 0.82 ............................203
13.20 Revision 0.81 ............................203
13.21 Revision 0.80 ............................204
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3. System Overview
3.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-
M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32G
microcontroller is well suited for any battery operated application as well as other systems requiring high performance and low-energy
consumption. This section gives a short introduction to each of the modules in general terms and also shows a summary of the configu-
ration for the EFM32G devices. For a complete feature set and in-depth information on the modules, the reader is referred to the
EFM32G Reference Manual.
The diagram shows a superset of features available on the family, which vary by OPN. For more information about specific device fea-
tures, consult Ordering Information.
32-bit bus
Lowest power mode with peripheral operational:
EM2 – Deep Sleep
EM1 - Sleep EM4 - Shutoff
EM0 - Active EM3 - Stop
Core / Memory
Flash Program
Memory
RAM Memory
ARM CortexTM
M3 processor
Debug Interface
DMA Controller
Memory
Protection Unit
Security
Hardware AES
Energy Management
Brown-Out
Detector
Voltage
Regulator
Voltage
Comparator
Power-On Reset
Clock Management
High Frequency
RC Oscillator
Low Frequency
RC Oscillator
Low Frequency
Crystal
Oscillator
Watchdog
Oscillator
Auxiliary High
Freq. RC Osc.
High Frequency
Crystal Oscillator
Analog Interfaces
DACADC
LCD Controller Analog
Comparator
Peripheral Reflex System
Serial Interfaces
UART
I2C
I/O Ports Timers and Triggers
Timer/Counter
Low Energy Timer Watchdog Timer
External
Interrupts Pin Reset
External Bus
Interface
General
Purpose I/O
Pulse Counter
Real Time
Counter
USART
Low Energy
UARTTM
Figure 3.1. Block Diagram
3.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection
Unit with support for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts triggered while
the CPU is asleep. The EFM32 implementation of the Cortex-M3 is described in detail in EFM32G Reference Manual.
3.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface . In addition there is also a 1-wire Serial Wire
Viewer pin which can be used to output profiling information, data trace and software-generated messages.
3.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32G microcontroller. The flash memory is readable and
writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block.
Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock
bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations
are supported in the energy modes EM0 and EM1.
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 10
3.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing
the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance
data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230
µDMA controller licensed from ARM.
3.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32G.
3.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32G microcontrollers. Each energy mode man-
ages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks.
3.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32G. The CMU provides
the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the
available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not
wasting power on peripherals and oscillators that are inactive.
3.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may
e.g. be caused by an external event, such as an ESD pulse, or by a software failure.
3.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each
other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex
signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but
edge triggers and other functionality can be applied by the PRS.
3.1.10 External Bus Interface (EBI)
The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH, ADCs and LCDs. The inter-
face is memory mapped into the address bus of the Cortex-M3. This enables seamless access from software without manually manipu-
lating the IO settings each time a read or write is performed. The data and address lines are multiplexed in order to reduce the number
of pins required to interface the external devices. The timing is adjustable to meet specifications of the external devices. The interface is
limited to asynchronous devices.
3.1.11 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as both a master and a slave, and
supports multi-master buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all
the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant
system. The interface provided to software by the I2C module, allows both fine-grained control of the transmission process and close to
automatic transfers. Automatic recognition of slave addresses is provided in all energy modes.
3.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full
duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 Smart-
Cards, and IrDA devices.
3.1.13 Pre-Programmed USB/UART Bootloader
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Autobaud and destructive write are
supported. The autobaud feature, interface and commands are described further in the application note.
EFM32G Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 2.10 | 11
3.1.14 Universal Asynchronous Receiver/Transmitter (UART)
The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module. It supports full- and half-du-
plex asynchronous UART communication.
3.1.15 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on a strict power budget. Only a
32.768 kHz clock is needed to allow UART communication up to 9600 baud/ s. The LEUART includes all necessary hardware support
to make asynchronous serial communication possible with minimum of software intervention and energy consumption.
3.1.16 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-Width Modulation (PWM) out-
put. TIMER0 also includes a Dead-Time Insertion module suitable for motor control applications.
3.1.17 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal oscillator, or a 32.768 kHz RC
oscillator. In addition to energy modes EM0 and EM1, the RTC is also available in EM2. This makes it ideal for keeping track of time
since the RTC is enabled in EM2 where most of the device is powered down.
3.1.18 Low Energy Timer (LETIMER)
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2 in addition to EM1 and EM0.
Because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks to be
performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of
waveforms with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be configured to start
counting on compare matches from the RTC.
3.1.19 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature encoded inputs. It runs off either
the internal LFACLK or the PCNTn_S0IN pin as external clock source. The module may operate in energy mode EM0 - EM3.
3.1.20 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs can either be one of the selectable internal references or from external pins. Response time and thereby also the current
consumption can be configured by altering the current supply to the comparator.
3.1.21 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can be generated when the supply
falls below or rises above a programmable threshold. Response time and thereby also the current consumption can be configured by
altering the current supply to the comparator.
3.1.22 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per
second. The integrated input mux can select inputs from 8 external pins and 6 internal signals.
3.1.23 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC is fully differential rail-to-rail,
with 12-bit resolution. It has two single-ended output buffers which can be combined into one differential output. The DAC may be used
for a number of different applications such as sensor interfaces or sound output.
EFM32G Data Sheet
System Overview
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3.1.24 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data
block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave
which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or
16-bit operations are not supported.
3.1.25 General Purpose Input/Output (GPIO)
General Purpose Input/Output (GPIO) pins are organized into ports with up to 16 pins each. These pins can individually be configured
as either an output or input. More advanced configurations like open-drain, filtering and drive strength can also be configured individual-
ly for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM outputs or USART communica-
tion, which can be routed to several locations on the device. The GPIO supports up to 16 asynchronous external pin interrupts, which
enables interrupts from any pin on the device. Also, the input value of a pin can be routed through the Peripheral Reflex System to
other peripherals.
3.1.26 Liquid Crystal Display Driver (LCD)
The LCD driver is capable of driving a segmented LCD display with up to 4x40 segments. A voltage boost function enables it to provide
the LCD display with higher voltage than the supply voltage for the device. In addition, an animation feature can run custom animations
on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame
Counter interrupt that can wake-up the device on a regular basis for updating data.
EFM32G Data Sheet
System Overview
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3.2 Configuration Summary
3.2.1 EFM32G200
The features of the EFM32G200 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.1. EFM32G200 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
ACMP0 Full configuration ACMP0_CH[1:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:5], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:4]
DAC0 Full configuration DAC0_OUT[0]
GPIO 24 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
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3.2.2 EFM32G210
The features of the EFM32G210 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.2. EFM32G210 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
ACMP0 Full configuration ACMP0_CH[1:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:5], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:4]
DAC0 Full configuration DAC0_OUT[0]
AES Full configuration NA
GPIO 24 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
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3.2.3 EFM32G222
The features of the EFM32G222 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.3. EFM32G222 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
ACMP0 Full configuration ACMP0_CH[4:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:4]
DAC0 Full configuration DAC0_OUT[1]
AES Full configuration NA
GPIO 37 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
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3.2.4 EFM32G230
The features of the EFM32G230 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.4. EFM32G230 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[1:0]
AES Full configuration NA
GPIO 56 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
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3.2.5 EFM32G232
The features of the EFM32G232 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.5. EFM32G232 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[15:8], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[0]
AES Full configuration NA
GPIO 53 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
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3.2.6 EFM32G280
The features of the EFM32G280 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.6. EFM32G280 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
EBI Full configuration EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn,
EBI_CS[3:0], EBI_AD[15:0]
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
UART0 Full configuration U0_TX, U0_RX
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[1:0]
AES Full configuration NA
GPIO 86 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
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3.2.7 EFM32G290
The features of the EFM32G290 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.7. EFM32G290 Configuration Summary
Module Configuration Pin Connections
Cortex-M3 Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
EBI Full configuration EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn,
EBI_CS[3:0], EBI_AD[15:0]
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration US2_TX, US2_RX, US2_CLK, US2_CS
UART0 Full configuration U0_TX, U0_RX
LEUART0 Full configuration LEU0_TX, LEU0_RX
LEUART1 Full configuration LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
LETIMER0 Full configuration LET0_O[1:0]
PCNT0 Full configuration, 8-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O
ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:0]
DAC0 Full configuration DAC0_OUT[1:0]
AES Full configuration NA
GPIO 90 pins Available pins are shown in Table 4.3 (p. 57)
EFM32G Data Sheet
System Overview
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