SL74HC151
System Logic
Semiconductor
SLS
8-Input Data Selector/Multiplexer
High-Performance Silicon-Gate CMOS
The SL74HC151 is identical in pinout to the LS/ALS151. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The device selects one of the eight binary Data Inputs, as
determined by the Address Inputs. The Strobe pin must be at a low
level for the sele cted data to appear at the outputs. If Strobe is high,
the Y output is forced to a low level and the Y output is forced to a
high level.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC151N Plastic
SL74HC151D SOIC
TA = -55° to 125° C for all packages
FUNCTION TABLE
Inputs Outputs
A2 A1 A0 Strobe Y Y
X X X H L H
L L L L D0 D0
L L H L D1 D1
L H L L D2 D2
L H H L D3 D3
H L L L D4 D4
H L H L D5 D5
H H L L D6 D6
H H H L D7 D7
D0,D1...D7=the level of the respective D
input
X = don’t care
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
PIN ASSIGNMENT
SL74HC151
System Logic
Semiconductor
SLS
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND(VIN or VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC).
Unused outputs must be left open.
SL74HC151
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
85
°C 125
°C Unit
VIH Minimum High-Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT 20 µA 2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL Maximum Low -Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT 20 µA 2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH Minimum High-Level
Output Voltage VIN=VIH or VIL
IOUT 20 µA 2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
IOUT 4.0 mA
IOUT 5.2 mA
4.5
6.0 3.98
5.48 3.84
5.34 3.7
5.2
VOL Maximum Low-Level
Output Voltage VIN=VIH or VIL
IOUT 20 µA 2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH or VIL
IOUT 4.0 mA
IOUT 5.2 mA
4.5
6.0 0.26
0.26 0.33
0.33 0.4
0.4
IIN Maximum Input
Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA 6.0 8.0 80 160 µA
SL74HC151
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C to
-55°C 85°C 125°C Unit
tPLH, tPHL Maximum Propagation Delay, Input D to
Output Y or Y (Figures 1,3 and 6) 2.0
4.5
6.0
185
37
31
230
46
39
280
56
48
ns
tPLH, tPHL Maximum Propagation Delay , Input A to
Output Y or Y (Figures 2 and 6) 2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
ns
tPLH, tPHL Maximum Propagation Delay , Strobe to
Output Y or Y (Figures 4,5 and 6) 2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 6) 2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN Maximum Input Capacitance - 10 10 10 pF
Power Dissipation Capacitance (Per Package) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
36 pF
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Switching Waveforms
SL74HC151
System Logic
Semiconductor
SLS
Figure 5. Switching waveforms Figure 6.Test Circuit
EXPANDED LOGIC DIAGRAM