MAX696MJE/883B - Maxim Integrated

General Description

The MAX696/MAX697 supervisory circuits reduce the

complexity and number of components required for

power-supply monitoring and battery-control functions

in microprocessor (μP) systems. These include μP reset

and backup-battery switchover, watchdog timer, CMOS

RAM write protection, and power-failure warning. The

MAX696/MAX697 significantly improve system reliability

and accuracy compared to that obtained with separate

ICs or discrete components.

The MAX696 and MAX697 are supplied in 16-pin pack-

ages and perform six functions:

1) A reset output during power-up, power-down, and

brownout conditions. The threshold for this “lowline”

reset is adjustable by an external voltagedivider.

2) A reset pulse if the optional watchdog timer has not

been toggled within a specified time.

3) Individual outputs for low-line and watchdog fault con-

ditions.

4) The reset time may be left at its default value of 50ms,

or may be varied with an external capacitor or clock

pulses.

5) A separate 1.3V threshold detector for power-fail warn-

ing, low-battery detection, or to monitor a power supply

other than VCC.

The MAX696 also has battery-backup switching for CMOS

RAM, CMOS microprocessor, or other lowpower logic.

The MAX697 lacks battery-backup switching, but has

write-protection pins (CE IN and CE OUT) for CMOS

RAM or EPROM. In addition, it consumes less than 250

microamperes.

Applications

●Computers

●Controllers

●Intelligent Instruments

● Critical μP Power Monitoring

Features

● Adjustable Low-Line Monitor and Power-Down Reset

● Power-OK/Reset Time Delay

● Watchdog Timer—100ms, 1.6s, or Adjustable

●Minimum Component Count

● 1μA Standby Current

● Battery-Backup Power Switching (MAX696)

● On-Board Gating of Chip-Enable Signals (MAX697)

● Separate Monitor for Power-Fail or Low-Battery

Warning

Typical Operating Circuit appears at end of data sheet.

Pin Configurations continued at end of data sheet.

Ordering Information continued at end of data sheet.

19-0829; Rev 5; 7/14

Devices in PDIP and SO packages are available in both leaded

and lead(Pb)-free packaging. Specify lead free by adding the +

symbol at the end of the part number when ordering. Lead free

not available for CERDIP package.

PART TEMP RANGE PIN-PACKAGE

MAX696C/D 0°C to +70°C Dice

MAX696CPE 0°C to +70°C 16 PDIP

MAX696CWE 0°C to +70°C 16 Wide SO

MAX696EPE -40°C to +85°C 16 PDIP

MAX696EJE -40°C to +85°C 16 CERDIP

MAX696EWE -40°C to +85°C 16 Wide SO

MAX696MJE -55°C to +125°C 16 CERDIP

VOUT

VBATT

VCC

GND LLIN

N.C.

BATT ON

PFI

WDI

OSC IN

OSC SEL

PFO

LOW LINE

TOP VIEW

RESET

WDO

MAX696

MAX696/MAX697 Microprocessor Supervisory Circuits

Ordering Information

Pin Congurations

Terminal Voltage (with respect to GND)

VCC.......................................................................-0.3V to +6V

VBATT............

.................................

......................-0.3V to +6V

All Other Inputs (Note 1).....................-0.3V to (VOUT + 0.5V)

Input Current

VCC................................................................................200mA

VBATT..............................................................................50mA

GND.................................................................................20mA

Output Current

VOUT....................................................Short-Circuit Protected

All Other Outputs.............................................................20mA

Rate-of-Rise, VBATT, VCC...............................................100V/μs

Operating Temperature Range

C Suffix................................................................0°C to +70°C

E Suffix.............................................................-40°C to +85°C

M Suffix..........................................................-55°C to +125°C

Power Dissipation (TA = +70°C)

16-Pin PDIP (derated 7mW/°C above +70°C)..............600mW

16-Pin SO (derated 7mW/°C above +70°C).................600mW

16-Pin CERDIP (derated 10mW/°C above +85°C)......600mW

Storage Temperature Range..............................-65°C to +160°C

Lead Temperature (soldering, 10s)..................................+300°C

(VCC = full operating range, VBATT = 2.8V, TA = +25°C, unless otherwise noted.)

Note 1: The input voltage limits on PFI and WDI may be exceeded providing the input current is limited to less than 10mA.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Operating Voltage Range TA = full

MAX696 VCC 3.0 5.5

VMAX696 VBATT 2.0 VCC - 0.3V

MAX697 VCC 3.0 5.5

Supply Current (MAX697) TA = full 160 300 µA

BATTERY-BACKUP SWITCHING (MAX696)

VOUT Output Voltage

IOUT = 1mA, TA = full VCC -

0.3

VCC -

0.1 V

IOUT = 50mA, TA = full VCC -

0.5

VCC -

0.25

VOUT in Battery-Backup Mode IOUT = 250µA, VCC < (VBATT - 0.2V), TA = full VBATT -

0.1

VBATT

- 0.02 V

Supply Current (Excludes IOUT)IOUT = 1mA 1.5 4mA

IOUT = 50mA 2.5 7

Supply Current in Battery-Backup

Mode

VCC = 0V, VBATT = 2.8V, TA = +25°C 0.6 1µA

VCC = 0V, VBATT = 2.8V, TA = full 10

Battery Standby Leakage Current 5.5V > VCC > (VBATT +

0.3V)

TA = +25°C -100 +20 nA

TA = full -1.00 +0.02 µA

Battery Switchover Threshold VCC

- VBATT

Power-up 70 mV

Power-down 50

Battery Switchover Hysteresis 20 mV

BATT ON Output Voltage ISINK - 1.6mA 0.4 V

BATT ON Output Short-Circuit

Current

BATT ON = VOUT = 2.4V sink current 7 mA

BATT ON = VOUT, VCC = 0V 0.5 2.5 25.0 µA

RESET AND WATCHDOG TIMER

Low-Line Voltage Threshold (LLIN) VCC = +5V, +3V; TA = full 1.25 1.30 1.35 V

Reset Timeout Delay Figure 6, OSC SEL HIGH, VCC = 5V 35 50 70 ms

Watchdog Timeout Period,

Internal Oscillator

Long period, VCC = 5V 1.00 1.6 2.25 s

Short period, VCC = 5V 70 100 140 ms

MAX696/MAX697 Microprocessor Supervisory Circuits

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Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Electrical Characteristics

(VCC = full operating range, VBATT = 2.8V, TA = +25°C, unless otherwise noted.)

Note 2: TA = full operating range

Note 3: WDI is guaranteed to be in the mid-level (inactive) state if WDI is floating and VCC is in the operating voltage range. WDI is

internally biased to 38% of VCC with an impedance of approximately 125kΩ.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Watchdog Timeout Period,

External Clock

Long period 4032 4097 Clock

cycles

Short period 960 1025

Minimum WDI Input Pulse Width VIL = 0.4V, VIH = 3.5V, VCC = 5V 200 ns

RESET and RESET Output

Voltage (Note 2)

ISINK = 400µA, VCC = 2V, VBATT = 0V 0.4

VISINK = 1.6mA, 3V < VCC < 5.5V 0.4

ISOURCE = 1µA, VCC = 5V 3.5

LOW LINE and WDO Output

Voltage

ISINK = 800µA, TA = full 0.4 V

ISOURCE = 1µA, VCC = 5V, TA = full 3.5

Output Short-Circuit Current RESET, RESET, WDO, LOW LINE 1 3 25 µA

WDI Input Threshold VCC = 5V

(Note 3)

Logic-low 0.8

VLogic-high (MAX696) 3.5

Logic-high (MAX697) 3.8

WDI Input Current VWDI = VOUT 20 50 µA

VWDI = 0V -50 -15

POWER-FAIL DETECTOR

PFI Input Threshold VCC = 3V, 5V 1.2 1.3 1.4 V

PFI - LLIN Threshold Difference VCC = 3V, 5V ±15 ±50 mV

PFI Input Current ±0.01 ±25 nA

LLIN Input Current MAX697 -25 ±0.01 +25 nA

MAX696 -500 ±0.01 +25

PFO Output Voltage ISINK = 1.6mA 0.4 V

ISOURCE = 1µA, VCC = 5V 3.5

PFO Short-Circuit Source Current VPFI = 0V, VPFO = 0V 1 3 25 µA

CHIP-ENABLE GATING (MAX697)

CE IN Thresholds VIL 0.8 V

VIH, VCC = 5V 3.0

CE IN Pullup Current 3 µA

CE OUT Output Voltage

ISINK = 1.6mA 0.4

VISOURCE = 800µA VCC - 0.5V

ISOURCE = 1µA, VCC = 0V VCC - 0.05V

CE Propagation Delay VCC = 5V 80 150 ns

OSCILLATOR

OSC IN Input Current ±2 µA

OSC SEL Input Pullup Current 5 µA

OSC IN Frequency Range VOSC SEL = 0V 0 250 kHz

OSC IN Frequency with External

Capacitor VOSC SEL = 0V, COSC = 47pF 4 kHz

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Electrical Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

MAX696

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

VCC MODE

543

0.25

0.50

0.75

1.00

1.25

1.50

0.25

0.50

0.75

1.00

1.25

1.50

2 6

SUPPLY CURRENT AS A FUNCTION

OF SUPPLY VOLTAGE

SUPPLY CURRENT (µA)

BATTERY MODE

MAX697

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

543

100

150

200

250

2 6

SUPPLY CURRENT AS A FUNCTION

OF SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

RESET TIMEOUT DELAY

(ms)

543

100

150

200

250

300

2 6

RESET TIMEOUT DELAY AS A

FUNCTION OF SUPPLY VOLTAGE

VCC MODE

TA = +25°C

BATTERY MODE

TA = 25°C

MAX696/MAX697 Microprocessor Supervisory Circuits

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Typical Operating Characteristics

PIN NAME FUNCTION

MAX696 MAX697

1 — VBATT Backup-Battery Input. Connect to ground if a backup battery is not used.

2 — VOUT The higher of VCC or VBATT is internally switched to VOUT. Connect VOUT to VCC if

VOUT and VBATT are not used.

3 3 VCC +5V Input

45 GND 0V Ground Reference for All Signals

5— BATT ON

BATT ON goes High when VOUT is Internally Switched to the VBATT Input. It goes

low when VOUT is internally switched to VCC. The output typically sinks 7mA and

can directly drive the base of an external pnp transistor to increase the output current

above the 50mA rating of VOUT.

6 6 LOW LINE LOW LINE goes Low when LLIN Falls Below 1.3V. It returns high as soon as LLIN

rises above 1.3V. See Figure 5.

7 7 OSC IN

OSC IN Sets the Reset Delay Timing and Watchdog Timeout Period when OSC SEL

Floats or is Driven Low. The timing can also be adjusted by connecting an external

capacitor to this pin. See Figure 7. When OSC SEL is high, OSC IN selects between

fast and slow watchdog timeout periods

8 8 OSC SEL

When OSC SEL is Unconnected or Driven High, the Internal Oscillator Sets the

Reset Time Delay and Watchdog Timeout Period. When OSC SEL is low, the

external oscillator input, OSC IN, is enabled. OSC SEL has a 3µA internal pullup. See

Table 1.

9 9 PFI PFI is the Noninverting Input to the Power-Fail Comparator. When PFI is less than

1.3V, PFO goes low. Connect PFI to GND or VOUT when not used. See Figure 1.

10 10 PFO PFO is the Output of the Power-Fail Comparator. It goes low when PFI is less than

1.3V. The comparator is turned off and PFO goes low when VCC is below VBATT.

11 11 WDI

The Watchdog Input, WDI, is a Three-Level Input. If WDI remains either high or low

for longer than the watchdog timeout period, RESET pulses low and WDO goes low.

The watchdog timer is disabled when WDI is left oating or is driven to mid-supply.

The timer resets with each transition at the watchdog timer input.

12 2 N.C. No Connection. Leave this pin open.

13 4 LLIN

Low-Line Input. LLIN is the CMOS input to a comparator whose other input is a

precision 1.3V reference. The output is LOW LINE and is also connected to the reset

pulse generator. See Figure 2.

14 14 WDO

The Watchdog Output, WDO, goes Low if WDI Remains either High or Low for

Longer than the Watchdog Timeout Period. WDO is set high by the next transition at

WDI. If WDI is unconnected or at mid-supply, WDO remains high. WDO also goes

high when LOW LINE goes low.

15 15 RESET

RESET goes Low whenever LLIN Falls Below 1.3V or VCC Falls Below the VBATT

Input Voltage. RESET remains low for 50ms after LLIN goes above 1.3V. RESET also

goes low for 50ms if the watchdog timer is enabled but not serviced within its timeout

period. The RESET pulse width can be adjusted as shown in Table 1.

16 16 RESET RESET is an Active-High Output. It is the inverse of RESET.

MAX696/MAX697 Microprocessor Supervisory Circuits

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Pin Description

Typical Applications

MAX696

A typical connection for the MAX696 is shown in

Figure 1. CMOS RAM is powered from VOUT. VOUT

is internally connected to VCC when power is present,

or to VBATT when VCC is less than the battery voltage.

VOUT can supply 50mA from VCC, but if more current is

required, an external pnp transistor can be added. When

VCC is higher than VBATT, the BATT ON output goes

low, providing 7mA of base drive for the external transis-

tor. When VCC is lower than VBATT, an internal 200Ω

MOSFET connects the backup battery to VOUT. The qui-

escent current in the battery-backup mode is 1μA maxi-

mum when VCC is between 0V and (VBATT - 700mV).

Reset Output

A voltage detector monitors VCC and generates a RESET

output to hold the microprocessor’s RESET line low when

LLIN is below 1.3V. An internal monostable holds RESET

Figure 1. MAX696 Typical Application

PIN NAME FUNCTION

MAX696 MAX697

— 1 TEST Used During Maxim Manufacture Only. Always ground this pin.

— 12 CE OUT CE OUT goes low only when CE IN is low and LLIN is above 1.3V. See Figure 5.

— 13 CE IN The Input to the CE Gating Circuit. Connect to GND or VOUT if not used.

0.1µF

3 5

VOUT

VBATT

RESETRESET

LOW LINE

RESET

LLIN

PFO

WDO

BATT ON

CMOS

RAM

A0–A15

MICROPROCESSOR

I/O

NMI

WDI

OTHER SYSTEM RESET SOURCES

SYSTEM STATUS INDICATORS

AUDIBLE

ALARM

146

+5V

VCC

INPUT

PFI

GND

OSC IN

OSC SEL

NO CONNECTION

RESET

BATTERY

MAX696

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Pin Description (continued)

low for 50ms after LLIN rises above 1.3V. This prevents

repeated toggling of RESET even if the VCC power drops

out and recovers with each power line cycle.

The crystal oscillator normally used to generate the clock

for microprocessors takes several milliseconds to start.

Since most microprocessors need several clock cycles to

reset, RESET must be held low until the microprocessor

clock oscillator has started. The power-up RESET pulse

lasts 50ms to allow for this oscillator startup time. An

inverted, active-high RESET output is also supplied.

Power-Fail Detector

The MAX696 issues a nonmaskable interrupt (NMI) to the

microprocessor when a power failure occurs. The power

line is monitored by two external resistors connected to the

power-fail input (PFI). When the voltage at PFI falls below

1.3V, the power-fail output (PFO) drives the processor’s

NMI input low. An earlier power-fail warning can be gener-

ated if the unregulated DC input of the regulator is available

for monitoring.

Watchdog Timer

The microprocessor drives the watchdog input (WDI)

with an I/O line. When OSC IN and OSC SEL are uncon-

nected, the microprocessor must toggle the WDI pin once

every 1.6 seconds to verify proper software execution. If

a hardware or software failure occurs so that WDI is not

toggled, the MAX696 will issue a 50ms RESET pulse after

1.6 seconds. This typically restarts the microprocessor’s

power-up routine. A new RESET pulse is issued every 1.6

seconds until WDI is again strobed.

The watchdog output (WDO) goes low if the watchdog

timer is not serviced within its timeout period. Once WDO

goes low, it remains low until a transition occurs at WDI

while RESET is high. The watchdog timer feature can be

disabled by leaving WDI unconnected. OSC IN and OSC

SEL also allow other watchdog timing options, as shown

in Table 1 and Figure 7.

Figure 2. MAX696/MAX697 Block Diagram

BATT ON (MAX696)

VOUT (MAX696)

VBATT (MAX696)

VCC

CHIP-ENABLE

OUTPUT (MAX697)

LOW LINE

RESET

WATCHDOG OUTPUT

POWER-FAIL OUTPUT

WATCHDOG

TIMER

GROUND

1.30V

POWER-FAIL

INPUT

WATCHDOG TRANSITION

DETECTOR

TIMEBASE FOR RESET

AND

WATCHDOG

RESET GENERATOR

WATCHDOG INPUT

LLIN

OSC IN

OSC SEL

(MAX697)

CHIP-ENABLE INPUT

1 5

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MAX697

The MAX697 is nearly identical to the MAX696. The MAX697

lacks the battery-backup feature, so it does not have the

VBATT, VOUT, or BATT ON pins. This allows the MAX697

to consume less than 250 microamperes, and it allows the

inclusion of RAM write-protection pins. See Figure 2.

Detailed Description

Battery Switchover and VOUT (MAX696)

Battery Switchover and VOUT (MAX696) The battery-

switchover circuit compares VCC to the VBATT input, and

connects VOUT to whichever is higher. Switchover occurs

when VCC is 50mV greater than VBATT as VCC falls, and

when VCC is 70mV more than VBATT as VCC rises (see

Figure 3). The switchover comparator has 20mV of hys-

teresis to prevent repeated, rapid switching if VCC falls

very slowly or remains nearly equal to the battery voltage.

When VCC is higher than VBATT, VCC is internally

switched to VOUT with a low-saturation pnp transistor.

VOUT has 50mA output current capability. Use an external

pnp pass transistor in parallel with the internal transistor

if the output current requirement at VOUT exceeds 50mA

or if a lower VCC - VOUT voltage differential is desired.

The BATT ON output can directly drive the base of the

external transistor.

It should be noted that the MAX696 need only supply

the average current drawn by the CMOS RAM if there is

adequate filtering. Many RAM data sheets specify a 75mA

maximum supply current, but this peak current spike lasts

only 100ns. A 0.1μF bypass capacitor at VOUT supplies

the high instantaneous current, while VOUT need only

supply the average load current, which is much less. A

capacitance of 0.1μF or greater must be connected to the

VOUT terminal to ensure stability.

A 200Ω MOSFET connects the VBATT input to VOUT

during battery backup. This MOSFET has very low input-

to-output differential (dropout voltage) at the low current

levels required for battery backup of CMOS RAM or other

low-power CMOS circuitry. When VCC equals VBATT, the

supply current is typically 12μA. When VCC is between 0V

and (VBATT - 700mV), the typical supply current is only

600nA (typ), 1μA (max).

Figure 3. MAX696 Battery-Switchover Block Diagram

700mV

100mV

BATTERY

INPUT

BASE DRIVE

VCC

0.1µF

TO CMOS

RAM AND

REAL-TIME

CLOCK

VCC IN

BATT ON

p-CHANNEL

MOSFET

INTERNAL

SHUTDOWN

SIGNAL WHEN

VBATT > VCC + 0.7V

LOW IQ MODE SELECT

VOUT

VCC

+5V

VBATT

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The MAX696 operates with battery voltages from 2.0V

to 4.25V. The battery voltage should not be within 0.5V

of VCC, or switchover may occur. High-value capacitors,

either standard electrolytic or the farad-size double-

layer capacitors, can also be used for short-term memory

backup. The capacitor charging voltage should include a

diode to limit the fully charged voltage to approximately

0.5V less than VCC. The charging resistor for recharge-

able batteries should be connected to VOUT since this

eliminates the discharge path that exists if the resistor is

connected to VCC.

A small leakage current of typically 10nA (20nA max)

flows out of the VBATT terminal. This current varies with

the amount of current that is drawn from VOUT, but its

polarity is such that the backup battery is always slightly

charged, and is never discharged while VCC is in its

operating voltage range. This extends the shelf life of the

backup battery by compensating for its self-discharge cur-

rent. Also note that this current poses no problem when

lithium batteries are used for backup since the maximum

current (20nA) is safe for even the smallest lithium cells.

If the battery-switchover section is not used, connect

VBATT to GND and connect VOUT to VCC. Table 2 shows

the state of the inputs and output in the lowpower battery-

backup mode.

Reset Output

RESET is an active-low output that goes low whenever

LLIN falls below 1.3V. It remains low until LLIN rises above

1.312V for 50ms. (See Figures 4 and 5.)

The guaranteed minimum and maximum low-line thresh-

olds of the MAX696/MAX697 are 1.25V and 1.35V. The

LLIN comparator has approximately 12mV of hysteresis.

The response time of the reset voltage comparator is

about 100μs. LLIN should be bypassed to ensure that

glitches do not activate the RESET output.

RESET also goes low if the watchdog timer is enabled and

WDI remains either high or low longer than the watchdog

timeout period. RESET has an internal 3μA pullup, and

can either connect to an open-collector reset bus or direct-

ly drive a CMOS gate without an external pullup resistor.

Figure 4. Reset Block Diagram

(MAX697) CE IN CE OUT (MAX697)

LOW LINE

VCC

LLIN

WATCHDOG

FROM

WATCHDOG

TIMER

10kHz CLOCK

FROM TIMEBASE

SECTION

RESET RESET

TIME Qn

POWER-ON

RESET

1.3V

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CE Gating and RAM Write Protection

The MAX697 uses two pins to control the CE or WRITE

inputs of CMOS RAMs. When LLIN is > 1.3V, CE OUT is a

buffered replica of CE IN, with a 50ns propagation delay.

If LLIN input falls below 1.3V (1.2V min, 1.4V max), an

internal gate forces CE OUT high, independent of CE IN.

The CE output is also forced high when VCC is less than

VBATT. (See Figure 4.)

CE OUT typically drives the CE, CS, or WRITE input of

battery backed up CMOS RAM. This ensures the integrity

of the data in memory by preventing write operations when

VCC is at an invalid level. Similar protection of EEPROMs

can be achieved by using the CE OUT to drive the STORE

or WRITE inputs of an EEPROM, EAROM, or NOVRAM.

If the 50ns typical propagation delay of CE OUT is too

long, connect CE IN to GND and use the resulting CE

OUT to control a high-speed external logic gate. A second

alternative is to AND the LOW LINE output with the CE or

WR signal. An external logic gate and the RESET output

of the MAX696/MAX697 can also be used for CMOS RAM

write protection.

1.25V Comparator and Power-Fail Warning

The power-fail input (PFI) is compared to an internal 1.3V

reference. The power-fail output (PFO) goes low when the

voltage at PFI is less than 1.3V. Typically PFI is driven bay

an external voltage-divider that senses either the unregu-

lated DC input to the system’s VCC regulator or the regu-

lated output. The voltage-divider ration can be chosen so

the voltage at PFI falls below 1.3V several milliseconds

before the LLIN falls below 1.3V. PFO is normally used to

interrupt the microprocessor so that data can be stored in

RAM before LLIN falls below 1.3V and the RESET output

goes low.

The power-fail detector can also monitor the backup bat-

tery to warn of a low-battery condition. To conserve bat-

tery power, the power-fail detector comparator is turned

off and PFO is forced low when VCC is lower than the

VBATT input voltage.

Watchdog Timer and Oscillator

The watchdog circuit monitors the activity of the micropro-

cessor. If the microprocessor does not toggle the watch-

dog input (WDI) within the selected timeout period, a 50ms

RESET pulse is generated. Since many systems cannot

service the watchdog timer immediately after a reset,

the MAX696/MAX697 have a longer timeout period after

Figure 5. MAX697 Reset Timing

LLIN

1.312V 1.3V 1.312V 1.3V

50ms 50ms

LOW LINE

OUTPUT

(MAX697) CE IN

(MAX697) CE OUT

RESET

OUTPUT

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a reset is issued. The normal timeout period becomes

effective following the first transition of WDI after RESET

has gone high. The watchdog timer is restarted at the end

of reset, whether the reset was caused by lack of activ-

ity on WDI or by LLIN falling below 1.3V. If WDI remains

either high or low, reset pulses will be issued every 1.6s.

The watchdog monitor can be deactivated by floating the

watchdog input (WDI).

The watchdog output (WDO) goes low if the watchdog

timer times out, and it remains low until set high by the

next transition on the watchdog input. WDO is also set

high when LLIN goes below 1.3V. The watchdog timeout

period defaults to 1.6s and the reset pulse width defaults

to 50ms. The MAX696 and MAX697 allow these times to

be adjusted per Table 1.

The internal oscillator is enabled when OSC SEL is high

or floating. In this mode, OSC IN selects between the

1.6s and 100ms watchdog timeout periods. In either case,

immediately after a reset, the timeout period is 1.6s. This

gives the microprocessor time to reinitialize the system.

WD transmissions while RESET is low are ignored. If OSC

IN is low, then the 100ms watchdog period becomes effec-

tive after the first transition of WDI. The software should

be written so the I/O port driving WDI is left in its power-up

reset state until the initialization routines are completed

and the microprocessor is able to toggle WDI at the mini-

mum 70ms watchdog timeout period.

Figure 6. Watchdog Timer Block Diagram

WATCHDOG

TIMEOUT

SELECTOR

LOGIC

WATCHDOG

COUNTER

PRESCALER

RESET

COUNTER

Q11

Q13

Q15

RR Q10/12

WATCHDOG

FAULT FF

LONG/SHORT

RESET

FLIP FLOP

QQQ

10.24kHz FROM INTERNAL OSCILLATOR

OR EXTERNALLY SET FREQUENCY FROM

OSC IN PIN

S R SRS Q

LOW

LINE

GOES HIGH AT THE

END OF WATCHDOG

TIMEOUT PERIOD

RESET RESET

TRANSITION

DETECTOR

LOW LINE

(HI IF LLIN < 1.3V)

FOR EACH TRANSITION

VCC

1.0V

2.7V

WATCHDOG INPUT

HI IF WATCHDOG

INPUT IS FLOATING WATCHDOG TIMEOUT SELECT

WATCHDOG OUTPUT

MAX696/MAX697 Microprocessor Supervisory Circuits

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Applications Information

Adding Hysteresis to the

Power-Fail Comparator

Since the power-fail comparator circuit is noninvert-

ing, hysteresis can be added by connecting a resistor

between the PFO output and the PFI input as shown in

Figure 7. When PFO is low, resistor R3 sinks current from

the summing junction at the PFI pin. When PFO is high,

the series combination of R3 and R4 source current into

the PFI summing junction.

Alternate Watchdog Input Drive Circuits

The watchdog feature can be enabled and disabled

under program control by driving WDI with a three-state

buffer (Figure 8). The drawback to this circuit is that a

software fault may erroneously three-state the buffer,

thereby preventing the MAX696/MAX697 from detecting

that the microprocessor is no longer working. In most

cases, a better method is to extend the watchdog period

rather than disabling the watchdog. See Figure 9. When

the control input is high, the OSC SEL pin is low and

the watchdog timeout is set by the external capacitor.

A 0.01μF capacitor sets a watchdog timeout delay of

100s. When the control input is low, the OSC SEL pin is

driven high, selecting the internal oscillator. The 100ms or

the 1.6s period is chosen, depending on which diode in

Figure 9 is used.

Figure 7. Adding Hysteresis to the Power-Fail Voltage

Comparator

Figure 8. Disabling the Watchdog Under Program Control

Figure 9. Selecting Internal or External Watchdog Timeout

VCC

PFO

PFI GND

7805

7V - 15V +5V

75kΩ

10kΩ

13kΩ

300kΩ

TOP

VH = 9.125V

VL = 7.9V

HYSTERESIS = 1.23V

VH = 1.3V

VL = 1.3V

{ }

1 + +

{ }

1 + +

(5V - 1.3V) R1

1.3V (R3 + R4)

HYSTERESIS 5V x R1

ASSUMING R4 << R3

MAX696

MAX697

WDI

GND

+5V

WATCHDOG

STROBE

WATCHDOG

DISABLE

VCC

MAX696

MAX697

OSC SEL

OSC IN

GND

+5V

VCC

LOW = INTERNAL

WATCHDOG TIMEOUT

HI = EXTERNAL

WATCHDOG

TIMEOUT

CONNECT FOR

100ms TIMEOUT

WHEN INTERNAL

TIMEOUT IS

SELECTED

CONNECT FOR

1.6s INTERNAL

TIMEOUT

MAX696

MAX697

MAX696/MAX697 Microprocessor Supervisory Circuits

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Table 1. MAX696 and MAX697 Reset Pulse Width and Watchdog Timeout Selections

(Notes 1, 2)

Table 2. Input and Output Status in Battery-Backup Mode

OSC SEL

(Note 3) OSC IN

WATCHDOG TIMEOUT PERIOD RESET TIMEOUT

PERIOD

NORMAL IMMEDIATELY

AFTER RESET

Low External Clock Input 1024 clocks 4096 clocks 512 clocks

Low External Capacitor 400ms/47pF x C 1.6s/47pF x C 200ms/47pF x C

High/Floating Low 100ms 1.6s 50ms

High/Floating Floating 1.6s 1.6s 50ms

I/O STATUS

VBATT, VOUT VBATT is connected to VOUT with an internal MOSFET (MAX696 only).

RESET Logic-low.

RESET Logic-high. The open-circuit output voltage is equal to VOUT.

LOW LINE Logic-low.

BATT ON Logic-high (MAX696 only).

WDI WDI is internally disconnected from its internal pullup and does not source or sink current as long as its input

voltage is between GND and VOUT. The input voltage does not affect supply current.

WDO Logic-high.

PFI The power-fail comparator is turned off and the power-fail input voltage has no effect on the power-fail output.

PFO Logic-low.

CE IN CE IN is internally disconnected from its internal pullup and does not source or sink current as long as its input

voltage is between GND and VOUT. The input voltage does not affect supply current (MAX696 only).

CE OUT Logic-high (MAX697 only).

OSC IN OSC IN is ignored.

OSC SEL OSC SEL is ignored.

VCC Approximately 12µA is drawn from the VBATT input when VCC is between (VBATT + 100mV) and (VBATT -

700mV). The supply current is 1µA maximum when VCC is less than VBATT - 700mV.

Note 1: When the MAX696/MAX697 OSC SEL pin is low, OSC IN can be driven by an external clock signal, or an external

capacitor can be connected between OSC IN and GND. The nominal internal oscillator frequency is 10.24kHz. The

nominal oscillator frequency with external capacitor is fOSC (Hz) = 184,000/COSC (pF).

Note 2: See the Electrical Characteristics table for minimum and maximum timing values.

Note 3: High for the OSC SEL pin should be connected to VOUT, not VCC (on the MAX696).

MAX696/MAX697 Microprocessor Supervisory Circuits

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Devices in PDIP and SO packages are available in both leaded

and lead(Pb)-free packaging. Specify lead free by adding the +

symbol at the end of the part number when ordering. Lead free

not available for CERDIP package.

PART TEMP RANGE PIN-PACKAGE

MAX697C/D 0°C to +70°C Dice

MAX697CPE 0°C to +70°C 16 PDIP

MAX697CWE 0°C to +70°C 16 Wide SO

MAX697EPE -40°C to +85°C 16 PDIP

MAX697EJE -40°C to +85°C 16 CERDIP

MAX697EWE -40°C to +85°C 16 Wide SO

MAX697MJE -55°C to +125°C 16 CERDIP

POWER TO

CMOS RAM

POWER

µP

SYSTEM

VOUT

VBATT

VCC

µP RESET

RESET

LLIN

PFO

WDI I/O

LINE

µP NMI

-5V

PFI

GND

RESET

MAX696

CE IN

VCC

LLIN

N.C. RESET

RESET

TEST

WDO

GND

LOW LINE

OSC SEL

OSC IN

PFI

WDI

TOP VIEW

PFO

CE OUT

MAX697

MAX696/MAX697 Microprocessor Supervisory Circuits

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Typical Operating Circuit

Ordering Information Pin Congurations (continued)

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

16 CERDIP J16-3 21-0045 —

16 PDIP P16+1 21-0043 —

16 Wide SO W16+1 21-0042 90-0107

VCC VCC

LLIN

GND

BATT ON

TEST RESET RESET VBATT

VOUT RESET RESET

WDO WDO

LOW LINE OSC IN OSC

SEL

PFI PFO LOW LINE OSC IN OSC

SEL

PFI PFO

WDI WDI

CE IN

CE OUT

MAX697 MAX696

0.084”

[2.13mm]

0.116”

[2.95mm]

0.084”

[2.13mm]

0.116”

[2.95mm]

MAX696/MAX697 Microprocessor Supervisory Circuits

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Chip Topography

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

45/14 No /V OPNs; removed automotive reference from Applications section 1

57/14 Corrected typos in Figures 4, 5; updated Reset Output section 9, 10

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

MAX696/MAX697 Microprocessor Supervisory Circuits

│

Revision History

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

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MAX696EWE+ MAX696MJE/883B MAX697MJE/883B MAX696CPE+ MAX696CWE+ MAX696CWE+T

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MAX697EWE+T 5962-9204102MEA MAX194AEWE+T 5962-9214101MPA MAX194AEWE+