1
Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
FEATURES
• 2.5V to 28V Dual Input Stepdown
• Output Voltage down to 0.8V
• 6A Output Capability
• Built-in Low RDSON
• Highly Integrated Design, Minimal Components
• 600kHz Fixed-frequency Operation
• UVLO Detects Both Vcc and Vin
• Over Temperature Protection
• Short Circuit Protection with Auto-Restart
• Wide Bandwith Amp Allows Type II or III Compensation
• Programmable Soft Start
• Fast Transient Response
• Asynchronous Start-Up into a Pre-Charged Output
• Small 7mm x 4mm DFN Package
be especially attractive for dual supply, 12V step down with 5V used to power the controller. This lower Vcc voltage
minimizes power dissipation in the part. The SP7652 is designed to provide a fully integrated buck regulator solu-
shutdown and output short circuit protection. The SP7652 is available in the space saving DFN package.
TYPICAL APPLICATION CIRCUIT
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13 14
15
16
17
18
19
20
21
22
23
24
25
26
TOP VIEW
Heatsink Pad 1
Connect to Lx
Heatsink Pad 2
Connect to GND
Heatsink Pad 3
Connect to VIN
P
GND
P
GND
GND
V
FB
COMP
UVIN
GND
SS
V
IN
LX
LX
LX
LX
V
CC
GND
GND
GND
BST
NC
LX
LX
LX
DFN PACKAGE
7mm x 4mm
SP7652
P
GND
V
IN
V
IN
V
IN
Ceramic
X5R 6.3V
5V VCC
RSET
1uF
1.5uH, Irate=8A
C1
22uF
CVCC
1uF
U1
SP7652
1
2
3
4
VFB
5
COMP
6
UVIN
7
8
SS
VIN
10
VIN
11
VIN
12
VIN
13 LX 14
LX 15
LX 16
NC 17
BST 18
20
21
VCC 22
LX 23
LX 24
LX 25
LX 26
CSS
22nF
22pF
3.3V
0-6A
21.5kΩ
D
47uF
Notes:
5V - 20V
VIN
SD101AWS
1. U1 Bottom-Side Layout should have
three contacts isolated from one
VOUT
5.1KΩ100pF
1nF 68.1kΩ
12KΩ
CF1
100pF
5.1Ω
ENABLE
SP7652
Wide Input Voltage Range 6A,
600kHz, Buck Regulator
Notes:
1. U1 bottom-side layout should have
three contacts isolated from one another:
Vin, SWnODE,
2. RSEt= 54.48 (VOut- 0.8V)(
2
Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
ELECTRICAL SPECIFICATIONS
ambcc in + 5V, LX
0.0V, UVIN = 3.0V, CVcc = 1µF, CcOmp = 0.1µF, CSS = 50nF, Typical measured at Vcc = 5V.
The •
Vcc................................................................................................... 7V
Vin .................................................................................................. 30V
Ilx .................................................................................................. 10A
BST ................................................................................................ 35V
LX-BST ...............................................................................-0.3V to 7V
LX ........................................................................................-1V to 30V
All other pins ............................................................-0.3V to Vcc+0.3V
Storage Temperature ...................................................
Power Dissipation ..................................................... Internally Limited
ESD Rating ........................................................................... 2kV HBM
Thermal Resistance Øjc ...........................................................
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the
PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
QUIESCENT CURRENT
Vcc 1.5 3 mA Vfb
Vcc 11 15 mA •
0.2 0.4 mA Vfb
8 12 mA •
PROTECTION: UVLO
Vcc UVLO Start Threshold 4.00 4.25 4.5 V
Vcc UVLO Hysteresis 100 200 300 mV
UVIN Start Threshold 2.3 2.5 2.65 V •
UVIN Hysteresis 200 300 400 mV
UVIN Input Current 1 µA UVIN= 3.0V
ERROR AMPLIFIER REFERENCE
0.800 0.808 V
-
sure Vfb; Vcc =5V,
Over Line and Temperature 0.788 0.800 0.812 V •
6 mA/V
60 dB No Load
COMP Sink Current 150 µA Vfb
COMP Source Current 150 µA Vfb =0.7V, COMP=
2.2V
Vfb Input Bias Current 50 200 nA Vfb = 0.8V
Internal Pole 4 MHz
COMP Clamp 2.5 V Vfb
-2
3
Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
ELECTRICAL SPECIFICATIONS
ambcc in
=0.0V, UVIN = 3.0V, CVcc=1µF, CcOmp=0.1µF, CSS=50nF, Typical measured at Vcc=5V.
PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
Ramp Amplitude 1.1 1.28 V
RAMP Offset 1.1 V Ta
COMP
-2
180 ns •
Maximum Controllable Duty Ratio Maximum Duty Ratio
pulsing begins
Maximum Duty Ratio 100 Valid for 20 cycles
Internal Oscillator Ratio 420 600 720 kHz •
TIMERS: SOFT START
SS Charge Current: 10 µA
SS Discharge Current: 1 mA • Fault Present, SS =
0.2V
PROTECTION: Short Circuit & Thermal
Short Circuit Threshold Voltage 0.2 0.25 0.3 V • Measured VREf
— Vfb
Hiccup Timeout 200 ms Vfb = 0.5V
Number of Allowable Clock Cycles
20 Cycles
0.5 Cycles Vfb = 0.7V
Thermal Shutdown Temperature 145 Vfb = 0.7V
Thermal Recovery Temperature 135
Thermal Hysteresis 10
OUTPUT: POWER STAGE
High Side RDSOn 15 Vcc = 5V ; IOut= 6A
Tamb
Synchronous FET RDSOn 15 Vcc = 5V ; IOut= 6A
Tamb
Maximum Output Current 6 A
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Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
General Overview
mode, synchronous PWM regulator opti-
designed to be especially attractive for split
plane applications utilizing 5V to power
the controller and 3V to 20V for step down
conversion.
The heart of the SP7652 is a wide bandwidth
-
commodate Type II and Type III compensa-
tion schemes. A precision 0.8V reference,
present on the positive terminal of the error
output voltage down to 0.8V via the Vfb pin.
The output of the error
ampli
which is compared to a 1.1V peak-to-peak
ramp, is responsible for trailing edge PWM
control. This voltage ramp and PWM control
logic are governed by the internal oscillator
that accurately sets the PWM frequency to
600kHz.
THEORY OF OPERATION
The SP7652 contains two unique control
features that are very powerful in distributed
applications. First, asynchronous driver con-
trol is enabled during start up, to prohibit the
low side NFET from pulling down the output
until the high side NFET has attempted to
ensures that the low side NFET is periodically
enhanced during extended periods
at
duty cycle. This guarantees the synchronized
refreshing of the BST capacitor during very
large duty cycle ratios.
The SP7652 also contains a number of
valuable protection features. Programmable
UVLO allows the user to set the exact Vin
value at which the conversion voltage can
safely begin down conversion, and an inter-
nal Vcc UVLO ensures that the controller
itself has enough voltage to operate properly.
Other protection features include thermal
shutdown and short-circuit detection. In the
event that either a thermal, short-circuit, or
PIN DESCRIPTION
Pin # Pin Name Description
1-3 PgnD
Out.
5 Vfb
Feedback Voltage and Short Circuit Detection pin. The inverting input of the Error
divider. Whenever VFB drops 0.25V below the positive reference, a short circuit
fault is detected and the IC enters hiccup mode.
6 COMP
pin and either ground or VFB to stabilize the voltage mode loop.
7 UVIN UVLO input for Vin voltage. Connect a resistor divider between Vin and UVin to
set minimum operating voltage.
SS
start rate based on the 10µA source current. The SS pin is held low via a 1mA
10-13 Vin Input connection to the high-side N-channel MOSFET. Place a decoupling capaci-
14-16,23-
26 LX Connect an inductor between this pin and VOut.
17 NC No Connect.
18 BST
High-side driver supply pin. Connect BST to the external boost diode and capaci-
tor as shown in the Typical Application Circuit on page one. High-side driver is
connected between BST and SWN pin.
22 Vcc Input for external 5V bias supply.
5
Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
UVLO fault is detected, the SP7652 is forced
into an idle state where the output drivers are
is attempted.
Soft Start
Soft start is achieved when a power con-
verter ramps up the output voltage while
controlling the magnitude of the input sup-
ply source current. In a modern step down
converter, ramping up the positive terminal
As a result, excess source current can be
the output capacitor.
IVin = COutOutSOft-StaRt
The SP7652 provides the user with the op-
tion to program the soft start rate by tying
selection of this capacitor is based on the
10uA pull up current present at the SS pin
and the 0.8V reference voltage. Therefore,
IVin = COutOut *10µA / (CSS
Under Voltage Lock Out (UVLO)
The SP7652 contains two separate UVLO
comparators to monitor the internal bias
(Vccin
independently. The Vcc UVLO threshold
is internally set to 4.25V, whereas the Vin
UVLO threshold is programmable through
the UVIN pin. When the UVIN pin is
greater than 2.5V, the SP7652 is permit-
ted to start up pending the removal of all
other faults. Both the Vcc and Vin UVLO
comparators have been designed with
hysteresis to prevent noise from resetting
a fault.
Thermal and Short-Circuit Protection
Because the SP7652 is designed to drive
large output current, there is a chance that the
power converter will become too hot. There-
has been included to prevent the IC from
malfunctioning at extreme te
mp
eratures.
A short-circuit detection comparator has
also been included in the SP7652 to protect
against an accidental short at the output
of the power converter. This comparator
constantly monitors the positive and nega-
the Vfb
below the positive reference, a short-circuit
fault is set. Because the SS pin overrides the
internal 0.8V reference during soft start, the
SP7652 is capable of detecting short-circuit
faults throughout the duration of soft start as
well as in regular operation.
Handling of Faults
-
mal, or short-circuit faults, the SP7652 is
forced into an idle state where the SS and
COMP pins are pulled low and the NFETS
are held off. In the event of UVLO fault, the
SP7652 remains in this idle state until the
UVLO fault is removed. Upon the detection
of a thermal or short-circuit fault, an internal
200ms timer is activated. In the event of a
short-circuit fault, a re-start is attempted im-
mediately after the 200ms timeout expires.
Whereas, when a thermal fault is detected,
the 200ms delay continuously recycles and a
re-start cannot be attempted until the thermal
fault is removed and the timer expires.
Error Amplier and Voltage Loop
Since the heart of the SP7652 voltage error
loop is a high performance, wide bandwidth
transconductance amplifier, great care
should be taken to select the optimal compen-
there are many ways to compensate the
voltage loop or to control the COMP pin ex-
ternally. If a simple, single-pole, single-zero
response is desired, then compensation can
a more complex compensation is required,
to run Type III compensation schemes with
adequate gain and phase margins at cross-
THEORY OF OPERATION
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Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
THEORY OF OPERATION
over frequencies greater than 50kHz.
The common mode output of the error am-
voltage ramp has been set between 1.1V and
capability. The voltage loop also includes
two other very important features. One is an
asynchronous startup mode. Basically, the
the high-side NFET has attempted to turn
on or the SS pin has exceeded 1.7V. This
feature prevents the controller from “dragging
down” the output voltage during startup or in
duty cycle timeout that ensures synchronized
refreshing of the BST capacitor at very high
duty ratios. In the event that the high-side
NFET is on for 20 continuous clock cycles,
way through the 21st
to rise for the cycle, in turn refreshing the
BST capacitor.
Power MOSFETs
The SP7652 contains a pair of integrated low
resistance N-MOSFETs designed to drive up
to 6A of output current. Maximum output cur-
rent could be limited by thermal limitations of
a particular application. The SP7652 incorpo-
rates a built-in over-temperature protection
to prevent internal overheating.
GH
Voltage
GL
Voltage
V(V IN)
0V
-0V
-V(Diode) V
V(V IN)+V(V CC )
BST
Voltage
V(V CC )
TIME
SWN
Voltage
VBST
VSWN
V(V CC)
The SP7652 can be set to different output
voltages. The relationship in the following
formula is based on a voltage divider from
the output to the feedback pin VFB, which is
set to an internal reference voltage of 0.80V.
mount size 0603 are recommended.
VOut = 0.80V (R1/R2+1)
=> R2=
Out = 0.80V
setting, simply remove R2 from the board.
Furthermore, one could select the value
of the R1 and R2 combination to meet the
exact output voltage setting by restricting
Setting Output Voltages
R1
{(VOut / 0.8V) -1}
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Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
Inductor Selection
There are many factors to consider in
selecting the inductor including core
material, inductance vs. frequency, cur-
and EMI. In a typical SP7652 circuit, the
inductor is chosen primarily by operat-
ing frequency, saturation current and DC
resistance. Increasing the inductor value
will decrease output voltage ripple, but
degrade transient response. Low induc-
tor values provide the smallest size, but
and require more output capacitance to
smooth out the larger ripple current. The
inductor must be able to handle the peak
current at the switching frequency without
saturating, and the copper resistance in
the winding should be kept as low as pos-
sible to minimize resistive power loss. A
good compromise between size, loss and
cost is to set the inductor ripple current
output current.
The switching frequency and the inductor
operating point determine the inductor value
as follows:
where:
Fs = switching frequency
KR = ratio of the AC inductor ripple current
to the maximum output current
The peak to peak inductor ripple current
is:
Once the required inductor value is selected,
the proper selection of core material is based
-
quirements. The core must be large enough
not to saturate at the peak inductor current
and provide low core loss at the high switch-
ing frequency. Low cost powdered-iron cores
for consideration. Select devices that have
operating data shown up to 1MHz. Ferrite
materials, on the other hand, are more
expensive and have an abrupt saturation
characteristic with the inductance dropping
sharply when the peak design current is
exceeded. Nevertheless, they are preferred
at high switching frequencies because they
present very low core loss and the design
only needs to prevent saturation. In general,
ferrite or molypermalloy materials are bet-
ter choice for all but the most cost sensitive
applications.
Optimizing Efciency
The power dissipated in the inductor is equal
to the sum of the core and copper losses.
To minimize copper losses, the winding
resistance needs to be minimized, but this
usually comes at the expense of a larger
contribution at low output current where the
copper losses are at a minimum, and can
typically be neglected at higher output cur-
rents where the copper losses dominate.
Core loss information is usually available
from the magnetics vendor. Proper inductor
selection can affect the resulting power sup-
The copper loss in the inductor can be cal-
culated using the following equation:
where IL(RMS) is the RMS inductor current
that can be calculated as follows:
L= VOut(Vin(max) - VOut
Vin(max)FS•KR•iOut(max)
Ipp=VOut (Vin(max) - VOut)
Vin(max)•Fs•L
IpEak = iOut(max) + Ipp
2
Pl(cu) = i2l(RmS) RWinDing
Il(RmS) = iOut(max) 1+ 1
32
Ipp
IOut(max)
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Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
Output Capacitor Selection
The required ESR (Equivalent Series Re-
-
tion of the type and quantity of the output
capacitors. The ESR must be small enough
that both the resistive voltage deviation due
to a step change in the load current and
the output ripple voltage do not exceed
the tolerance limits expected on the output
voltage. During an output load transient,
the output capacitor must supply all the ad-
ditional current demanded by the load until
the new value.
In order to maintain VOut, the capacitance
must be large enough so that the output
voltage is held up while the inductor current
ramps up or down to the value correspond-
ing to the new load current. Additionally, the
ESR in the output capacitor causes a step
in the output voltage equal to the current.
Because of the fast transient response and
provided by the SP7652 when exposed to
output load transient, the output capacitor
is typically chosen for ESR, not for capaci-
tance value.
The ESR of the output capacitor, combined
with the inductor ripple current, is typically
the main contributor to output voltage ripple.
The maximum allowable ESR required to
can be calculated by:
RESR VOUT
IPK-PK
where:
out = Peak-to-Peak Output Voltage
Ripple
Ipk-pk = Peak-to-Peak Inductor Ripple Cur-
rent
The total output ripple is a combination of
the ESR and the output capacitance value
and can be calculated as follows:
APPLICATIONS INFORMATION
Icin(RmS)= iOut(max) D(1-D)
Pcin=i2cin(RmS) RESR(cin)
Out =
(
IPP
2 + (IppRESR2
COutFS
FS = Switching Frequency
D = Duty Cycle
COut = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for
ripple current rating, capacitance and voltage
rating. The input capacitor must meet the
ripple current requirement imposed by the
switching current. In continuous conduction
mode, the source current of the high-side
MOSFET is approximately a square wave
of duty cycle VOut/Vin. Most of this current
is supplied by the input bypass capacitors.
The RMS value of input capacitor current is
determined at the maximum output current
and under the assumption that the peak
to peak inductor ripple current is low; it is
given by:
The worse case occurs when the duty cycle
equal to IOut/2.
Select input capacitors with adequate ripple
current rating to ensure reliable operation.
The power dissipated in the input capaci-
tor is:
losses in a converter and hurt the overall
-
age ripple primarily depends on the input
capacitor ESR and capacitance. Ignoring
the inductor ripple current, the input voltage
ripple can be determined by:
Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
tors. However, exercise additional caution
when tantalum capacitors are used. Tantalum
capacitors are known for catastrophic failure
when exposed to surge current, and input
capacitors are prone to such surge current
when power supplies are connected “live”
to low impedance power sources.
Loop Compensation Design
The open loop gain of the whole system can
be divided into the gain of the error ampli-
stage, and feedback resistor divider. In order
to cross over at the selected frequency FCO,
for the attenuation caused by the rest of the
loop at this frequency.
The goal of loop compensation is to manipu-
late loop frequency response such that its
gain crosses over 0db at a slope of -20db/
is to pick the loop crossover frequency.
High crossover frequency is desirable for
the system stability. Crossover frequency
should be higher than the ESR zero but
less than 1/5 of the switching frequency.
The ESR zero is contributed by the ESR
associated with the output capacitors and
can be determined by:
ƒ = 1 .
OUT RESR
The next step is to calculate the complex
ƒ = 1
OUT
When the output capacitors are of a Ceramic
Type, the SP7652 Evaluation Board requires
a Type III compensation circuit to give a phase
of an underdamped resonance of the output
SP7652 Voltage Mode Control Loop with Loop
(SRz2Cz2+1)(SR1Cz3+1) (SR
ESR
C
OUT
+ 1)
[S^2LC
OUT
+S(R
ESR
+R
DC
) C
OUT
+1]
V
IN
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1) V
RAMP_PP
V
OUT
(Volts)
+
_
V
REF
(Volts)
Notes: R
ESR
= Output Capacitor Equivalent Series Resistance.
R
DC
= Output Inductor DC Resistance.
V
RAMP_PP
= SP6132 Internal RA MP Amplitude Peak to Peak V oltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> R
ESR
& R
DC
R
2
V
REF
(R
1
+ R
2
)
or V
OUT
V
FBK
(Volts)
Type III V oltage Loop
Compensation
G
AMP
(s) Gain Block
PWM Stage
G
PWM
Gain
Block
Output Stage
G
OUT
(s) Gain
Block
Voltage Feedback
G
FBK
Gain Block
RESR = Output Capacitor Equivalent Series Resistance
RDC = Output Inductor DC Resistance
RRAMP_PP = SP7652 internal RAMP Amplitude Peak to Peak Voltage
Conditions:
CZ 2 >> Cp1 and R1 >> RZ 3
Output Load Resistance >> RESR and RDC
in=iOut(max) RESR(cin)+ IOut(max) VOut (Vin-VOut)
FScinVin2
The capacitor type suitable for the output ca-
pacitors can also be used for the input capaci-
10
Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
Frequency
(Hz)
Error Amplifier Gain
Bandwidth Product
Condition:
C22 >> CP1, R1 >> RZ3
20 Log (RZ2/R1)
Gain
(dB)
CP1
RZ2
CZ2
-
+6
5
VFB
COMP
+
-0.8V
CF1
VOUT
R1
68.1k, 1% RSET
CZ3
RZ3
RSET =54.48/ (V OUT -0.8) (kΩ)
1/2π
1/2π
1/2π
1/2π
1/2π
11
Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
SP765X Thermal Resistance
The SP765X family has been tested with a
variety of footprint layouts along with differ-
ent copper area and thermal resistance has
been measured. The layouts were done on
4 layer FR4 PCB with the top and bottom
layers using 3oz copper and the power and
ground layers using 1oz copper.
For the Minimum footprint, only about 0.1
used on the top or footprint layer, and this
layer had no vias to connect to the 3 other
layers. For the Medium footprint, about 0.7
used on the top layer, but vias were used
to connect to the other 3 layers. For the
Maximum footprint, about 1.0 square inch
layer and many vias were used to connect
to the 3 other layers.
The results show that only about 0.7 square
layer and vias connecting to the 3 other
layers are needed to get the best thermal
top beyond the 0.7 square inches did not
reduce thermal resistance.
Using a minimum of 0.1 square inches of
no vias connecting to the 3 other layers
than the medium and large footprint layouts,
indicating that space constrained designs
family of ICs. This indicates that a minimum
footprint of 0.1 square inch, if used on a 4 layer
-
tance. This approach is still very worthwhile
if used in a space constrained design.
The following page shows the footprint
data was taken for still air, not with forced
air. If forced air is used, some improvement
in thermal resistance would be seen.
SP765X Thermal Resistance
4 Layer Board:
Top Layer 3ounces Copper
Power Layer 1ounce Copper
Bottom Layer 3ounces Copper
Top Layer: 0.1 square inch
No Vias to other 3 Layers
Top Layer: 0.7 square inch
Vias to other 3 Layers
Top Layer: 1.0 square inch
Vias to other 3 Layers
APPLICATIONS INFORMATION
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Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
13
Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
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Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
15
Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
PACKAGE: 26 PIN DFN
16
Rev F: 11/01/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation
ORDERING INFORMATION
Part Number Temperature Package
SP7652ER ............................................... .................................. 26 Pin 7 X 4 DFN
SP7652ER-L ............................................ ...............
SP7652ER/TR ......................................... .................................. 26 Pin 7 X 4 DFN
SP7652ER-L/TR ...................................... ...............
Bulk Pack minimum quantity is 500.
/TR = Tape and Reel. Pack quantity is 3,000 DFN.
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the applica-
tion or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Sipex Corporation
Headquarters and
Sales Ofce
233 South Hillview Drive
