© 2005 Fairchild Semiconductor Corporation DS500238 www.fairchildsemi.com
October 1999
Revised February 2005
74LCX07 Low Voltage Hex Buffer with Open Drain Outputs
74LCX07
Low Voltage Hex Buffer with Open Drain Outputs
General Descript ion
The LCX07 contains six buffers. The inputs tolerate volt-
ages up to 7V allowing the interface of 5V systems to 3V
systems.
The outputs of th e LCX07 are open drai n and can be co n-
nected to other open drain outputs to implement active
HIGH wire AND or active LOW wire OR functions.
The 74LC X07 is fabricated with advanced CMO S technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
5V tolerant inputs
2.3V to 5.5V VCC specifications pro vided
2.9 ns tPD max (VCC
3.3V), 10
P
A ICC max
Power down high impedance inputs and outputs
24 mA output drive (VCC
3.0V)
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performa nce :
Human body model
!
2000V
Machine model
!
200V
Leadless Pb-Free DQFN package
Ordering Code:
Devices also available in Tape and Reel. Specify by append ing the suffix let t er “X” to the ordering co de.
Note 1: “_NL” indicat es Pb-Fre e pac k age (per JE D EC J -STD-0 20B). Devic e availa ble in Tape and Reel only.
Note 2: DQFN packag e av ailable in Tape and Reel only.
Order Number Package Package Description
Number
74LCX07M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX07MX_NL
(Note 1) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX07SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX07BQX
(Note 2) MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX07MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX07MTCX_NL
(Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
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74LCX07
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
Pad Assignments for DQFN
(Top Throu gh View)
Pin Names Description
AnInputs
OnOutputs
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74LCX07
Absolute Maximum Ratings(Note 3)
Recommended Operating Conditions (Note 5)
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these li mits. The parametric values d efined in the Electrical Ch aracteristics tables are not guaranteed a t the Absolute M aximum Ratings. The Recom-
mende d Operating Cond it ions table will define th e c onditions fo r ac tual de vi c e operation.
Note 4: IO Absolu te Maximu m Rating must be observed.
Note 5: Unused input s m ust be he ld H I GH or LOW. They may not f loat.
DC Electrical Characteristics
Symbol Parameter Value Conditions Units
VCC Supply Voltage
0.5 to
7.0 V
VIDC Input Voltage
0.5 to
7.0 V
VODC Output Voltage
0.5 to
7.0 Output in HIGH or LOW State (Note 4) V
IIK DC Input Diode Current
50 VI
GND mA
IOK DC Output Diode Current
50 VO
GND mA
50 VO
!
VCC
IODC Output Current
r
50 mA
ICC DC Supply Current per Supply Pin
r
100 mA
IGND DC Ground Current per Ground Pin
r
100 mA
TSTG Storage Temperature
65 to
150
q
C
Symbol Parameter Min Max Units
VCC Supply Voltage Operating 2.0 5.5 V
Data Retention 1.5 5.5
VIInput Voltage 05.5V
VOOutput Vol tage 0 5.5 V
IOL Output Curren t VCC
4.5
5.5V
32
mA
VCC
3.0V
3.6V
24
VCC
2.7V
3.0V
12
VCC
2.3V
2.7V
8
TAFree-Air Operating Temperature
40 85
q
C
'
t/
'
V Input Edge Rate, VIN
0.8V2.0V, VCC
3.0V 0 10 ns/V
Symbol Parameter Conditions VCC TA
40
q
C to
85
q
CUnits
(V) Min Max
VIH HIGH Level Input Voltage 2.3
2.7 1.7 V2.7
3.6 2.0
4.5
5.5 0.7 x VCC
VIL LOW Level Input Voltage 2.3
2.7 0.7 V2.7
3.6 0.8
4.5 - 5.5 0.3 x VCC
VOL LOW Level Output Voltage IOL
100
P
A2.3
5.5 0.2
V
IOL
8 mA 2.3 0.6
IOL
12 mA 2.7 0.4
IOL
16 mA 3.0 0.4
IOL
24 mA 3.0 0.55
IOL
32 mA 4.5 0.55
IIInput Leakage Current 0
d
VI
d
5.5V 2.3
5.5
r
5.0
P
A
IOFF Power-Off Leakage Current VI or VO
5.5V 0 10
P
A
ICC Quiescent Supply Current VI
VCC or GND 2.3
5.5 10
P
A
3.6V
d
VI
d
5.5V 2.3
5.5
r
10
'
ICC Increase in ICC per Input VIH
VCC
0.6V 2.3
3.6 500
P
A
4.5
5.5 1 mA
IOHZ Off State Current VO
5.5 2 - 5 .5 10
P
A
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74LCX07
AC Electrical Characteristics
Dynamic Switching Characteristics
Capacitance
Symbol Parameter
TA
40
q
C to
85
q
C, RL
500
:
Units
VCC
5.0V
r
0.5V VCC
3.3V
r
0.3V VCC
2.7V VCC
2.5V
r
0.2V
CL
50 pF CL
50 pF CL
50 pF CL
30 pF
Min Max Min Max Min Max Min Max
tPZL Propagation Delay Time 0.5 3.0 0.8 3.7 1.0 4.4 0.8 3.8 ns
tPLZ 0.5 3.0 0.8 3.7 1.0 4.4 0.8 3.8
Symbol Parameter Conditions VCC TA
25
q
CUnits
(V) Typical
VOLP Quiet Output Dynamic Peak VOL CL
50 pF, VIH
3.3V, VIL
0V 3.3 0.9 V
CL
30 pF, VIH
2.5V, VIL
0V 2.5 0.7
VOLV Quiet Output Dynamic Valley VOL CL
50 pF, VIH
3.3V, VIL
0V 3.3
0.8 V
CL
30 pF, VIH
2.5V, VIL
0V 2.5
0.6
Symbol Parameter Conditions Typical Units
CIN Input Capacitance VCC
Open, VI
0V or VCC 7pF
COUT Output Capacitance VCC
3.3V, VI
0V or VCC 8pF
CPD Power Dissipation Capacitance VCC
3.3V, VI
0V or VCC, f
10 MHz 25 pF
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74LCX07
AC Loading and Waveforms
FIGURE 1. AC Test Circuit
(CL incl udes probe and jig capacitance)
3-STATE Output Low Enable and
Disable Times for Logic trise and tfall
FIGURE 2. Waveforms
(Input Pulse Characteristics; f =1MHz, tr = tf = 3ns)
Test Switch
tPZL, tPLZ
VCC x 2 at VCC
5.0
r
0.5V
6V at VCC
3.3
r
0.3V
VCC x 2 at VCC
2.5
r
0.2V
Symbol VCC
5.0V
r
0.5V 3.3V
r
0.3V 2.7V 2. 5V
r
0.2V
Vmi VCC/2 1.5V 1.5V VCC/2
Vmo VCC/2 1.5V 1.5V VCC/2
VxVOL
0.3V VOL
0.3V VOL
0.3V VOL
0.15V
VyVOH
0.3V VOH
0.3V VOH
0.3V VOH
0.15V
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74LCX07
Tape and Reel Specification
Tape Format for DQ FN
TAPE DIMENSIONS inches (millimeters)
REEL DIMENSIONS inches (millimeters)
Package Tape Number Cavity Cover Tape
Designator Section Cavities Status Status
Leader (Start End) 125 (typ) Empty Sealed
BQX Carrier 2500/3000 Filled Sealed
Trailer (Hub End) 75 (typ) Empty Sealed
Tape SizeABCDNW1W2
12 mm 13.0 0.059 0.512 0.795 7.008 0.488 0.724
(330) (1.50) (13.00) (20.20) (178) (12.4) (18.4)
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74LCX07
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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74LCX07
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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74LCX07
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm
Package Nu mber MLP 014A
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74LCX07 Low Voltage Hex Buffer with Open Drain Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent in any componen t of a life support
device or system whose failure to perform can be rea-
sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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