1
LTC1065
1065fb
■
Clock-Tunable Cutoff Frequency
■
1mV DC Offset (Typical)
■
80dB CMR (Typical)
■
Internal or External Clock
■
50µV
RMS
Clock Feedthrough
■
100:1 Clock-to-Cutoff Frequency Ratio
■
80µV
RMS
Total Wideband Noise
■
0.004% Noise + THD at 2V
RMS
Output Level
■
50kHz Maximum Cutoff Frequency
■
Cascadable for Faster Roll-Off
■
Operates from ±2.375 to ±8V Power Supplies
■
Self-Clocking with 1 RC
■
Available in 8-Pin DIP and 16-Pin SW Packages
The LTC
®
1065 is the first monolithic filter providing both
clock-tunability with low DC output offset and over 12-bit
DC accuracy. The frequency response of the LTC1065
closely approximates a 5th order Bessel polynomial. With
appropriate PCB layout techniques the output DC offset is
typically 1mV and is constant over a wide range of clock
frequencies. With ±5V supplies and ±4V input voltage
range, the CMR of the device is typically 80dB.
The filter cutoff frequency is controlled either by an inter-
nal or external clock. The clock-to-cutoff frequency ratio is
100 : 1. The on-board clock is nearly power supply inde-
pendent and it is programmed via an external RC. The
50µV
RMS
clock feedthrough of the device is considerably
lower than other existing monolithic filters.
The LTC1065 wideband noise is 80µV
RMS
and it can
process large AC input signals with low distortion. With
±7.5V supplies, for instance, the filter handles up to
4V
RMS
(94dB S/N ratio) while the standard 1kHz THD is
below 0.005%; 87dB dynamic range (S/N + THD) is ob-
tained with input levels between 2V
RMS
and 2.5V
RMS
.
The LTC1065 is available in 8-pin miniDIP and 16-pin SW
packages. For a Butterworth response, see LTC1063 data
sheet. The LTC1065 is pin compatible with the LTC1063.
APPLICATIO S
U
TYPICAL APPLICATIO
U
DESCRIPTIO
U
FEATURES
DC Accurate, Clock-Tunable
Linear Phase 5th Order Bessel
Lowpass Filter
3.4kHz Single 5V Supply Bessel Lowpass Filter
■
Audio
■
Strain Gauge Amplifiers
■
Anti-Aliasing Filters
■
Low Level Filtering
■
Digital Voltmeters
■
Smoothing Filters
■
Reconstruction Filters
V
IN
4.53k
13k*
5V
0.1µF
V
OUT
1065 TA01
SELF-CLOCKING SCHEME
*
200pF*
1
2
3
4
8
7
6
5
LTC1065
0.1µF
5V
4.99k
+
1µF
TANT
Frequency Response
FREQUENCY (kHz)
1
GAIN (dB)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 10 100
1065 TA01b
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 4857860.
2
LTC1065
1065fb
PARAMETER CONDITIONS MIN TYP MAX UNITS
Clock-to-Cutoff Frequency Ratio (f
CLK
/f
C
)±2.375V ≤ V
S
≤ ±7.5V 100±0.5
Maximum Clock Frequency (Note 2) V
S
= ±7.5V 5 MHz
V
S
= ±5V 4 MHz
V
S
= ±2.5V 3 MHz
Minimum Clock Frequency (Note 3) ±2.5V ≤ V
S
≤ ±7.5V, T
A
< 85°C30Hz
Input Frequency Range 00.9f
CLK
Filter Gain V
S
= ±5V, f
CLK
= 25kHz, f
C
= 250Hz
f
IN
= 250Hz ● – 3.5 – 3.1 – 2.7 dB
f
IN
= 1kHz ●– 43.0 – 41.0 – 39.0 dB
V
S
= ±5V, f
CLK
= 500kHz, f
C
= 5kHz
f
IN
= 100Hz 0 dB
f
IN
= 1kHz = 0.2f
C
●– 0.215 – 0.175 –0.135 dB
f
IN
= 2.5kHz = 0.5f
C
●– 1.1 –0.972 –0.84 dB
f
IN
= 4kHz = 0.8f
C
●– 2.35 – 2.13 –1.9 dB
f
IN
= 5kHz = f
C
●– 3.35 – 3.1 –2.7 dB
f
IN
= 10kHz = 2f
C
●– 14.5 – 14.15 –13.0 dB
f
IN
= 20kHz = 4f
C
●– 43.0 –41.15 –39.0 dB
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
PACKAGE/ORDER I FOR ATIO
UUW
Total Supply Voltage (V
+
to V
–
) .......................... 16.5V
Power Dissipation............................................. 400mW
Voltage at Any Input .... (V
–
– 0.3V) ≤ V
IN
≤ (V
+
+ 0.3V)
Burn-In Voltage ...................................................... 16V
Storage Temperature Range ................ – 65°C to 150°C
Operating Temperature Range (Note 7)
LTC1065C .............................................. 0°C to 70°C
LTC1065I........................................... –40°C to 85°C
LTC1065M (OBSOLETE).................. – 55°C to 125°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
ORDER PART
NUMBER
LTC1065CN8
LTC1065IN8
LTC1065MJ8
LTC1065CSW
LTC1065ISW
TJMAX = 100°C, θJA = 85°C/W
TOP VIEW
SW PACKAGE
16-LEAD PLASTIC SO WIDE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
VIN
GND
NC
V–
NC
NC
CLK OUT
VOS ADJ
NC
VOUT
NC
V+
NC
NC
CLK IN
ABSOLUTE AXI U RATI GS
W
WW
U
(Note 1)
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C unless otherwise specified.
1
2
3
4
8
7
6
5
TOP VIEW
V
IN
GND
V
–
CLK OUT
V
OS
ADJ
V
OUT
V
+
CLK IN
N8 PACKAGE
8-LEAD PLASTIC DIP
T
JMAX
= 100°C, θ
JA
= 110°C/W (N)
J8 PACKAGE
8-LEAD CERAMIC DIP
T
JMAX
= 150°C, θ
JA
= 100°C/W (J)
OBSOLETE PACKAGE
Consider the N Package for an Alernate Source
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF, Lead Free Tape and Reel: Add #TRPBF, Lead Free Part Marking: http://www.linear.com/leadfree/
3
LTC1065
1065fb
PARAMETER CONDITIONS MIN TYP MAX UNITS
Filter Gain V
S
= ±2.375V, f
CLK
= 500kHz, f
C
= 5kHz
f
IN
= 1kHz ●– 0.225 – 0.185 – 0.145 dB
f
IN
= 2.5kHz ●– 1.1 –1.0 – 0.83 dB
f
IN
= 4kHz ●– 2.35 – 2.15 –1.9 dB
f
IN
= 5kHz ●–3.35 – 3.1 – 2.7 dB
f
IN
= 10kHz ●– 14.5 –14.1 –13.0 dB
Clock Feedthrough ±2.375V ≤ V
S
≤ ±7.5V 50 µV
RMS
Wideband Noise (Note 4) ±2.375V ≤ V
S
≤ ±7.5V, 1Hz < f < f
CLK
80 µV
RMS
THD + Wideband Noise (Note 5) V
S
= ±7.5V, f
C
= 20kHz, f
IN
= 1kHz, – 87 dB
2V
RMS
≤ V
IN
≤ 2.5V
RMS
Filter Output ± DC Swing V
S
= ±2.375V 1.5/– 2.0 1.7/– 2.2 V
●1.3/– 1.8 V
V
S
= ±5V 4.0/– 4.5 4.3/– 4.8 V
●3.8/– 4.3 V
V
S
= ±7.5V 6.5/– 7.0 6.8/– 7.3 V
●6.3/–6.8 V
Input Bias Current 10 nA
Dynamic Input Impedance 800 MΩ
Output DC Offset (Note 6) V
S
= ±2.375V 2 mV
V
S
= ±5V 0 ±5mV
V
S
= ±7.5V – 4 mV
Output DC Offset Drift V
S
= ±2.375V 10 µV/°C
V
S
= ±5V 20 µV/°C
V
S
= ±7.5V 25 µV/°C
Self-Clocking Frequency (f
OSC
) R (Pin 4 to 5) = 20k, C (Pin 5 to GND) = 470pF
V
S
= ±2.375V 99 103 112 kHz
LTC1065C ●95 103 112 kHz
LTC1065M ●92 100 112 kHz
V
S
= ±5V 100 106 112 kHz
LTC1065C ●98 106 114 kHz
LTC1065M ●97 105 114 khz
V
S
= ±7.5V 102 106 114 kHz
LTC1065C ●101 109 116 kHz
LTC1065M ●100 108 116 kHz
External CLK Pin Logic Thresholds V
S
= ±2.375V Min Logical “1” 1.43 V
Max Logical “0” 0.47 V
V
S
= ±5V Min Logical “1” 3 V
Max Logical “0” 1 V
V
S
= ±7.5V Min Logical “1” 4.5 V
Max Logical “0” 1.5 V
Power Supply Current V
S
= ±2.375V, f
CLK
= 500kHz 2.5 4.0 mA
LTC1065C ●5.5 mA
LTC1065M ●6.0 mA
V
S
= ±5V, f
CLK
= 500kHz 5.5 9 mA
LTC1065C ●11 mA
LTC1065M ●12 mA
V
S
= ±7.5V, f
CLK
= 500kHz 7.0 12.0 mA
LTC1065C ●14.5 mA
LTC1065M ●16.0 mA
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C unless otherwise specified.
4
LTC1065
1065fb
INPUT FREQUENCY (kHz)
1
GAIN (dB)
10 100
1065 G06
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
200
AB C
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
E. fCLK = 5MHz
V
IN
= 1.4V
RMS
T
A
= 25°C
E
D
INPUT FREQUENCY (kHz)
1
GAIN (dB)
10 100
1065 G05
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
200
AB C D
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
V
IN
= 1.4V
RMS
T
A
= 25°C
INPUT FREQUENCY (kHz)
1
GAIN (dB)
10 100
1065 G04
B C
VIN = 750mVRMS
TA = 25°C
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
200
A
A. fCLK = 0.5MHz
B. fCLK = 1MHz
C. fCLK = 2MHz
ELECTRICAL C CHARA TERISTICS
Output Offset vs Clock,
Medium Clock RatesSelf-Clocking Frequency vs R
Output Offset vs Clock,
Low Clock Rates
EXTERNAL CLOCK FREQUENCY (kHz)
OUTPUT OFFSET (mV)
5
4
3
2
1
0
–1
–2
–3
–4
–5
1065 G03
500 1000
0
V
S
= ±7.5V
V
S
= ±5V
V
S
= ±2.5V
FREQUENCY (kHz)
R PINS 4 TO 5 (kΩ)
110
100
90
80
70
60
50
40
30
20
10
1065 G01
100 300 500
LTC1065
RC
45
C = 200pF
f
OSC
≅ 1/RC
Gain vs Frequency; VS = ±7.5VGain vs Frequency; VS = ±2.5V Gain vs Frequency; VS = ±5V
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The maximum clock frequency is arbitrarily defined as the
frequency at which the filter AC response exhibits ≥ 1dB of gain peaking.
Note 3: At limited temperature ranges (i.e., T
A
≤ 50°C) the minimum clock
frequency can be as low as 10Hz. The typical minimum clock frequency is
arbitrarily defined as the clock frequency at which the output DC offset
changes by more than 1mV.
Note 4: The wideband noise specification does not include the clock
feedthrough.
Note 5: To properly evaluate the filter’s harmonic distortion an inverting
output buffer is recommended. An output buffer (although recommended)
is not necessarily needed when measuring output DC offset or wideband
noise (see Figure 3).
Note 6: The output DC offset is optimized for ±5V supply. The output DC
offset shifts when the power supplies change; however, this phenomenon
is repeatable and predictable.
Note 7: The LTC1065C is guaranteed to meet the specified performance
from 0°C to 70°C and is designed, characterized and expected to meet
specified performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. The LTC1065I is guaranteed to meet
specified performance from –40°C to 85°C.
EXTERNAL CLOCK FREQUENCY (Hz)
OUTPUT OFFSET (mV)
50
45
40
35
30
25
20
15
10
5
0
1065 G02
10 110 210
A
B
A. T
A
= 25°C
B. T
A
= 85°C
V
S
= ±5V
5
LTC1065
1065fb
TOTAL POWER SUPPLY VOLTAGE (V)
0
POWER SUPPLY CURRENT (mA)
15
12
9
6
3
016
1065 G15
4812 20
610 14 18
2
–40°C
85°C
25°C
INPUT FREQUENCY (kHz)
0
PHASE MISMATCH (±DEG)
0.6
0.5
0.4
0.3
0.2
0.1
0481216
1065 G14
20 2426
10 14 18 22
VS = ± 7.5V
VIN = 1VRMS
fC = 20kHz
fCLK = 2MHz
INPUT FREQUENCY (Hz)
100
PASSBAND GAIN (dB)
1
0
–1
–2
–3
–4
–5
–6
1k 10k 100k
1065 G13
40
0
–40
–80
–120
–160
–200
–240
PHASE (DEG)
±2.5V ≤ V
S
≤ ±7.5V, T
A
= 25°C
B
AAB
PHASE PHASE
f
C
=1kHz
f
CLK
=100kHz
f
C
=10kHz
f
CLK
=1MHz
INPUT (V
RMS
)
0.1
0.001
THD + NOISE (%)
15
1065 G11
0.01
0.1
1
A
B
f
IN
= 1kHz
T
A
= 25°C
A. f
C
= 10kHz, f
CLK
= 1MHz
B. f
C
= 20kHz, f
CLK
= 2MHz
FREQUENCY (kHz)
1
0.001
THD (%)
0.01
0.1
1
10
1065 G12
5
VIN = 2.5VRMS, S/N = 90dB
fC = 10kHz, fCLK = 1MHz
TA = 25°C
FREQUENCY (kHz)
1
0.001
THD (%)
0.01
0.1
1
10
1065 G10
5
VIN = 1.5VRMS
fC = 10kHz, fCLK = 1MHz
TA = 25°C
INPUT (V
RMS
)
0.1
0.001
THD + NOISE (%)
15
1065 G09
0.01
0.1
1
A
B
f
IN
= 1kHz, T
A
= 25°C
A. f
C
= 10kHz, f
CLK
= 1MHz
B. f
C
= 20kHz, f
CLK
= 2MHz
FREQUENCY (kHz)
1
0.001
THD (%)
0.01
0.1
1
2
1065 G08
3 4 5
VIN = 0.75VRMS, S/N = 80dB
fC = 5kHz, fCLK = 500kHz
TA = 25°C
INPUT (V
RMS
)
0.1
0.001
THD + NOISE (%)
15
1065 G07
0.01
0.1
1
A
B
f
IN
= 1kHz, T
A
= 25°C
A. f
C
= 5kHz, f
CLK
= 0.5MHz
B. f
C
= 10kHz, f
CLK
= 1MHz
Passband Gain and Phase
vs Input Frequency
Power Supply Current vs
Power Supply Voltage
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
THD + Noise vs Input Voltage;
VS = Single 5V, AGND = 2V
THD vs Frequency;
VS = Single 5V, AGND = 2V
THD + Noise vs Input Voltage;
VS = ±7.5V
THD vs Frequency; VS = ±5V
Typical Phase Matching
Device to Device
THD vs Frequency;
VS = ±7.5V
THD + Noise vs Input Voltage;
VS = ±5V
6
LTC1065
1065fb
INPUT FREQUENCY (kHz)
0
GROUP DELAY (µs)
45
40
35
30
25
20
15
10
5
0
621
391815
12
V
S
= ±5V
f
C
= 10kHz
1065 G17
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
HORIZONTAL: 0.1ms/DIV, VERTICAL: 2V/DIV
V
S
= ±5V, f
C
= 10kHz, V
IN
= 1kHz ±3V
P
SQUARE WAVE
1065 G16
Transient Response Group Delay
PI FU CTIO S
U
UU
Power Supply Pins (Pins 6, 3, N Package)
The positive and negative supply pin should be bypassed
with a high quality 0.1µF ceramic capacitor. In applications
where the clock pin (5) is externally swept to provide
several cutoff frequencies, the output DC offset variation
is minimized by connecting an additional 1µF solid tanta-
lum capacitor in parallel with the 0.1µF disc ceramic. This
technique was used to generate the graphs of the output
DC offset variation versus clock; they are illustrated in the
Typical Performance Characteristics section.
When the power supply voltage exceeds ±7V, and when
V
–
is applied before V
+
(if V
+
is allowed to go below
ground) connect a signal diode between the positive
supply pin and ground to prevent latch-up (see Typical
Applications).
Ground Pin (Pin 2, N Package)
The ground pin merges the internal analog and digital
ground paths. The potential of the ground pin is the
reference for the internal switched-capacitor resistors,
and the reference for the external clock. The positive input
of the internal op amp is also tied to the ground pin.
For dual supply operation, the ground pin should be
connected to a high quality AC and DC ground. A ground
plane, if possible, should be used. A poor ground will
degrade DC offset and it will increase clock feedthrough,
noise and distortion.
A small amount of AC current flows out of the ground pin
whether or not the internal oscillator is used. The fre-
quency of the ground current equals the frequency of the
clock. The average value of this current is approximately
55µA, 110µA, 170µA for ±2.5V, ±5V and ±7.5V supplies
respectively.
For single supply operation, the ground pin should be
preferably biased at half supply (see Typical Applications).
V
OS
Adjust Pin (Pin 8, N Package)
The V
OS
adjust pin can be used to trim any small amount
of output DC offset voltage or to introduce a desired output
DC level. The DC gain from the V
OS
adjust pin to the filter
output pin equals two.
Any DC voltage applied to this pin will reflect at the output
pin of the filter multiplied by two.
If the V
OS
adjust pin is not used, it should be shorted to the
ground pin. The DC bias current flowing into the V
OS
adjust
pin is typically 10pA.
The V
OS
adjust pin should always be connected to an AC
ground; AC signals applied to this pin will degrade the filter
response.
7
LTC1065
1065fb
CLOCK FREQUENCY (MHz)
1
MAXIMUM LOAD CAPACITANCE (pF )
200
180
160
140
120
100
80
60
40
20
0310
1065 F02
245
678
9
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±7.5V
T
A
= 25°C
PI FU CTIO S
U
UU
Input Pin (Pin 1, N Package)
Pin 1 is the filter input and it is connected to an internal
switched-capacitor resistor. If the input pin is left floating,
the filter output will saturate. The DC input impedance of
pin 1 is very high; with ±5V supplies and 1MHz clock, the
DC input impedance is typically 1GΩ. A resistor R
IN
in
series with the input pin will not alter the value of the filter’s
DC output offset (Figure 1). R
IN
should however, be limited
to a maximum value (Table 1), otherwise the filter’s pass-
band will be affected. Refer to the Applications Information
section for more details.
VIN
VOUT
1065 F01
V–V+
RIN 1
2
3
4
8
7
6
5
LTC1065
fCLK
Figure 1.
Table 1. RIN(MAX) vs Clock and Power Supply
R
IN(MAX)
V
S
= ±7.5V V
S
= ±5V V
S
= ±2.5V
f
CLK
= 4MHz 1.82k – –
f
CLK
= 3MHz 3.01k 2.49k –
f
CLK
= 2MHz 4.32k 3.65k 2.37k
f
CLK
= 1MHz 9.09k 8.25k 7.5k
f
CLK
= 500kHz 17.8k 16.9k 16.9k
f
CLK
= 100kHz 95.3k 90.9k 90.9k
100:1. The high (V
HIGH
) and low (V
LOW
) clock logic
threshold levels are illustrated in Table 2. Square wave
clocks with duty cycles between 30% and 50% are strongly
recommended. Sinewave clocks are not recommended.
Output Pin (Pin 7, N Package)
Pin 7 is the filter output. This pin can typically source over
20mA and sink 2mA. Pin 7 should not drive long coax
cables, otherwise the filter’s total harmonic distortion will
degrade. The maximum load the filter output can drive and
still maintain the distortion levels, shown in the Typical
Performance Characteristics, is 20k.
Clock Input Pin (Pin 5, N Package)
An external clock, when applied to pin 5, tunes the filter
cutoff frequency. The clock-to-cutoff frequency ratio is
Table 2. Clock Pin Threshold Levels
POWER SUPPLY V
HIGH
V
LOW
V
S
= ±2.5V 1.5V 0.5V
V
S
= ±5V 3V 1V
V
S
= ±7.5V 4.5V 1.5V
V
S
= ±8V 4.8V 1.6V
V
S
= 5V, 0V 4V 3V
V
S
= 12V, 0V 9.6V 7.2V
V
S
=15V, 0V 12V 9V
Clock Output Pin (Pin 4, N Package)
Any external clock applied to the clock input pin appears
at the clock output pin. The duty cycle of the clock output
equals the duty cycle of the external clock applied to the
clock input pin. The clock output pin swings to the power
supply rails. When the LTC1065 is used in a self-clocking
mode, the clock of the internal oscillator appears at the
clock output pin with a 30% duty cycle. The clock output
pin can be used to drive other LTC1065s or other ICs. The
maximum capacitance, C
L(MAX)
, the clock output pin can
drive is illustrated in Figure 2.
Figure 2. Maximum Load Capacitance at the Clock Output Pin
8
LTC1065
1065fb
INTERNAL CLOCK FREQUENCY (kHz)
K
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
1065 F04b
100 300 500
V
S
= ±7.5V
V
S
= ±2.5V
f
CLK
= K/RC
C = 200pF
T
A
= 25°C
V
S
= ±5V
200 400
V
IN
R
V
OUT
1065 F04a
C
V
–
V
+
1
2
3
4
8
7
6
5
LTC1065
V
–
50k
V
+
0.1µF
V
OUT
1065 F03
0.1µF
CLOCK IN
–
+
LT1022
20pF
V
IN
50k
8
7
6
5
1
2
3
4
LTC1065
TEST CIRCUIT
Figure 3. Test Circuit for THD
Self-Clocking Operation
The LTC1065 features an internal oscillator which can be
tuned via an external RC. The LTC1065’s internal oscillator
is primarily intended for generation of clock frequencies
below 500kHz. The first curve of the Typical Performance
Characteristics section shows how to quickly choose the
value of the RC for a given frequency. More precisely, the
frequency of the internal oscillator is equal to:
f
CLK
= K/RC
For clock frequencies (f
CLK
) below 100kHz, K equals 1.07.
Figure 4b shows the variation of the parameter K versus
clock frequency and power supply. First choose the de-
sired clock frequency (f
CLK
< 500kHz), then through Figure
4b pick the right value of K, set C = 200pF and solve for R.
Example 1: f
CUTOFF
= 2kHz, f
CLK
= 200kHz, V
S
= ±5V,
T
A
= 25°C, K = 1.0, C = 200pF
then, R = (1.0)/(200kHz × 204pF) = 24.5k.
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Figure 4a. Figure 4b. fCLK vs K
Note a 4pF parasitic capacitance is assumed in parallel
with the external 200pF timing capacitor. Figure 5 shows
the clock frequency variation from – 40°C to 85°C. The
200kHz clock of Example 1 will change by –1.75% at 85°C.
For a limited temperature range, the internal oscillator of
the LTC1065 can be used to generate clock frequencies
above 500kHz (Figures 6 and 7). The data of Figure 6 is
derived from several devices. For a given external (RC)
value, the observed device-to-device clock frequency varia-
tion was ±1% (V
S
= ±5V), and ±1.25% for V
S
= ±2.5V.
Example 2: f
CUTOFF
= 20kHz, f
CLK
= 2MHz, V
S
= ±7.5V,
T
A
= 25°C, C = 10pF
from Figure 6, K = 0.575,
and, R = (0.575)/(2MHz × 14pF) = 20.5k.
9
LTC1065
1065fb
CLOCK FREQUENCY (MHz)
0.5
K
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40 2.5
1065 F07
1.0 1.5 2.0 3.0
f
CLK
= K/RC
C = 10pF
T
A
= 70°C
V
S
= ±7.5V
V
S
= ±2.5V
V
S
= ±5V
CLOCK FREQUENCY (MHz)
0.5
K
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40 2.5
1065 F06
1.0 1.5 2.0 3.0
f
CLK
= K/RC
C = 10pF
T
A
= 25°C
V
S
= ±7.5V
V
S
= ±2.5V
V
S
= ±5V
CLOCK FREQUENCY (kHz)
0
f
CLK
CHANGE NORMALIZED
TO ITS 25°C VALUE (%)
4
3
2
1
0
–1
–2
–3
–4 400
1065 F05
100 200 300 500
C = 200pF T
A
= –40°C
T
A
= 85°C
V
S
= ±2.5V V
S
= ±5V
V
S
= ±7.5V
V
S
= ±7.5V
V
S
= ±5V
V
S
= ±2.5V
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Figure 5. fCLK vs Temperature
Figure 6. fCLK vs K
Figure 7. fCLK vs K
A 4pF parasitic capacitance is assumed in parallel with the
external 10pF capacitor. A ±1% clock frequency variation
from device to device can be expected. The 2MHz clock
frequency designed above will typically drift to 1.74MHz at
70°C (Figure 7).
The internal clock of the LTC1065 can be overridden by an
external clock provided that the external clock source can
drive the timing capacitor C, which is connected from the
clock input pin to ground.
Output Offset
The DC output offset of the LTC1065 is trimmed to
typically less than ±1mV. The trimming is done at V
S
=
±5V. To obtain optimum DC offset performance, appropri-
ate PC layout techniques should be used and the filter IC
should be soldered to the PC board. A socket will degrade
the output DC offset by typically 1mV. The output DC offset
is sensitive to the coupling of the clock output pin 4 (N
package) to the negative power supply pin 3 (N package).
The negative supply pin should be well decoupled. When
the surface mount package is used, all NC pins should be
grounded. When the output DC voltage is measured with
a voltmeter, the filter output pin should be buffered. Long
test leads should be avoided.
With fixed power supplies, the output DC offset should not
change by more than ±100µV over 10Hz to 1MHz clock
frequency variation. When the filter clock frequency is
fixed, the output DC offset will typically change by –4mV
(2mV) when the power supply varies from ±5V to ±7.5V
(±2.5V). See Typical Performance Characteristics.
Common Mode Rejection
The common mode rejection is defined as the change of
the output DC offset with respect to the DC change of the
input voltage applied to the filter.
CMR = 20log (∆V
OS OUT
/∆V
IN
)(dB)
Table 3 illustrates the common mode rejection for three
power supplies and three temperatures. The common
mode rejection improves if the output offset is adjusted to
approximately 0V. The output offset can be adjusted via
pin 8 (N package). See Typical Applications.
10
LTC1065
1065fb
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Table 3. CMR Data, fCLK = 100kHz
25°C
POWER SUPPLY ∆V
IN
–40°C25°C85°C(V
OS
Nulled)
±2.5V ±1.8V 84dB 83dB 80dB 83dB
±5V ±4V 82dB 78dB 77dB 78dB
±7.5V ±6V 80dB 77dB 76dB 80dB
5mV/DIV
2µs/DIV
1065F08
f
CLK
= 100kHz, f
C
= 1kHz, V
S
= ±5V, 1MHz SCOPE BW
Figure 8. LTC1065 Output Clock Feedthrough + Noise
0.5mV/DIV
2µs/DIV
1063 F09
f
CLK
= 100kHz, f
C
= 1kHz, V
S
= ±5V, 1MHz SCOPE BW
Figure 9. LTC1065 Output Clock Feedthrough + Noise
The above data is valid for clock frequencies up to 800kHz, 900kHz, 1MHz, for
V
S
= ±2.5V, ±5V, ±7.5V respectively.
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics which are present at the
filter’s output pin. The clock feedthrough is tested with the
filter input grounded and it depends on the quality of the
PC board layout and power supply decoupling. Any para-
sitic switching transients during the rise and fall of the
incoming clock, are not part of the clock feedthrough
specifications; their amplitude strongly depends on scope
probing techniques as well as ground quality and power
supply bypassing. For a power supply V
S
= ±5V, the clock
feedthrough of the LTC1065 is 50µV
RMS
; for V
S
= ±7.5V,
the clock feedthrough approaches 75µV
RMS
. Figures 8
and 9 show a typical scope photo of the LTC1065 output
pin when the input pin is grounded. The filter cutoff
frequency was 1kHz, while scope bandwidth was chosen
to be 1MHz so that switching transients above the 100kHz
clock frequency would show.
Wideband Noise
The wideband noise data is used to determine the operat-
ing signal-to-noise ratio at a given distortion level. The
wideband noise (µV
RMS
) is nearly independent of the value
of the clock frequency and excludes the clock feedthrough.
The LTC1065’s typical wideband noise is 80µV
RMS
. Figure
9 shows the same scope photo as Figure 8 but with a more
sensitive vertical scale. The clock feedthrough is imbed-
ded in the filter’s wideband noise. The peak-to-peak wide-
band noise of the filter can be clearly seen; it is approxi-
mately 420µV
P-P
. Note that 420µV
P-P
equals the 80µV
RMS
wideband noise of the part multiplied by a crest factor
of 5.25.
Aliasing
Aliasing is an inherent phenomenon of sampled data
filters. It primarily occurs when the frequency of an input
signal approaches the sampling frequency. For the
LTC1065, an input signal whose frequency is in the range
of f
CLK
±6% will generate an alias signal into the filter’s
passband and stopband. Table 4 shows details.
Example: LTC1065, f
CLK
= 20kHz, f
C
= 200kHz,
f
IN
= (19.6kHz, 100mV
RMS
)
f
ALIAS
= (400Hz, 3.16mV
RMS
)
11
LTC1065
1065fb
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An input RC can be used to attenuate incoming signals
close to the filter clock frequency (Figure 10). A Bessel
passband response will be maintained if the value of the
input resistor follows Table 1.
Table 4. Aliasing Data
INPUT FREQUENCY OUTPUT FREQUENCY
0.9995 f
CLK
0.0005 f
CLK
–0.01 dB
0.995 f
CLK
0.005 f
CLK
–0.98 dB
0.99 f
CLK
0.01 f
CLK
–3.13 dB
0.9875 f
CLK
0.0125 f
CLK
–4.79 dB
0.985 f
CLK
0.015 f
CLK
– 7.21 dB
0.9825 f
CLK
0.0175 f
CLK
– 10.43 dB
0.98 f
CLK
0.02 f
CLK
– 14.14 dB
0.975 f
CLK
0.025 f
CLK
– 21.84 dB
0.97 f
CLK
0.03 f
CLK
– 28.98 dB
0.965 f
CLK
0.035 f
CLK
– 35.31 dB
0.96 f
CLK
0.04 f
CLK
– 40.94 dB
0.955 f
CLK
0.045 f
CLK
– 45.96 dB
0.95 f
CLK
0.05 f
CLK
– 50.46 dB
0.94 f
CLK
0.06 f
CLK
– 58.29 dB
0.93 f
CLK
0.07 f
CLK
– 64.90 dB
0.9 f
CLK
0.1 f
CLK
–80.20 dB
OUTPUT AMPLITUDE
REFERENCED TO
INPUT SIGNAL
VIN
VOUT
1065 F10
C
V–V+
R
0.1µF
1
2
3
4
8
7
6
5
LTC1065
0.1µF
fCLK
20 102πRC
≤≤
1fCLK
fCLK
Figure 10. Adding an Input Anti-Aliasing RC
12
LTC1065
1065fb
VIN
–5V
R
5V
0.1µF
VOUT
1065 TA03
1
2
3
4
8
7
6
5
LTC1065
C
1
2
3
4
8
7
6
5
LTC1065
–5V 5V
0.1µF
0.1µF
0.1µF
VIN
VOUT
VIN
–5V
R
5V
0.1µF
VOUT
1065 TA02
1
2
3
4
8
7
6
5
LTC1065
C
1
2
3
4
8
7
6
5
LTC1065
–5V 5V
0.1µF
0.1µF
0.1µF
fC ≅ (1/RC)(1/100)
WIDEBAND NOISE = 110µVRMS
ATTENUATION AT f = 2fC = 60dB
Cascading Two LTC1065s for Steeper Roll-Off Sharing Clock for Multichannel Applications
TYPICAL APPLICATIO S
U
13
LTC1065
1065fb
J8 0801
.014 – .026
(0.360 – 0.660)
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.125
3.175
MIN
.100
(2.54)
BSC
.300 BSC
(7.62 BSC)
.008 – .018
(0.203 – 0.457) 0° – 15°
.005
(0.127)
MIN
.405
(10.287)
MAX
.220 – .310
(5.588 – 7.874)
1234
87
65
.025
(0.635)
RAD TYP
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
CORNER LEADS OPTION
(4 PLCS)
.045 – .065
(1.143 – 1.651)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
PACKAGE DESCRIPTIO
U
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
OBSOLETE PACKAGE
14
LTC1065
1065fb
N8 1002
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.020
(0.508)
MIN
.018 ± .003
(0.457 ± 0.076)
.120
(3.048)
MIN
12 34
87 65
.255 ± .015*
(6.477 ± 0.381)
.400*
(10.160)
MAX
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
N Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
PACKAGE DESCRIPTIO
U
15
LTC1065
1065fb
SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
S16 (WIDE) 0502
NOTE 3
.398 – .413
(10.109 – 10.490)
NOTE 4
16 15 14 13 12 11 10 9
1
N
2345678
N/2
.394 – .419
(10.007 – 10.643)
.037 – .045
(0.940 – 1.143)
.004 – .012
(0.102 – 0.305)
.093 – .104
(2.362 – 2.642)
.050
(1.270)
BSC .014 – .019
(0.356 – 0.482)
TYP
0° – 8° TYP
NOTE 3
.009 – .013
(0.229 – 0.330)
.005
(0.127)
RAD MIN
.016 – .050
(0.406 – 1.270)
.291 – .299
(7.391 – 7.595)
NOTE 4
× 45°
.010 – .029
(0.254 – 0.737)
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.420
MIN
.325 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
N
1 2 3 N/2
.050 BSC
.030 ±.005
TYP
16
LTC1065
1065fb
TYPICAL APPLICATIO S
U
VIN
5V
13k
5V
0.1µF
VOUT
1065 TA04
0.1µF
200pF
1
2
3
4
8
7
6
5
LTC1065
4.53k
+
4.99k
1µF
TANT
V
IN
V
–
–7.5V
V
+
7.5V
0.1µF
1
2
3
4
8
7
6
5
LTC1065
f
CLK
0.1µF
7.5V
1µF
TANT
+
1065 TA05
V
OUT
10k
≅2.5mV
LT1009
10k
*
* OPTIONAL, 1N4148
Adjusting VOS(OUT) for
±7.5 Supply Operation
Single 5V Supply Operation (fC = 3.4kHz)
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1063 Clock Tunable, 5th Order Bessel Low Pass Internal or External Clock, 1mV
DC
Offset, Cascadable
LTC1064-1/2/3/4/7 Clock Tunable, 8th Order Low Pass Elliptic, Butterworth, Bessel, Cauer or Linear Phase
LTC1164-5/6/7 Clock Tunable, Low Power, 8th Order Low Pass Butterworth, Bessel or Elliptic, F
O
Max = 20KHz
LTC1264-7 Clock Tunable, 8th Order Low Pass Flat Group Delay, F
O
Max = 200KHz, Steeper Roll-Off than Bessel
LTC1569-6/7 Clock Tunable, 10th Order Low Pass Internal or External Clock, Root Raised Cosine Response
© LINEAR TECHNOLOGY CORPORATION 1993
LT/LT 0705 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
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