5962F9659503QXX - Aeroflex / Colorado Springs

UT54ACTS541E

Octal Buffers & Line Drivers, Three-State Outputs

October, 2008

www.aeroflex.com/Logic

FEATURES

• Three-state outputs drive bus lines or buffer memory address

registers

• 0.6μm CRH CMOS Process

- Latchup immune

• High speed

• Low power consumption

• Wide operating power suppl y from 3.0V to 5.5V

• Available QML Q or V processes

• 20-lead flatpack

DESCRIPTION

The UT54ACTS541E is a non-inverting octal buffer and line

driver which improves the perform ance and density of three-

state memory address drivers, clock drivers, and bus-oriented

receivers and transmitters.

The device is characterized over full HiRel temperature range

of -55°C to +125°C.

PINOUT

20-Lead Flatpack

Top View

FUNCTION TABLE

LOGIC SYMBOL

VDD

A7 Y6

A8 Y7

VSS Y8

120

219

318

417

516

615

714

813

912

10 11

INPUTS OUTPUT

1G 2G An Yn

LLLL

L L H H

H X X Z

X H X Z

(1) EN

(2)

A1 (3)

A2 (4)

(18) Y1

(16)

(17) Y2

Note:

1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC

Publication 617-12.

A3 (5)

A4 (6)

A5 (7)

(13) Y6

(14) Y5

(15) Y4

(8)

A7 (9)

A8 (11) Y8

(12) Y7

(19)

LOGIC DIAGRAM

OPERATIONAL ENVIRONMENT1

Notes:

1. Logic will not latchup during radiation exposure within the limits defined in the table.

2. Device storage elements are immune to SEU affects.

PARAMETER LIMIT UNITS

Total Dose 1.0E6 rads(Si)

SEU Threshold 280 MeV-cm2/mg

SEL Threshold 120 MeV-cm2/mg

Neutron Fluence 1.0E14 n/cm2

A1A2A3A4A5

(1)(2)(3)(4)(5)(6)

(7)

(9)

(19)

(8)

Y1Y2Y3Y4Y5

Y8 Y7

(18)(17)(16)(15)(14)

(13)

(11) (12)

ABSOLUTE MAXIMUM RATINGS1

Note:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only , functional operation of the device at these

or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMIT UNITS

VDD Supply voltage -0.3 to 7.0 V

VI/O Voltage any pin -.3 to VDD +.3 V

TSTG Storage Temperature range -65 to +150 °C

TJMaximum junction temperature +175 °C

TLS Lead temperature (soldering 5 seconds) +300 °C

ΘJC Thermal resistance junction to case 20 °C/W

IIDC input current ±10 mA

PDMaximum power dissipation 1 W

SYMBOL PARAMETER LIMIT UNITS

VDD Supply voltage 3.0 to 5.5 V

VIN Input voltage any pin 0 to VDD V

TCTemperature range -55 to +125 °C

DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS541E7 ( VDD = 3.0V to 5.5V; VSS = 0V6; -55°C < TC < +125°C)

Notes:

1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -

50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above spec ified range, but ar e

guaranteed to VIH(min) and VIL(max).

2. Supplied as a design limit but not guaranteed or tested.

3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/

MHz.

4. Not more than one output may be shorted at a time for maximum duration of one second.

5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at

frequency of 1MHz and a signal amplitude of 50mV rms maximum.

6. Maximum allowable relative shift equals 50mV.

7. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.

8. Power does not include power contribution of any TTL output sink cu rrent

9. Power dissipation specified per switching output.

10. This value is guaranteed based on characterization data, but not tested.

SYMBOL Description CONDITION VDD MIN MAX UNIT

VIL Low-level input voltage 13.0V 0.8 V

5.5V 0.8

VIH High-level input voltage 13.0V 2.0 V

5.5V 2.75

IIN Input leakage current VIN = VDD or VSS 5.5V -1 1μA

VOL Low-level output voltage 3IOL = 8mA 3.0V 0.4 V

IOL = 12mA 4.5V 0.4 V

VOH High-level output voltage 3IOH = -8mA 3.0V 2.4 V

IOH= -12mA 4.5V 3.15 V

IOS Short-circuit output current 2 ,4 VO = VDD and VSS 3.0V -150 150 mA

5.5V -300 300

IOL Low level output current10 VIN = VDD or VSS

VOL = 0.4V

3.0V 8mA

5.5V 12

IOH High level output current10 VIN = VDD or VSS

VOH = VDD-0.4V

3.0V -8 mA

5.5V -12

Ptotal Power dissipatio n 2, 8 ,9 CL = 50pF 5.5V

3.0V

2.1

0.84 mW/

MHz

IDDQ Quiescent Supply Current VIN = VDD or VSS 5.5V 10 μA

ΔIDDQ Quiescent Supply Current Delta For input under test

VIN = VDD - 2.1V

For all other inputs

VIN = VDD or VSS

5.5V 1.6 mA

CIN Input capacitance 5ƒ = 1MHz 0V 15 pF

COUT Output capacitance 5 ƒ = 1MHz 0V 15 pF

AC ELECTRICAL CHARACTERIST ICS FOR THE UT54 ACTS541 E 2

(VDD = 3.0V to 5.5V; VSS = 0V 1, -55°C < TC < +125°C)

Notes:

1. Maximum allowable relative shift equals 50mV.

2. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.

SYMBOL PARAMETER CONDITION VDD MINIMUM MAXIMUM UNIT

tPLH An to Yn CL = 30pF 3.0V & 3.6V 111 ns

4.5V & 5.5V 1 8

CL = 50pF 3.0V & 3.6V 115 ns

4.5V & 5.5V 111

tPHL An to Yn CL = 30pF 3.0V & 3.6V 114 ns

4.5V & 5.5V 110

CL = 50pF 3.0V & 3.6V 118 ns

4.5V & 5.5V 114

tPZH G low to Yn active CL = 30pF 3.0V & 3.6V 215 ns

4.5V & 5.5V 211

CL = 50pF 3.0V & 3.6V 219 ns

4.5V & 5.5V 215

tPZL G low to Yn active CL = 30pF 3.0V & 3.6V 214 ns

4.5V & 5.5V 210

CL = 50pF 3.0V & 3.6V 218 ns

4.5V & 5.5V 214

tPHZ G low to Yn active CL = 30pF 3.0V & 3.6V 113 ns

4.5V & 5.5V 1 9

CL = 50pF 3.0V & 3.6V 217 ns

4.5V & 5.5V 213

tPLZ G low to Yn active CL = 30pF 3.0V & 3.6V 212 ns

4.5V & 5.5V 2 8

CL = 50pF 3.0V & 3.6V 216 ns

4.5V & 5.5V 212

Packaging

Ordering Information: UT54ACTS541E: SMD

Drawing Number:

96595 = UT54ACTS541E

Device Type:

02 = 1 rad(Si)/sec

Package Type:

X = 20-lead ceramic bottom-brazed dual-in-line Flatpack

Lead Finish: (Notes 1 & 2)

A = Solder

C = Gold

X = Optional

5962 ***** ** * * **

Total Dose: (Note 3 and 4)

R = 1E5 rads(Si)

F = 3E5 rads(Si)

G = 5E5 rads(Si)

H = 1E6 rads(Si)

03 = 50 to 300 rads(Si)/sec

Class Designator:

Q = QML Class Q

V = QML Class V

Notes:

1. Lead fini sh (A,C, or X) must be specified.

2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For proto type inquiries, contact

factory.

4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test

Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(S i), and 5E5

rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A.

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without notice. Consult Aeroflex or an authorized sales

representative to verify that the information in this data sheet

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Aeroflex Colorado Springs - Datasheet Definition

Advanced Datasheet - Product In Development

Preliminary Datasheet - Shipping Prototype

Datasheet - Shipping QML & Reduced HiRel