Rev. 0.1 / Apr. 2013 1
8Gb DDR3 SDRAM
8Gb DDR3 SDRAM
(Dual Die Package)
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TQ8G43AMR-xxC
H5TQ8G83AMR-xxC
H5TQ8G63AMR-xxC
* SK hynix reserves the right to change products or specifications without notice.
Rev. 0.1 / Apr 2013 2
Revision History
Revision No. History Draft Date Remark
0.1 Initial Release Apr. 2013
Rev. 0.1 / Apr 2013 3
Description
The H5TQ8G43AMR-xxC, H5TQ8G83AMR-xxC and H5TQ8G63AMR-xxC are a 8Gb normal power Double
Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires
large memory density and high bandwidth and normal power operation at 1.5V.
SK hynix 8Gb DDR3 SDRAMs off er fully sync hronous operations r eferenc ed to both rising and f alling edges
of the clock. While all addresses and control inputs are latched on the rising edges of the CK (f alling edges
of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of
it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS tr ansition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• Programmable CAS laten cy 5, 6, 7, 8, 9, 10, 11 and 13
supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7 , 8, 9,
10
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
- 7 .8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 o nly)
• Write Levelization supported
• 8 bit pre-fetch
• This product in compliance with the RoHS directive.
Rev. 0.1 / Apr 2013 4
ORDERING INFORMATION
* xx means Speed Bin Grade
OPERATING FREQUENCY
Part No. Configuration Package
H5TQ8G43AMR-*xxC 2G x 4 78ball FBGA
H5TQ8G83AMR-*xxC 1G x 8
H5TQ8G63AMR-*xxC 512M x 16 96ball FBGA
Grade Frequency [MHz] Remark
CL5 CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13
-G7 667 800 1066 1066
-H9 667 800 1066 1066 1333 1333
-PB 667 800 1066 1066 1333 1333 1600
-RD 800 1066 1066 1333 1333 1600 1866
Rev. 0.1 / Apr 2013 5
Package Ballout/Mechanical Dimension
x4 Package Ball out (Top view): 78ball FBGA Package
Note: NF (No Function) - This is applied to balls only used in x4 configuration.
1 2 3 4 5 6 7 8 9
AVSS VDD NC NF VSS VDD A
BVSS VSSQ DQ0 DM VSSQ VDDQ B
CVDDQ DQ2 DQS DQ1 DQ3 VSSQ C
DVSSQ NF DQS VDD VSS VSSQ D
EVREFDQ VDDQ NF NF NF VDDQ E
FODT1 VSS RAS CK VSS CKE1 F
GODT0 VDD CAS CK VDD CKE0 G
HCS1 CS0 WE A10/AP ZQ0 ZQ1 H
JVSS BA0 BA2 A15 VREFCA VSS J
KVDD A3 A0 A12/BC BA1 VDD K
LVSS A5 A2 A1 A4 VSS L
MVDD A7 A9 A11 A6 VDD M
NVSS RESET A13 A14 A8 VSS N
1 2 3 4 5 6 7 8 9
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Populated ball
Ball not populated
2789
(Top View: See the balls through the Package)
3
Rev. 0.1 / Apr 2013 6
x8 Package Ball out (Top view): 78ball FBGA Package
1 2 3 4 5 6 7 8 9
AVSS VDD NC NF/TDQS VSS VDD A
BVSS VSSQ DQ0 DM/TDQS VSSQ VDDQ B
CVDDQ DQ2 DQS DQ1 DQ3 VSSQ C
DVSSQ DQ6 DQS VDD VSS VSSQ D
EVREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ E
FODT1 VSS RAS CK VSS CKE1 F
GODT0 VDD CAS CK VDD CKE0 G
HCS1 CS0 WE A10/AP ZQ0 ZQ1 H
JVSS BA0 BA2 A15 VREFCA VSS J
KVDD A3 A0 A12/BC BA1 VDD K
LVSS A5 A2 A1 A4 VSS L
MVDD A7 A9 A11 A6 VDD M
NVSS RESET A13 A14 A8 VSS N
1 2 3 4 5 6 7 8 9
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Populated ball
Ball not populated
2789
(Top View: See the balls through the Package)
3
Rev. 0.1 / Apr 2013 7
x16 Package Ball out (Top view): 96bal l FBG A Pa ckage
1 2 3 4 5 6 7 8 9
AVDDQ DQU5 DQU7 DQU4 VDDQ VSS A
BVSSQ VDD VSS DQSU DQU6 VSSQ B
CVDDQ DQU3 DQU1 DQSU DQU2 VDDQ C
DVSSQ VDDQ DMU DQU0 VSSQ VDD D
EVSS VSSQ DQL0 DML VSSQ VDDQ E
FVDDQ DQL2 DQSL DQL1 DQL3 VSSQ F
GVSSQ DQL6 DQSL VDD VSS VSSQ G
HVREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ H
JODT1 VSS RAS CK VSS CKE1 J
KODT0 VDD CAS CK VDD CKE0 K
LCS1 CS0 WE A10/AP ZQ0 ZQ1 L
MVSS BA0 BA2 NC VREFCA VSS M
NVDD A3 A0 A12/BC BA1 VDD N
PVSS A5 A2 A1 A4 VSS P
RVDD A7 A9 A11 A6 VDD R
TVSS RESET A13 A14 A8 VSS T
1 2 3 4 5 6 7 8 9
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Populated ball
Ball not populated
2789
(Top View: See the balls through the Package)
3
P
R
T
Rev. 0.1 / Apr 2013 8
Pin Functional Description
Symbol Type Function
CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK.
CKE, (CKE0),
(CKE1) Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any
bank).
CKE is asynchronous for Self-Refresh exit. Af ter VREFCA and VREFDQ have become stable
during the power on and initialization sequence, they must be maintained during all
operations (including Self-Refresh). CKE must be maintained high throughout read and
write accesses. Input buff ers, excluding CK, CK, ODT and CKE, are disabled during power-
down. Input buffers, excluding CKE, are disabled during Self-Refresh.
CS, (CS0),
(CS1), (CS2),
(CS3) Input Chip Select: All commands are masked when CS is registered HIGH.
CS provides for external Rank selection on systems with multiple Ranks.
CS is considered part of the command code.
ODT, (ODT0),
(ODT1) Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS ,
NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x4/x8
configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU, DQSL,
DQSL, DMU, and DML signal. The ODT pin will be ignor ed if MR1 is programmed to disa ble
ODT.
RAS.
CAS. WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM, (DMU),
(DML) Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a Write acce ss. DM is sampled
on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by
Mode Register A11 setting in MR1.
BA0 - BA2 Input Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, W rite or Precharge
command is being applied. Bank address also determine s if the mode register or extended
mode register is to be accessed during a MRS cycle.
A0 - A15 Input
Address Inputs: Pro vide the row address f or Active comma nds and the column address f or
Read/Write commands to select one location out of the memory array in the respective
bank. (A10/AP and A12/BC have additional functions, see below).
The address inputs also prov ide the op-code during Mode Register Set commands.
A10 / AP Input
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be perform ed to the accessed bank after the R ead/W rite oper ation.
(HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank
addresses.
A12 / BC Input Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst
chop (on-the-fly) will be performed.
(HIGH, no burst chop; LOW: burst chopped). See command truth table for details.
Rev. 0.1 / Apr 2013 9
RESET Input
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when
RESET is HIGH. RESET must be HIGH during normal operation.
RESET is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD, i.e.
1.20V for DC high and 0.30V for DC low.
DQ Input /
Output Data Input/ Output: Bi-directional data bus.
DQU, DQL,
DQS, DQS,
DQSU, DQSU,
DQSL, DQSL
Input /
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. The data strobe DQS , DQSL, and DQSU are paired with diff erential
signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the
system during reads and writes. DDR3 SDRAM supports differential data strobe only and
does not support single-ended.
TDQS, TDQS Output
Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via
Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance
function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11
= 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/x16
DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.
NC No Connect: No internal electrical connection is present.
NF No Function
VDDQ Supply DQ Power Supply: 1.35 V +0.100/- 0.067 V
VSSQ Supply DQ Ground
VDD Supply Power Supply: 1.35 V +0.100/- 0.067 V
VSS Supply Ground
VREFDQ Supply Reference volt age for DQ
VREFCA Supply Reference voltage for CA
ZQ Supply Reference Pin for ZQ calibration
Note:
Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination.
Symbol Type Function
Rev. 0.1 / Apr 2013 10
ROW AND COLUMN ADDRESS TABLE
8Gb
Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers
when an ACTIVE command is registered. Page size is per bank, calculated as follows:
page size = 2 COLBITS * ORG 8
where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
Configuration 2Gb x 4 1Gb x 8 512Mb x 16
# of Banks 8 8 8
Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2
Auto precharge A10/AP A10/AP A10/AP
BL switch on the fly A12/BC A12/BC A12/BC
Row Address A0 - A15 A0 - A15 A0 - A14
Column Address A0 - A9,A11 A0 - A9 A0 - A9
Page si ze 11 KB 1 KB 2 KB
Rev. 0.1 / Apr 2013 11
x8 Package pinout and addressing
x16 Package pinout and addressing
ODT
CKE
ZQ
CS
DQ 0-7
DM/TDQS,TDQS
DQS,DQS
CK,CK,CA
ODT0
CKE0
ZQ0
CS0
DQ 0-7
CK,CK,RAS,CAS,WE,An,BAn
DM/TDQS,TDQS
DQS,DQS
ODT
CKE
ZQ
CS
DQ 0-7
DM/TDQS,TDQS
DQS,DQS
CK,CK,CA
ODT1
CKE1
ZQ1
CS1
4Gb x 8
DDR3L
4Gb x 8
DDR3L
ODT
CKE
ZQ
CS
DQ 0-15
DQSU,DQSU
DQSL,DQSL
CK,CK,CA
ODT0
CKE0
ZQ0
CS0
DQ 0-15
CK,CK,RAS,CAS,WE,An,BAn
DQSU,DQSU
DQSL,DQSL
ODT
CKE
ZQ
CS
DQ 0-15
DQSU,DQSU
DQSL,DQSL
CK,CK,CA
ODT1
CKE1
ZQ1
CS1
4Gb x 16
DDR3L
4Gb x 16
DDR3L
Rev. 0.1 / Apr 2013 12
Absolute Maximum Ratings
Absolute Maximum DC Ratings
DRAM Component Operating Temperature Range
Absolute Maximum DC Ratings
Symbol Parameter Rating Units Notes
VDD Voltage on VDD pin relative to Vss - 0.4 V ~ 1.80 V V 1,3
VDDQ Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.80 V V 1,3
VIN, VOUT Voltage on any pin relative to Vss - 0.4 V ~ 1.80 V V 1
TSTG Storage Temperature -55 to +100 oC1, 2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Expo sure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
Temperature Range
Symbol Parameter Rating Units Notes
TOPER Normal Operating Te mperature Ra nge 0 to 85 oC 1,2
Extended Temperature Range (Optional) 85 to 95 oC1,3
Notes:
1. Operating Temper ature T OPER is the case surf ace temperat ure on the center / top side of the DRAM. F or measure-
ment conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefor e reducing the Refresh interv al tREFI to 3.9 µs. It is
also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self -R efresh oper ation is require d in the Extended Temperature Range, then it is mandatory to use the Man -
ual Self-Refresh mode with Extended Temperature Ra nge capability (MR2 A6 = 0b and MR2 A7 = 1b). DDR3
SDRAMs support Extended Temperature Range and please refer to component datasheet and/or the DIMM
SPD for tREFI requirements in the Extended Temperature Range.
Rev. 0.1 / Apr 2013 13
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions
Symbol Parameter Rating Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.425 1.500 1.575 V 1,2
VDDQ Supply Voltage for Output 1.425 1.500 1.575 V 1,2
Notes:
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
Rev. 0.1 / Apr 2013 14
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls
of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under t est tied together. An y IDD current is not included in IDDQ cur -
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
• ”0” and “LOW” is defined as VIN <= VILAC(max).
• ”1” and “HIGH” is defined as VIN >= VIHAC(max).
• “MID_LEVEL” is defined as inputs are VREF = VDD/2.
• Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD and IDDQ Measurement Conditions are described in Table 2.
• Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
• IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
• Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
• Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
• Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 0.1 / Apr 2013 15
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above]
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
VDD
DDR3
SDRAM
VDDQ
RESET
CK/CK
DQS, DQS
CS
RAS, CAS, WE
A, BA
ODT
ZQ VSS VSSQ
DQ, DM,
TDQS, TDQS
CKE RTT = 25 OhmVDDQ/2
IDD IDDQ (optional)
Application specific
memory channel
environment
Channel
IO Power
Simulation IDDQ
Simulation
IDDQ
Simulation
Channel IO Power
Number
IDDQ
Test Load
Correction
Rev. 0.1 / Apr 2013 16
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit
7-7-7 9-9-9 11-11-11 13-13-13
t
CK 1.875 1.5 1.25 1.07 ns
CL 7 9 11 13 nCK
n
RCD 7 9 11 13 nCK
n
RC 27 33 39 45 nCK
n
RAS 20 24 28 32 nCK
n
RP 7 9 11 13 nCK
n
FAW 1KB page size 20 20 24 26 nCK
2KB page size 27 30 32 33 nCK
n
RRD 1KB page size 4 4 5 5 nCK
2KB page size 6 5 6 6 nCK
n
RFC -512Mb 48 60 72 85 nCK
n
RFC-1 Gb 59 74 88 103 nCK
n
RFC- 2 Gb 86 107 128 150 nCK
n
RFC- 4 Gb 139 174 208 243 nCK
n
RFC- 8 Gb 187 234 280 328 nCK
Symbol Description
I
DD0
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT
and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see
Table 3); Output Buffer and RTT: Ena ble d in Mod e Registersb); ODT Signal: stable at 0; Patter n D etails:
see Table 3.
I
DD1
Operating One Bank Activ e-Pr echarge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD , CL: see Table 1; BL: 8a); AL: 0; CS : High between
ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to
Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table
4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 4.
Rev. 0.1 / Apr 2013 17
I
DD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Comm and, Add ress,
Bank Address Inputs: partially toggling ac cording to Table 5; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Ena bled in Mode Registers b); ODT Signal: stable
at 0; Pattern Details : see Table 5.
I
DD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Comm and, Add ress,
Bank Address Inputs: partially toggling ac cording to Table 6; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: tog-
gling according to Table 6; Pattern Details: see Table 6.
I
DD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: s table at 0; Da ta IO: MID _LEVEL; DM: stable at 0; Bank Activit y: all bank s closed;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down
Mode: Slow Exitc)
I
DD2P1
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: s table at 0; Da ta IO: MID _LEVEL; DM: stable at 0; Bank Activit y: all bank s closed;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down
Mode: Fast Exitc)
I
DD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Comm and, Add ress,
Bank Address Inputs : stable at 0; Data IO: MID_L EVEL; DM: stab le at 0; Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
I
DD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Comm and, Add ress,
Bank Address Inputs: partially toggling ac cording to Table 5; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable
at 0; Pattern Details : see Table 5.
Symbol Description
Rev. 0.1 / Apr 2013 18
I
DD3P
Active Power -Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
I
DD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command,
Address, Bank Address Inputs : partially toggling according to Table 7; Data IO: seamless read data burst
with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank
Activity: all banks open, RD commands cycling throug h banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.
I
DD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command,
Address, Bank Address Inputs : partially toggling according to Table 8; Data IO: seamless read data burst
with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
I
DD5B
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Com-
mand, Address, Bank Address Inputs: partially togglin g accord ing to Table 9; Data IO: MID_LEVEL; DM:
stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in
Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9.
I
DD6
Self-Refresh Current: Normal Temperature Range
T
CASE: 0 - 85 oC; Auto Self -R efresh (A SR): Disabled d);Self-Refresh Temperature R ange (SRT): Normale);
CKE: Low; External clock: Off; CK and CK: LOW ; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address,
Bank Address I nputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Out-
put Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
I
DD6ET
Self-Refresh Current: Extended Temperature Range (optional)
T
CASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extend-
ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command,
Address, Bank Address Inputs, D ata IO: MI D_LEVEL; DM: stable at 0; Bank Activity: Extended Tempera-
ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
MID_LEVEL
Symbol Description
Rev. 0.1 / Apr 2013 19
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
I
DD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a), f); AL: CL-
1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling accord-
ing to Table 10; Data IO: read data burst with different data between one burst and the next one
according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0,
1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Pattern Details: see Table 10.
Symbol Description
Rev. 0.1 / Apr 2013 20
Table 3 - IDD0 Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID- LEVE L.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00ACT001100000000 -
1,2 D, D100000000000 -
3,4 D, D 111100000000 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE001000000000 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
1*nRC+3, 4 D, D 1111000000F0 -
... repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead
Rev. 0.1 / Apr 2013 21
Table 4 - IDD1 Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 11110000000 0 -
... repeat pattern 1...4 until nRCD - 1, truncate if necessary
nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
1*nRC+3,4 D, D 1111000000F 0 -
... repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
1*nRC+nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011
... repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead
Rev. 0.1 / Apr 2013 22
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEV EL.
b) DQ signals are MID-LEVEL.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEV EL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00D10000000000 -
1D10000000000-
2D
1111 000 0 0 F0 -
3D
1111 000 0 0 F0 -
1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 24-17 repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00D10000000000 -
1D10000000000-
2D
1111000 0 0 F0 -
3D
1111000 0 0 F0 -
1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6 24-17 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
Rev. 0.1 / Apr 2013 23
Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00RD 0 1 0 1 0 0 00 0 0 0 0 00000000
1D100000000000-
2,3 D,D 111100000 0 00 -
4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011
5D1000000000F0-
6,7 D,D 111100000 0 F0 -
1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1
2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7
Rev. 0.1 / Apr 2013 24
Table 8 - IDD4W Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 9 - IDD5B Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEV EL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00WR 0 1 0 0 1 0 00 0 0 0 0 00000000
1D100010000000-
2,3 D,D 111110000 0 00 -
4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011
5D1000100000F0-
6,7 D,D 111110000 0 F0 -
1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1
2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00REF 0 0 0 1 0 0 0 0 0 0 0 -
11.2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1111000000 F0 -
5...8 repeat cycles 1...4, but BA[2:0] = 1
9...12 repeat cycles 1...4, but BA[2:0] = 2
13...16 repeat cycles 1...4, but BA[2:0] = 3
17...20 repeat cycles 1...4, but BA[2:0] = 4
21...24 repeat cycles 1...4, but BA[2:0] = 5
25...28 repeat cycles 1...4, but BA[2:0] = 6
29...32 repeat cycles 1...4, but BA[2:0] = 7
2 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
Rev. 0.1 / Apr 2013 25
Table 10 - IDD7 Measurement-Loop Patterna)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00ACT 0 0 1 1 0 0 00 0 0 0 0 -
1RDA 0 1 0 1 0 0 00 1 0 0 0 00000000
2 D 1 0 0 0 0 0 00 0 0 0 0 -
... repeat above D Command until nRRD - 1
1
nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 -
nRRD+1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011
nRRD+2 D 1 0 0 0 0 1 00 0 0 F 0 -
... repeat above D Command until 2* nRRD - 1
22*nRRD repeat Sub-Loop 0, but BA[2:0] = 2
33*nRRD repeat Sub-Loop 1, but BA[2:0] = 3
44*nRRD D 1 0 0 0 0 3 00 0 0 F 0 -
Assert and repeat above D Command until nFAW - 1, if necessary
5nFAW repeat Sub-Loop 0, but BA[2:0] = 4
6nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5
7 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6
8 nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7
9nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 F 0 -
Assert and repeat above D Command until 2* nFAW - 1, if necessary
10
2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011
2&nFAW+2 D 1 0 0 0 0 0 00 0 0 F 0 -
Repeat above D Command until 2* nFAW + nRRD - 1
11
2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 -
2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000
2&nFAW+nRRD+
2D 1 0 0 0 0 1 00 0 0 0 0 -
Repeat above D Command until 2* nFAW + 2* nRRD - 1
12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2
13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3
14 2*nFAW+4*nRRD D 1 0 0 0 0 3 00 0 0 0 0 -
Assert and repeat above D Command until 3* nFAW - 1, if necessary
15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4
16 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5
17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6
18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7
19 3*nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 0 0 -
Assert and repeat above D Command until 4* nFAW - 1, if necessary
Rev. 0.1 / Apr 2013 26
IDD Specifications
IDD values are for full operating range of voltage and temperature unless otherwise noted.
I
DD Specification
Notes:
1. Applicable for MR2 settings A6=0 and A7=0. Temperature range for IDD6 is 0 - 85oC.
2. Applicable for MR2 settings A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95oC.
Speed Grade
Bin DDR3 - 1066
7-7-7 DDR3 - 1333
9-9-9 DDR3 - 1600
11-11-11 DDR3 - 1600
11-11-11 Unit Notes
Symbol Max. Max. Max. Max.
I
DD0 55 57 59 61 mA x4/8
74 76 79 80 mA x16
I
DD01 63 64 67 70 mA x4/8
86 88 90 92 mA x16
I
DD2P0 22 22 22 22 mA x4/8
34 34 34 34 mA x16
I
DD2P1 24 26 26 28 mA x4/8
36 36 38 40 mA x16
I
DD2N 40 40 42 44 mA x4/8
52 54 58 58 mA x16
I
DD2NT 44 48 52 54 mA x4/8
60 62 68 72 mA x16
I
DD2Q 40 42 44 42 mA x4/8
54 54 58 60 mA x16
I
DD3P 40 40 42 42 mA x4/8
46 46 48 50 mA x16
I
DD3N 56 58 62 64 mA x4/8
64 66 70 74 mA x16
I
DD4R 90 105 116 132 mA x4/8
131 152 174 194 mA x16
I
DD4w 95 110 121 137 mA x4/8
141 162 184 204 mA x16
I
DD5B 220 220 221 222 mA x4/8
226 227 229 229 mA x16
I
DD6 30 30 30 30 mA x4/8, 1
38 38 388 38 mA x16, 1
I
DD6ET 38 38 38 38 mA x4/8, 2
46 46 46 46 mA x16, 2
I
DD7 140 165 171 182 mA x4/8
211 242 249 254 mA x16
Rev. 0.1 / Apr 2013 27
Input/Output Capacitance
Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Units Notes
Min Max Min Max Min Max Min Max Min Max
Input/output capacitance
(DQ, DM, DQS, DQS,
TDQS, TDQS)CIO 1.4 3.0 1.4 2.7 1.4 2.5 1.4 2.3 1.4 2.2 pF 1,2,3
Input capacitance, CK and
CK CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 pF 2,3
Input capacitance delta
CK and CK CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4
Input capacitance delta,
DQS and DQS CDDQS 00.2000.2000.1500.1500.15pF 2,3,5
Input capacitance
(All other input-only pins) CI0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 pF 2,3,6
Input capacitance delta
(All CTRL input-only pins) CDI_CTR
L-0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 2,3,7,8
Input capacitance delta
(All ADD/CMD input-only
pins)
CDI_ADD
_CMD -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2,3,9,10
Input/output capacitance
delta
(DQ, DM, DQS, DQS)CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11
Input/output capacitance
of ZQ pin CZQ - 3 - 3 - 3 - 3 - 3 pF 2,3,12
Notes:
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS.
2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is
measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE,
RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK.
5. Absolute value of CIO(DQS)-CIO(DQS).
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTR applies to ODT, CS and CKE.
8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE.
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5* (CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ) - 0. 5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance an ZQ pin: 5 pF.
Rev. 0.1 / Apr 2013 28
Standard Speed Bins
DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin DDR3-800E Unit Notes
CL - nRCD - nRP 6-6-6
Parameter Symbol min max
Internal read command to first data
t
AA 15 20 ns
ACT to internal read or write delay time
t
RCD 15 — ns
PRE command period
t
RP 15 — ns
ACT to ACT or REF command period
t
RC 52.5 — ns
ACT to PRE command period
t
RAS 37.5 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) 3.0 3.3 ns 1,2,3,4,11,12
CL = 6 CWL = 5
t
CK(AVG) 2.5 3.3 ns 1,2,3
Supported CL Settings 5, 6
n
CK 12
Supported CWL Settings 5
n
CK
Rev. 0.1 / Apr 2013 29
DDR3-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin DDR3-1066F Unit Note
CL - nRCD - nRP 7-7-7
Parameter Symbol min max
Internal read command to
first data
t
AA 13.125 20 ns
ACT to internal read or
write delay time
t
RCD 13.125 — ns
PRE command period
t
RP 13.125 — ns
ACT to ACT or REF
command period
t
RC 50.625 — ns
ACT to PRE command
period
t
RAS 37.5 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) 3.0 3.3 ns 1,2,3,4,6,11,12
CWL = 6
t
CK(AVG) Reserved ns 4
CL = 6 CWL = 5
t
CK(AVG) 2.5 3.3 ns 1,2,3,6
CWL = 6
t
CK(AVG) Reserved ns 1,2,3,4
CL = 7 CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1,2,3,4
CL = 8 CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1,2,3
Supported CL Settings 5, 6, 7, 8
n
CK 12
Supported CWL Settings 5, 6
n
CK
Rev. 0.1 / Apr 2013 30
DDR3-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin DDR3-1333H Unit Note
CL - nRCD - nRP 9-9-9
Parameter Symbol min max
Internal read
command to first data
t
AA 13.5
(13.125)5,10 20 ns
ACT to internal read or
write delay time
t
RCD 13.5
(13.125)5,10 —ns
PRE command period
t
RP 13.5
(13.125)5,10 —ns
ACT to ACT o r REF
command period
t
RC 49.5
(49.125)5,10 —ns
ACT to PRE command
period
t
RAS 36 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) 3.0 3.3 ns 1,2,3,4,7,11,12
CWL = 6, 7
t
CK(AVG) Reserved ns 4
CL = 6
CWL = 5
t
CK(AVG) 2.5 3.3 ns 1,2,3,7
CWL = 6
t
CK(AVG) Reserved ns 1,2,3,4,7
CWL = 7
t
CK(AVG) Reserved ns 4
CL = 7
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1,2,3,4,7
(Optional)5,10
CWL = 7
t
CK(AVG) Reserved ns 1,2,3,4
CL = 8
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1,2,3,7
CWL = 7
t
CK(AVG) Reserved ns 1,2,3,4
CL = 9 CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1,2,3,4
CL = 10 CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1,2,3
(Optional) ns 5
Supported CL Settings 5, 6, 7, 8, 9, 10
n
CK
Supported CWL Settings 5, 6, 7
n
CK
Rev. 0.1 / Apr 2013 31
DDR3-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin DDR3-1600K Unit Note
CL - nRCD - nRP 11-11-11
Parameter Symbol min max
Internal read
command to first data
t
AA 13.75
(13.125)5,10 20 ns
ACT to internal read or
write delay time
t
RCD 13.75
(13.125)5,10 —ns
PRE command period
t
RP 13.75
(13.125)5,10 —ns
ACT to ACT o r REF
command period
t
RC 48.75
(48.125)5,10 —ns
ACT to PRE command
period
t
RAS 35 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) 3.0 3.3 ns 1,2,3,4,8,11,12
CWL = 6, 7
t
CK(AVG) Reserved ns 4
CL = 6 CWL = 5
t
CK(AVG) 2.5 3.3 ns 1,2,3,8
CWL = 6
t
CK(AVG) Reserved ns 1,2,3,4,8
CWL = 7
t
CK(AVG) Reserved ns 4
CL = 7
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1,2,3,4,8
(Optional)5,10
CWL = 7
t
CK(AVG) Reserved ns 1,2,3,4,8
CWL = 8
t
CK(AVG) Reserved ns 4
CL = 8
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1,2,3,8
CWL = 7
t
CK(AVG) Reserved ns 1,2,3,4,8
CWL = 8
t
CK(AVG) Reserved ns 1,2,3,4
CL = 9
CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1,2,3,4,8
(Optional)5,10
CWL = 8
t
CK(AVG) Reserved ns 1,2,3,4
CL = 10 CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1,2,3,8
CWL = 8
t
CK(AVG) Reserved ns 1,2,3,4
CL = 11 CWL = 5, 6,7
t
CK(AVG) Reserved ns 4
CWL = 8
t
CK(AVG) 1.25 <1.5 ns 1,2,3
Supported CL Settings 5, 6, 7, 8, 9, 10, 11
n
CK
Supported CWL Settings 5, 6, 7, 8
n
CK
Rev. 0.1 / Apr 2013 32
DDR3-1866 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin DDR3-1866M Unit Note
CL - nRCD - nRP 13-13-13
Parameter Symbol min max
Internal read command
to first data
t
AA 13.91
(13.125)5,13 20 ns
ACT to internal read or
write delay time
t
RCD 13.91
(13.125)5,13 —ns
PRE command period
t
RP 13.91
(13.125)5,13 —ns
ACT to PRE command
period
t
RAS 34 9 * tREFI ns
ACT to ACT or PRE
command period
t
RC 47.91
(47.125)5,13 -ns
CL = 5 CWL = 5
t
CK(AVG) 3.0 3.3 ns 1, 2, 3, 4, 9
CWL = 6,7,8,9
t
CK(AVG) Reserved ns 4
CL = 6 CWL = 5
t
CK(AVG) 2.5 3.3 ns 1, 2, 3, 9
CWL = 6
t
CK(AVG) Reserved ns 1, 2, 3, 4, 9
CWL = 7,8,9
t
CK(AVG) Reserved ns 4
CL = 7
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 4, 9
(optional)
CWL = 7,8,9
t
CK(AVG) Reserved ns 4
CL = 8
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 9
CWL = 7
t
CK(AVG) Reserved ns 1, 2, 3, 4, 9
CWL = 8,9
t
CK(AVG) Reserved ns 4
CL = 9
CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1, 2, 3, 4, 9
(optional)
CWL = 8
t
CK(AVG) Reserved ns 1, 2, 3, 4, 9
CWL = 9
t
CK(AVG) Reserved ns 4
CL = 10 CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1, 2, 3, 9
CWL = 8
t
CK(AVG) Reserved ns 1, 2, 3, 4, 9
CL = 11
CWL = 5,6,7
t
CK(AVG) Reserved ns 4
CWL = 8
t
CK(AVG) 1.25 <1.5 ns 1, 2, 3, 4, 9
(optional)
CWL = 9
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 12 CWL = 5,6,7,8
t
CK(AVG) Reserved ns 4
CWL = 9
t
CK(AVG) Reserved ns 1,2,3,4
CL = 13 CWL = 5,6,7,8
t
CK(AVG) Reserved ns 4
CWL = 9
t
CK(AVG) 1.07 <1.25 ns 1, 2, 3
Supported CL Settings 6, 7, 8, 9, 10, 11, 13
n
CK
Supported CWL Settings 5, 6, 7, 8, 9
n
CK
Rev. 0.1 / Apr 2013 33
Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak-
ing a selection of tCK(A VG), both need to be f ulfilled: R e quirements fr om CL set ting as well as r equire-
ments from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchro-
nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat-
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =
3.0 ns should only be used for CL = 5 calculation.
3. tCK(AV G).MAX limits: Calculate tCK(A VG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man-
datory feature. Refer to DIMM data sheet and/or the DIMM SPD information if and how this setting is
supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
10. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must
be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H
devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to
DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byt e 20) is progr ammed to 13.125ns, t RCmin (Byte 21,23)
also should be progr ammed ac cordin gly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125
ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
11. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.
12. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not manda-
tory in SPD coding.
13. DDR3 SDRAM devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin
must be 13.125ns. SPD setting must be programed to match. For example, DDR3-1866M devices sup-
porting down binning to DDR3-1600K or DDR3-1333H or 1066F should program 13.125ns in SPD
bytes for tAAmin(byte 16), tR CDmin(byte 18) and tRPmin(byte 20) is programmed to 13.125ns, tRC-
min(byte 21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin
= 34ns + 13.125ns)
Rev. 0.1 / Apr 2013 34
Package Dimensions
Package Dimension(x4/x8): 78Ball Fine Pitch Ball Grid Array Outline
A1 INDEX MARK
9.000 0.100
11.100 0.100
0.290 0.050
1.100 0.100
987 21
A
B
C
D
E
F
G
H
J
K
L
M
N
0.800 X 8 = 6.400
0.800
1.600
0.800 X 12 = 9.600
0.800
1.600
78
x
0.400 0.050
0.750 0.100
TOP VIEW
BOTTOM VIEW
SIDE VIEW
A1 BALL MARK
3
1.300 0.100
Rev. 0.1 / Apr 2013 35
Package Dimension(x16): 96Ball Fine Pitch Ball Grid Array Outline
9.000 0.100
13.000 0.100
987 21
A
B
C
D
E
F
G
H
J
K
L
M
N
1.300 0.100
0.800 X 8 = 6.400
0.800
1.600
0.800 X 15 = 12.000
0.800
1.600
96
x
0.400 0.050
0.500 0.100
TOP VIEW
BOTTOM VIEW
SIDE VIEW
A1 BALL MARK
3
O
P
Q
A1 INDEX MARK
0.290 0.050
1.100 0.100
