LM4946
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LM4946 Output Capacitor-Less Audio Subsystem with
Programmable TI 3D
Check for Samples: LM4946
1FEATURES DESCRIPTION
The LM4946 is an audio power amplifier capable of
2• I2C/SPI Control Interface delivering 540mW of continuous average power into a
• I2C/SPI Programmable TI 3D Audio mono 8Ωbridged-tied load (BTL) with 1% THD+N,
• I2C/SPI Controlled 32 Step Digital Volume 35mW per channel of continuous average power into
Control (-54dB to +18dB) stereo 32Ωsingle-ended (SE) loads with 1% THD+N,
or an output capacitor-less (OCL) configuration with
• Three Independent Volume Channels (Left, identical specifications as the SE configuration, from
Right, Mono) a 3.3V power supply.
• Eight Distinct Output Modes The LM4946 has three input channels: one pair for a
• WQFN and DSBGA Surface Mount Packaging two-channel stereo signal and the third for a
• “Click and Pop” Suppression Circuitry differential single-channel mono input. The LM4946
features a 32-step digital volume control and eight
• Thermal Shutdown Protection distinct output modes. The digital volume control, 3D
• Low Shutdown Current (0.02uA, typ) enhancement, and output modes (mono/SE/OCL) are
• RF Immunity Topology programmed through a two-wire I2C or a three-wire
SPI compatible interface that allows flexibility in
APPLICATIONS routing and mixing audio channels.
• Mobile Phones The LM4946 is designed for cellular phone, PDA, and
other portable handheld applications. It delivers high
• PDAs quality output power from a surface-mount package
and requires only seven external components in the
KEY SPECIFICATIONS OCL mode (two additional components in SE mode).
• THD+N at 1kHz, 540mW into 8ΩBTL (3.3V)
1.0% (typ)
• THD+N at 1kHz, 35mW into 32ΩSE (3.3V) 1.0%
(typ)
• Single Supply Operation (VDD) 2.7 to 5.5V
• I2C/SPI Single Supply Operation
– WQFN 2.2 to 5.5V
– DSBGA 1.7 to 5.5V
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
8:
MONO +
MONO-
ROUT
Handsfree
Speaker
AUDIO
INPUT
AUDIO
INPUT 0.22 PF
+
CIN1
Mixer
and
Output
Mode
Select
Interface
6 dB
SDA
SCL
ID_ENB
RIN
LIN
3D
LOUT
Bias
2.2 PF
+
CB
Bypass
LHP3D1
LHP3D2
RHP3D1
RHP3D2
C3DR
C3DL
Volume Control
-54 dB to +18 dB
MONO_IN+
MONO_IN-
+
-
Volume Control
-54 dB to +18 dB
Volume Control
-54 dB to +18 dB
-6 dB
VOC
0.22 PF
+
CIN2
+
CIN3
+
CIN4
CO
100 PF
+
32:
CO
100 PF32:
+
1 PF
1 PF
+
0.1 PF
CS1
1 PFceramic
CS2
GND
0 dB
0 dB
VDD
I2C/SPI
I2CSPI_VDD
I2CSPI_SEL
8:
MONO +
MONO -
ROUT
32:
Handsfree
Speaker
AUDIO
INPUT
AUDIO
INPUT
+
CIN1
Mixer
and
Output
Mode
Select
Interface
6dB
I2
SDA
SCL
ID_ENB
3D
LOUT 32:
+
VDD
Bias
+
CB
Bypass
LHP3D1
LHP3D2
RHP3D1
RHP3D2
C3DR
C3DL
Volume Control
-54dB to +18dB
MONO_IN+
MONO_IN-
+
-
Volume Control
-54dB to +18dB
Volume Control
-54dB to +18dB
-6dB
VOC
+
++
1 PF
1 PF
0.1 PF
CS1
1 PFceramic
CS2
GND
0dB
0dB
RIN
CIN2
0.22 PF
0.22 PF
LIN
CIN4
CIN3
CSPI_VDD
I2CSPI_SEL
I2C/SPI
2.2 PF
LM4946
SNAS335E –JANUARY 2006–REVISED AUGUST 2007
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Typical Application
Figure 1. Typical Audio Amplifier Application Circuit-Output Capacitor-less
Figure 2. Typical Audio Amplifier Application Circuit-Single Ended
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E
D
C
B
A
1 2 3 4 5
VOC VDD GND ROUT LOUT
LHP3D2 LIN I2CSPI_VDD RIN
SDA
MONO_IN+ BYPASSMONO_IN- SCL
RHP3D1 VDD ID_ENB
LHP3D1 MONO- MONO+
VDD I2CSPI_SEL
GND GND
RHP3D2
24
23
7
22
8
21
9
20
10
17
16
15
14
13
11
12
18
19
6
1
2
3
4
5
LM4946
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SNAS335E –JANUARY 2006–REVISED AUGUST 2007
Connection Diagram
Figure 3. 24 Lead WQFN Package (Top View)
Figure 4. 25 Bump DSBGA Package (Top View)
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PIN DESCRIPTIONS
Pin Number (WQFN) Bump (DSBGA) Name Description
1 B2 LHP3D2 Left Headphone 3D Input 1
2 A1 VOC Center Amplifier Output
3 A2 VDD Voltage Supply
4 A3 GND Ground
5 A4 ROUT Right Headphone Output
6 A5 LOUT Left Headphone Output
7 B4 I2CSPI_VDD I2C or SPI Interface Voltage Supply
8 B5 RIN Right Input Channel
9 B3 LIN Left Input Channel
10 C5 SDA Data
11 C4 SCL Clock
12 D5 GND Ground
13 D4 ID_ENB Address Identification/Enable Bar
14 E5 I2CSPI_SEL I2C or SPI Select
15 E4 MONO+ Loudspeaker Output Positive
16 D3 VDD Voltage Supply
17 E2 MONO- Loudspeaker Output Negative
18 E1 LHP3D1 Left Headphone 3D Input 2
19 D2 RHP3D1 Right Headphone 3D Input 1
20 D1 GND Ground
21 C3 BYPASS Half-Supply Bypass
22 C1 MONO_IN- Loudspeaker Negative Input
23 C2 MONO_IN+ Loudspeaker Positive Input
24 B1 RHP3D2 Right Headphone 3D Input 2
E3 VDD Voltage Supply
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage 6.0V
Storage Temperature −65°C to +150°C
Input Voltage −0.3 to VDD +0.3
ESD Susceptibility(3) 2.0kV
ESD Machine model(4) 200V
Junction Temperature 150°C
Soldering Information Vapor Phase (60 sec.) 215°C
Infrared (15 sec.) 220°C
Thermal Resistance(5) θJA (typ) - RTW0024A 46°C/W
θJA (typ) - YFQ0025 49°C/W
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Human body model, 100pF discharged through a 1.5kΩresistor.
(4) Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then
discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω).
(5) The given θJA for an LM4946SQ mounted on a demonstration board with a 9in2area of 1oz printed circuit board copper ground plane.
Operating Ratings
Temperature Range −40°C to 85°C
Supply Voltage (VDD) 2.7V ≤VDD ≤5.5V
Supply Voltage (I2C/SPI)(1) I2CSPI_VDD ≤VDD
WQFN 2.2V ≤I2CSPI_VDD ≤5.5V
DSBGA 1.7V ≤I2CSPI_VDD ≤5.5V
(1) Refer to this table.
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Electrical Characteristics 3.3V(1)(2)
The following specifications apply for VDD = 3.3V, TA= 25°C, all volume controls set to 0dB, unless otherwise specified.
Symbol Parameter Conditions LM4946 Units
(Limits)(3)
Typical(4) Limits(5)
Output Modes 2, 4, 6
VIN = 0V; No load, 3.25 mA
SE Headphone
Output Modes 1, 3, 5, 7
VIN = 0V; No load, 5.65 mA
SE Headphone
Output Modes 2, 4, 6
IDD Supply Current VIN = 0V; No load, 4 6.5 mA (max)
OCL Headphone
Output Modes 1, 3, 5,
VIN = 0V; No load, 5 mA
OCL Headphone
Output Modes 7
VIN = 0V; No load, 6.5 10.5 mA (max)
OCL Headphone
ISD Shutdown Current Output Mode 0 0.02 1 µA (max)
VIN = 0V, Mode 7 12 50
Mono
VOS Output Offset Voltage mV (max)
VIN = 0V, Mode 7 3 15
Headphones (Note 11)
MONO OUT; RL= 8Ω540 500 mW (min)
THD+N = 1%; f = 1kHz, BTL, Mode 1
POOutput Power ROUT and LOUT; RL= 32Ω35 30 mW (min)
THD+N = 1%; f = 1kHz, SE, Mode 4
MONOOUT
f = 1kHz 0.05 %
POUT = 250mW; RL= 8Ω, BTL, Mode 1
THD+N Total Harmonic Distortion + Noise ROUT and LOUT
f = 1kHz 0.015 %
POUT = 12mW; RL= 32Ω, SE, Mode 4
A-weighted,
inputs terminated to GND, output referred
Speaker; Mode 1 17 μV
Speaker; Mode 3, 7 27 μV
Speaker; Mode 5 33 μV
Headphone; SE, Mode 2 8 μV
NOUT Output Noise Headphone; SE, Mode 4, 7 8 μV
Headphone; SE, Mode 6 12 μV
Headphone; OCL, Mode 2 8 μV
Headphone; OCL, Mode 4, 7 9 μV
Headphone; OCL, Mode 6 12 μV
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to the ground pin, unless otherwise specified.
(3) Datasheet min/max specifications are specified by design, test, or statistical analysis.
(4) Typical specifications are specified at +25°C and represent the most likely parametric norm.
(5) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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Electrical Characteristics 3.3V(1)(2) (continued)
The following specifications apply for VDD = 3.3V, TA= 25°C, all volume controls set to 0dB, unless otherwise specified.
Symbol Parameter Conditions LM4946 Units
(Limits)(3)
Typical(4) Limits(5)
VRIPPLE = 200mVPP; f = 217Hz, RL= 8Ω
CB= 2.2µF, BTL
All audio inputs terminated to GND;
output referred
Power Supply Rejection Ratio
MONOOUT BTL, Output Mode 1 76 dB
BTL, Output Mode 3, 7 65 dB
BTL, Output Mode 5 63 dB
VRIPPLE = 200mVPP; f = 217Hz, RL= 32Ω
CB= 2.2µF,
PSRR All audio inputs terminated to GND
output referred
SE, Output Mode 2 78 dB
Power Supply Rejection Ratio SE, Output Mode 4,7 82 dB
ROUT and LOUT SE, Output Mode 6 78 dB
OCL, Output Mode 2 84 dB
OCL, Output Mode 4, 7 78 dB
OCL, Output Mode 6 77 dB
Volume Control Step Size Error ±0.2 dB
–56 dB (max)
Maximum attenuation -54 –52 dB (min)
Digital Volume Control Range 17.4 dB (min)
Maximum gain 18 18.6 dB (max)
HP(SE) Mute Attenuation Output Mode 1, 3, 5 96 dB
10 kΩ(min)
Maximum gain setting 12.5 15 kΩ(max)
MONO_IN Input Impedance
RIN and LIN Input Impedance 90 kΩ(min)
Maximum attenuation setting 110 130 kΩ(max)
f = 217Hz, VCM = 1Vpp, 61
Mode 1, BTL, RL= 8Ω
CMRR Common-Mode Rejection Ratio dB
f = 217Hz, VCM = 1Vpp, 66
Mode 2, RL= 32Ω
Headphone; PO= 12mW dB
–54
f = 1kHz, OCL, Mode 4
XTALK Crosstalk Headphone; PO= 12mW dB
–72
f = 1kHz, SE, Mode 4
CB= 2.2μF, OCL 100 ms
TWU Wake-Up Time from Shutdown CB= 2.2μF, SE 135 ms
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Electrical Characteristics 5.0V(1)(2)
The following specifications apply for VDD = 5.0V, TA= 25°C, all volume controls set to 0dB, unless otherwise specified.
Symbol Parameter Conditions LM4946 Units
(Limits)(3)
Typical(4) Limits(5)
Output Modes 2, 4, 6
VIN = 0V; No load 3.8 mA
SE Headphone
Output Modes 1, 3, 5, 7
VIN = 0V; No Load, 6.6 mA
SE Headphone
Output Modes 2, 4, 6
IDD Supply Current VIN = 0V; No load, 4.6 mA
OCL Headphone
Output Modes 1, 3, 5
VIN = 0V; No Load, 6 mA
OCL Headphone
Output Modes 7
VIN = 0V; No Load, 7.4 mA
OCL Headphone
ISD Shutdown Current Output Mode 0 0.05 µA
VIN = 0V, Mode 7 12
Mono
VOS Output Offset Voltage mV
VIN = 0V, Mode 7 3
Headphones
MONOOUT; RL= 8Ω1.3 W
THD+N = 1%; f = 1kHz, BTL, Mode 1
POOutput Power ROUT and LOUT; RL= 32Ω85 mW
THD+N = 1%; f = 1kHz, SE, Mode 4
MONOOUT, f = 1kHz 0.05 %
POUT = 500mW; RL= 8Ω, BTL, Mode 1
THD+N Total Harmonic Distortion + Noise ROUT and LOUT, f = 1kHz 0.012 %
POUT = 30mW; RL= 32Ω, SE, Mode 4
A-weighted,
inputs terminated to GND, output referred
Speaker; Mode 1 17 μV
Speaker; Mode 3, 7 27 μV
Speaker; Mode 5 33 μV
Headphone; SE, Mode 2 8 μV
NOUT Output Noise Headphone; SE, Mode 4, 7 8 μV
Headphone; SE, Mode 6 12 μV
Headphone; OCL, Mode 2 8 μV
Headphone; OCL, Mode 4, 7 9 μV
Headphone; OCL, Mode 6 12 μV
VRIPPLE = 200mVPP; f = 217Hz, RL= 8Ω
CB= 2.2µF, BTL
All audio inputs terminated to GND;
output referred
Power Supply rejection Ratio
PSRR MONOOUT BTL, Output Mode 1 69 dB
BTL, Output Mode 3, 7 60 dB
BTL, Output Mode 5 58 dB
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to the ground pin, unless otherwise specified.
(3) Datasheet min/max specifications are specified by design, test, or statistical analysis.
(4) Typical specifications are specified at +25°C and represent the most likely parametric norm.
(5) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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Electrical Characteristics 5.0V(1)(2) (continued)
The following specifications apply for VDD = 5.0V, TA= 25°C, all volume controls set to 0dB, unless otherwise specified.
Symbol Parameter Conditions LM4946 Units
(Limits)(3)
Typical(4) Limits(5)
VRIPPLE = 200mVPP; f = 217Hz, RL= 32Ω
CB= 2.2µF, BTL
All audio inputs terminated to GND;
output referred
SE, Output Mode 2 75 dB
Power Supply Rejection Ratio
PSRR SE, Output Mode 4,7 75 dB
ROUT and LOUT SE, Output Mode 6 72 dB
OCL, Output Mode 2 75 dB
OCL, Output Mode 4, 7 79 dB
OCL, Output Mode 6 72 dB
-56 dB (max)
Maximum attenuation -54 -52 dB (min)
Digital Volume Control Range 17.4 dB (min)
Maximum gain 18 18.6 dB (max)
HP(SE) Mute Attenuation Output Mode 1, 3, 5 96 dB
10 kΩ(min)
Maximum gain setting 12.5 15 kΩ(max)
MONO_IN Input Impedance
RIN and LIN Input Impedance 90 kΩ(min)
Maximum attenuation setting 110 130 kΩ(max)
f = 217Hz, VCM = 1Vpp, 0dB gain 61
Mode 1, BTL, RL= 8Ω
CMRR Common-Mode Rejection Ratio dB
f = 217Hz, VCM = 1Vpp, 0dB gain 66
Mode 2, RL= 32Ω
Headphone; PO= 30mW, OCL, Mode 4 –55 dB
XTALK Crosstalk Headphone; PO= 30mW, SE, Mode 4 –72 dB
CB= 2.2μF, OCL 135 ms
TWU Wake-Up Time from Shutdown CB= 2.2μF, SE 180 ms
I2C/SPI WQFN/DSBGA(1)(2)
The following specifications apply for VDD = 5.0V and 3.3V, TA= 25°C, 2.2V ≤I2CSPI_VDD ≤5.5V, unless otherwise specified.
Symbol Parameter Conditions LM4946(3) Units
(Limits)(4)
Typical(5) Limits(6) (2)
t1I2C Clock Period 2.5 µs (min)
t2I2C Data Setup Time 100 ns (min)
t3I2C Data Stable Time 0 ns (min)
t4Start Condition Time 100 ns (min)
t5Stop Condition Time 100 ns (min)
t6I2C Data Hold Time 100 ns (min)
fSPI Maximum SPI Frequency 1000 kHz (max)
tEL SPI ENB High Time 100 ns (min)
tDS SPI Data Setup Time 100 ns (min)
tES SPI ENB Setup Time 100 ns (min)
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to the ground pin, unless otherwise specified.
(3) For LM4946 WQFN package, revised specification goes into effect starting with date code 79. Existing specification is per datasheet rev
1.0
(4) Datasheet min/max specifications are specified by design, test, or statistical analysis.
(5) Typical specifications are specified at +25°C and represent the most likely parametric norm.
(6) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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I2C/SPI WQFN/DSBGA(1)(2) (continued)
The following specifications apply for VDD = 5.0V and 3.3V, TA= 25°C, 2.2V ≤I2CSPI_VDD ≤5.5V, unless otherwise specified.
Symbol Parameter Conditions LM4946(3) Units
(Limits)(4)
Typical(5) Limits(6) (2)
tDH SPI Data Hold Time 100 ns (min)
tEH SPI Enable Hold Time 100 ns (min)
tCL SPI Clock Low Time 500 ns (min)
tCH SPI Clock High Time 500 ns (min)
0.7xI2CSPI
VIH I2C/SPI Input Voltage High V (min)
VDD
0.3xI2CSPI
VIL I2C/SPI Input Voltage Low V (max)
VDD
I2C/SPI DSBGA only(1)(2)
The following specifications apply for VDD = 5.0V and 3.3V, TA= 25°C, 1.7V ≤I2CSPI_VDD ≤2.2V, unless otherwise specified.
Symbol Parameter Conditions LM4946 Units
(Limits)(3)
Typical(4) Limits(5) (2)
t1I2C Clock Period 2.5 µs (min)
t2I2C Data Setup Time 250 ns (min)
t3I2C Data Stable Time 0 ns (min)
t4Start Condition Time 250 ns (min)
t5Stop Condition Time 250 ns (min)
t6I2C Data Hold Time 250 ns (min)
fSPI Maximum SPI Frequency 250 kHz (max)
tEL SPI ENB High Time 250 ns (min)
tDS SPI Data Setup Time 250 ns (min)
tES SPI ENB Setup Time 250 ns (min)
tDH SPI Data Hold Time 250 ns (min)
tEH SPI Enable Hold Time 250 ns (min)
tCL SPI Clock Low Time 500 ns (min)
tCH SPI Clock High Time 500 ns (min)
0.7xI2CSPI
VIH I2C/SPI Input Voltage High V (min)
VDD
0.25 xI2CSPI
VIL I2C/SPI Input Voltage Low V (max)
VDD
(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to the ground pin, unless otherwise specified.
(3) Datasheet min/max specifications are specified by design, test, or statistical analysis.
(4) Typical specifications are specified at +25°C and represent the most likely parametric norm.
(5) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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0.001
10
0.01
0.1
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.001
10
0.01
0.1
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.001
10
0.01
0.1
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.001
10
0.01
0.1
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.001
10
0.01
0.1
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.001
10
0.01
0.1
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
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Typical Performance Characteristics
THD+N vs Frequency THD+N vs Frequency
VDD = 3.3V, RL= 8Ω, PO= 250mW VDD = 3.3V, RL= 32Ω, PO= 12mW
Mode 1, BTL, BW = 80kHz Mode 4, 7, OCL, BW = 80kHz
Figure 5. Figure 6.
THD+N vs THD+N vs Frequency
Frequency VDD = 3.3V, RL= 32Ω, PO= 12mW VDD = 3.3V, RL= 32Ω, PO= 12mW
Mode 6, OCL, BW = 80kHz Mode 4, 7, SE, BW = 80kHz
Figure 7. Figure 8.
THD+N vs Frequency THD+N vs Frequency
VDD = 3.3V, RL= 32Ω, PO= 12mW VDD = 3.3V, RL= 8Ω, PO= 250mW
Mode 6, SE, BW = 80kHz Mode 5, BTL, BW = 80kHz
Figure 9. Figure 10.
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0.001
10
0.01
0.1
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.001
10
0.01
0.1
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.001
10
0.01
0.1
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.001
10
0.01
0.1
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.001
10
0.01
0.1
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.001
10
0.01
0.1
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
LM4946
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Typical Performance Characteristics (continued)
THD+N vs Frequency THD+N vs Frequency
VDD = 5V, RL= 8Ω, PO= 500mW VDD = 5V, RL= 32Ω, PO= 30mW
Mode 1, BTL, BW = 80kHz Mode 4, 7, OCL, BW = 80kHz
Figure 11. Figure 12.
THD+N vs Frequency THD+N vs Frequency
VDD = 5V, RL= 32Ω, PO= 30mW VDD = 5V, RL= 32Ω, PO= 30mW
Mode 4, 7, SE, BW = 80kHz Mode 6, OCL, BW = 80kHz
Figure 13. Figure 14.
THD+N vs Frequency THD+N vs Frequency
VDD = 5V, RL= 32Ω, PO= 30mW VDD = 5V, RL= 8Ω, PO= 500mW
Mode 6, SE, BW = 80kHz Mode 5, BTL
Figure 15. Figure 16.
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0.01
10
0.1
1
1 10010
OUTPUT POWER (mW)
THD+N (%)
0.01
10
0.1
1
THD+N (%)
10 1000
100
OUTPUT POWER (mW)
0.01
10
0.1
1
THD+N (%)
10 1000
100
OUTPUT POWER (mW)
0.1
10
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.1
10
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.001
10
1
THD+N (%)
20 20k200 2k
FREQUENCY (Hz)
0.1
0.01
LM4946
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SNAS335E –JANUARY 2006–REVISED AUGUST 2007
Typical Performance Characteristics (continued)
THD+N vs Frequency THD+N vs Frequency
VDD = 3.3V, RL= 32Ω, PO= 12mW VDD = 3.3V, RL= 32Ω, PO= 12mW
Mode 2, OCL Mode 2, SE, BW = 80kHz
Figure 17. Figure 18.
THD+N vs Frequency THD+N vs Output Power
VDD = 3.3V, RL= 8Ω, PO= 250mW VDD = 3.3V, RL= 8Ω, f = 1kHz
Mode 3, BTL Mode 1, BTL
Figure 19. Figure 20.
THD+N vs Output Power THD+N vs Output Power
VDD = 3.3V, RL= 8Ω, f = 1kHz VDD = 3.3V, RL= 32Ω, f = 1kHz
Mode 5, BTL Mode 4, 7, OCL
Figure 21. Figure 22.
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0.001
10
0.01
0.1
1
THD+N (%)
22005 10 20 50 100
OUTPUT POWER (mW)
0.001
10
0.01
0.1
1
THD+N (%)
22005 10 20 50 100
OUTPUT POWER (mW)
20 2k50 100 200 500 1k
0.01
10
0.1
1
THD+N (%)
OUTPUT POWER (mW)
20 2k50 100 200 500 1k
0.01
10
0.1
1
THD+N (%)
OUTPUT POWER (mW)
0.01
10
0.1
1
1 10010
OUTPUT POWER (mW)
THD+N (%)
1 10010
0.01
10
0.1
1
THD+N (%)
OUTPUT POWER (mW)
LM4946
SNAS335E –JANUARY 2006–REVISED AUGUST 2007
www.ti.com
Typical Performance Characteristics (continued)
THD+N vs Output Power THD+N vs Output Power
VDD = 3.3V, RL= 32Ω, f = 1kHz VDD = 3.3V, RL= 32Ω, f = 1kHz
Mode 4, 7, SE Mode 6, SE
Figure 23. Figure 24.
THD+N vs Output Power THD+N vs Output Power
VDD = 5V, RL= 8Ω, f = 1kHz VDD = 5V, RL= 8Ω, f = 1kHz
Mode 1, BTL Mode 5, BTL
Figure 25. Figure 26.
THD+N vs Output Power THD+N vs Output Power
VDD = 5V, RL= 32Ω, f = 1kHz VDD = 5V, RL= 32Ω, f = 1kHz
Mode 4, 7, OCL Mode 4, 7, SE
Figure 27. Figure 28.
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Product Folder Links: LM4946
1
1 10010
0.01
10
THD+N (%)
OUTPUT POWER (mW)
0.1
1
1
0.01 0.1
10
THD+N (%)
OUTPUT POWER (W)
0.1
10
0.1
1
1 10010
THD+N (%)
0.01
OUTPUT POWER (mW)
0.1
1
1 10010
0.01
10
THD+N (%)
OUTPUT POWER (mW)
10
0.1
1
1 10010
THD+N (%)
OUTPUT POWER (mW)
0.01
0.001
10
0.01
0.1
1
THD+N (%)
22005 10 20 50 100
OUTPUT POWER (mW)
LM4946
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SNAS335E –JANUARY 2006–REVISED AUGUST 2007
Typical Performance Characteristics (continued)
THD+N vs Output Power THD+N vs Output Power
VDD = 5V, RL= 32Ω, f = 1kHz VDD = 3.3V, RL= 32Ω, f = 1kHz
Mode 6, SE Mode 6, Mono Input, OCL
Figure 29. Figure 30.
THD+N vs Output Power THD+N vs Output Power
VDD = 3.3V, RL= 32Ω, f = 1kHz VDD = 3.3V, RL= 32Ω, f = 1kHz
Mode 6, Stereo Input, OCL Mode 2, OCL
Figure 31. Figure 32.
THD+N vs Output Power THD+N vs Output Power
VDD = 3.3V, RL= 32Ω, f = 1kHz VDD = 3.3V, RL= 8Ω, f = 1kHz
Mode 2, SE Mode 3, BTL
Figure 33. Figure 34.
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-80
-60
-40
-20
-100
0
PSRR (dB)
FREQUENCY (Hz)
-10
-30
-50
-70
-90
20 200 2k 20k
-80
-60
-40
-20
-100
0
PSRR (dB)
FREQUENCY (Hz)
-10
-30
-50
-70
-90
20 200 2k 20k
-80
-60
-40
-20
-100
0
PSRR (dB)
FREQUENCY (Hz)
-10
-30
-50
-70
-90
20 200 2k 20k
-80
-60
-40
-20
-100
0
PSRR (dB)
FREQUENCY (Hz)
-10
-30
-50
-70
-90
20 200 2k 20k
-80
-60
-40
-20
-100
0
PSRR (dB)
FREQUENCY (Hz)
-10
-30
-50
-70
-90
20 200 2k 20k
-80
-60
-40
-20
-100
0
PSRR (dB)
FREQUENCY (Hz)
-10
-30
-50
-70
-90
20 200 2k 20k
LM4946
SNAS335E –JANUARY 2006–REVISED AUGUST 2007
www.ti.com
Typical Performance Characteristics (continued)
PSRR vs Frequency PSRR vs Frequency
VDD = 3.3V, 0dB VDD = 3.3V, 0dB
Mode 4, 7, OCL Mode 4, 7, SE
Figure 35. Figure 36.
PSRR vs Frequency PSRR vs Frequency
VDD = 3.3V, 0dB VDD = 3.3V, 0dB
Mode 6, OCL Mode 6, SE
Figure 37. Figure 38.
PSRR vs Frequency PSRR vs Frequency
VDD = 3.3V, 6dB VDD = 3.3V, RL= 8Ω
Mode 1, BTL Mode 3, 7, BTL
Figure 39. Figure 40.
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Product Folder Links: LM4946
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
-90
-1003.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
3.0 3.5 4.0 4.5 5.0 5.5 6.0
-80
-70
-60
-50
-40
-30
-20
-10
0
SUPPLY VOLTAGE (V)
PSRR (dB)
-90
-100
3.0 3.5 4.0 4.5 5.0 5.5 6.0
-80
-70
-60
-50
-40
-30
-20
-10
0
SUPPLY VOLTAGE (V)
PSRR (dB)
-90
-100
-80
-60
-40
-20
-100
0
PSRR (dB)
FREQUENCY (Hz)
-10
-30
-50
-70
-90
20 200 2k 20k
20 20k200 2k
FREQUENCY (Hz)
0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
PSRR (dB)
20 20k200 2k
FREQUENCY (Hz)
0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
PSRR (dB)
LM4946
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SNAS335E –JANUARY 2006–REVISED AUGUST 2007
Typical Performance Characteristics (continued)
PSRR vs Frequency PSRR vs Frequency
VDD = 3.3V, RL= 32ΩVDD = 3.3V, RL= 8Ω
Mode 2, OCL Mode 2, SE
Figure 41. Figure 42.
PSRR vs Frequency PSRR vs Supply Voltage
VDD = 3.3V, 6dB RL= 8Ω, 217Hz
Mode 5, BTL Mode 1, BTL
Figure 43. Figure 44.
PSRR vs Supply Voltage PSRR vs Supply Voltage
RL= 32Ω, 217Hz RL= 32Ω, 217Hz
Mode 4, OCL Mode 4, SE
Figure 45. Figure 46.
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0 10 20 30 40 50
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
0
50
100
150
200
250
0 10 20 30 40 50
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
0
50
100
150
200
250
0
50
100
150
200
250
300
350
0 50 100 150 200 250 300 350
POWER DISSIPATION (mW)
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
0
50
100
150
200
250
300
OUTPUT POWER (mW)
0 20 40 60 80 100
0 10 20 30 40 50
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
10
20
30
40
50
60
70
80
90
100
0
OuUTPUT POWER (mW)
0 200 400 600 800 1000 1200
POWER DISSIPATION (mW)
0
100
200
300
400
500
600
700
LM4946
SNAS335E –JANUARY 2006–REVISED AUGUST 2007
www.ti.com
Typical Performance Characteristics (continued)
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 3.3V, RL= 32ΩVDD = 5V, RL= 8Ω
f = 1kHz, Mode 2, 4, 6, SE f = 1kHz, Mode 1, 3, 5, BTL
Figure 47. Figure 48.
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 5V, RL= 32ΩVDD = 3.3V, RL= 8Ω, f = 1kHz,
f = 1kHz, Mode 2, 4, 6, OCL Modes 1, 3, 5, BTL
Figure 49. Figure 50.
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 3.3V, RL= 32Ω, f = 1kHz, VDD = 3.3V, RL= 8Ω, f = 1kHz,
Modes 2, 4, 6, OCL Mode 7, OCL
Figure 51. Figure 52.
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0
2
4
6
8
10
12
3 4 5 6
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
20 200 2k
-80
-60
-40
-20
-100
0
CROSSTALK (dB)
FREQUENCY (Hz)
20k
-10
-30
50
-70
-90
Right to Left
Left to Right
20 200 2k
-80
-60
-40
-20
-100
0
CROSSTALK (dB)
FREQUENCY (Hz)
20k
-10
-30
50
-70
-90
Right to Left
Left to Right
20 200 2k
-80
-60
-40
-20
-100
0
CROSSTALK (dB)
FREQUENCY (Hz)
20k
-10
-30
50
-70
-90 Right to Left
Left to Right
0 10 20 30 40 50
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
0
10
20
30
40
50
60
70
80
90
100
20 200 2k
-80
-60
-40
-20
-100
0
CROSSTALK (dB)
FREQUENCY (Hz)
20k
-10
-30
50
-70
-90
Right to Left
Left to Right
LM4946
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SNAS335E –JANUARY 2006–REVISED AUGUST 2007
Typical Performance Characteristics (continued)
Power Dissipation vs Output Power Crosstalk vs Frequency
VDD = 3.3V, RL= 32Ω, f = 1kHz, VDD = 3.3V, RL= 32Ω, PO= 12mW
Mode 7, SE Right-Left, Mode 4, OCL
Figure 53. Figure 54.
Crosstalk vs Frequency Crosstalk vs Frequency
VDD = 5V, RL= 32Ω, PO= 30mW VDD = 3.3V, RL= 32Ω, PO= 12mW
Left-Right, Mode 4, OCL Mode 4, SE
Figure 55. Figure 56.
Crosstalk vs Frequency
VDD = 5V, RL= 32Ω, PO= 30mW Supply Current vs Supply Voltage
Mode 4, SE No Load, Mode 7
Figure 57. Figure 58.
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OUTPUT POWER (W)
0
0.5
1.0
1.5
2.0
2.5
VOLTAGE SUPPLY (V)
3.0 3.5 4.0 4.5 5.0 5.5 6.0
THD+N = 1%
THD+N = 10%
OUTPUT POWER (mW)
0
20
60
80
100
120
140
160
VOLTAGE SUPPLY (V)
3.0 3.5 4.0 4.5 5.0 5.5 6.0
40
THD+N = 10%
THD+N = 1%
0
2
4
6
8
10
12
3 4 5 6
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
0
2
4
6
8
10
12
3 4 5 6
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
LM4946
SNAS335E –JANUARY 2006–REVISED AUGUST 2007
www.ti.com
Typical Performance Characteristics (continued)
Supply Current vs Supply Voltage Supply Current vs Supply Voltage
VDD = 3.3V, No Load, Modes 1, 3, 5 No Load, Modes 2, 4, 6
Figure 59. Figure 60.
Output Power vs Supply Voltage Output Power vs Supply Voltage
RL= 8Ω, f = 1kHz, Mono, Mode 1 RL= 32Ω, f = 1kHz, OCL, Mode 4
Figure 61. Figure 62.
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LM4946
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SNAS335E –JANUARY 2006–REVISED AUGUST 2007
APPLICATION INFORMATION
I2C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ID_ENB: This is the address select input pin.
I2CSPI_SEL: This is tied LOW for I2C mode.
I2C COMPATIBLE INTERFACE
The LM4946 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4946.
The I2C address for the LM4946 is determined using the ID_ENB pin. The LM4946's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1= 0, if ID_ENB is logic LOW; and X1= 1, if ID_ENB is
logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4946's chip address can
be changed to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 63. The bus format diagram is broken up into six major
sections:
1. The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will
alert all devices attached to the I2C bus to check the incoming address against their own address.
2. The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the
clock. Each address bit must be stable while the clock level is HIGH.
For I2C interface operation, the I2CSPI_SEL pin needs to be tied LOW (and tied high for SPI operation).
3. After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up
resistor). Then the master sends an acknowledge clock pulse. If the LM4946 has received the address
correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the
acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4946.
4. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable HIGH.
5. After the data byte is sent, the master must check for another acknowledge to see if the LM4946 received
the data.
If the master has more data bytes to send to the LM4946, then the master can repeat the previous two steps
until all data bytes have been sent.
6. The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is
HIGH. The data line should be held HIGH when not in use.
I2C INTERFACE POWER SUPPLY PIN (I2CSPI_VDD)
The LM4946's I2C interface is powered up through the I2CSPI_VDD pin. The LM4946's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
Figure 63. I2C Bus Format
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Data 7 Data 6 Data 1 Data 0
tDH
tDS
tCL
tCH
tES
tCS tEH tEL
ID_ENB
CLK
DATA
LM4946
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Figure 64. I2C Timing Diagram
SPI DESCRIPTION
(For 2.2V ≤I2CSPI_VDD ≤5.5V, see I2C/SPI WQFN/DSBGA for more information).
0. I2CSPI_SEL: This pin is tied HIGH for SPI mode.
1. The data bits are transmitted with the MSB first.
2. The maximum clock rate is 1MHz for the CLK pin.
3. CLK must remain HIGH for at least 500ns (tCH ) after the rising edge of CLK, and CLK must remain LOW for at
least 500ns (tCL) after the falling edge of CLK.
4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 100ns
(tDS) before the rising edge of CLK. Also, any transition on DATA must occur at least 100ns (tDH) after the rising
edge of CLK and stabilize before the next rising edge of CLK.
5.ID_ENB should be LOW only during serial data transmission.
6. ID_ENB must be LOW at least 100ns (tES ) before the first rising edge of CLK, and ID_ENB has to remain
LOW at least 100ns (tEH) after the eighth rising edge of CLK.
7. If ID_ENB remains HIGH for more than 100ns before all 8 bits are transmitted then the data latch will be
aborted.
8. If ID_ENB is LOW for more than 8 CLK pulses then only the first 8 data bits will be latched and activated when
ID_ENB transitions to logic-high.
9. ID_ENB must remain HIGH for at least 100ns (tEL ) to latch in the data.
10. Coincidental rising or falling edges of CLK and ID_ENB are not allowed. If CLK is to be held HIGH after the
data transmission, the falling edge of CLK must occur at least 100ns (tCS) before ID_ENB transitions to LOW for
the next set of data.
Figure 65. SPI Timing Diagram
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Table 1. Chip Address
A7 A6 A5 A4 A3 A2 A1 A0
Chip Address 1 1 1 1 1 0 EC(1) 0
ID_ENB = 0 1 1 1 1 1 0 0 0
ID_ENB = 1 1 1 1 1 1 0 1 0
(1) EC — Externally Controlled
Table 2. Control Registers(1)
D7 D6 D5 D4 D3 D2 D1 D0
Mode Control 0 0 0 0 OCL MC2 MC1 MC0
Programmable 3D 0 1 0 0 N3D3 N3D2 N3D1 N3D0
Mono Volume Control 1 0 0 MVC4 MVC3 MVC2 MVC1 MVC0
Left Volume Control 1 1 0 LVC4 LVC3 LVC2 LVC1 LVC0
Right Volume Control 1 1 1 RVC4 RVC3 RVC2 RVC1 RVC0
(1) Bits MVC0 — MVC4 control 32 step volume control for MONO input
Bits LVC0 — LVC4 control 32 step volume control for LEFT input
Bits RVC0 — RVC4 control 32 step volume control for RIGHT input
Bits MC0 — MC2 control 8 distinct modes
Bits N3D3, N3D2, N3D1, N3D0 control programmable 3D function
N3D0 turns the 3D function ON (N3D0 = 1) or OFF (N3D0 = 0), and N3D1 = 0 provides a “wider” aural effect or N3D1 = 1 a “narrower”
aural effect
Bit OCL selects between SE with output capacitor (OCL = 0) or SE without output capacitors (OCL = 1). Default is OCL = 0
Table 3. Programmable TI 3D Audio
N3D3 N3D2
Low 0 0
Medium 0 1
High 1 0
Maximum 1 1
Table 4. Output Mode Selection(1)
Output Mode MC2 MC1 MC0 Handsfree Speaker Output Right HP Output Left HP Output
Number
0 0 0 0 SD SD SD
1 0 0 1 GPX P MUTE MUTE
2 0 1 0 SD GPX P/2 GPX P/2
3 0 1 1 2 X (GLX L + GRX R) MUTE MUTE
4 1 0 0 SD GRX R GLX L
5 1 0 1 2 X (GLX L + GRX R) + GPMUTE MUTE
X P
6 1 1 0 SD GRX R + GPX P/2 GLX L + GPX P/2
7 1 1 1 2 X (GRX R + GLX L) GRX R GLX L
(1) On initial POWER ON, the default mode is 000
P = Phone-in (Mono)
R = RIN
L = LIN
SD = Shutdown
MUTE = Mute Mode
GP= Phone In (Mono) volume control gain
GR= Right stereo volume control gain
GL= Left stereo volume control gain
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Table 5. Volume Control Table(1)
Volume Step xVC4 xVC3 xVC2 xVC1 xVC0 Gain,dB
1 0 0 0 0 0 –54.00
2 0 0 0 0 1 –46.50
3 0 0 0 1 0 –40.50
4 0 0 0 1 1 –34.50
5 0 0 1 0 0 –30.00
6 0 0 1 0 1 –27.00
7 0 0 1 1 0 –24.00
8 0 0 1 1 1 –21.00
9 0 1 0 0 0 –18.00
10 0 1 0 0 1 –15.00
11 0 1 0 1 0 –13.50
12 0 1 0 1 1 –12.00
13 0 1 1 0 0 –10.50
14 0 1 1 0 1 –9.00
15 0 1 1 1 0 –7.50
16 0 1 1 1 1 –6.00
17 1 0 0 0 0 –4.50
18 1 0 0 0 1 –3.00
19 1 0 0 1 0 –1.50
20 1 0 0 1 1 0.00
21 1 0 1 0 0 1.50
22 1 0 1 0 1 3.00
23 1 0 1 1 0 4.50
24 1 0 1 1 1 6.00
25 1 1 0 0 0 7.50
26 1 1 0 0 1 9.00
27 1 1 0 1 0 10.50
28 1 1 0 1 1 12.00
29 1 1 1 0 0 13.50
30 1 1 1 0 1 15.00
31 1 1 1 1 0 16.50
32 1 1 1 1 1 18.00
(1) x = M, L, or R
Gain / Attenuation is from input to output
TI 3D ENHANCEMENT
The LM4946 features a stereo headphone, 3D audio enhancement effect that widens the perceived soundstage
from a stereo audio signal. The 3D audio enhancement creates a perceived spatial effect optimized for stereo
headphone listening. The LM4946 can be programmed for a “narrow” or “wide” soundstage perception. The
narrow soundstage has a more focused approaching sound direction, while the wide soundstage has a spatial,
theater-like effect. Within each of these two modes, four discrete levels of 3D effect that can be programmed:
low, medium, high, and maximum (Table 2,Table 3), each level with an ever increasing aural effect, respectively.
The difference between each level is 3dB.
The external capacitors, shown in Figure 66, are required to enable the 3D effect. The value of the capacitors set
the cutoff frequency of the 3D effect, as shown by Equation 1 and Equation 2. Note that the internal 20kΩ
resistor is nominal.
24 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated
Product Folder Links: LM4946
LM4946 20 k:(internal resistor)
LHP3D1
LHP3D2
RHP3D1
RHP3D2
C3DR
C3DL
R3DL R3DR
C3DR
RHP3D1
LHP3D1
LHP3D2
C3DL
LM4946 20 k:(internal resistor)
RHP3D2
LM4946
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SNAS335E –JANUARY 2006–REVISED AUGUST 2007
Figure 66. External 3D Effect Capacitors
f3DL(-3dB) = 1 / 2π* 20kΩ* C3DL (1)
f3DR(-3dB) = 1 / 2π* 20kΩ* C3DR (2)
Optional resistors R3DL and R3DR can also be added (Figure 67) to affect the -3dB frequency and 3D magnitude.
Figure 67. External RC Network with Optional R3DL and R3DR Resistors
f3DL(-3dB) = 1 / 2π* (20kΩ+ R3DL) * C3DL (3)
f3DR(-3dB) = 1 / 2π* 20kΩ+ R3DR) * C3DR (4)
ΔAV (change in AC gain) = 1 / 1 + M, where M represents some ratio of the nominal internal resistor, 20kΩ(see
example below).
f3dB (3D) = 1 / 2π(1 + M)(20kΩ* C3D) (5)
CEquivalent (new) = C3D / 1 + M (6)
Table 6. Pole Locations
R3D (kΩ) C3D (nF) M ΔAV (dB) f-3dB (3D) Value of C3D new Pole
(optional) (Hz) to keep same Location
pole location (Hz)
(nF)
0 68 0 0 117
1 68 0.05 –0.4 111 64.8 117
5 68 0.25 –1.9 94 54.4 117
10 68 0.50 –3.5 78 45.3 117
20 68 1.00 –6.0 59 34.0 117
Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LM4946
LM4946
SNAS335E –JANUARY 2006–REVISED AUGUST 2007
www.ti.com
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8ΩLOAD
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by an 8Ωload from 158.3mW to 156.4mW. The problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
BRIDGE CONFIGURATION EXPLANATION
The LM4946 drives a load, such as a speaker, connected between outputs, MONO+ and MONO-.
This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage
of this phase difference, a load is placed between MONO- and MONO+ and driven differentially (commonly
referred to as ”bridge mode”). This results in a differential or BTL gain of:
AVD = 2(Rf/ Ri) = 2 (7)
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the single-
ended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces
four times the output power when compared to a single-ended amplifier under the same conditions. This increase
in attainable output power assumes that the amplifier is not current limited and that the output signal is not
clipped.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing MONO- and MONO+ outputs at half-supply. This eliminates the coupling capacitor that single supply,
single-ended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration
forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power
dissipation and may permanently damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power
dissipation. The LM4946 has a pair of bridged-tied amplifiers driving a handsfree speaker, MONO. The maximum
internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From Equation 8,
assuming a 5V power supply and an 8Ωload, the maximum MONO power dissipation is 634mW.
PDMAX-SPKROUT = 4(VDD)2/(2π2RL): Bridge Mode (8)
The LM4946 also has a pair of single-ended amplifiers driving stereo headphones, ROUT and LOUT. The maximum
internal power dissipation for ROUT and LOUT is given by Equation 9 and Equation 10. From Equation 9 and
Equation 10, assuming a 5V power supply and a 32Ωload, the maximum power dissipation for LOUT and ROUT is
40mW, or 80mW total.
PDMAX-LOUT = (VDD)2/ (2π2RL): Single-ended Mode (9)
PDMAX-ROUT = (VDD)2/ (2π2RL): Single-ended Mode (10)
The maximum internal power dissipation of the LM4946 occurs when all three amplifiers pairs are simultaneously
on; and is given by Equation 11.
PDMAX-TOTAL = PDMAX-SPKROUT + PDMAX-LOUT + PDMAX-ROUT (11)
The maximum power dissipation point given by Equation 11 must not exceed the power dissipation given by
Equation 12:
26 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated
Product Folder Links: LM4946
LM4946
www.ti.com
SNAS335E –JANUARY 2006–REVISED AUGUST 2007
PDMAX = (TJMAX - TA) / θJA (12)
The LM4946's TJMAX = 150°C. In the SQ package, the LM4946's θJA is 46°C/W. At any given ambient
temperature TA, use Equation 12 to find the maximum internal power dissipation supported by the IC packaging.
Rearranging Equation 12 and substituting PDMAX-TOTAL for PDMAX' results in Equation 13. This equation gives the
maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4946's
maximum junction temperature.
TA= TJMAX - PDMAX-TOTAL θJA (13)
For a typical application with a 5V power supply and an 8Ωload, the maximum ambient temperature that allows
maximum mono power dissipation without exceeding the maximum junction temperature is approximately 121°C
for the SQ package.
TJMAX = PDMAX-TOTAL θJA + TA(14)
Equation 14 gives the maximum junction temperature TJMAX. If the result violates the LM4946's 150°C, reduce
the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation 11 is greater than that of Equation 12,
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these
measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional
copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC,θCS, and θSA. (θJC is the junction-to-case thermal impedance,
θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance). Refer to the
Typical Performance Characteristics curves for power dissipation information at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 1µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitor and a parallel
0.1µF ceramic capacitor connected between the LM4946's supply pin and ground. Keep the length of leads and
traces that connect capacitors between the LM4946's power supply pin and ground as short as possible.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ciin Figure 1 &Figure 2).
A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many
cases, however, the speakers used in portable systems, whether internal or external, have little ability to
reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little
improvement by using large input capacitor.
The internal input resistor (Ri), minimum 10kΩ, and the input capacitor (Ci) produce a high pass filter cutoff
frequency that is found using Equation 15.
fc= 1 / (2πRiCi) (15)
As an example when using a speaker with a low frequency limit of 150Hz, Ci, using Equation 15 is 0.106µF. The
0.22µF Cishown in Figure 1 allows the LM4946 to drive high efficiency, full range speaker whose response
extends below 40Hz.
Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LM4946
LM4946
SNAS335E –JANUARY 2006–REVISED AUGUST 2007
www.ti.com
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS pin. Since CBdetermines how fast the LM4946 settles to quiescent operation, its
value is critical when minimizing turn-on pops. The slower the LM4946's outputs ramp to their quiescent DC
voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CBequal to 2.2µF along with a small value of Ci
(in the range of 0.1µF to 0.33µF), produces a click-less and pop-less shutdown function. As discussed above,
choosing Cino larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value
should be in the range of 7 to 10 times the value of Ci. This ensures that output transients are eliminated when
power is first applied or the LM4946 resumes operation after shutdown.
28 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated
Product Folder Links: LM4946
3
9
11
10
14
23
8
7
16
3
21
4
20
15
17
6
5
18
1
2
19
24
12
13
22 MONO_IN-
ID_ENB
VOC
VDD
VDD
I2CSPI_VDD
RIN
MONO_IN+
I2CSPI_SEL
SDA
SCL
SCL
SDA
I2CSPI_SEL
MONO_IN+
RIN
I2CSPI_VDD
VDD
VDD
CBYPASS
GND
GND
MONO+
MONO-
LOUT
ROUT
LHP3D1
LHP3D2
VOC
RHP3D1
RHP3D2
GND
ID_ENB
MONO_IN-
VDD
VDD
GND
VDD
VDD
MONO
MONO+
MONO-
RIGHT_IN
CIN4
CIN3
1 PF polarized
1 PF polarized
MONO_IN-
MONO_IN+
CIN2
RIN
GND
LIN
GND
LEFT_IN
0.22 PF polarized
0.22 PF polarized
CIN1
RIN
LIN
LIN
LIN
LM4946SQ
External I2CSPI_VDD
2
1
2
I2CSPI_VDD
SDA/DATA
SCL/CLOCK
ADDR/ID_ENB
NO CONNECT
GND
ID_ENB
SCL
SDA
I2CSPI Header
1
2
J1
1
2
1
2
J3 J4
Speaker
CBYPASS
2.2 PF Polarized
1
2
1
2
1
2
1
2
3
3
J2
J5
1
2
3
3
VOC
SLEEVE
SLEEVE 3
LOUT PIN2
ROUT PIN2
ROUT
LOUT
22
3
1
1
STEREO HEADPHONE JACK
I2CSPI_VDD
1
2
J6
1
2
3
3
VOC
ROUT_PIN2
1
2
J7
1
2
3
3
VOC
LOUT-PIN2
COL
COR
C3DL1
C3DR1
C3DL2
C3DR2
100 PF Polarized
100 PF Polarized
0 Farads
0 Farads ceramic
68 nF ceramic
0 Farads
0 Farads ceramic
68 nF ceramic
I2CSPI_SEL
SPI Mode = 1 - 2
I2C Mode = 2 - 3
R3DL
0:
R3DR
0:
CSUPPLY1
1 PF Polarized
CSUPPLY2
0.10 PF ceramic
CI2CSPI_Supply
1 PF Polarized
LM4946
www.ti.com
SNAS335E –JANUARY 2006–REVISED AUGUST 2007
Demo Board Schematic Diagram
Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: LM4946
LM4946
www.ti.com
SNAS335E –JANUARY 2006–REVISED AUGUST 2007
REVISION HISTORY
Rev Date Description
1.0 01/23/06 Initial release.
1.1 03/05/07 Added the YFQ0025XXX package.
1.2 03/13/07 Edited the 25–pin DSBGA connection
diagram.
1.3 04/24/07 Added the I2C/SPI (1.7V 2.2V ) table.
1.4 04/26/07 Added the numerical values for the X1,
X2, and X3 in the Physical Dimension
section.
1.5 05/02/07 Text edits. Added the YFQ package.
1.6 05/15/07 Added the TM board schematic and
input some text edits.
1.7 05/16/07 More text edits.
1.8 06/06/07 Added Note 11 and more text edits.
1.9 07/31/07 Edited the 5.0V EC table (MONO_IN
Input Impedance and Rin/Lin Input
Impedance).
Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: LM4946
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM4946SQ/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 L4946SQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2014
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM4946SQ/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM4946SQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
24X 0.3
0.2
24X 0.5
0.3
0.8 MAX
(0.1) TYP
0.05
0.00
20X 0.5
2X
2.5
2X 2.5
2.6 0.1
A4.1
3.9 B
4.1
3.9
WQFN - 0.8 mm max heightRTW0024A
PLASTIC QUAD FLATPACK - NO LEAD
4222815/A 03/2016
PIN 1 INDEX AREA
0.08 C
SEATING PLANE
1
613
18
7 12
24 19
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
EXPOSED
THERMAL PAD
25
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
24X (0.25)
24X (0.6)
( ) TYP
VIA
0.2
20X (0.5)
(3.8)
(3.8)
(1.05)
( 2.6)
(R )
TYP
0.05
(1.05)
WQFN - 0.8 mm max heightRTW0024A
PLASTIC QUAD FLATPACK - NO LEAD
4222815/A 03/2016
SYMM
1
6
712
13
18
19
24
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
25
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
24X (0.6)
24X (0.25)
20X (0.5)
(3.8)
(3.8)
4X ( 1.15)
(0.675)
TYP
(0.675) TYP
(R ) TYP0.05
WQFN - 0.8 mm max heightRTW0024A
PLASTIC QUAD FLATPACK - NO LEAD
4222815/A 03/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
6
712
13
18
19
24
25
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