Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS731 SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 TPS731xx Capacitor-Free, NMOS, 150-mA Low Dropout Regulator With Reverse Current Protection 1 Features 3 Description * * * The TPS731xx family of low-dropout (LDO) linear voltage regulators uses a new topology: an NMOS pass element in a voltage-follower configuration. This topology is stable using output capacitors with low equivalent series resistance (ESR), and even allows operation without a capacitor. The device also provides high reverse blockage (low reverse current) and ground pin current that is nearly constant over all values of output current. 1 * * * * * * * * Stable With or Without Capacitors of All Types Input Voltage Range of 1.7 V to 5.5 V Ultralow Dropout Voltage: 30 mV Typical (150-mA Load) Excellent Load Transient Response--With or Without Optional Output Capacitor New NMOS Topology Provides Low Reverse Leakage Current Low Noise: 30 VRMS Typical (10 kHz to 100 kHz) 0.5% Initial Accuracy 1% Overall Accuracy Over Line, Load, and Temperature Less Than 1-A Maximum IQ in Shutdown Mode Thermal Shutdown and Specified Minimum and Maximum Current Limit Protection Available in Multiple Output Voltage Versions - Fixed Outputs of 1.20 V to 5 V - Adjustable Outputs from 1.2 V to 5.5 V - Custom Outputs Available The TPS731xx uses an advanced BiCMOS process to yield high precision while delivering very low dropout voltages and low ground pin current. Current consumption, when not enabled, is less than 1 A and ideal for portable applications. The extremely low output noise (30 VRMS with 0.1-F CNR) is ideal for powering VCOs. These devices are protected by thermal shutdown and foldback current limit. Device Information(1) PART NUMBER TPS731xx PACKAGE SOT-23 (5) BODY SIZE (NOM) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications * * * * * * * Smart Grid and Energy Building Automation Set-Top Boxes Medical Equipment Test and Measurement Point-of-Sale Terminals Wireless Infrastructure Typical Application Circuit for Fixed-Voltage Versions 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS731 SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagrams ..................................... Feature Description................................................. Device Functional Modes........................................ 11 11 12 13 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Applications ................................................ 14 9 Power Supply Recommendations...................... 17 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Example .................................................... 17 10.3 Thermal Considerations ........................................ 17 11 Device and Documentation Support ................. 19 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support...................................................... Documentation Support ....................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 20 20 20 20 12 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision M (August 2009) to Revision N Page * Changed first and third Features bullets ................................................................................................................................ 1 * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 * Changed list of recommended Applications ........................................................................................................................... 1 * Changed Pin Configuration and Functions section; updated table format to meet new standards ...................................... 3 * Changed free-air temperature to junction temperature in Absolute Maximum Ratings condition statement ........................ 4 * Deleted Power Dissipation Ratings table ............................................................................................................................... 4 * Changed Thermal Information table; updated thermal resistance values for all packages .................................................. 4 Changes from Revision L (May, 2009) to Revision M Page * Changed Figure 10 ................................................................................................................................................................ 6 * Added paragraph about recommended start-up sequence to Internal Current Limit section .............................................. 13 * Added paragraph about current foldback and device start-up to Enable Pin and Shutdown section .................................. 13 2 Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 TPS731 www.ti.com SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View IN 1 GND 2 EN 3 5 OUT 4 NR/FB Pin Functions PIN NAME NO. I/O DESCRIPTION IN 1 I GND 2 -- Input supply. EN 3 I Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to Enable Pin and Shutdown for more details. EN can be connected to IN if not used. NR 4 -- Fixed-voltage versions only--connecting an external capacitor to this pin bypasses noise generated by the internal bandgap, reducing output noise to very low levels. FB 4 I Adjustable-voltage version only--this is the input to the control loop error amplifier, and is used to set the output voltage of the device. OUT 5 O Output of the regulator. There are no output capacitor requirements for stability. Ground. Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 3 TPS731 SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating junction temperature range (unless otherwise noted) Voltage Peak output current (1) MIN MAX VIN -0.3 6 VEN -0.3 6 VOUT -0.3 5.5 VNR, VFB -0.3 6 IOUT Temperature (1) V Internally limited Output short-circuit duration Continuous total power dissipation UNIT Indefinite PDISS See Power Dissipation Junction, TJ -55 150 Storage, Tstg -65 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000 Charged device model (CDM), per JEDEC specification JESD22C101, all pins (2) 500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN VIN Input supply voltage range IOUT Output current TJ Operating junction temperature NOM MAX UNIT 1.7 5.5 V 0 150 mA -40 125 C 6.4 Thermal Information TPS731xx THERMAL METRIC (1) DBV (SOT-23) UNIT 5 PINS RJA Junction-to-ambient thermal resistance 207.2 RJC(top) Junction-to-case (top) thermal resistance 124.2 RJB Junction-to-board thermal resistance JT Junction-to-top characterization parameter 13.5 JB Junction-to-board characterization parameter 34.1 (1) 4 35 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 TPS731 www.ti.com SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 6.5 Electrical Characteristics Over operating temperature range (TJ = -40C to +125C), VIN = VOUT(nom) + 0.5 V (1), IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 F, unless otherwise noted. Typical values are at TJ = 25C. PARAMETER TEST CONDITIONS VIN Input voltage range (1) VFB Internal reference (TPS73101) MIN TJ = 25C 1.198 VOUT(VIN) Accuracy (1) Nominal TJ = 25C VIN, IOUT, and T VOUT + 0.5 V VIN 5.5 V; 10 mA IOUT 150 mA (3) Line regulation (1) MAX V 1.210 V 5.5 - VDO V -0.5% 0.5% -1% VOUT(nom) + 0.5 V VIN 5.5 V 1.20 UNIT 5.5 VFB Output voltage range (TPS73101) (2) VOUT TYP 1.7 0.5% 1% 0.01 1 mA IOUT 150 mA 0.002 10 mA IOUT 150 mA 0.0005 %/V VOUT(IOUT) Load regulation VDO Dropout voltage (4) (VIN = VOUT (nom) - 0.1V) IOUT = 150 mA ZO(DO) Output impedance in dropout 1.7 V VIN VOUT + VDO ICL Output current limit VOUT = 0.9 x VOUT(nom) ISC Short-circuit current VOUT = 0 V 200 IREV Reverse leakage current (5) (-IIN) VEN 0.5 V, 0V VIN VOUT 0.1 10 IGND GND pin current IOUT = 10 mA (IQ) 400 550 IOUT = 150 mA 550 750 ISHDN Shutdown current (IGND) VEN 0.5 V, VOUT VIN 5.5 V, -40C TJ 100C 0.02 1 A IFB FB pin current (TPS73101) 0.1 0.3 A 30 100 150 360 58 PSRR Power-supply rejection ratio (ripple rejection) f = 10 kHz, IOUT = 150 mA 37 Vn Output noise voltage BW = 10Hz - 100kHz COUT = 10 F, No CNR 27 x VOUT COUT = 10 F, CNR = 0.01 F 8.5 x VOUT tSTR Startup time VEN(high) EN pin high (enabled) VEN(low) EN pin low (shutdown) IEN(high) EN pin current (enabled) TSD Thermal shutdown temperature TJ Operating junction temperature VOUT = 3 V, RL = 30 COUT = 1 F, CNR = 0.01 F mV 0.25 f = 100 Hz, IOUT = 150 mA (1) (2) (3) (4) (5) %/mA 500 mA mA A A dB VRMS s 600 1.7 VIN 0 0.5 V 0.1 A VEN = 5.5V 0.02 Shutdown Temp increasing 160 Reset Temp decreasing 140 -40 V C 125 C Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater. TPS73101 is tested at VOUT = 2.5 V. Tolerance of external resistors not included in this specification. VDO is not measured for fixed output versions with VOUT(nom) < 1.8 V because minimum VIN = 1.7 V. Fixed-voltage versions only; refer to Application Information for more information. Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 5 TPS731 SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 www.ti.com 6.6 Typical Characteristics For all voltage versions at TJ= 25C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 F, unless otherwise noted. 0.5 0.20 Referred to IOUT = 10 mA 0.4 Change in VOUT (%) 0.3 Change in VOUT (%) Referred to VIN = VOUT + 0.5 V at IOUT = 10 mA 0.15 0.2 0.1 0 -0.1 -0.2 0.10 +25 C +125 C 0.05 0 -0.05 -40 C -0.10 -0.3 -0.15 -0.4 -0.5 -0.20 0 15 30 45 60 75 90 105 120 135 150 0 0.5 1.0 1.5 IOUT (mA) Figure 1. Load Regulation 2.5 3.0 3.5 4.0 4.5 Figure 2. Line Regulation 50 50 TPS73125DBV +125 C 40 30 +25 C 20 10 40 VDO (mV) VDO (mV) 2.0 VIN - VOUT (V) 0 30 60 90 120 30 20 10 -40 C 0 TPS73125DBV IOUT = 150 mA 0 -50 150 -25 0 25 50 75 100 IOUT (mA) Temperature (C) Figure 3. Dropout Voltage vs Output Current Figure 4. Dropout Voltage vs Temperature 30 18 I OUT = 10 mA 16 25 125 I OUT = 10 mA All Voltage Versions Percent of Units (%) Percent of Units (%) 14 20 15 10 12 10 8 6 4 5 2 0 6 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 VOUT Error (%) Worst Case dVOUT/dT (ppm/C) Figure 5. Output Voltage Accuracy Histogram Figure 6. Output Voltage Drift Histogram Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 TPS731 www.ti.com SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 Typical Characteristics (continued) 700 700 600 600 500 500 IGND (mA) IGND (mA) For all voltage versions at TJ= 25C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 F, unless otherwise noted. 400 300 200 IOUT = 150 mA 400 300 VIN = 5.5 V VIN = 4 V VIN = 2 V 200 VIN = 5.5 V VIN = 4 V VIN = 2 V 100 100 0 0 30 60 90 120 0 -50 150 -25 0 I OUT (mA) Figure 7. Ground Pin Current vs Output Current 50 75 100 125 Figure 8. Ground Pin Current vs Temperature 1 400 TPS73133 VENABLE = 0.5 V VIN = VO + 0.5 V 350 Output Current (mA) IGND (mA) 25 Temperature (C) 0.1 ICL 300 250 ISC 200 150 100 50 0.01 -50 -25 0 25 50 75 100 0 -0.5 125 0 0.5 Figure 9. Ground Pin Current in Shutdown vs Temperature 1.5 2.0 2.5 3.0 3.5 Figure 10. Current Limit vs VOUT (Foldback) 500 500 450 450 400 400 Current Limit (mA) Current Limit (mA) 1.0 Output Voltage (V) Temperature (C) 350 300 250 350 300 250 200 200 150 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 150 -50 -25 0 25 50 75 100 125 Temperature (C) VIN (V) Figure 12. Current Limit vs Temperature Figure 11. Current Limit vs VIN Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 7 TPS731 SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 www.ti.com Typical Characteristics (continued) For all voltage versions at TJ= 25C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 F, unless otherwise noted. 90 40 IOUT = 100mA COUT = Any 70 40 35 30 IOUT = 1mA COUT = 10mF 60 50 IOUT = 1mA COUT = 1mF IO = 100mA C O = 1m F IOUT = 1mA COUT = Any 30 20 0 VIN = VOUT + 1V 10 100 1k 10k 25 20 15 Frequency = 10kHz COUT = 10mF VOUT = 2.5V IOUT = 100mA 10 IOUT = 100mA COUT = 10mF IOUT = Any COUT = 0mF 10 PSRR (dB) Ripple Rejection (dB) 80 5 0 100k 1M 0 10M 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VIN - VOUT (V) Frequency (Hz) Figure 14. PSRR (Ripple Rejection) vs VIN - VOUT Figure 13. PSRR (Ripple Rejection) vs Frequency 1 1 COUT = 0mF 0.1 COUT = 10 mF eN (mV/Hz) eN (mV/Hz) C OUT = 1mF COUT = 1mF 0.1 COUT = 0mF COUT = 10mF I OUT = 150 mA 0.01 0.01 10 100 1k 10k 100k I OUT = 150 mA 10 100 Frequency (Hz) 1k 10k 100k Frequency (Hz) Figure 15. Noise Spectral Density CNR = 0 F Figure 16. Noise Spectral Density CNR = 0.01 F 60 140 50 120 VOUT = 5.0 V VOUT = 5.0 V 100 30 VN (RMS) VN (RMS) 40 VOUT = 3.3 V 20 0.1 8 20 CNR = 0.01 mF 10 Hz < Frequency < 100 kHz 0 1 10 VOUT = 3.3 V 60 40 VOUT = 1.5 V 10 0 80 VOUT = 1.5 V COUT = 0 mF 10 Hz < Frequency < 100 kHz 1p 10p 100p 1n COUT (mF) CNR (F) Figure 17. RMS Noise Voltage vs COUT Figure 18. RMS Noise Voltage vs CNR Submit Documentation Feedback 10n Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 TPS731 www.ti.com SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 Typical Characteristics (continued) For all voltage versions at TJ= 25C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 F, unless otherwise noted. VIN = 3.8 V COUT = 0 mF IOUT = 150 mA 40 mV/tick VOUT COUT = 0 mF 50 mV/div VOUT COUT = 1mF 40 mV/tick VOUT COUT = 10 mF 40 mV/tick VOUT COUT = 100 mF 50 mV/div VOUT dVIN 5.5 V 150 mA = 0.5 V/ms dt IOUT 25 mA/tick 4.5 V 1 V/div 10 mA VIN 10 ms/div 10 ms/div Figure 19. TPS73133 Load Transient Response RL = 1 kW COUT = 0 mF Figure 20. TPS73133 Line Transient Response RL = 20W COUT = 10 mF VOUT RL = 20 W 1 V/div C O UT = 1mF R L = 20 W C OUT = 1 mF 1 V/div RL = 1 kW COUT = 0mF RL = 20W COUT = 10mF VOUT 2V 2V VEN 1 V/div 1 V/div 0V 0V VEN 100ms/div 100ms/div Figure 21. TPS73133 Turnon Response Figure 22. TPS73133 Turnoff Response 10 6 5 VIN 4 VOUT IENABLE (nA) Volts 3 2 1 1 0.1 0 -1 0.01 -50 -2 50 ms/div -25 0 25 50 75 100 125 Temperature (C) Figure 23. TPS73133 Power Up and Power Down Figure 24. IENABLE vs Temperature Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 9 TPS731 SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 www.ti.com Typical Characteristics (continued) 60 160 55 140 50 120 45 100 IFB (nA) VN (rms) For all voltage versions at TJ= 25C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 F, unless otherwise noted. 40 60 35 30 25 80 VOUT = 2.5 V COUT = 0 mF R1 = 39.2 kW 10 Hz < Frequency < 100 kHz 20 10p 100p 40 20 1n 10n 0 -50 -25 0 25 50 75 100 CFB (F) Temperature (C) Figure 25. TPS73101 RMS Noise Voltage vs CFB Figure 26. TPS73101 IFB vs Temperature CFB = 10 nF R1 = 39.2 kW COUT = 0 mF 50 mV/div VOUT COUT = 0 mF 125 VOUT = 2.5 V CFB = 10 nF VOUT 100 mV/div COUT = 10 mF 100 mV/div COUT = 10 mF 50 mV/div VOUT VOUT 4.5 V 150 mA 3.5 V VIN 10 mA IOUT 25 ms/div 5 ms/div Figure 27. TPS73101 Load Transient, Adjustable Version 10 Figure 28. TPS73101 Line Transient, Adjustable Version Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 TPS731 www.ti.com SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 7 Detailed Description 7.1 Overview The TPS731xx family of low-dropout linear regulators operates down to an input voltage of 1.7 V and supports output voltages down to 1.2 V while sourcing up to 150 mA of load current. This linear regulator uses an NMOS pass element with an integrated 4-MHz charge pump to provide a dropout voltage of less than 100 mV at full load current. This unique architecture also permits stable regulation over a wide range of output capacitors. In fact, the TPS731xx family of devices does not require any output capacitor for stability. The increased insensitivity to the output capacitor value and type makes this family of linear regulators an ideal choice when powering a load where the effective capacitance is unknown. The TPS731xx family of devices also features a noise reduction (NR) pin that allows for additional reduction of the output noise. With a noise reduction capacitor of 0.01 F connected from the NR pin to GND, the TPS73115 output noise can be as low as 12.75 VRMS. The low noise output featured by the TPS731xx family makes it wellsuited for powering VCOs or any other noise sensitive load. 7.2 Functional Block Diagrams IN 4-MHZ Charge Pump EN Thermal Protection Ref Servo 27 kW Bandgap Error Amp Current Limit OUT 8 kW GND R1 R1 + R2 = 80 kW R2 NR Figure 29. Fixed-Voltage Version Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 11 TPS731 SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 www.ti.com Functional Block Diagrams (continued) IN Standard 1% Resistor Values for Common Output Voltages 4-MHZ Charge Pump EN Thermal Protection Ref Servo 27 kW Bandgap Error Amp GND 80 kW 8 kW R1 R2 1.2 V Short Open 1.5 V 23.2 kW 95.3kW 1.8 V 28.0 kW 56.2 kW 2.5 V 39.2kW 36.5 kW 2.8 V 44.2 kW 33.2 kW 3.0 V 46.4 kW 30.9 kW 3.3 V 52.3 kW 30.1 kW NOTE: VOUT = (R1 + R2)/R2 x 1.204; R1 R2 @ 19 kW for best accuracy. OUT Current Limit VO R1 FB R2 Figure 30. Adjustable-Voltage Version 7.3 Feature Description 7.3.1 Output Noise A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the TPS731xx and it generates approximately 32 VRMS (10 Hz to 100 kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by Equation 1: VOUT (R1 ) R2) V N + 32mVRMS + 32mVRMS R2 VREF (1) Because the value of VREF is 1.2 V, this relationship reduces to Equation 2 for the case of no CNR. mVV V N(mVRMS) + 27 RMS V OUT(V) (2) An internal 27-k resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF, the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2, giving the approximate relationship shown in Equation 3 for CNR = 10 nF. ae mV o VN (mVRMS ) = 8.5 c RMS / VOUT (V) e V o (3) This noise reduction effect is shown as RMS Noise Voltage vs CNR in Typical Characteristics. The TPS73101 adjustable version does not have the NR pin available. However, connecting a feedback capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improves load transient performance. 12 Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 TPS731 www.ti.com SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 Feature Description (continued) The TPS731xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above VOUT. The charge pump generates approximately 250 V of switching noise at approximately 4 MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT. 7.3.2 Internal Current Limit The TPS731xx internal current limit helps protect the regulator during fault conditions. Foldback current limit helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when VOUT drops below 0.5 V. See Figure 10. Note from Figure 10 that approximately -0.2 V of VOUT results in a current limit of 0 mA. Therefore, if OUT is forced below -0.2 V before EN goes high, the device may not start up. In applications that work with both a positive and negative voltage supply, the TPS731xx should be enabled first. 7.3.3 Enable Pin and Shutdown The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5 V (maximum) turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to shutdown the regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated VOUT (see Figure 21). When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster ramp times upon power up. In addition, for VIN ramp times slower than a few milliseconds, the output may overshoot upon power up. The current limit foldback can prevent device start-up under some conditions. See Internal Current Limit. 7.3.4 Reverse Current The NMOS pass element of the TPS731xx provides inherent protection against current flow from the output of the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is not done, the pass element may be left on due to stored charge on the gate. After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. The reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There will be additional current flowing into the OUT pin due to the 80-k internal resistor divider to ground (see Figure 29 and Figure 30). For the TPS73101, reverse current may flow when VFB is more than 1.0 V above VIN. 7.4 Device Functional Modes 7.4.1 Normal Operation With 1.7 V VIN 5.5 V and VEN 1.7 V The TPS731xx family requires an input voltage of at least 1.7 V to function properly and attempt to maintain regulation. When operating the device near 5.5 V, take care to suppress any transient spikes that may exceed the 6.0-V absolute maximum voltage rating. The device should never operate at a DC voltage greater than 5.5 V. Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 13 TPS731 SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS731xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints. These features, combined with low noise and an enable input, make the TPS731xx ideal for portable applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable output version. All versions have thermal and over-current protection, including foldback current limit. 8.2 Typical Applications Figure 31 shows the basic circuit connections for the fixed-voltage models. Figure 32 gives the connections for the adjustable output version (TPS73101). Optional input capacitor. May improve source impedance, noise, or PSRR. VIN Optional output capacitor. May improve load transient, noise, or PSRR. IN VOUT OUT TPS731xx EN GND NR ON OFF Optional bypass capacitor to reduce output noise. Figure 31. Typical Application Circuit for Fixed-Voltage Versions Optional input capacitor. May improve source impedance, noise, or PSRR. VIN IN Optional output capacitor. May improve load transient, noise, or PSRR. TPS73101 EN OFF VOUT OUT GND R1 CFB FB ON R2 VOUT = (R1 + R2) R2 x 1.204 Optional capacitor reduces output noise and improves transient response. Figure 32. Typical Application Circuit for Adjustable-Voltage Version 8.2.1 Design Requirements R1 and R2 can be calculated for any output voltage using the formula shown in Figure 32. Sample resistor values for common output voltages are shown in Figure 30. For best accuracy, make the parallel combination of R1 and R2 approximately equal to 19 k. This 19 k, in addition to the internal 8-k resistor, presents the same impedance to the error amp as the 27-k bandgap reference output. This impedance helps compensate for leakages into the error amp terminals. 14 Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 TPS731 www.ti.com SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 Typical Applications (continued) 8.2.2 Detailed Design Procedure 8.2.2.1 Input and Output Capacitor Requirements Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-F to 1-F, low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the power source. 8.2.2.2 Dropout Voltage The TPS731xx uses an NMOS pass transistor to achieve extremely low dropout. When (VIN - VOUT) is less than the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS(on) of the NMOS pass element. For large step changes in load current, the TPS731xx requires a larger voltage drop from VIN to VOUT to avoid degraded transient response. The boundary of this transient dropout region is approximately twice the DC dropout. Values of VIN - VOUT above this line insure normal transient response. Operating in the transient dropout region can cause an increase in recovery time. The time required to recover from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale instantaneous load change with (VIN - VOUT) close to DC dropout levels], the TPS731xx can take a couple of hundred microseconds to return to the specified regulation accuracy. 8.2.2.3 Transient Response The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration allows operation without an output capacitor for many applications. As with any regulator, the addition of a capacitor (nominal value 1 F) from the output pin (OUT) to ground will reduce undershoot magnitude but increase its duration. In the adjustable version, the addition of a capacitor, CFB, from the OUT pin to the FB pin will also improve the transient response. The TPS731xx does not have active pulldown when the output is overvoltage. This allows applications that connect higher voltage sources, such as alternate power supplies, to the output. This also results in an output overshoot of several percent if the load current quickly drops to zero when a capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determined by output capacitor COUT and the internal and external load resistance. The rate of decay is given by Equation 4 and Equation 5: (Fixed-voltage version) VOUT dV / dt = COUT 80kW P RLOAD (4) (Adjustable-voltage version) VOUT dV / dt = COUT 80kW P (R1 + R2 ) P RLOAD (5) Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 15 TPS731 SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 www.ti.com Typical Applications (continued) 8.2.3 Application Curves RL = 1 kW COUT = 0 mF RL = 20W COUT = 10 mF VOUT RL = 20 W 1 V/div C O UT = 1mF R L = 20 W C OUT = 1 mF 1 V/div RL = 1 kW COUT = 0mF RL = 20W COUT = 10mF VOUT 2V 2V VEN 1 V/div 1 V/div 0V 0V 100ms/div 100ms/div Figure 33. TPS73133 Turnon Response 16 VEN Submit Documentation Feedback Figure 34. TPS73133 Turnoff Response Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 TPS731 www.ti.com SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 9 Power Supply Recommendations These devices are designed to operate from an input voltage supply range between 1.7 V and 5.5 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. 10 Layout 10.1 Layout Guidelines To improve AC performance such as PSRR, output noise, and transient response, it is recommended that the PCB be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the ground pin (GND) of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. Solder pad footprint recommendations for the TPS731xx are presented in Application Bulletin Solder Pad Recommendations for Surface-Mount Devices (SBFA015), available from the TI website at www.ti.com. 10.2 Layout Example VIN GND PLANE VOUT COUT TPS731 CIN R1 GND PLANE R2 EN Figure 35. Example Layout (DBV Package) 10.3 Thermal Considerations Thermal protection disables the output when the junction temperature rises to approximately 160C, allowing the device to cool. When the junction temperature cools to approximately 140C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35C above the maximum expected ambient condition of your application. This produces a worstcase junction temperature of 125C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS731xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS731xx into thermal shutdown degrades device reliability. Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 17 TPS731 SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 www.ti.com Thermal Considerations (continued) 10.3.1 Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Thermal Information table. Using heavier copper will increase the effectiveness in removing heat from the device. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT): PD = (VIN - VOUT ) IOUT (6) Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required output voltage. 18 Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 TPS731 www.ti.com SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Spice Models Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS731 is available through the product folders under Tools & Software. 11.1.2 Device Nomenclature Table 1. Device Nomenclature (1) PRODUCT VOUT TPS731xx yyy z (1) xx is the nominal output voltage (for example, 25 = 2.5 V; 01 = Adjustable). yyy is the package designator. z is the tape and reel quantity (R = 3000, T = 250). For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: * Application report. Solder Pad Recommendations for Surface-Mount Devices. Literature number SBFA015. 11.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS73101 Click here Click here Click here Click here Click here TPS731125 Click here Click here Click here Click here Click here TPS73115 Click here Click here Click here Click here Click here TPS73118 Click here Click here Click here Click here Click here TPS73125 Click here Click here Click here Click here Click here TPS73130 Click here Click here Click here Click here Click here TPS73131 Click here Click here Click here Click here Click here TPS73132 Click here Click here Click here Click here Click here TPS73133 Click here Click here Click here Click here Click here TPS73150 Click here Click here Click here Click here Click here Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 19 TPS731 SBVS034N - SEPTEMBER 2003 - REVISED DECEMBER 2015 www.ti.com 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: TPS731 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS73101DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PWYQ TPS73101DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PWYQ TPS73101DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PWYQ TPS73101DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PWYQ TPS731125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BYX TPS731125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BYX TPS73115DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T31 TPS73115DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T31 TPS73115DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T31 TPS73118DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T32 TPS73118DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T32 TPS73118DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T32 TPS73118DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T32 TPS73125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHWI TPS73125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHWI TPS73125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHWI TPS73125DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHWI Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Aug-2018 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS73130DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T33 TPS73130DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T33 TPS73130DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T33 TPS73131DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BYS TPS73131DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BYS TPS73132DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T52 TPS73132DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T52 TPS73133DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T34 TPS73133DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T34 TPS73133DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T34 TPS73150DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T35 TPS73150DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T35 TPS73150DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T35 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS73101DBVR SOT-23 DBV 5 3000 178.0 9.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 TPS73101DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS731125DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS731125DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS73115DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 TPS73115DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73118DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73118DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73125DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73125DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73130DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73130DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73131DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73131DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73132DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS73132DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS73133DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TPS73133DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS73150DBVR SOT-23 DBV 5 3000 178.0 9.0 TPS73150DBVT SOT-23 DBV 5 250 178.0 9.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 3.23 3.17 1.37 4.0 8.0 Q3 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73101DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73101DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS731125DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS731125DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73115DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73115DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73118DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73118DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73125DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73125DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73130DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73130DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73131DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73131DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73132DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73132DBVT SOT-23 DBV 5 250 203.0 203.0 35.0 TPS73133DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73133DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TPS73150DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS73150DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 Pack Materials-Page 3 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. 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