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TPS731
SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
TPS731xx Capacitor-Free, NMOS, 150-mA Low Dropout Regulator With Reverse Current
Protection
1 Features 3 Description
The TPS731xx family of low-dropout (LDO) linear
1• Stable With or Without Capacitors of All Types voltage regulators uses a new topology: an NMOS
• Input Voltage Range of 1.7 V to 5.5 V pass element in a voltage-follower configuration. This
• Ultralow Dropout Voltage: 30 mV Typical (150-mA topology is stable using output capacitors with low
Load) equivalent series resistance (ESR), and even allows
operation without a capacitor. The device also
• Excellent Load Transient Response—With or provides high reverse blockage (low reverse current)
Without Optional Output Capacitor and ground pin current that is nearly constant over all
• New NMOS Topology Provides Low Reverse values of output current.
Leakage Current The TPS731xx uses an advanced BiCMOS process
• Low Noise: 30 μVRMS Typical (10 kHz to 100 kHz) to yield high precision while delivering very low
• 0.5% Initial Accuracy dropout voltages and low ground pin current. Current
consumption, when not enabled, is less than 1 μA
• 1% Overall Accuracy Over Line, Load, and and ideal for portable applications. The extremely low
Temperature output noise (30 μVRMS with 0.1-μF CNR) is ideal for
• Less Than 1-μA Maximum IQin Shutdown Mode powering VCOs. These devices are protected by
• Thermal Shutdown and Specified Minimum and thermal shutdown and foldback current limit.
Maximum Current Limit Protection Device Information(1)
• Available in Multiple Output Voltage Versions PART NUMBER PACKAGE BODY SIZE (NOM)
– Fixed Outputs of 1.20 V to 5 V TPS731xx SOT-23 (5) 2.90 mm × 1.60 mm
– Adjustable Outputs from 1.2 V to 5.5 V (1) For all available packages, see the orderable addendum at
– Custom Outputs Available the end of the data sheet.
2 Applications
• Smart Grid and Energy
• Building Automation
• Set-Top Boxes
• Medical Equipment
• Test and Measurement
• Point-of-Sale Terminals
• Wireless Infrastructure
Typical Application Circuit for Fixed-Voltage Versions
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS731
SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
www.ti.com
Table of Contents
1 Features.................................................................. 18 Application and Implementation ........................ 14
8.1 Application Information............................................ 14
2 Applications ........................................................... 18.2 Typical Applications ................................................ 14
3 Description............................................................. 19 Power Supply Recommendations...................... 17
4 Revision History..................................................... 210 Layout................................................................... 17
5 Pin Configuration and Functions......................... 310.1 Layout Guidelines ................................................. 17
6 Specifications......................................................... 410.2 Layout Example .................................................... 17
6.1 Absolute Maximum Ratings ...................................... 410.3 Thermal Considerations........................................ 17
6.2 ESD Ratings ............................................................ 411 Device and Documentation Support................. 19
6.3 Recommended Operating Conditions....................... 411.1 Device Support...................................................... 19
6.4 Thermal Information.................................................. 411.2 Documentation Support ....................................... 19
6.5 Electrical Characteristics........................................... 511.3 Related Links ........................................................ 19
6.6 Typical Characteristics.............................................. 611.4 Community Resources.......................................... 20
7 Detailed Description............................................ 11 11.5 Trademarks........................................................... 20
7.1 Overview................................................................. 11 11.6 Electrostatic Discharge Caution............................ 20
7.2 Functional Block Diagrams ..................................... 11 11.7 Glossary................................................................ 20
7.3 Feature Description................................................. 12 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 13 Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (August 2009) to Revision N Page
• Changed first and third Features bullets ................................................................................................................................ 1
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Changed list of recommended Applications........................................................................................................................... 1
• Changed Pin Configuration and Functions section; updated table format to meet new standards ...................................... 3
• Changed free-air temperature to junction temperature in Absolute Maximum Ratings condition statement ........................ 4
• Deleted Power Dissipation Ratings table ............................................................................................................................... 4
• Changed Thermal Information table; updated thermal resistance values for all packages .................................................. 4
Changes from Revision L (May, 2009) to Revision M Page
• Changed Figure 10 ................................................................................................................................................................ 6
• Added paragraph about recommended start-up sequence to Internal Current Limit section .............................................. 13
• Added paragraph about current foldback and device start-up to Enable Pin and Shutdown section.................................. 13
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IN
GND
EN NR/FB
OUT1
2
3 4
5
TPS731
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SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
IN 1 I Input supply.
GND 2 — Ground.
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into
EN 3 I shutdown mode. Refer to Enable Pin and Shutdown for more details. EN can be connected to IN if not
used.
Fixed-voltage versions only—connecting an external capacitor to this pin bypasses noise generated by
NR 4 — the internal bandgap, reducing output noise to very low levels.
Adjustable-voltage version only—this is the input to the control loop error amplifier, and is used to set the
FB 4 I output voltage of the device.
OUT 5 O Output of the regulator. There are no output capacitor requirements for stability.
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SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN –0.3 6
VEN –0.3 6
Voltage V
VOUT –0.3 5.5
VNR, VFB –0.3 6
Peak output current IOUT Internally limited
Output short-circuit duration Indefinite
Continuous total power PDISS See Power Dissipation
dissipation Junction, TJ–55 150
Temperature °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all ±2000
pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22- ±500
C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT
VIN Input supply voltage range 1.7 5.5 V
IOUT Output current 0 150 mA
TJOperating junction temperature –40 125 °C
6.4 Thermal Information TPS731xx
THERMAL METRIC(1) DBV (SOT-23) UNIT
5 PINS
RθJA Junction-to-ambient thermal resistance 207.2
RθJC(top) Junction-to-case (top) thermal resistance 124.2
RθJB Junction-to-board thermal resistance 35 °C/W
ψJT Junction-to-top characterization parameter 13.5
ψJB Junction-to-board characterization parameter 34.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
6.5 Electrical Characteristics
Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(nom) + 0.5 V(1), IOUT = 10 mA, VEN = 1.7 V, and
COUT = 0.1 μF, unless otherwise noted. Typical values are at TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range(1) 1.7 5.5 V
VFB Internal reference (TPS73101) TJ= 25°C 1.198 1.20 1.210 V
Output voltage range (TPS73101)(2) VFB 5.5 – VDO V
Nominal TJ= 25°C –0.5% 0.5%
VOUT Accuracy(1) (3) VOUT + 0.5 V ≤VIN ≤5.5 V;
VIN, IOUT, and T –1% ±0.5% 1%
10 mA ≤IOUT ≤150 mA
ΔVOUT(ΔVIN) Line regulation(1) VOUT(nom) + 0.5 V ≤VIN ≤5.5 V 0.01 %/V
1 mA ≤IOUT ≤150 mA 0.002
ΔVOUT(ΔIOUT) Load regulation %/mA
10 mA ≤IOUT ≤150 mA 0.0005
Dropout voltage(4)
VDO IOUT = 150 mA 30 100 mV
(VIN = VOUT (nom) – 0.1V)
ZO(DO) Output impedance in dropout 1.7 V ≤VIN ≤VOUT + VDO 0.25 Ω
ICL Output current limit VOUT = 0.9 × VOUT(nom) 150 360 500 mA
ISC Short-circuit current VOUT = 0 V 200 mA
IREV Reverse leakage current(5) (–IIN) VEN ≤0.5 V, 0V ≤VIN ≤VOUT 0.1 10 μA
IOUT = 10 mA (IQ) 400 550
IGND GND pin current μA
IOUT = 150 mA 550 750
VEN ≤0.5 V, VOUT ≤VIN ≤5.5 V,
ISHDN Shutdown current (IGND) 0.02 1 μA
–40°C ≤TJ≤100°C
IFB FB pin current (TPS73101) 0.1 0.3 μA
f = 100 Hz, IOUT = 150 mA 58
Power-supply rejection ratio
PSRR dB
(ripple rejection) f = 10 kHz, IOUT = 150 mA 37
COUT = 10 μF, No CNR 27 × VOUT
Output noise voltage
VnμVRMS
BW = 10Hz - 100kHz COUT = 10 μF, CNR = 0.01 μF 8.5 × VOUT
VOUT = 3 V, RL= 30 Ω
tSTR Startup time 600 μs
COUT = 1 μF, CNR = 0.01 μF
VEN(high) EN pin high (enabled) 1.7 VIN V
VEN(low) EN pin low (shutdown) 0 0.5 V
IEN(high) EN pin current (enabled) VEN = 5.5V 0.02 0.1 μA
Shutdown Temp increasing 160
TSD Thermal shutdown temperature °C
Reset Temp decreasing 140
TJOperating junction temperature –40 125 °C
(1) Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.
(2) TPS73101 is tested at VOUT = 2.5 V.
(3) Tolerance of external resistors not included in this specification.
(4) VDO is not measured for fixed output versions with VOUT(nom) < 1.8 V because minimum VIN = 1.7 V.
(5) Fixed-voltage versions only; refer to Application Information for more information.
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30
25
20
15
10
5
0
Percent of Units (%)
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VOUT Error (%)
IOUT = 10 mA
18
16
14
12
10
8
6
4
2
0
Percent of Units (%)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Worst Case dVOUT/dT (ppm/°C)
IOUT = 10 mA
All Voltage Versions
50
40
30
20
10
0
VDO (mV)
0 30 60 90 120 150
IOUT (mA)
+125 °C
TPS73125DBV
+25 °C
-40 °C
0.20
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
Change in VOUT (%)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIN
-VOUT (V)
+125 °C +25 °C
-40 °C
Referred to VIN = VOUT + 0.5 V at IOUT = 10 mA
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
Change in VOUT (%)
0 15 30 45 60 75 90 105 120 135 150
IOUT (mA)
Referred to IOUT = 10 mA
TPS731
SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
www.ti.com
6.6 Typical Characteristics
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
Figure 1. Load Regulation Figure 2. Line Regulation
Figure 3. Dropout Voltage vs Output Current Figure 4. Dropout Voltage vs Temperature
Figure 5. Output Voltage Accuracy Histogram Figure 6. Output Voltage Drift Histogram
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500
450
400
350
300
250
200
150
Current Limit (mA)
1.5 2.5 3.0 3.5 4.0 4.5 5.02.0 5.5
VIN (V)
500
450
400
350
300
250
200
150
Current Limit (mA)
-50 -25 0 25 50 75 100 125
Temperature (°C)
ICL
400
350
300
250
200
150
100
50
0
OutputCurrent(mA)
ISC
-0.5 0 1.0 1.5 2.0 2.5 3.0 3.5
OutputVoltage(V)
0.5
TPS73133
1
0.1
0.01
IGND (mA)
-50 -25 0 25 50 75 100 125
Temperature (°C)
VENABLE = 0.5 V
VIN = VO+ 0.5 V
700
600
500
400
300
200
100
0
IGND (mA)
0 30 60 90 120 150
IOUT (mA)
VIN = 5.5 V
VIN = 4 V
VIN = 2 V
700
600
500
400
300
200
100
0
IGND (mA)
-50 -25 0 25 50 75 100 125
Temperature (°C)
IOUT = 150 mA
VIN = 5.5 V
VIN = 4 V
VIN = 2 V
TPS731
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SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
Typical Characteristics (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
Figure 7. Ground Pin Current vs Output Current Figure 8. Ground Pin Current vs Temperature
Figure 9. Ground Pin Current in Shutdown vs Temperature Figure 10. Current Limit vs VOUT (Foldback)
Figure 12. Current Limit vs Temperature
Figure 11. Current Limit vs VIN
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60
50
40
30
20
10
0
VN(RMS)
COUT (mF)
0.1 1 10
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.5 V
CNR = 0.01 mF
10 Hz < Frequency < 100 kHz
140
120
100
80
60
40
20
0
VN(RMS)
CNR (F)
1p 10p 100p 1n 10n
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.5 V
COUT = 0 mF
10 Hz < Frequency < 100 kHz
1
0.1
0.01
eN(mV/√Hz)
10 100 1k 10k 100k
Frequency (Hz)
COUT = 1mF
COUT = 0mF
COUT = 10mF
IOUT = 150 mA
1
0.1
0.01
eN(mV/√Hz)
10 100 1k 10k 100k
Frequency (Hz)
IOUT = 150 mA
COUT = 1mF
COUT = 0mF
COUT = 10mF
10k10
90
80
70
60
50
40
30
20
10
0
RippleRejection(dB)
100 1k 100k 1M 10M
Frequency(Hz)
I =1mA
OUT
C =1 Fm
OUT
I =Any
OUT
C =0 Fm
OUT
V =V +1V
IN OUT
I =1mA
OUT
C =Any
OUT
I =1mA
OUT
C =10 Fm
OUT
I =100mA
OUT
C =Any
OUT
I =100mA
OUT
C =10 Fm
OUT
I =100mA
O
C =1 Fm
O
40
35
30
25
20
15
10
5
0
PSRR(dB)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V V-(V)
IN OUT
Frequency=10kHz
C =10 F
V =2.5V
I =100mA
m
OUT
OUT
OUT
TPS731
SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
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Typical Characteristics (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
Figure 14. PSRR (Ripple Rejection) vs VIN – VOUT
Figure 13. PSRR (Ripple Rejection) vs Frequency
Figure 15. Noise Spectral Density CNR = 0 μF Figure 16. Noise Spectral Density CNR = 0.01 μF
Figure 17. RMS Noise Voltage vs COUT Figure 18. RMS Noise Voltage vs CNR
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10
1
0.1
0.01
IENABLE (nA)
-50 -25 0 25 50 75 100 125
Temperature (°C)
6
5
4
3
2
1
0
-1
-2
Volts
50 ms/div
VIN
VOUT
100 s/divm
1 V/div
1 V/div
RL= 20W
COU T = 10 Fm
2 V
0 V
RL= 1 kW
COU T = 0 mF
RL= 20 W
CO UT = 1mF
VOUT
VEN
100 s/divm
1 V/div
1 V/div
RL= 20W
COU T = 10 mF
2 V
0 V
RL= 1 kW
COU T = 0 Fm
RL= 20 W
COUT = 1 mF
VOUT
VEN
10 ms/div
40 mV/tick
40 mV/tick
40 mV/tick
25 mA/tick
VIN = 3.8 V C
OUT = 0 mF
COUT = 1mF
COUT = 10 mF
10 mA
150 mA
VOUT
VOUT
VOUT
IOUT
10 ms/div
50 mV/div
50 mV/div
1 V/div
VOUT
VOUT
VIN
IOUT = 150 mA
5.5 V
4.5 V
dVIN
dt
= 0.5 V/ms
COUT = 0 mF
COUT = 100 mF
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SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
Typical Characteristics (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
Figure 19. TPS73133 Load Transient Response Figure 20. TPS73133 Line Transient Response
Figure 21. TPS73133 Turnon Response Figure 22. TPS73133 Turnoff Response
Figure 23. TPS73133 Power Up and Power Down Figure 24. IENABLE vs Temperature
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25 ms/div
50 mV/div
50 mV/div
VOUT
VOUT
IOUT
150 mA
10 mA
COUT = 0 mF
CFB = 10 nF
R1= 39.2 kW
COUT = 10 mF
5ms/div
100 mV/div
100 mV/div
VOUT
VOUT
VIN
4.5 V
3.5 V
COUT = 0 mF
VOUT = 2.5 V
CFB = 10 nF
COUT = 10 mF
60
55
50
45
40
35
30
25
20
VN(rms)
CFB (F)
10p 100p 1n 10n
VOUT = 2.5 V
COUT = 0 mF
R1= 39.2 kW
10 Hz < Frequency < 100 kHz
160
140
120
100
80
60
40
20
0
IFB (nA)
-50 -25 0 25 50 75 100 125
Temperature (°C)
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SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
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Typical Characteristics (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
Figure 26. TPS73101 IFB vs Temperature
Figure 25. TPS73101 RMS Noise Voltage vs CFB
Figure 27. TPS73101 Load Transient, Adjustable Version Figure 28. TPS73101 Line Transient, Adjustable Version
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Servo
Error
Amp
Ref
27 kW
8 kW
Current
Limit
Thermal
Protection
Bandgap
NR
OUT
R1
R2
EN
GND
IN
R1+ R2= 80 kW
4-MHZ
Charge Pump
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SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
7 Detailed Description
7.1 Overview
The TPS731xx family of low-dropout linear regulators operates down to an input voltage of 1.7 V and supports
output voltages down to 1.2 V while sourcing up to 150 mA of load current. This linear regulator uses an NMOS
pass element with an integrated 4-MHz charge pump to provide a dropout voltage of less than 100 mV at full
load current. This unique architecture also permits stable regulation over a wide range of output capacitors. In
fact, the TPS731xx family of devices does not require any output capacitor for stability. The increased
insensitivity to the output capacitor value and type makes this family of linear regulators an ideal choice when
powering a load where the effective capacitance is unknown.
The TPS731xx family of devices also features a noise reduction (NR) pin that allows for additional reduction of
the output noise. With a noise reduction capacitor of 0.01 µF connected from the NR pin to GND, the TPS73115
output noise can be as low as 12.75 µVRMS. The low noise output featured by the TPS731xx family makes it well-
suited for powering VCOs or any other noise sensitive load.
7.2 Functional Block Diagrams
Figure 29. Fixed-Voltage Version
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RMS
N RMS OUT
V
V ( V ) 8.5 V (V)
V
m
æ ö
m = ´
ç ÷
è ø
VN(mVRMS)+27ǒmVRMS
VǓ VOUT(V)
VN+32mVRMS (R1)R2)
R2
+32mVRMS VOUT
VREF
VO
1.2 V
1.5 V
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
R1
Short
23.2 kW
28.0 kW
39.2kW
44.2 kW
46.4 kW
52.3 kW
R2
Open
95.3kW
56.2 kW
36.5 kW
33.2 kW
30.9 kW
30.1 kW
Standard 1%
Resistor Values for
Common Output Voltages
NOTE: VOUT = (R1+ R2)/R2×1.204;
R
1
R2@19 kWfor best
accuracy.
Servo
Error
Amp
Ref
Current
Limit
Thermal
Protection
Bandgap
OUT
FB
R1
R2
EN
GND
IN
80 kW
8 kW
27 kW
4-MHZ
Charge Pump
ǁ
TPS731
SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
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Functional Block Diagrams (continued)
Figure 30. Adjustable-Voltage Version
7.3 Feature Description
7.3.1 Output Noise
A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the
dominant noise source within the TPS731xx and it generates approximately 32 μVRMS (10 Hz to 100 kHz) at the
reference output (NR). The regulator control loop gains up the reference noise with the same gain as the
reference voltage, so that the noise voltage of the regulator is approximately given by Equation 1:
(1)
Because the value of VREF is 1.2 V, this relationship reduces to Equation 2 for the case of no CNR.
(2)
An internal 27-kΩresistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage
reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF,
the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2, giving the
approximate relationship shown in Equation 3 for CNR = 10 nF.
(3)
This noise reduction effect is shown as RMS Noise Voltage vs CNR in Typical Characteristics.
The TPS73101 adjustable version does not have the NR pin available. However, connecting a feedback
capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improves load transient
performance.
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SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
Feature Description (continued)
The TPS731xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of
the NMOS pass element above VOUT. The charge pump generates approximately 250 μV of switching noise at
approximately 4 MHz; however, charge-pump noise contribution is negligible at the output of the regulator for
most values of IOUT and COUT.
7.3.2 Internal Current Limit
The TPS731xx internal current limit helps protect the regulator during fault conditions. Foldback current limit
helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when
VOUT drops below 0.5 V. See Figure 10.
Note from Figure 10 that approximately –0.2 V of VOUT results in a current limit of 0 mA. Therefore, if OUT is
forced below –0.2 V before EN goes high, the device may not start up. In applications that work with both a
positive and negative voltage supply, the TPS731xx should be enabled first.
7.3.3 Enable Pin and Shutdown
The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5 V
(maximum) turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to
shutdown the regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a
regulated VOUT (see Figure 21).
When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after
VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster
ramp times upon power up. In addition, for VIN ramp times slower than a few milliseconds, the output may
overshoot upon power up.
The current limit foldback can prevent device start-up under some conditions. See Internal Current Limit.
7.3.4 Reverse Current
The NMOS pass element of the TPS731xx provides inherent protection against current flow from the output of
the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed
from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is
not done, the pass element may be left on due to stored charge on the gate.
After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. The reverse
current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There will be
additional current flowing into the OUT pin due to the 80-kΩinternal resistor divider to ground (see Figure 29 and
Figure 30).
For the TPS73101, reverse current may flow when VFB is more than 1.0 V above VIN.
7.4 Device Functional Modes
7.4.1 Normal Operation With 1.7 V ≤VIN ≤5.5 V and VEN ≥1.7 V
The TPS731xx family requires an input voltage of at least 1.7 V to function properly and attempt to maintain
regulation.
When operating the device near 5.5 V, take care to suppress any transient spikes that may exceed the 6.0-V
absolute maximum voltage rating. The device should never operate at a DC voltage greater than 5.5 V.
Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS731
TPS73101
GNDEN FB
IN OUT
VIN VOUT
VOUT = x1.204
(R1+ R2)
R2
R1CFB
R2
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
Optionaloutputcapacitor.
Mayimproveloadtransient,
noise,orPSRR.
Optionalcapacitor
reducesoutputnoise
andimproves
transientresponse.
OFF ON
TPS731xx
GNDEN
ON
OFF
NR
IN OUT
VIN VOUT
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
Optionaloutputcapacitor.
Mayimproveloadtransient,
noise,orPSRR.
Optionalbypass
capacitortoreduce
outputnoise.
TPS731
SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS731xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints.
These features, combined with low noise and an enable input, make the TPS731xx ideal for portable
applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable
output version. All versions have thermal and over-current protection, including foldback current limit.
8.2 Typical Applications
Figure 31 shows the basic circuit connections for the fixed-voltage models. Figure 32 gives the connections for
the adjustable output version (TPS73101).
Figure 31. Typical Application Circuit for Fixed-Voltage Versions
Figure 32. Typical Application Circuit for Adjustable-Voltage Version
8.2.1 Design Requirements
R1and R2can be calculated for any output voltage using the formula shown in Figure 32. Sample resistor values
for common output voltages are shown in Figure 30.
For best accuracy, make the parallel combination of R1and R2approximately equal to 19 kΩ. This 19 kΩ, in
addition to the internal 8-kΩresistor, presents the same impedance to the error amp as the 27-kΩbandgap
reference output. This impedance helps compensate for leakages into the error amp terminals.
14 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated
Product Folder Links: TPS731
OUT
OUT 1 2 LOAD
V
dV / dt C 80k (R R ) R
=
´ W +P P
OUT
OUT LOAD
V
dV / dt
C 80k R
=
´ W P
TPS731
www.ti.com
SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
Typical Applications (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to
1-μF, low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and
improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if
large, fast rise-time load transients are anticipated or the device is located several inches from the power source.
8.2.2.2 Dropout Voltage
The TPS731xx uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDS(on) of the NMOS pass element.
For large step changes in load current, the TPS731xx requires a larger voltage drop from VIN to VOUT to avoid
degraded transient response. The boundary of this transient dropout region is approximately twice the DC
dropout. Values of VIN – VOUT above this line insure normal transient response.
Operating in the transient dropout region can cause an increase in recovery time. The time required to recover
from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load
current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale
instantaneous load change with (VIN – VOUT) close to DC dropout levels], the TPS731xx can take a couple of
hundred microseconds to return to the specified regulation accuracy.
8.2.2.3 Transient Response
The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration
allows operation without an output capacitor for many applications. As with any regulator, the addition of a
capacitor (nominal value 1 μF) from the output pin (OUT) to ground will reduce undershoot magnitude but
increase its duration. In the adjustable version, the addition of a capacitor, CFB, from the OUT pin to the FB pin
will also improve the transient response.
The TPS731xx does not have active pulldown when the output is overvoltage. This allows applications that
connect higher voltage sources, such as alternate power supplies, to the output. This also results in an output
overshoot of several percent if the load current quickly drops to zero when a capacitor is connected to the output.
The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determined
by output capacitor COUT and the internal and external load resistance. The rate of decay is given by Equation 4
and Equation 5:
(Fixed-voltage version)
(4)
(Adjustable-voltage version)
(5)
Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS731
100 s/divm
1 V/div
1 V/div
RL= 20W
COU T = 10 Fm
2 V
0 V
RL= 1 kW
COU T = 0 mF
RL= 20 W
CO UT = 1mF
VOUT
VEN
100 s/divm
1 V/div
1 V/div
RL= 20W
COU T = 10 mF
2 V
0 V
RL= 1 kW
COU T = 0 Fm
RL= 20 W
COUT = 1 mF
VOUT
VEN
TPS731
SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
www.ti.com
Typical Applications (continued)
8.2.3 Application Curves
Figure 33. TPS73133 Turnon Response Figure 34. TPS73133 Turnoff Response
16 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated
Product Folder Links: TPS731
EN
VOUT
VIN
GND
PLANE
TPS731
COUT
GND
PLANE
R1R2
CIN
TPS731
www.ti.com
SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range between 1.7 V and 5.5 V. The input
voltage range provides adequate headroom in order for the device to have a regulated output. This input supply
must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
10 Layout
10.1 Layout Guidelines
To improve AC performance such as PSRR, output noise, and transient response, it is recommended that the
PCB be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the
ground pin (GND) of the device. In addition, the ground connection for the bypass capacitor should connect
directly to the GND pin of the device.
Solder pad footprint recommendations for the TPS731xx are presented in Application Bulletin Solder Pad
Recommendations for Surface-Mount Devices (SBFA015), available from the TI website at www.ti.com.
10.2 Layout Example
Figure 35. Example Layout (DBV Package)
10.3 Thermal Considerations
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 35°C above the maximum expected ambient condition of your application. This produces a worst-
case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS731xx has been designed to protect against overload conditions. It
was not intended to replace proper heatsinking. Continuously running the TPS731xx into thermal shutdown
degrades device reliability.
Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS731
D IN OUT OUT
P (V V ) I= - ´
TPS731
SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
www.ti.com
Thermal Considerations (continued)
10.3.1 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Thermal
Information table. Using heavier copper will increase the effectiveness in removing heat from the device.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current times the voltage drop across the output pass element (VIN to VOUT):
(6)
Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required
output voltage.
18 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated
Product Folder Links: TPS731
TPS731
www.ti.com
SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS731 is available through the product folders under Tools
& Software.
11.1.2 Device Nomenclature
Table 1. Device Nomenclature(1)
PRODUCT VOUT
TPS731xx yyy z xx is the nominal output voltage (for example, 25 = 2.5 V; 01 = Adjustable).
yyy is the package designator.
zis the tape and reel quantity (R = 3000, T = 250).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Application report. Solder Pad Recommendations for Surface-Mount Devices. Literature number SBFA015.
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
TPS73101 Click here Click here Click here Click here Click here
TPS731125 Click here Click here Click here Click here Click here
TPS73115 Click here Click here Click here Click here Click here
TPS73118 Click here Click here Click here Click here Click here
TPS73125 Click here Click here Click here Click here Click here
TPS73130 Click here Click here Click here Click here Click here
TPS73131 Click here Click here Click here Click here Click here
TPS73132 Click here Click here Click here Click here Click here
TPS73133 Click here Click here Click here Click here Click here
TPS73150 Click here Click here Click here Click here Click here
Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS731
TPS731
SBVS034N –SEPTEMBER 2003–REVISED DECEMBER 2015
www.ti.com
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated
Product Folder Links: TPS731
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS73101DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PWYQ
TPS73101DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PWYQ
TPS73101DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PWYQ
TPS73101DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PWYQ
TPS731125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BYX
TPS731125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BYX
TPS73115DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T31
TPS73115DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T31
TPS73115DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T31
TPS73118DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T32
TPS73118DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T32
TPS73118DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T32
TPS73118DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T32
TPS73125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHWI
TPS73125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHWI
TPS73125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHWI
TPS73125DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHWI
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS73130DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T33
TPS73130DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T33
TPS73130DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T33
TPS73131DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BYS
TPS73131DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BYS
TPS73132DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T52
TPS73132DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T52
TPS73133DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T34
TPS73133DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T34
TPS73133DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T34
TPS73150DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T35
TPS73150DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T35
TPS73150DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T35
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 3
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS73101DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73101DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS731125DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS731125DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS73115DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TPS73115DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73118DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73118DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73125DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73125DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73130DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73130DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73131DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73131DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73132DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73132DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73133DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73133DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2018
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS73150DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73150DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73101DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73101DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS731125DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS731125DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73115DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73115DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73118DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73118DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73125DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73125DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73130DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73130DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73131DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73131DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73132DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2018
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73132DBVT SOT-23 DBV 5 250 203.0 203.0 35.0
TPS73133DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73133DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73150DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73150DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2018
Pack Materials-Page 3
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
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Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
TPS73132DBVTG4 TPS731125DBVT TPS731125DBVTG4 TPS73132DBVRG4 TPS73101DBVR
TPS73101DBVRG4 TPS73101DBVT TPS73101DBVTG4 TPS73115DBVR TPS73115DBVRG4 TPS73115DBVT
TPS73115DBVTG4 TPS73118DBVR TPS73118DBVRG4 TPS73118DBVT TPS73118DBVTG4 TPS73125DBVR
TPS73125DBVRG4 TPS73125DBVT TPS73125DBVTG4 TPS73130DBVR TPS73130DBVRG4 TPS73130DBVT
TPS73130DBVTG4 TPS73132DBVR TPS73132DBVT TPS73133DBVR TPS73133DBVRG4 TPS73133DBVT
TPS73133DBVTG4 TPS73150DBVR TPS73150DBVRG4 TPS73150DBVT TPS73150DBVTG4 TPS731125DBVR
TPS731125DBVRG4 TPS73131DBVR TPS73131DBVRG4 TPS73131DBVT TPS73131DBVTG4