8-Channel, 1.5 MSPS, 12-Bit and 10-Bit
Parallel ADCs with a Sequencer
AD7938/AD7939
Rev. B
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FEATURES
Throughput rate: 1.5 MSPS
Specified for VDD of 2.7 V to 5.25 V
Power consumption
6 mW maximum at 1.5 MSPS with 3 V supplies
13.5 mW maximum at 1.5 MSPS with 5 V supplies
8 analog input channels with a sequencer
Software-configurable analog inputs
8-channel single-ended inputs
4-channel fully differential inputs
4-channel pseudo differential inputs
7-channel pseudo differential inputs
Accurate on-chip 2.5 V reference
±0.2% maximum @ 25°C, 25 ppm/°C maximum
70 dB SINAD at 50 kHz input frequency
No pipeline delays
High speed parallel interface—word/byte modes
Full shutdown mode: 2 μA maximum
32-lead LFCSP and TQFP packages
FUNCTIONAL BLOCK DIAGRAM
03715-001
V
IN
7
T/H
PARALLEL INTE RFACE/ CONTROL REGIST E R
SEQUENCER
12-/10-BIT
SAR ADC
AND
CONTROL
I/P
MUX
2.5V
VREF
DB0 DB11
V
DRIVE
V
DD
AD7938/AD7939
V
IN
0
AGND
V
REFIN/
V
REFOUT
CLKIN
BUSY
CONVST
CS DGNDRD WR W/B
Figure 1.
GENERAL DESCRIPTION
The AD7938/AD7939 are 12-bit and 10-bit, high speed, low
power, successive approximation (SAR) analog-to-digital
converters (ADCs). The parts operate from a single 2.7 V to
5.25 V power supply and feature throughput rates up to
1.5 MSPS. The parts contain a low noise, wide bandwidth,
differential track-and-hold amplifier that can handle input
frequencies up to 50 MHz.
The AD7938/AD7939 feature eight analog input channels with
a channel sequencer that allows a preprogrammed selection of
channels to be converted sequentially. These parts can operate
with either single-ended, fully differential, or pseudo
differential analog inputs.
The conversion process and data acquisition are controlled
using standard control inputs that allow easy interfacing with
microprocessors and DSPs. The input signal is sampled on the
falling edge of CONVST and the conversion is also initiated at
this point.
The AD7938/AD7939 have an accurate on-chip 2.5 V reference
that can be used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
These parts use advanced design techniques to achieve very
low power dissipation at high throughput rates. They also
feature flexible power management options. An on-chip control
register allows the user to set up different operating conditions,
including analog input range and configuration, output coding,
power management, and channel sequencing.
PRODUCT HIGHLIGHTS
1. High throughput with low power consumption.
2. Eight analog inputs with a channel sequencer.
3. Accurate on-chip 2.5 V reference.
4. Single-ended, pseudo differential, or fully differential
analog inputs that are software selectable.
5. Single-supply operation with VDRIVE function. The VDRIVE
function allows the parallel interface to connect directly to
3 V or 5 V processor systems independent of VDD.
6. No pipeline delay.
7. Accurate control of the sampling instant via a CONVST
input and once-off conversion control.
Table 1. Related Devices
Device No. of Bits No. of Channels Speed
AD7933/AD7934 12/10 4 1.5 MSPS
AD7938-6 12 8 625 kSPS
AD7934-6 12 4 625 kSPS
AD7938/AD7939
Rev. B | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7938 Specifications................................................................. 3
AD7939 Specifications................................................................. 5
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 13
On-Chip Registers.......................................................................... 15
Control Register.......................................................................... 15
Sequencer Operation ................................................................. 16
Shadow Register.......................................................................... 17
Circuit Information........................................................................ 18
Converter Operation.................................................................. 18
ADC Transfer Function............................................................. 18
Typical Connection Diagram ................................................... 19
Analog Input Structure.............................................................. 19
Analog Inputs ............................................................................. 20
Analog Input Selection .............................................................. 22
Reference ..................................................................................... 23
Parallel Interface......................................................................... 25
Power Modes of Operation....................................................... 28
Power vs. Throughput Rate....................................................... 29
Microprocessor Interfacing....................................................... 29
Application Hints ........................................................................... 31
Grounding and Layout .............................................................. 31
PCB Design Guidelines for Chip Scale Package .................... 31
Evaluating AD7938/AD7939 Performance ............................ 31
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 33
REVISION HISTORY
2/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Sequencer Operation Section................................... 16
Updated Outline Dimensions....................................................... 32
7/05—Rev. 0 to Rev. A
Changes to Specifications................................................................ 3
Added Figure 3.................................................................................. 9
Changes to Table 5.......................................................................... 10
Updated Typical Performance Characteristics ........................... 13
Changes to Table 11........................................................................ 16
Changes to Analog Input Structure Section ............................... 18
Changes to Analog Inputs Section ............................................... 19
Changes to Figure 17...................................................................... 17
Changes to Figure 20...................................................................... 18
Changes to Figure 21...................................................................... 19
Changes to Figure 22...................................................................... 19
Changes to Figure 24...................................................................... 19
Changes to Figure 28...................................................................... 21
Changes to Figure 29...................................................................... 21
Changes to Figure 41...................................................................... 28
Changes to Figure 43...................................................................... 28
Changes to Figure 44...................................................................... 29
Changes to Figure 45...................................................................... 29
Changes to Figure 46...................................................................... 29
Updated Outline Dimensions....................................................... 31
Changes to Ordering Guide.......................................................... 32
10/04—Revision 0: Initial Version
AD7938/AD7939
Rev. B | Page 3 of 36
SPECIFICATIONS
AD7938 SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted, fCLKIN= 25.5 MHz, fSAMPLE = 1.5 MSPS;
TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Value1Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 50 kHz sine wave
Signal-to-Noise and Distortion (SINAD)270 dB min Differential mode
68 dB min Single-ended mode
Signal-to-Noise Ratio (SNR)271 dB min Differential mode
69 dB min Single-ended mode
Total Harmonic Distortion (THD)2−73 dB max −85 dB typ, differential mode
−70 dB max −80 dB typ, single-ended mode
Peak Harmonic or Spurious Noise (SFDR)2−73 dB max −82 dB typ
Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz
Second-Order Terms −6 dB typ
Third-Order Terms −90 dB typ
Channel-to-Channel Isolation −85 dB typ fIN = 50 kHz, fNOISE = 300 kHz
Aperture Delay25 ns typ
Aperture Jitter272 ps typ
Full Power Bandwidth250 MHz typ @ 3 dB
10 MHz typ @ 0.1 dB
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity2±1 LSB max Differential mode
±1.5 LSB max Single-ended mode
Differential Nonlinearity2
Differential Mode ±0.95 LSB max Guaranteed no missed codes to 12 bits
Single-Ended Mode −0.95/+1.5 LSB max Guaranteed no missed codes to 12 bits
Single-Ended and Pseudo Differential Input Straight binary output coding
Offset Error2±6 LSB max
Offset Error Match2±1 LSB max
Gain Error2±3 LSB max
Gain Error Match2±1 LSB max
Fully Differential Input Twos complement output coding
Positive Gain Error2±3 LSB max
Positive Gain Error Match2±1 LSB max
Zero-Code Error2±6 LSB max
Zero-Code Error Match2±1 LSB max
Negative Gain Error2±3 LSB max
Negative Gain Error Match2±1 LSB max
ANALOG INPUT
Single-Ended Input Range 0 to VREF V RANGE bit = 0
0 to 2 × VREF V RANGE bit = 1
Pseudo Differential Input Range
VIN+ 0 to VREF V RANGE bit = 0
0 to 2 × VREF V RANGE bit = 1
VIN− −0.3 to +0.7 V typ VDD = 3 V
−0.3 to +1.8 V typ VDD = 5 V
Fully Differential Input Range
VIN+ and VIN− V
CM ± VREF/2 V VCM = common-mode voltage3 = VREF/2
VIN+ and VIN− V
CM ± VREF V VCM = VREF, VIN+ or VIN− must remain within GND/VDD
DC Leakage Current4±1 μA max
Input Capacitance 45 pF typ When in track
10 pF typ When in hold
AD7938/AD7939
Rev. B | Page 4 of 36
Parameter Value1Unit Test Conditions/Comments
REFERENCE INPUT/OUTPUT
VREF Input Voltage52.5 V ±1% for specified performance
DC Leakage Current ±1 μA max
VREFOUT Output Voltage 2.5 V ±0.2% max @ 25°C
VREFOUT Temperature Coefficient 25 ppm/°C max
5 ppm/°C typ
VREF Noise 10 μV typ 0.1 Hz to 10 Hz bandwidth
130 μV typ 0.1 Hz to 1 MHz bandwidth
VREF Output Impedance 10 Ω typ
VREF Input Capacitance 15 pF typ When in track
25 pF typ When in hold
LOGIC INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IIN ±5 μA max Typically 10 nA, VIN = 0 V or VDRIVE
Input Capacitance, CIN410 pF typ
LOGIC OUTPUTS
Output High Voltage, VOH 2.4 V min ISOURCE = 200 μA
Output Low Voltage, VOL 0.4 V max ISINK = 200 μA
Floating-State Leakage Current ±3 μA max
Floating-State Output Capacitance410 pF typ
Output Coding Straight (natural) binary CODING bit = 0
Twos complement CODING bit = 1
CONVERSION RATE
Conversion Time t2 + 13 tCLKIN ns
Track-and-Hold Acquisition Time 125 ns max Full-scale step input
80 ns typ Sine wave input
Throughput Rate 1.5 MSPS max
POWER REQUIREMENTS
VDD 2.7/5.25 V min/max
VDRIVE 2.7/5.25 V min/max
IDD6 Digital inputs = 0 V or VDRIVE
Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V
2.0 mA max VDD = 2.7 V to 3.6 V
Autostandby Mode 0.3 mA typ fSAMPLE = 100 kSPS, VDD = 5 V
160 μA typ Static
Full/Autoshutdown Mode (Static) 2 μA max SCLK on or off
Power Dissipation
Normal Mode (Operational) 13.5 mW max VDD = 5 V
6 mW max VDD = 3 V
Autostandby Mode (Static) 800 μW typ VDD = 5 V
480 μW typ VDD = 3 V
Full/Autoshutdown Mode (Static) 10 μW max VDD = 5 V
6 μW max VDD = 3 V
1 Temperature range is −40°C to +85°C.
2 See the Terminology section.
3 For full common-mode range, see Figure 26 and Figure 27.
4 Sample tested during initial release to ensure compliance.
5 This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference section for more information.
6 Measured with a midscale dc analog input.
AD7938/AD7939
Rev. B | Page 5 of 36
AD7939 SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted, fCLKIN = 25.5 MHz, fSAMPLE= 1.5 MSPS;
TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Value1Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 50 kHz sine wave
Signal-to-Noise and Distortion (SINAD)261 dB min Differential mode
60 dB min Single-ended mode
Total Harmonic Distortion (THD)2−70 dB max
Peak Harmonic or Spurious Noise (SFDR)2−72 dB max
Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz
Second-Order Terms −86 dB typ
Third-Order Terms −90 dB typ
Channel-to-Channel Isolation −75 dB typ fIN = 50 kHz, fNOISe = 300 kHz
Aperture Delay25 ns typ
Aperture Jitter272 ps typ
Full Power Bandwidth250 MHz typ @ 3 dB
10 MHz typ @ 0.1 dB
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity2±0.5 LSB max
Differential Nonlinearity2±0.5 LSB max Guaranteed no missed codes to 10 bits
Single-Ended and Pseudo Differential Input Straight binary output coding
Offset Error2±2 LSB max
Offset Error Match2±0.5 LSB max
Gain Error2±1.5 LSB max
Gain Error Match2±0.5 LSB max
Fully Differential Input Twos complement output coding
Positive Gain Error2±1.5 LSB max
Positive Gain Error Match2±0.5 LSB max
Zero-Code Error2±2 LSB max
Zero-Code Error Match2±0.5 LSB max
Negative Gain Error2±1.5 LSB max
Negative Gain Error Match2±0.5 LSB max
ANALOG INPUT
Single-Ended Input Range 0 to VREF V RANGE bit = 0
0 to 2 × VREF V RANGE bit = 1
Pseudo Differential Input Range
VIN+ 0 to VREF V RANGE bit = 0
0 to 2 × VREF V RANGE bit =1
VIN− −0.3 to +0.7 V typ VDD = 3 V
−0.3 to +1.8 V typ VDD = 5 V
Fully Differential Input Range
VIN+ and VIN− V
CM ± VREF/2 V VCM = common-mode voltage3 = VREF/2
VIN+ and VIN− V
CM ± VREF V VCM = VREF, VIN+ or VIN− must remain within GND/VDD
DC Leakage Current4±1 μA max
Input Capacitance 45 pF typ When in track
10 pF typ When in hold
AD7938/AD7939
Rev. B | Page 6 of 36
Parameter Value1Unit Test Conditions/Comments
REFERENCE INPUT/OUTPUT
VREF Input Voltage52.5 V ±1% for specified performance
DC Leakage Current4±1 μA max External reference applied to pin
VREFOUT Output Voltage 2.5 V ±0.2% max @ 25°C
VREFOUT Temperature Coefficient 25 ppm/°C max
5 ppm/°C typ
VREF Noise 10 μV typ 0.1 Hz to 10 Hz bandwidth
130 μV typ 0.1 Hz to 1 MHz bandwidth
VREF Output Impedance 10 Ω typ
VREF Input Capacitance 15 pF typ When in track
25 pF typ When in hold
LOGIC INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IIN ±5 μA max Typically 10 nA, VIN = 0 V or VDRIVE
Input Capacitance, CIN410 pF typ
LOGIC OUTPUTS
Output High Voltage, VOH 2.4 V min ISOURCE = 200 μA
Output Low Voltage, VOL 0.4 V max ISINK = 200 μA
Floating-State Leakage Current ±3 μA max
Floating-State Output Capacitance410 pF typ
Output Coding Straight (natural) binary CODING bit = 0
Twos complement CODING bit =1
CONVERSION RATE
Conversion Time t2 + 13 tCLKIN ns
Track-and-Hold Acquisition Time 125 ns max Full-scale step input
80 ns typ Sine wave input
Throughput Rate 1.5 MSPS max
POWER REQUIREMENTS
VDD 2.7/5.25 V min/max
VDRIVE 2.7/5.25 V min/max
IDD6 Digital inputs = 0 V or VDRIVE
Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) 2.7 mA max VDD = 4.75 V to 5.25 V
2.0 mA max VDD = 2.7 V to 3.6 V
Autostandby Mode 0.3 mA typ fSAMPLE = 100 kSPS, VDD = 5 V
160 μA typ Static
Full/Autoshutdown Mode (Static) 2 μA max SCLK on or off
Power Dissipation
Normal Mode (Operational) 13.5 mW max VDD = 5 V
6 mW max VDD = 3 V
Autostandby Mode (Static) 800 μW typ VDD = 5 V
480 μW typ VDD = 3 V
Full/Autoshutdown Mode (Static) 10 μW max VDD = 5 V
6 μW max VDD = 3 V
1 Temperature range is −40°C to +85°C.
2 See the Terminology section.
3 For full common-mode range, see Figure 26 and Figure 27.
4 Sample tested during initial release to ensure compliance.
5 This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference section for more details.
6 Measured with a midscale dc analog input.
AD7938/AD7939
Rev. B | Page 7 of 36
TIMING SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted; fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
Parameter1 AD7938 AD7939 Unit Description
fCLKIN2700 700 kHz min CLKIN frequency.
25.5 25.5 MHz max
tQUIET 30 30 ns min Minimum time between end of read and start of next conversion; in other words, time
from when the data bus goes into three-state until the next falling edge of CONVST.
t1 10 10 ns min CONVST pulse width.
t2 15 15 ns min CONVST falling edge to CLKIN falling edge setup time.
t3 50 50 ns max CLKIN falling edge to BUSY rising edge.
t4 0 0 ns min CS to WR setup time.
t5 0 0 ns min
CS to WR hold time.
t6 10 10 ns min
WR pulse width.
t7 10 10 ns min Data setup time before WR.
t8 10 10 ns min Data hold after WR.
t9 10 10 ns min New data valid before falling edge of BUSY.
t10 0 0 ns min CS to RD setup time.
t11 0 0 ns min CS to RD hold time.
t12 30 30 ns min RD pulse width.
t13330 30 ns max Data access time after RD.
t1443 3 ns min Bus relinquish time after RD.
50 50 ns max Bus relinquish time after RD.
t15 0 0 ns min HBEN to RD setup time.
t16 0 0 ns min HBEN to RD hold time.
t17 10 10 ns min Minimum time between reads/writes.
t18 0 0 ns min HBEN to WR setup time.
t19 10 10 ns min HBEN to WR hold time.
t20 40 40 ns max CLKIN falling edge to BUSY falling edge.
t21 15.7 15.7 ns min CLKIN low pulse width.
t22 7.8 7.8 ns min CLKIN high pulse width.
1 Sample tested during initial release to ensure compliance. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 36, Figure 37, Figure 38, and Figure 39).
2 Minimum CLKIN for specified performance, with slower SCLK frequencies performance specifications apply typically.
3 The time required for the output to cross 0.4 V or 2.4 V.
4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
AD7938/AD7939
Rev. B | Page 8 of 36
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to AGND/DGND −0.3 V to +7 V
VDRIVE to AGND/DGND −0.3 V to VDD + 0.3 V
Analog Input Voltage to AGND −0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +7 V
VDRIVE to VDD −0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to VDRIVE + 0.3 V
VREFIN to AGND −0.3 V to VDD + 0.3 V
AGND to DGND −0.3 V to +0.3 V
Input Current to Any Pin
Except Supplies1
±10 mA
Operating Temperature Range
Commercial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 108.2°C/W (LFCSP)
121°C/W (TQFP)
θJC Thermal Impedance 32.71°C/W (LFCSP)
45°C/W (TQFP)
Lead Temperature, Soldering
Reflow Temperature (10 sec to 30 sec) 255°C
ESD 1.5 kV
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD7938/AD7939
Rev. B | Page 9 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
03715-006
PIN 1
INDICATOR
1DB0
2DB1
3DB2
4DB3
5DB4
6DB5
7DB6
8DB7
24 V
IN
1
23 V
IN
0
22 V
REFIN
/V
REFOUT
21 AGND
20 CS
19 RD
18 WR
17 CONVST
9
V
DRIVE
10
DGND
11
DB8/HBEN
12
DB9
13
DB10
14
DB11
15
BUSY
16
CLKIN
32 W/B
31 V
DD
30 V
IN
7
29 V
IN
6
28 V
IN
5
27 V
IN
4
26 V
IN
3
25 V
IN
2
TOP VIEW
(Not to Scale)
AD7938/AD7939
Figure 2. LFCSP Pin Configuration
03715-050
1
2
3
4
5
6
7
8
DB1
DB2
DB3
DB6
DB5
DB4
DB0
DB7
23
V
IN
0
22
V
REFIN
/V
REFOUT
21
AGND
18
WR
19
RD
20
CS
24
V
IN
1
17
CONVST
PIN 1
9
V
DRIVE
10
DGND
11
DB8/HBEN
12
DB9
13
DB10
14
DB11
15
BUSY
16
CLKIN
32
W/B
31
V
DD
30
V
IN
7
29
V
IN
6
28
V
IN
5
27
V
IN
4
26
V
IN
3
25
V
IN
2
AD7938/AD7939
TOP VIEW
(Not to Scale)
Figure 3. TQFP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 8 DB0 to DB7 Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow the control
and shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage
levels for these pins are determined by the VDRIVE input. When reading from the AD7939, the two LSBs (DB0 and
DB1) are always 0 and the LSB of the conversion result is available on DB2.
9 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the
AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that
at VDD but should never exceed VDD by more than 0.3 V.
10 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
11 DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by
CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data
being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four bits of the
data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to
DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel
address bits in Table 10). When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when
reading from the AD7939, the two LSBs of the low byte are 0s, and the remaining six bits are conversion data.
12 to
14
DB9 to
DB11
Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the
control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR. The
logic high/low voltage levels for these pins are determined by the VDRIVE input.
15 BUSY Busy Output. Logic output that indicates the status of the conversion. The BUSY output goes high following the
falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the
result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just
prior to the falling edge of BUSY on the 13th rising edge of CLKIN. See Figure 36.
16 CLKIN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7938/AD7939 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the
conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.
17 CONVST Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track
mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following
power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is used to power up
the device.
18 WR Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.
19 RD Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion
result is placed on the data bus following the falling edge of RD read while CS is low.
20 CS Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to
the internal registers.
AD7938/AD7939
Rev. B | Page 10 of 36
Pin No. Mnemonic Description
21 AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7938/AD7939. All analog input
signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
22 VREFIN/VREFOUT Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC.
The nominal internal reference voltage is 2.5 V, which appears at this pin. It is recommended that this pin is
decoupled to AGND with a 470 nF capacitor. This pin can be overdriven by an external reference. The input voltage
range for the external reference is 0.1 V to VDD; however, care must be taken to ensure that the analog input range
does not exceed VDD + 0.3 V. See the Reference section.
23 to
30
VIN0 to VIN7 Analog Input 0 to Analog Input 7. Eight analog input channels that are multiplexed into the on-chip track-and-
hold. The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four
pseudo differential pairs, or seven pseudo differential inputs by setting the MODE bits in the control register
appropriately (see Table 10). The analog input channel to be converted can either be selected by writing to the
address bits (ADD2 to ADD0) in the control register prior to the conversion or the on-chip sequencer can be used.
The SEQ and SHDW bits in conjunction with the address bits in the control register allow the shadow register to be
programmed. The input range for all input channels can either be 0 V to VREF or 0 V to 2 × VREF, and the coding can
be binary or twos complement, depending on the states of the RANGE and CODING bits in the control register.
Any unused input channels should be connected to AGND to avoid noise pickup.
31 VDD Power Supply Input. The VDD range for the AD7938/AD7939 is 2.7 V to 5.25 V. The supply should be decoupled to
AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor.
32 W/B Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938/AD7939 in 12-bit/10-bit
words on the DB0/DB2 to DB11 pins. When this pin is logic low, byte transfer mode is enabled. Data and the
channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data
lines when operating in byte transfer mode should be tied off to DGND.
AD7938/AD7939
Rev. B | Page 11 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
SUPPLY RIPPLE FREQUENCY (kHz)
PSRR (dB)
–
60
–70
–80
–90
–110
–100
–120
10 210 610410 810 1010
03715-007
100mV p-p SINE WAVE ON V
DD
AND/OR V
DRIVE
NO DECOUPLING
DIFFERENTIAL/SINGLE-ENDED MODE
INT REF
EXT REF
Figure 4. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
NOISE FREQUENCY (kHz)
ISOLATION (dB)
–
70
–75
–90
–85
–80
–95
0 100 400200 300 600500 800700
03715-021
INTERNAL/EXTERNAL REFERENCE
V
DD
=5V
Figure 5. AD7938 Channel-to-Channel Isolation
FREQUENCY (kHz)
SINAD (dB)
80
70
60
50
40
30
20 0 100 400200 300 600500 1000700 800 900
03715-008
F
SAMPLE
=1.5MSPS
RANGE = 0 TO V
REF
DIFFERENTIAL MODE
V
DD
=5V
V
DD
=3V
Figure 6. AD7938 SINAD vs. Analog Input Frequency
for Various Supply Voltages
FREQUENCY (kHz)
0
–10
–20
–50
–40
–30
–90
–100
–80
–70
–60
–110
0
100
200
300
400
500
600
700
03715-009
4096 POINT FFT
V
DD
=5V
F
SAMPLE
=1.5MSPS
F
IN
= 49.62kHz
SINAD = 70.94dB
THD = –90.09dB
DIFFERENTIAL MODE
AMPLITUDE (dB)
Figure 7. AD7938 FFT @ VDD = 5 V
CODE
DNL ERROR (LSB)
1.0
0.8
0.6
0.4
0.2
–0.2
0
–0.8
–0.6
–0.4
–1.0
0 500 20001000 1500 30002500 40003500
03715-010
V
DD
=5V
DIFFERENTIAL MODE
Figure 8. AD7938 Typical DNL @ VDD = 5 V
CODE
INL ERROR (LSB)
1.0
0.8
0.6
0.4
0.2
–0.2
0
–0.8
–0.6
–0.4
–1.0
0 500 20001000 1500 30002500 40003500
03715-011
V
DD
=5V
DIFFERENTIAL MODE
Figure 9. AD7938 Typical INL @ VDD = 5 V
AD7938/AD7939
Rev. B | Page 12 of 36
V
REF
(V)
DNL (LSB)
4
3
1
2
0
–1
0.25 0.50 1.250.75 1.00 2.001.751.50 2.752.502.25
03715-012
SINGLE-ENDED MODE
POSITIVE DNL
NEGATIVE DNL
Figure 10. AD7938 DNL vs. VREF for VDD = 3 V
V
REF
(V)
EFFECTIVE NUMBER OF BITS
12
11
10
8
9
7
6
00.5 1.51.0 2.52.0 4.03.53.0
03715-013
V
DD
=5V
DIFFERENTIAL MODE
V
DD
=5V
SINGLE-ENDED MODE
V
DD
=3V
SINGLE-ENDED MODE
V
DD
=3V
DIFFERENTIAL MODE
Figure 11. AD7938 ENOB vs. VREF
V
REF
(V)
OFFSET (LSB)
0
–0.5
–1.5
–1.0
–3.5
–3.0
–2.5
–2.0
–4.0
–4.5
–5.0
00.5 1.51.0 2.52.0 3.53.0
03715-014
SINGLE-ENDED MODE
V
DD
=5V
V
DD
=3V
Figure 12. AD7938 Offset vs. VREF
CODE
???
10000
9000
7000
8000
3000
4000
5000
6000
2000
1000
0
2046 2047 2048 2049 2050
03715-015
DIFFERENTIAL MODE
3CODES
INTERNAL
REF
9997
CODES
Figure 13. AD7938 Histogram of Codes for
10k Samples @ VDD = 5 V with the Internal Reference
RIPPLE FREQUENCY (kHz)
CMRR (dB)
60
70
80
100
90
110
120
0 200 400 800600 12001000
03715-017
DIFFERENTIAL MODE
Figure 14. CMRR vs. Ripple Frequency with VDD = 5 V and 3 V
AD7938/AD7939
Rev. B | Page 13 of 36
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, 1 LSB below
the first code transition, and full scale, 1 LSB above the last code
transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00…000) to
(00…001) from the ideal (that is, AGND + 1 LSB).
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111…110) to
(111…111) from the ideal (that is, VREF − 1 LSB) after the offset
error has been adjusted out.
Gain Error Match
This is the difference in gain error between any two channels.
Zero-Code Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the
midscale transition (all 0s to all 1s) from the ideal VIN voltage
(that is, VREF).
Zero-Code Error Match
This is the difference in zero-code error between any two
channels.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the last
code transition (011…110) to (011…111) from the ideal (that
is, VREF − 1 LSB) after the zero-code error has been adjusted out.
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREF point. It is the deviation of the first
code transition (100…000) to (100…001) from the ideal (that is,
−VREFIN + 1 LSB) after the zero-code error has been adjusted out.
Negative Gain Error Match
This is the difference in negative gain error between any two
channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale sine wave signal to all seven nonselected input channels
and applying a 50 kHz signal to the selected channel. The
channel-to-channel isolation is defined as the ratio of the power
of the 50 kHz signal on the selected channel to the power of the
noise signal on the unselected channels that appears in the FFT
of this channel. The noise frequency on the unselected channels
varies from 40 kHz to 740 kHz. The noise amplitude is at 2 × VREF,
while the signal amplitude is at 1 × VREF. See Figure 5.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency, fS. The frequency
of the noise varies from 1 kHz to 1 MHz.
PSRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency, fS.
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
AD7938/AD7939
Rev. B | Page 14 of 36
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±½ LSB, after the end of conversion.
Signal-to-Noise and Distortion Ratio (SINAD)
This is the measured ratio of signal-to-noise and distortion at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fSAMPLE/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the
quantization noise.
The theoretical signal-to-noise and distortion ratio for an ideal
N-bit converter with a sine wave input is given by
SINAD = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, SINAD is 74 dB, and for a 10-bit
converter, it is 62 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7938/AD7939, it is defined as
()
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛++++
−=
1
6
54
32
V
VVVVV
THD
22222
log20dB
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fSAMPLE/2 and excluding dc) to the rms value of
the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to 0. For example,
the second-order terms include (fa + fb) and (fa − fb), while
the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb),
and (fa − 2fb).
The AD7938/AD7939 are tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second-order terms are usually
distanced in frequency from the original sine waves while the
third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The intermodulation distortion is
calculated per the THD specification, as the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals, expressed in dB.
AD7938/AD7939
Rev. B | Page 15 of 36
ON-CHIP REGISTERS
The AD7938/AD7939 have two on-chip registers that are
necessary for the operation of the device. These are the control
register, which is used to set up different operating conditions,
and the shadow register, which is used to program the analog
input channels to be converted.
CONTROL REGISTER
The control register on the AD7938/AD7939 is a 12-bit, write-
only register. Data is written to this register using the CS and
WR pins. The control register is shown in Table 7 and the
functions of the bits are described in Table 8 . At power up, the
default bit settings in the control register are all 0s.
Table 7. Control Register Bits
MSB
LSB
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PM1 PM0 CODING REF ADD2 ADD1 ADD0 MODE1 MODE0 SHDW SEQ RANGE
Table 8. Control Register Bit Function Description
Bit No. Mnemonic Description
11, 10 PM1, PM0 Power Management Bits. These two bits are used to select the power mode of operation. The user can choose
between either normal mode or various power-down modes of operation, as shown in Table 9.
9 CODING This bit selects the output coding of the conversion result. If this bit is set to 0, the output coding is straight
(natural) binary. If this bit is set to 1, the output coding is twos complement.
8 REF This bit selects whether the internal or external reference is used to perform the conversion. If this bit is Logic 0, an
external reference should be applied to the VREF pin. If this bit is Logic 1, the internal reference is selected. See the
Reference section.
7 to 5 ADD2 to
ADD0
These three address bits are used to either select which analog input channel is converted in the next conversion if
the sequencer is not used, or to select the final channel in a consecutive sequence when the sequencer is used, as
described in Table 11. The selected input channel is decoded as shown in Table 10.
4, 3 MODE1,
MODE0
The two mode pins select the type of analog input on the eight VIN pins. The AD7938/AD7939 can have either eight
single-ended inputs, four fully differential inputs, four pseudo differential inputs, or seven pseudo differential
inputs. See Table 10.
2 SHDW The SHDW bit in the control register is used in conjunction with the SEQ bit to control the sequencer function and
access the SHDW register. See Table 11.
1 SEQ The SEQ bit in the control register is used in conjunction with the SHDW bit to control the sequencer function and
access the SHDW register. See Table 11.
0 RANGE This bit selects the analog input range of the AD7938/AD7939. If it is set to 0, the analog input range extends from
0 V to VREF. If it is set to 1, the analog input range extends from 0 V to 2 × VREF. When this range is selected, VDD must
be 4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that the analog input remains
within the supply rails. See the Analog Inputs section for more information.
Table 9. Power Mode Selection Using the Power Management Bits in the Control Register
PM1 PM0 Mode Description
0 0 Normal Mode When operating in normal mode, all circuitry is fully powered up at all times.
0 1 Autoshutdown
When operating in autoshutdown mode, the AD7938/AD7939 enter full shutdown mode at the end of
each conversion. In this mode, all circuitry is powered down.
1 0 Autostandby
When the AD7938/AD7939 enter this mode, all circuitry is powered down except for the reference and
reference buffer. This mode is similar to autoshutdown mode, but it allows the part to power up in 7 μs (or
600 ns if an external reference is used). See the Power Modes of Operation section for more information.
1 1 Full Shutdown
When the AD7938/AD7939 enter this mode, all circuitry is powered down. The information in the control
register is retained.
AD7938/AD7939
Rev. B | Page 16 of 36
SEQUENCER OPERATION
The configuration of the SEQ and SHDW bits in the control
register allows the user to select a particular mode of operation
of the sequencer function. Table 11 outlines the four modes of
operation of the sequencer.
Writing to the Control Register to Program the Sequencer
The AD7938/AD7939 need 13 full CLKIN periods to perform a
conversion. If the ADC does not receive the full 13 CLKIN
periods, the conversion aborts. If a conversion is aborted after
applying 12.5 CLKIN periods to the ADC, ensure that a rising
edge of CONVST or a falling edge of CLKIN is applied to the
part before writing to the control register to program the
sequencer. If these conditions are not met, the sequencer will
not be in the correct state to handle being reprogrammed for
another sequence of conversions and the performance of the
converter is not guaranteed.
Table 10. Analog Input Type Selection
MODE0 = 0, MODE1 = 0 MODE0 = 0, MODE1 = 1 MODE0 = 1, MODE1 = 0 MODE0 = 1, MODE1 = 1
Channel Address
Eight Single-Ended
Input Channels
Four Fully Differential
Input Channels
Four Pseudo Differential Input
Channels (Pseudo Mode 1)
Seven Pseudo Differential Input
Channels (Pseudo Mode 2)
ADD2 ADD1 ADD0 VIN+ V
IN− V
IN+ V
IN− V
IN+ V
IN− V
IN+ V
IN−
0 0 0 VIN0 AGND VIN0 VIN1 VIN0 VIN1 VIN0 VIN7
0 0 1 VIN1 AGND VIN1 VIN0 VIN1 VIN0 VIN1 VIN7
0 1 0 VIN2 AGND VIN2 VIN3 VIN2 VIN3 VIN2 VIN7
0 1 1 VIN3 AGND VIN3 VIN2 VIN3 VIN2 VIN3 VIN7
1 0 0 VIN4 AGND VIN4 VIN5 VIN4 VIN5 VIN4 VIN7
1 0 1 VIN5 AGND VIN5 VIN4 VIN5 VIN4 VIN5 VIN7
1 1 0 VIN6 AGND VIN6 VIN7 VIN6 VIN7 VIN6 VIN7
1 1 1 VIN7 AGND VIN7 VIN6 VIN7 VIN6 Not Allowed
Table 11. Sequence Selection
SEQ SHDW Sequence Type
0 0 This configuration is selected when the sequence function is not used. The analog input channel selected on each
individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write
operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function
being used, where each write to the AD7938/AD7939 selects the next channel for conversion.
0 1 This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to
DB7 to the shadow register. This programs the sequence of channels to be converted continuously after each CONVST
falling edge. See the Shadow Register section and Table 12.
1 0 If the SEQ and SHDW bits are set in this way, the sequence function is not interrupted upon completion of the write
operation. This allows other bits in the control register to be altered between conversions while in a sequence without
terminating the cycle.
1 1 This configuration is used in conjunction with the channel address bits (ADD2 to ADD0) to program continuous
conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by
the channel address bits in the control register.
AD7938/AD7939
Rev. B | Page 17 of 36
SHADOW REGISTER
The shadow register on the AD7938/AD7939 is an 8-bit, write-
only register. Data is loaded from DB0 to DB7 on the rising
edge of WR. The eight LSBs load into the shadow register. The
information is written into the shadow register provided that
the SEQ and SHDW bits in the control register were set to 0 and
1, respectively, in the previous write to the control register. Each
bit represents an analog input from Channel 0 through Channel 7.
A sequence of channels can be selected through which the
AD7938/AD7939 cycles with each consecutive conversion after
the write to the shadow register. To select a sequence of
channels to be converted, if operating in single-ended mode or
Pseudo Mode 2, the associated channel bit in the shadow
register must be set for each required analog input. When
operating in fully differential mode or Pseudo Mode 1, the
associated pair of channel bits must be set for each pair of
analog inputs required in the sequence. With each consecutive
CONVST pulse after the sequencer has been set up, the
AD7938/AD7939 progress through the selected channels in
ascending order, beginning with the lowest channel. This
continues until a write operation occurs with the SEQ and
SHDW bits configured in any way except 1, 0 (see Table 11).
When a sequence is set up in fully differential mode or Pseudo
Mode 1, the ADC does not convert on the inverse pairs (that is,
VIN1, VIN0). The bit functions of the shadow register are
outlined in Table 12. See the Analog Input Selection section for
further information on using the sequencer.
Table 12. Shadow Register Bit Functions
MSB LSB
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0
AD7938/AD7939
Rev. B | Page 18 of 36
CIRCUIT INFORMATION
The AD7938/AD7939 are fast, 8-channel, 12-bit and 10-bit,
single-supply, successive approximation analog-to-digital
converters. The parts can operate from a 2.7 V to 5.25 V
power supply and feature throughput rates up to 1.5 MSPS.
The AD7938/AD7939 provide the user with an on-chip track-
and-hold, an accurate internal reference, an analog-to-digital
converter, and a parallel interface housed in a 32-lead LFCSP or
TQFP package.
The AD7938/AD7939 have eight analog input channels that
can be configured to be eight single-ended inputs, four fully
differential pairs, four pseudo differential pairs, or seven pseudo
differential inputs with respect to one common input. There is
an on-chip user-programmable channel sequencer that allows
the user to select a sequence of channels through which the
ADC can progress and cycle with each consecutive falling edge
of CONVST.
The analog input range for the AD7938/AD7939 is 0 V to VREF
or 0 V to 2 × VREF, depending on the status of the RANGE bit in
the control register. The output coding of the ADC can be either
binary or twos complement, depending on the status of the
CODING bit in the control register.
The AD7938/AD7939 provide flexible power management
options to allow the user to achieve the best power performance
for a given throughput rate. These options are selected by
programming the power management bits, PM1 and PM0, in
the control register.
CONVERTER OPERATION
The AD7938/AD7939 are successive approximation ADCs
based around two capacitive digital-to-analog converters
(DACs). Figure 15 and Figure 16 show simplified schematics of
the ADC in acquisition and conversion phase, respectively. The
ADC comprises control logic, an SAR, and two capacitive DACs.
Both figures show the operation of the ADC in differential/pseudo
differential mode. Single-ended mode operation is similar but
VIN− is internally tied to AGND. In acquisition phase, SW3 is
closed, SW1 and SW2 are in Position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
03715-023
V
IN+
V
IN–
A
B
SW1 SW3
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
C
S
C
S
V
REF
SW2
B
A
Figure 15. ADC Acquisition Phase
When the ADC starts a conversion (Figure 16), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the output code of the ADC. The output impedances
of the sources driving the VIN+ and the VIN− pins must match;
otherwise, the two inputs have different settling times, resulting
in errors.
03715-024
V
IN+
V
IN–
A
B
SW1 SW3
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
C
S
C
S
V
REF
SW2
B
A
Figure 16. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7938/AD7939 is either straight
binary or twos complement, depending on the status of the
CODING bit in the control register. The designed code
transitions occur at successive LSB values (1 LSB, 2 LSBs, and
so on) and the LSB size is VREF/4,096 for the AD7938 and
VREF/1,024 for the AD7939. The ideal transfer characteristics
of the AD7938/AD7939 for both straight binary and twos
complement output coding are shown in Figure 17 and Figure 18,
respectively.
03715-025
000...000
111...111
1LSB=V
REF
/4096 (AD7938)
1LSB=V
REF
/1024 (AD7939)
1LSB +V
REF
–1LSB
ANALO G INP UT
ADC CODE
0V
NOTES
1. V
REF
IS EITHER V
REF
OR 2 × V
REF
.
000...001
000...010
111...110
111...000
011...111
Figure 17. AD7938/AD7939 Ideal Transfer Characteristic
with Straight Binary Output Coding
AD7938/AD7939
Rev. B | Page 19 of 36
03715-026
100...000
011...111
1LSB=2×V
REF
/4096 (AD7938)
1LSB=2×V
REF
/1024 (AD7939)
–V
REF
+1LSB V
REF
+V
REF
–1LSB
ADC CODE
100...001
100...010
011...110
000...001
000...000
111...111
Figure 18. AD7938/AD7939 Ideal Transfer Characteristic
with Twos Complement Output Coding and 2 × VREF Range
TYPICAL CONNECTION DIAGRAM
Figure 19 shows a typical connection diagram for the
AD7938/AD7939. The AGND and DGND pins are connected
together at the device for good noise suppression. The
VREFIN/VREFOUT pin is decoupled to AGND with a 0.47 μF
capacitor to avoid noise pickup if the internal reference is used.
Alternatively, VREFIN/VREFOUT can be connected to an external
reference source. In this case, the reference pin should be
decoupled with a 0.1 μF capacitor. In both cases, the analog
input range can either be 0 V to VREF (RANGE bit = 0) or 0 V to
2 × VREF (RANGE bit = 1). The analog input configuration can
be either eight single-ended inputs, four differential pairs, four
pseudo differential pairs, or seven pseudo differential inputs
(see Table 10). The VDD pin is connected to either a 3 V or 5 V
supply. The voltage applied to the VDRIVE input controls the
voltage of the digital interface. Here, it is connected to the same
3 V supply of the microprocessor to allow a 3 V logic interface
(see the Digital Inputs section).
0.1µF 10µF
3V/5
V
SUPPLY
3V
SUPPLY
AD7938/AD7939
0.1µF
0.1µF EXTERNAL V
REF
0.47µF INTERNAL V
REF
AGND
DGND
W/B
CLKIN
CS
V
DRIVE
V
DD
V
REFIN
/V
REFOUT
10µF
2.5V
V
REF
RD
CONVST
WR
BUSY
DB0
DB11/DB9
03715-027
+ +
+ +
+
0 TO V
REF
/
0
TO 2 × V
REF
V
IN
0
V
IN
7
MICROCONTROLLER/
MICROPROCESSOR
Figure 19. Typical Connection Diagram
ANALOG INPUT STRUCTURE
Figure 20 shows the equivalent circuit of the analog input
structure of the AD7938/AD7939 in differential/pseudo
differential mode. In single-ended mode, VIN− is internally
tied to AGND. The four diodes provide ESD protection for the
analog inputs. Care must be taken to ensure that the analog
input signals never exceed the supply rails by more than
300 mV. Doing so causes these diodes to become forward-
biased and start conducting into the substrate. These diodes can
conduct up to 10 mA without causing irreversible damage to
the part.
The C1 capacitors in Figure 20 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the sampling capacitors of the ADC and
typically have a capacitance of 45 pF.
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application.
R1 C2
VIN+
V
DD
C1
D
D
03715-028
R1 C2
VIN–
VDD
C1
D
D
Figure 20. Equivalent Analog Input Circuit,
Conversion Phase: Switches Open, Track Phase: Switches Closed
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of THD that can be
tolerated. The THD increases as the source impedance increases
and performance degrades. Figure 21 and Figure 22 show a
graph of the THD vs. source impedance with a 50 kHz input
tone for both VDD = 5 V and 3 V in single-ended mode and fully
differential mode, respectively.
AD7938/AD7939
Rev. B | Page 20 of 36
R
SOURCE
(Ω)
THD (dB)
–
40
–45
–50
–55
–80
–75
–70
–65
–60
–90
–85
10 100 1k
03715-018
F
IN
= 50kHz
V
DD
=5V
V
DD
=3V
Figure 21. THD vs. Source Impedance in Single-Ended Mode
R
SOURCE
(Ω)
THD (dB)
–
60
–80
–75
–70
–65
–100
–85
–90
–95
10 100 1k
03715-019
F
IN
= 50kHz
V
DD
=5V
V
DD
=3V
Figure 22. THD vs. Source Impedance in Fully Differential Mode
Figure 23 shows a graph of the THD vs. the analog input
frequency for various supplies while sampling at 1.5 MHz
with an SCLK of 25.5 MHz. In this case, the source impedance
is 10 Ω.
INPUT FREQUENCY (kHz)
THD (dB)
–
50
–60
–70
–80
–110
–100
–90
–120
0 100 400200 300 600500 700
03715-020
F
SAMPLE
=1.5MSPS
RANGE = 0 TO V
REF
V
DD
=3V
SINGLE-ENDED MODE
V
DD
=5V/3V
DIFFERENTIAL MODE
V
DD
=5V
SINGLE-ENDED MODE
Figure 23. THD vs. Analog Input Frequency for Various Supply Voltages
ANALOG INPUTS
The AD7938/AD7939 have software-selectable analog input
configurations. The user can choose eight single-ended inputs,
four fully differential pairs, four pseudo differential pairs, or
seven pseudo differential inputs. The analog input
configuration is chosen by setting the MODE0/MODE1 bits in
the internal control register (see Table 10).
Single-Ended Mode
The AD7938/AD7939 can have eight single-ended analog input
channels by setting the MODE0 and MODE1 bits in the control
register to 0. In applications where the signal source has a high
impedance, it is recommended to buffer the analog input before
applying it to the ADC. An op amp suitable for this function is
the AD8021. The analog input range of the AD7938/AD7939
can be programmed to be either 0 V to VREF or 0 V to 2 × VREF.
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it the correct format for the ADC.
Figure 24 shows a typical connection diagram when operating
the ADC in single-ended mode. This diagram shows a bipolar
signal of amplitude ±1.25 V being preconditioned before it is
applied to the AD7938/AD7939. In cases where the analog
input amplitude is ±2.5 V, the 3R resistor can be replaced with a
resistor of value R. The resultant voltage on the analog input of
the AD7938/AD7939 is a signal ranging from 0 V to 5 V. In this
case, the 2 × VREF mode can be used.
0.47µF
+1.25V
V
IN
R
R
R
3R
0V
–
1.25V
+2.5
V
0V
V
IN
0
V
IN
7V
REFOUT
AD7938/
AD7939*
R
*ADDITIONAL PINS OMITTED FOR CLARITY.
03715-031
Figure 24. Single-Ended Mode Connection Diagram
Differential Mode
The AD7938/AD7939 can have four differential analog input
pairs by setting the MODE0 and MODE1 bits in the control
register to 0 and 1, respectively.
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 25 defines the fully differential analog
input of the AD7938/AD7939.
AD7938/AD7939
Rev. B | Page 21 of 36
03715-032
V
REF
p-p V
IN+
V
IN–
V
REF
p-p
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD7938/
AD7939*
COMMON-MODE
VOLTAGE
Figure 25. Differential Input Definition
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN− pins in each
differential pair (that is, VIN+ − VIN−). VIN+ and VIN− should be
simultaneously driven by two signals each of amplitude VREF (or
2 × VREF depending on the range chosen) that are 180° out of
phase. The amplitude of the differential signal is therefore −VREF
to +VREF peak-to-peak (that is, 2 × VREF). This is regardless of
the common mode (CM). The common mode is the average of
the two signals (that is, (VIN+ + VIN−)/2) and is therefore the
voltage on which the two inputs are centered. This results in the
span of each input being CM ± VREF/2. This voltage has to be set
up externally and its range varies with the reference value VREF.
As the value of VREF increases, the common-mode range
decreases. When driving the inputs with an amplifier, the actual
common-mode range is determined by the amplifier’s output
voltage swing.
Figure 26 and Figure 27 show how the common-mode range
typically varies with VREF for a 5 V power supply using the 0 V
to VREF range or 2 × VREF range, respectively. The common
mode must be in this range to guarantee the functionality of
the AD7938/AD7939.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise-free signal of amplitude −VREF to
+VREF, corresponding to the digital codes of 0 to 4096 for the
AD7938 and 0 to 1024 for the AD7939. If the 2 × VREF range is
used, the input signal amplitude extends from −2 VREF to +2 VREF
after conversion.
V
REF
(V)
COMMON-MODE RANGE (V)
3.5
3.0
2.0
1.5
2.5
1.0
0.5
0
00.5 1.51.0 2.0 2.5 3.0
03715-033
T
A
=25°C
Figure 26. Input Common-Mode Range vs. VREF (0 V to VREF Range, VDD = 5 V)
V
REF
(V)
COMMON-MODE RANGE (V)
4.5
4.0
3.0
1.5
2.0
2.5
3.5
1.0
0.5
0
0.1 0.6 1.61.1 2.1 2.6
03715-034
T
A
= 25°C
Figure 27. Input Common-Mode Range vs. VREF (2 × VREF Range, VDD = 5 V)
Driving Differential Inputs
Differential operation requires that VIN+ and VIN− be
simultaneously driven with two equal signals that are 180° out
of phase. The common mode must be set up externally and has
a range that is determined by VREF, the power supply, and the
particular amplifier used to drive the analog inputs. Differential
modes of operation with either an ac or dc input provide the
best THD performance over a wide frequency range. Since not
all applications have a signal preconditioned for differential
operation, there is often a need to perform single-ended-to-
differential conversion.
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential
signal to one of the analog input pairs of the AD7938/AD7939.
The circuit configurations shown in Figure 28 and Figure 29
show how a dual op amp can be used to convert a single-ended
signal into a differential signal for both a bipolar and unipolar
input signal, respectively.
The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. A suitable dual op amp
that can be used in this configuration to provide differential
drive to the AD7938/AD7939 is the AD8022.
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 28 and Figure 29 are optimized for
dc coupling applications requiring best distortion performance.
The differential op amp driver circuit in Figure 28 is configured
to convert and level shift a single-ended, ground-referenced
(bipolar) signal to a differential signal centered at the VREF level
of the ADC.
The circuit configuration shown in Figure 29 converts a
unipolar, single-ended signal into a differential signal.
AD7938/AD7939
Rev. B | Page 22 of 36
220Ω
10kΩ
2×V
REF
p-p
GND
440Ω
220Ω
220Ω
20kΩ
220Ω
27Ω
27Ω
V+
V–
V+
V–
A
V
IN+
V
IN–
V
REF
AD7938/
AD7939
0.47µF
03715-035
3.75V
2.5V
1.25V
3.75V
2.5V
1.25V
+
Figure 28. Dual Op Amp Circuit to Convert a Single-Ended
Bipolar Signal into a Differential Unipolar Signal
10kΩ
V
REF
p-p
V
REF
GND
440Ω
220Ω
220Ω
20kΩ
220Ω
27Ω
27Ω
V+
V–
V+
V–
A
V
IN+
V
IN–
V
REF
AD7938/
AD7939
0.47µF
03715-036
3.75V
2.5V
1.25V
3.75V
2.5V
1.25V
+
Figure 29. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
into a Differential Signal
Another method of driving the AD7938/AD7939 is to use the
AD8138 differential amplifier. The AD8138 can be used as a
single-ended-to-differential amplifier or as a differential-to-
differential amplifier. The device is as easy to use as an op amp
and greatly simplifies differential signal amplification and
driving.
Pseudo Differential Mode
The AD7938/AD7939 can have four pseudo differential pairs
(Pseudo Mode 1) or seven pseudo differential inputs (Pseudo
Mode 2) by setting the MODE0 and MODE1 bits in the control
register to 1, 0 and 1, 1, respectively. In the case of the four
pseudo differential pairs, VIN+ is connected to the signal source,
which must have an amplitude of VREF (or 2 × VREF depending
on the range chosen) to make use of the full dynamic range of
the part. A dc input is applied to the VIN− pin. The voltage
applied to this input provides an offset from ground or a pseudo
ground for the VIN+ input. In the case of the seven pseudo
differential inputs, the seven analog input signals inputs are
referred to a dc voltage applied to VIN7.
The benefit of pseudo differential inputs is that they separate
the analog input signal ground from the ADC ground, allowing
dc common-mode voltages to be cancelled. Typically, this range
can extend from −0.3 V to +0.7 V when VDD = 3 V or −0.3 V to
+1.8 V when VDD = 5 V. Figure 30 shows a connection diagram
for pseudo differential mode.
V
IN+
V
IN–
V
REF
AD7938/
AD7939*
*
ADDITIONAL PINS OMITTED FOR CLARITY.
03715-037
V
REF
p-p
0.47µF
DC INPUT
VOLTAGE +
Figure 30. Pseudo Differential Mode Connection Diagram
ANALOG INPUT SELECTION
As shown in Table 10, users can set up their analog input
configuration by setting the values in the MODE0 and MODE1
bits in the control register. Assuming the configuration has been
chosen, there are different ways of selecting the analog input to
be converted depending on the state of the SEQ and SHDW bits
in the control register.
Traditional Multichannel Operation (SEQ = SHDW = 0)
Any one of eight analog input channels or four pairs of channels
can be selected for conversion in any order by setting the SEQ
and SHDW bits in the control register to 0. The channel to be
converted is selected by writing to the address bits, ADD2 to
ADD0, in the control register to program the multiplexer prior
to the conversion. This mode of operation is that of a traditional
multichannel ADC where each data write selects the next
channel for conversion. Figure 31 shows a flowchart of this
mode of operation. The channel configurations are shown in
Table 10.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION.
SET SEQ = SHDW = 0. SELECT THE DESIRED
CHANNEL TO CONVERT (ADD2 TO ADD0).
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SEQ = SHDW = 0.
03715-038
Figure 31. Traditional Multichannel Operation Flow Chart
AD7938/AD7939
Rev. B | Page 23 of 36
Using the Sequencer: Programmable Sequence
(SEQ = 0, SHDW = 1)
The AD7938/AD7939 can be configured to automatically cycle
through a number of selected channels using the on-chip
programmable sequencer by setting SEQ = 0 and SHDW = 1 in
the control register. The analog input channels to be converted
are selected by setting the relevant bits in the shadow register
to 1 (see Table 12).
Once the shadow register has been programmed with the
required sequence, the next conversion executed is on the
lowest channel programmed in the SHDW register. The next
conversion executed is on the next highest channel in the
sequence and so on. When the last channel in the sequence
is converted, the internal multiplexer returns to the first
channel selected in the shadow register and commences the
sequence again.
It is not necessary to write to the control register again once a
sequencer operation has been initiated. The WR input must be
kept high to ensure that the control register is not accidentally
overwritten or that a sequence operation is not interrupted. If
the control register is written to at any time during the sequence,
ensure that the SEQ and SHDW bits are set to 1, 0 to avoid
interrupting the conversion sequence. The sequence program
remains in force until such time as the AD7938/AD7939 is
written to and the SEQ and SHDW bits are configured with any
bit combination except 1, 0. Figure 32 shows a flow chart of the
programmable sequence operation.
POW ER O N
WRI TE TO T HE CONT ROL REG IST E R TO
SET UP OP ERATING M ODE, ANALOG INPUT
AND OUT P UT CONFIGURATION
SET SEQ = 0 SHDW = 1.
INITIATE A WRITE CYCLE.
THI S WRITE CYCLE I S TO PROGRAM THE SHADO W REGISTER.
SET RE LEVANT BITS TO SELECT
THE CHANNELS TO BE INCLUDED IN T HE S E QUENCE.
SEQ BIT = 1
SHDW BIT = 0
CONT INUOUSLY CONV ERT
CONSECUTIVE
CHANNELS SEL E CTED
WITH EACH CONVST PULSE
BUT ALLOWS T HE RANG E,
CODI NG, ANALOG INP UT TYPE,
ETC BIT S IN THE CONTROL
REGIST E R TO BE CHANGED
WITHOUT INTERRUPTING
THE S E QUENCE.
CONT INUOUSLY CONVE RT
CONSECUTIVE
CHANNELS SEL E CTED
IN THE SHADO W REGIS TER
WI TH EACH CONVST P ULSE.
04751-039
WR = HIGH
SEQ BIT = 0
SHDW BIT = 1
Figure 32. Programmable Sequence Flow Chart
Consecutive Sequence (SEQ = 1, SHDW = 1)
A sequence of consecutive channels can be converted beginning
with Channel 0 and ending with a final channel selected by
writing to the ADD2 to ADD0 bits in the control register. This
is done by setting the SEQ and SHDW bits in the control
register to 1. In this mode, the sequencer can be used without
having to write to the shadow register. To set this mode up, the
next conversion, once the control register is written to, is on
Channel 0, then Channel 1, and so on, until the channel
selected by the address bits (ADD2 to ADD0) is reached. The
cycle begins again provided the WR input is tied high. If low,
the SEQ and SHDW bits must be set to 1, 0 to allow the ADC to
continue its preprogrammed sequence uninterrupted. Figure 33
shows the flowchart of the consecutive sequence mode.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATI NG MODE,ANALOG INPUT
AND OUT PUT CONFIGURATION SELECT
FINAL CHANNEL ( ADD2 TO ADD0) IN
CONSECUTIVE SEQUENCE.
SET SEQ = 1 SHDW = 1.
CONTINUOUSLY CONVERT A CONSECUTIVE
SEQUENCE O F CHANNELS FROM CHANNEL 0
UP TO AND INCLUDI NG THE P RE VIOUSLY
SEL E CTED FINAL CHANNEL ON ADD2 TO ADD0
WITH EACH CONVST PULSE.
SEQ BIT = 1
SHDW BIT = 0
CONTINUOUSLY CONVERT
CONSECUTIVE CHANNELS SELECTED
WITH EACH CONVST PULSE BUT
ALLOWS THE RANGE, CODING, ANALOG
INPUT TYPE, ETC. BITS IN THE
CONTROL REGISTER TO BE CHANGED
WI THOUT INTERRUPTING
THE SEQUENCE.
03715-040
Figure 33. Consecutive Sequence Mode Flow Chart
REFERENCE
The AD7938/AD7939 can operate with either the on-chip
reference or external reference. The internal reference is
selected by setting the REF bit in the internal control register
to 1. A block diagram of the internal reference circuitry is
shown in Figure 34. The internal reference circuitry includes an
on-chip 2.5 V band gap reference and a reference buffer. When
using the internal reference, the VREFIN/VREFOUT pin should be
decoupled to AGND with a 0.47 μF capacitor. This internal
reference not only provides the reference for the analog-to-
digital conversion, but it can also be used externally in the
system. It is recommended that the reference output is buffered
using an external precision op amp before applying it anywhere
in the system.
REFERENCE
AD7938/
AD7939
ADC
BUFFER
03715-041
V
REFIN
/
V
REFOUT
Figure 34. Internal Reference Circuit Block Diagram
AD7938/AD7939
Rev. B | Page 24 of 36
Alternatively, an external reference can be applied to the VREFIN/
VREFOUT pin of the AD7938/AD7939. An external reference
input is selected by setting the REF bit in the internal control
register to 0. The external reference input range is 0.1 V to VDD.
It is important to ensure that, when choosing the reference
value, the maximum analog input range (VIN MAX) is never
greater than VDD + 0.3 V, to comply with the maximum ratings
of the device. For example, if operating in differential mode and
the reference is sourced from VDD, the 0 V to 2 × VREF range
cannot be used. This is because the analog input signal range
now extends to 2 × VDD, which exceeds the maximum rating
conditions. In the pseudo differential modes, the user must
ensure that VREF + (VIN−) ≤ VDD when using the 0 V to VREF range,
or when using the 2 × VREF range that 2 × VREF + (VIN−) ≤ VDD.
In all cases, the specified reference is 2.5 V.
The performance of the part with different reference values is
shown in Figure 10 to Figure 12. The value of the reference sets
the analog input span and the common-mode voltage range.
Errors in the reference source result in gain errors in the
AD7938/AD7939 transfer function and add to specified full-
scale errors on the part.
Table 13 lists examples of suitable voltage references available
from Analog Devices that can be used. Figure 35 shows a typical
connection diagram for an external reference.
Table 13. Examples of Suitable Voltage References
Reference
Output
Voltage (V)
Initial Accuracy
(% Max)
Operating
Current (μA)
AD780 2.5/3 0.04 1000
ADR421 2.5 0.04 500
ADR420 2.048 0.05 500
03715-029
1
AD780
NC
8
2
+V
IN
NC
7
3
GND
6
4
TEMP
5
O/P SELECT
TRIM
V
OUT
V
REF
2.5V
NC
NC
V
DD
NC = NO CONNECT
10nF 0.1µF 0.1µF
0.1µF
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD7938/
AD7939*
Figure 35. Typical VREF Connection Diagram
Digital Inputs
The digital inputs applied to the AD7938/AD7939 are not
limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the VDD + 0.3 V limit as on the analog inputs.
Another advantage of the digital inputs not being restricted by
the VDD + 0.3 V limit is the fact that power supply sequencing
issues are avoided. If any of these inputs are applied before VDD,
there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V was applied prior to VDD.
VDRIVE Input
The AD7938/AD7939 have a VDRIVE feature. VDRIVE controls the
voltage at which the parallel interface operates. VDRIVE allows the
ADC to easily interface to 3 V and 5 V processors.
For example, if the AD7938/AD7939 are operated with an VDD
of 5 V and the VDRIVE pin is powered from a 3 V supply, the
AD7938/AD7939 have better dynamic performance with an
VDD of 5 V while still being able to interface directly to 3 V
processors. Care should be taken to ensure VDRIVE does not
exceed VDD by more than 0.3 V (see the Absolute Maximum
Ratings section).
AD7938/AD7939
Rev. B | Page 25 of 36
PARALLEL INTERFACE
The AD7938/AD7939 have a flexible, high speed, parallel
interface. This interface is 12-bits (AD7938) or 10-bits
(AD7939) wide and is capable of operating in either word
(W/B tied high) or byte (W/B tied low) mode. The CONVST
signal is used to initiate conversions; when operating in
autoshutdown or autostandby mode, it is used to initiate
power-up.
A falling edge on the CONVST signal is used to initiate
conversions and it puts the ADC track-and-hold into track.
Once the CONVST signal goes low, the BUSY signal goes high
for the duration of the conversion. In between conversions,
CONVST must be brought high for a minimum time of t1. This
must happen after the 14th falling edge of CLKIN; otherwise, the
conversion is aborted and the track-and-hold goes back into track.
At the end of the conversion, BUSY goes low and can be used to
activate an interrupt service routine. The CS and RD lines are
then activated in parallel to read the 12- or 10-bits of conversion
data. When power supplies are first applied to the device, a
rising edge on CONVST is necessary to put the track-and-hold
into track. The acquisition time of 125 ns minimum must be
allowed before CONVST is brought low to initiate a conversion.
The ADC then goes into hold on the falling edge of CONVST
and back into track on the 13th rising edge of CLKIN after this
(see Figure 36). When operating the device in autoshutdown or
autostandby mode, where the ADC powers down at the end of
each conversion, a rising edge on the CONVST signal is used to
power up the device.
t
2
t
3
t
20
t
14
t
11
t
9
t
13
t
12
t
10
t
CONVERT
t
ACQUISITION
t
QUIET
t
1
12 345 121314
B
A
DATA
DATAOLD DATADB0 TO DB11
DB0 TO DB11
RD
CS
INTERNAL
TRACK/HOLD
BUSY
CLKIN
CONVST
THREE-STATE
THREE-STATE
WITH CS AND RD TIED LOW
03715-004
Figure 36. AD7938/AD7939 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/B = 1)
AD7938/AD7939
Rev. B | Page 26 of 36
Reading Data from the AD7938/AD7939
With the W/B pin tied logic high, the AD7938/AD7939
interface operates in word mode. In this case, a single read
operation from the device accesses the conversion data-word
on Pins DB0/DB2 to Pin DB11. The DB8/HBEN pin assumes
its DB8 function. With the W/B pin tied to logic low, the
AD7938/AD7939 interface operates in byte mode. In this case,
the DB8/HBEN pin assumes its HBEN function. Conversion
data from the AD7938/AD7939 must be accessed in two read
operations with eight bits of data provided on DB0 to DB7 for
each of the read operations. The HBEN pin determines whether
the read operation accesses the high byte or the low byte of the
12-bit or 10-bit word. For a low byte read, DB0 to DB7 provide
the eight LSBs of the 12-bit word. For 10-bit operation, the two
LSBs of the low byte are 0s, followed by six bits of conversion
data. For a high byte read, DB0 to DB3 provide the four MSBs
of the 12-bit or10-bit word. DB5 to DB7 of the high byte
provide the channel ID. Figure 36 shows the read cycle timing
diagram for a 12-bit or 10-bit transfer. When operating in word
mode, the HBEN input does not exist, and only the first read
operation is required to access data from the device. When
operating in byte mode, the two read cycles shown in Figure 37
are required to access the full data-word from the device.
The CS and RD signals are gated internally and the level is
triggered active low. In either word mode or byte mode, CS and
RD can be tied together because the timing specifications for t10
and t11 are 0 ns minimum. This means the bus is constantly
driven by the AD7938/AD7939.
The data is placed onto the data bus a time t13 after both CS and
RD go low. The RD rising edge can be used to latch data out of
the device. After a time, t14, the data lines become three-stated.
Alternatively, CS and RD can be tied permanently low and the
conversion data is valid and placed onto the data bus a time, t9,
before the falling edge of BUSY.
Note that if RD is pulsed during the conversion time, this
causes a degradation in linearity performance of approximately
0.25 LSB. Reading during conversion by way of tying CS and
RD low does not cause any degradation.
t
11
t
10
t
13
t
15
t
15
t
16
t
16
t
14
t
12
t
17
LOW BYTE HIGH BYTE
DB0 TO DB7
HBEN/DB8
RD
CS
03715-005
Figure 37. AD7938/AD7939 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/B = 0)
AD7938/AD7939
Rev. B | Page 27 of 36
Writing Data to the AD7938/AD7939
With W/B tied logic high, a single write operation transfers the
full data-word on DB0 to DB11 to the control register on the
AD7938/AD7939. The DB8/HBEN pin assumes its DB8
function. Data written to the AD7938/AD7939 should be
provided on the DB0 to DB11 inputs, with DB0 being the LSB
of the data-word. With W/B tied logic low, the
AD7938/AD7939 requires two write operations to transfer a full
12-bit word. DB8/HBEN assumes its HBEN function. Data
written to the AD7938/AD7939 should be provided on the DB0
to DB7 inputs. HBEN determines whether the byte written is
high byte or low byte data. The low byte of the data-word
should be written first with DB0 being the LSB of the full data-
word. For the high byte write, HBEN should be high and the
data on the DB0 input should be data Bit 8 of the 12-bit word.
In both word and byte mode, a single write operation to the
shadow register is always sufficient since it is only eight bits
wide.
Figure 38 shows the write cycle timing diagram of the
AD7938/AD7939 in word mode. When operating in word
mode, the HBEN input does not exist and only one write
operation is required to write the word of data to the device.
Data should be provided on DB0 to DB11. When operating in
byte mode, the two write cycles shown in Figure 39 are required
to write the full data-word to the AD7938/AD7939. In Figure 39,
the first write transfers the lower eight bits of the data-word
from DB0 to DB7, and the second write transfers the upper four
bits of the data-word. When writing to the AD7938/AD7939, the
top four bits in the high byte must be 0s.
The data is latched into the device on the rising edge of WR.
The data needs to be setup a time, t7, before the WR rising edge
and held for a time, t8, after the WR rising edge. The CS and
WR signals are gated internally. CS and WR can be tied
together as the timing specifications for t4 and t5 are 0 ns
minimum (assuming CS and RD have not already been tied
together).
t
8
t
5
t
7
t
6
t
4
DATA
DB0 TO DB11
WR
CS
03715-002
Figure 38. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/B = 1)
t
5
t
4
t
7
t
18
t
18
t
19
t
19
t
8
t
6
t
17
LOW BYTE HIGH BYTE
DB0 TO DB11
HBEN/DB8
WR
CS
03715-003
Figure 39. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/B = 0)
AD7938/AD7939
Rev. B | Page 28 of 36
POWER MODES OF OPERATION
The AD7938/AD7939 have four different power modes of
operation. These modes are designed to provide flexible power
management options. Different options can be chosen to
optimize the power dissipation/throughput rate ratio for
differing applications. The mode of operation is selected by the
power management bits, PM1 and PM0, in the control register,
as detailed in Table 9. When power is first applied to the
AD7938/AD7939, an on-chip, power-on reset circuit ensures
that the default power-up condition is normal mode.
Note that, after power-on, the track-and-hold is in hold mode
and the first rising edge of CONVST places the track-and-hold
into track mode.
Normal Mode (PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate
performance because the user does not have to worry about any
power-up times associated with the AD7938/AD7939. It
remains fully powered up at all times. At power-on reset, this
mode is the default setting in the control register.
Autoshutdown (PM1 = 0; PM0 = 1)
In this mode of operation, the AD7938/AD7939 automatically
enter full shutdown at the end of each conversion, which is
shown at Point A in Figure 36 and Figure 40. In shutdown
mode, all internal circuitry on the device is powered down.
The parts retain information in the control register during
shutdown. The track-and-hold also goes into hold at this point
and remains in hold as long as the device is in shutdown. The
AD7938/AD7939 remains in shutdown mode until the next
rising edge of CONVST (see Point B in Figure 36 or Figure 40).
In order to keep the device in shutdown for as long as possible,
CONVST should idle low between conversions, as shown in
Figure 40. On this rising edge, the part begins to power-up and
the track-and-hold returns to track mode. The power-up time
required is 10 ms minimum regardless of whether the user is
operating with the internal or external reference. The user
should ensure that the power-up time has elapsed before
initiating a conversion.
Autostandby (PM1 = 1; PM0 = 0)
In this mode of operation, the AD7938/AD7939 automatically
enter standby mode at the end of each conversion, which is
shown as Point A in Figure 36. When this mode is entered, all
circuitry on the AD7938/AD7939 is powered down except for
the reference and reference buffer. The track-and-hold goes into
hold at this point also and remains in hold as long as the device
is in standby. The parts remain in standby until the next rising
edge of CONVST powers up the device. The power-up time
required depends on whether the internal or external reference
is used. With an external reference, the power-up time required
is a minimum of 600 ns, while when using the internal
reference, the power-up time required is a minimum of 7 μs.
The user should ensure this power-up time has elapsed before
initiating another conversion as shown in Figure 40. This
rising edge of CONVST also places the track-and-hold back
into track mode.
Full Shutdown Mode (PM1 =1; PM0 = 1)
When this mode is programmed, all circuitry on the
AD7938/AD7939 is powered down upon completion of the
write operation, that is, on the rising edge of WR. The track-
and-hold enters hold mode at this point. The parts retain
the information in the control register while the part is in
shutdown. The AD7938/AD7939 remain in full shutdown
mode, with the track-and-hold in hold mode, until the power
management bits (PM1 and PM0) in the control register are
changed. If a write to the control register occurs while the part
is in full shutdown mode, and the power management bits are
changed to PM0 = PM1 = 0 (normal mode), the part begins to
power up on the WR rising edge and the track-and-hold returns
to track. To ensure the part is fully powered up before a conversion
is initiated, the power-up time of 10 ms minimum should be
allowed before the next CONVST falling edge; otherwise,
invalid data is read.
Note that all power-up times quoted apply with a 470 nF
capacitor on the VREFIN pin.
t
POWER-UP
1 114 14
BUSY
CLKIN
CONVST
03715-049
AB
Figure 40. Autoshutdown/Autostandby Mode
AD7938/AD7939
Rev. B | Page 29 of 36
POWER vs. THROUGHPUT RATE
A considerable advantage of powering the ADC down after a
conversion is that the power consumption of the part is
significantly reduced at lower throughput rates. When using the
different power modes, the AD7938/AD7939 are only powered
up for the duration of the conversion. Therefore, the average
power consumption per cycle is significantly reduced. Figure 41
shows a plot of the power vs. throughput rate when operating in
autostandby mode for both VDD = 5 V and 3 V. For example, if
the maximum CLKIN frequency of 25.5 MHz is used to
minimize the conversion time, this accounts for only 0.525 μs of
the overall cycle time while the AD7938/AD7939 remains in
standby mode for the remainder of the cycle. If the devices run
at a throughput rate of 10 kSPS, for example, the overall cycle
time is 100 μs.
Figure 42 shows a plot of the power vs. throughput rate when
operating in normal mode for both VDD = 5 V and VDD = 3 V. In
both plots, the figures apply when using the internal reference.
If an external reference is used, the power-up time reduces to
600 ns; therefore, the AD7938/AD7939 remain in standby for a
greater time in every cycle. Additionally, the current consumption,
when converting, should be lower than the specified maximum
of 2.7 mA with VDD = 5 V, or 2.0 mA with VDD = 3 V.
THROUGHPUT (kSPS)
POWER (mW)
1.8
0.8
1.0
1.2
1.4
1.6
0
0.6
0.4
0.2
0 20 40 60 80 100 120 140
03715-042
TA= 25°C
VDD =5V
VDD =3V
Figure 41. Power vs. Throughput in
Autostandby Mode Using Internal Reference
THROUGHPUT (kSPS)
POWER (mW)
10
4
5
6
7
8
9
0
3
2
1
0 200 400 600 800 1000 1200 16001400
03715-043
TA= 25°C
VDD =5V
VDD =3V
Figure 42. Power vs. Throughput in Normal Mode Using Internal Reference
MICROPROCESSOR INTERFACING
AD7938/AD7939 to ADSP-21xx Interface
Figure 43 shows the AD7938/AD7939 interfaced to the ADSP-
21xx series of DSPs as a memory-mapped device. A single wait
state may be necessary to interface the AD7938/AD7939 to the
ADSP-21xx depending on the clock speed of the DSP. The wait
state can be programmed via the data memory wait state
control register of the ADSP-21xx (see the ADSP-21xx family
User’s Manual for details). The following instruction reads from
the AD7938/AD7939:
MR = DM (ADC)
where ADC is the address of the AD7938/AD7939.
AD7938/
AD7939*
ADSP-21xx*
WR
RD
DB0 TO DB11
D0 TO D23
A0 TO A15
DMS
IRQ2 BUSY
CS
CONVST
DSP
/
USER SYSTEM
WR
RD
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
DATA BUS
ADDRESS
DECODER
03715-045
Figure 43. Interfacing to the ADSP-21xx
AD7938/AD7939
Rev. B | Page 30 of 36
AD7938/AD7939 to ADSP-21065L Interface
Figure 44 shows a typical interface between the
AD7938/AD7939 and the ADSP-21065L SHARC® processor.
This interface is an example of one of three DMA handshake
modes. The MSX control line is actually three memory select
lines. Internal ADDR25-24 are decoded into MS3 to 0, and these
lines are then asserted as chip selects. The DMAR1 (DMA
request 1) is used in this setup as the interrupt to signal the end
of conversion. The rest of the interface is a standard
handshaking operation.
AD7938/
AD7939*
ADSP-21065L*
WR
DB0 TO DB11
D0 TO D31
ADDR
0
TO ADDR
23
MS
X
DMAR
1
BUSY
CS
CONVST
DSP
/
USER SYSTEM
WR
RDRD
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
03715-046
Figure 44. Interfacing to the ADSP-21065L
AD7938/AD7939 to TMS32020, TMS320C25, and
TMS320C5x Interface
Parallel interfaces between the AD7938/AD7939 and the
TMS32020, TMS320C25, and TMS320C5x family of DSPs are
shown in Figure 45. The memory mapped address chosen for
the AD7938/AD7939 should be chosen to fall in the I/O
memory space of the DSPs. The parallel interface on the
AD7938/AD7939 is fast enough to interface to the TMS32020
with no extra wait states. If high speed glue logic, such as 74AS
devices, is used to drive the RD and the WR lines when
interfacing to the TMS320C25, no wait states are necessary.
However, if slower logic is used, data accesses can be slowed
sufficiently when reading from, and writing to, the part to
require the insertion of one wait state. Extra wait states are
necessary when using the TMS320C5x at their fastest clock
speeds (see the TMS320C5x User’s Guide for details).
Data is read from the ADC using the following instruction
IN D, ADC
where:
D is the data memory address.
ADC is the AD7938/AD7939 address.
AD7938/
AD7939*
TMS32020/
TMS320C25/
TMS320C50*
WR
RD
DB11 TO DB0DMD0 TO DMD15
A0 TO A15
IS
READY
INT
X
BUSY
CSEN
CONVST
DSP
/
USER SYSTEM
TMS320C25
ONLY
R/W
STRB
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
DATA BUS
ADDRESS
DECODER
03715-047
MSC
Figure 45. Interfacing to the TMS32020/TMS320C25/TMS320C5x
AD7938/AD7939 to 80C186 Interface
Figure 46 shows the AD7938/AD7939 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer can
occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7938/AD7939 finish a conversion,
the BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation that also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request is serviced before the completion of the next conversion.
AD7938/
AD7939*
80C186*
WR
DB0 TO DB11
AD0 TO AD15
A16 TO A19
ALE
DRQ1
BUSY
CS
QR
S
CONVST
MICROPROCESSOR/
USER SYSTEM
WR
RDRD
*
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS/DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
03715-048
Figure 46. Interfacing to the 80C186
AD7938/AD7939
Rev. B | Page 31 of 36
APPLICATION HINTS
GROUNDING AND LAYOUT
The printed circuit board that houses the AD7938/AD7939
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily separated.
Generally, a minimum etch technique is best for ground planes
since it gives the best shielding. Digital and analog ground
planes should be joined in only one place, and the connection
should be a star ground point established as close to the ground
pins on the AD7938/AD7939 as possible. Avoid running digital
lines under the device as this couples noise onto the die. The
analog ground plane should be allowed to run under the
AD7938/AD7939 to avoid noise coupling. The power supply
lines to the AD7938/AD7939 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog
inputs. Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best but is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to ground planes,
while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 μF tantalum capacitors in parallel with
0.1 μF capacitors to GND. To achieve the best performance
from these decoupling components, they must be placed as
close as possible to the device, ideally right up against the
device. The 0.1 μF capacitors should have low effective series
resistance (ESR) and effective series inductance (ESI), such as
the common ceramic types or surface-mount types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-32-2) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized. The
bottom of the chip scale package has a thermal pad. The
thermal pad on the printed circuit board should be at least as
large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This ensures that
shorting is avoided. Thermal vias can be used on the printed
circuit board thermal pad to improve thermal performance of
the package. If vias are used, they should be incorporated in the
thermal pad at 1.2 mm pitch grid. The via diameter should be
between 0.3 mm and 0.33 mm, and the via barrel should be
plated with 1 oz copper to plug the via. The user should connect
the printed circuit board thermal pad to AGND.
EVALUATING AD7938/AD7939 PERFORMANCE
The recommended layout for the AD7938/AD7939 is outlined
in the evaluation board documentation. The evaluation board
package includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from the
PC via the evaluation board controller. The evaluation board
controller can be used in conjunction with the AD7938/AD7939
evaluation board, as well as many other Analog Devices evaluation
boards ending in the CB designator, to demonstrate and
evaluate the ac and dc performance of the AD7938/AD7939.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the
AD7938/AD7939. The software and documentation are on the
CD that ships with the evaluation board.
AD7938/AD7939
Rev. B | Page 32 of 36
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12° MAX
1.00
0.85
0.80 SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
0.50
0.40
0.30
3.50 REF
0.50
BSC
PIN 1
INDICATOR TOP
VIEW
5.00
BSC SQ
4.75
BSC SQ 3.25
3.10 SQ
2.95
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
COMP LIANT TO JE DE C S TANDARDS MS-026-ABA
0.45
0.37
0.30
0.80
BSC
LEAD PITCH
7.00
BSC S Q
9.00 BS C S Q
124
25
32
8
9
17
16
1.20
MAX
0.75
0.60
0.45
1.05
1.00
0.95
0.20
0.09
0.08 M AX
COPLANARITY
SEATING
PLANE
0° M IN
7°
3.5°
0°
0.15
0.05
VIEW A
ROTATED 90° CCW
VIEW A
PIN 1
TOP VIEW
(PINS DOWN)
020607-A
Figure 48. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
AD7938/AD7939
Rev. B | Page 33 of 36
ORDERING GUIDE
Model Temperature Range Linearity Error (LSB)1Package Description Package Option
AD7938BCP –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2
AD7938BCP-REEL –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2
AD7938BCP-REEL7 –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2
AD7938BCPZ2–40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2
AD7938BCPZ-REEL72–40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2
AD7938BSU –40°C to +85°C ±1 32-Lead TQFP SU-32-2
AD7938BSU-REEL –40°C to +85°C ±1 32-Lead TQFP SU-32-2
AD7938BSU-REEL7 –40°C to +85°C ±1 32-Lead TQFP SU-32-2
AD7938BSUZ2–40°C to +85°C ±1 32-Lead TQFP SU-32-2
AD7938BSUZ-REEL72–40°C to +85°C ±1 32-Lead TQFP SU-32-2
EVAL-AD7938CB3 Evaluation Board
AD7939BCP –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2
AD7939BCP-REEL –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2
AD7939BCP-REEL7 –40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2
AD7939BCPZ2–40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2
AD7939BCPZ-REEL72–40°C to +85°C ±1 32-Lead LFCSP_VQ CP-32-2
AD7939BSU –40°C to +85°C ±1 32-Lead TQFP SU-32-2
AD7939BSU-REEL –40°C to +85°C ±1 32-Lead TQFP SU-32-2
AD7939BSU-REEL7 –40°C to +85°C ±1 32-Lead TQFP SU-32-2
AD7939BSUZ2–40°C to +85°C ±1 32-Lead TQFP SU-32-2
AD7939BSUZ-REEL72–40°C to +85°C ±1 32-Lead TQFP SU-32-2
EVAL-AD7939CB3 Evaluation Board
EVAL-CONTROL-BRD24 Controller Board
1 Linearity error here refers to integral linearity error.
2 Z = Pb-free part.
3 This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.
4 Evaluation Board Controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the letters
CB. The following needs to be ordered to obtain a complete evaluation kit: the ADC Evaluation Board (for example, EVAL AD7938CB), the EVAL-CONTROL-BRD2, and a
12 V ac transformer. See the relevant evaluation board data sheet for more details.
AD7938/AD7939
Rev. B | Page 34 of 36
NOTES
AD7938/AD7939
Rev. B | Page 35 of 36
NOTES
AD7938/AD7939
Rev. B | Page 36 of 36
NOTES
©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03715-0-2/07(B)
