v1.3 ProASIC3 Flash Family FPGAs (R) with Optional Soft ARM(R) Support Features and Benefits High Capacity * 15 k to 1 M System Gates * Up to 144 kbits of True Dual-Port SRAM * Up to 300 User I/Os Reprogrammable Flash Technology * * * * 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live at Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design when Powered Off High Performance * 350 MHz System Performance * 3.3 V, 66 MHz 64-Bit PCI * Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V * Bank-Selectable I/O Voltages--up to 4 Banks per Chip * Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS 2.5 V / 5.0 V Input * Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above) * I/O Registers on Input, Output, and Enable Paths * Hot-Swappable and Cold Sparing I/Os * Programmable Output Slew Rate and Drive Strength * Weak Pull-Up/-Down * IEEE 1149.1 (JTAG) Boundary Scan Test * Pin-Compatible Packages across the ProASIC3 Family Clock Conditioning Circuit (CCC) and PLL In-System Programming (ISP) and Security * Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM-enabled ProASIC(R)3 devices) via JTAG (IEEE 1532-compliant) * FlashLock(R) to Secure FPGA Contents Low Power * Six CCC Blocks, One with an Integrated PLL * Configurable Phase-Shift, Multiply/Divide, Capabilities and External Feedback * Wide Input Frequency Range (1.5 MHz to 350 MHz) Delay Embedded Memory * 1 kbit of FlashROM User Nonvolatile Memory * SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations) * True Dual-Port SRAM (except x18) * Core Voltage for Low Power * Support for 1.5 V-Only Systems * Low-Impedance Flash Switches High-Performance Routing Hierarchy ARM Processor Support in ProASIC3 FPGAs * Segmented, Hierarchical Routing and Clock Structure * M1 ProASIC3 Devices--ARM(R)CortexTM-M1 Soft Processor Available with or without Debug Advanced I/O * 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above) * 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Table 1 * ProASIC3 Product Family ProASIC3 Devices A3P015 Cortex-M1 Devices 1 System Gates 15 k Typical Equivalent Macrocells 128 VersaTiles (D-flip-flops) 384 RAM kbits (1,024 bits) - 4,608-Bit Blocks - FlashROM Bits 1k Secure (AES) ISP 2 - Integrated PLL in CCCs - VersaNet Globals 3 6 I/O Banks 2 Maximum User I/Os 49 Package Pins QFN QN68 CS VQFP TQFP PQFP FBGA A3P030 A3P060 A3P125 30 k 256 768 - - 1k - - 6 2 81 60 k 512 1,536 18 4 1k Yes 1 18 2 96 125 k 1,024 3,072 36 8 1k Yes 1 18 2 133 A3P250 M1A3P250 250 k 2,048 6,144 36 8 1k Yes 1 18 4 157 QN48, QN68, QN132 QN132 QN132 QN132 5 VQ100 TQ144 PQ208 FG144 VQ100 VQ100 CS121 VQ100 TQ144 FG144 PQ208 FG144/256 5 A3P400 M1A3P400 400 k - 9,216 54 12 1k Yes 1 18 4 194 A3P600 M1A3P600 600 k - 13,824 108 24 1k Yes 1 18 4 235 A3P1000 M1A3P1000 1M - 24,576 144 32 1k Yes 1 18 4 300 PQ208 FG144/256/ 484 PQ208 FG144/256/ 484 PQ208 FG144/256/ 484 Notes: 1. Refer to the Cortex-M1 product brief for more information. 2. AES is not available for ARM-enabled ProASIC3 devices. 3. Six chip (main) and three quadrant global networks are available for A3P060 and above. 4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs handbook. 5. The M1A3P250 device does not support this package. A3P015 and A3P030 devices do not support this feature. October 2009 (c) 2009 Actel Corporation Supported only by A3P015 and A3P030 devices. I I/Os Per Package 1 ProASIC3 Devices A3P015 A3P030 A3P060 A3P125 Cortex-M1 Devices A3P250 3 A3P400 3 A3P600 A3P1000 M1A3P250 3,6 M1A3P400 3 M1A3P600 M1A3P1000 Single-Ended I/O2 Differential I/O Pairs Single-Ended I/O2 Differential I/O Pairs Differential I/O Pairs Single-Ended I/O2 Differential I/O Pairs 49 - - - - - - - - - QN132 - 81 80 84 87 19 - - - - - CS121 - - 96 - - - - - - - - VQ100 - 77 71 71 68 13 - - - - - TQ144 - - 91 100 - - - - - - - - PQ208 - - - 133 151 34 151 34 154 35 154 35 FG144 - - 96 97 97 24 97 25 97 25 97 25 FG256 - - - - 157 38 178 38 177 43 177 44 FG484 - - - - - - 194 38 235 60 300 74 QN48 Single-Ended I/O2 Single-Ended I/O 49 Single-Ended I/O QN68 Package Single-Ended I/O Single-Ended I/O I/O Type 34 - Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 Flash Family FPGAs handbook to ensure complying with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to the ProASIC3 Flash Family FPGAs handbook for position assignments of the 15 LVPECL pairs. 4. FG256 and FG484 are footprint-compatible packages. 5. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 Ordering Information" on page III for the location of the "G" in the part number. 6. The M1A3P250 device does not support FG256 or QN132 packages. Table 2 * ProASIC3 FPGAs Package Sizes Dimensions Package QN48 CS121 QN68 QN132 VQ100 TQ144 PQ208 FG144 FG256 FG484 Length x Width (mm\mm) 6x6 6x6 8x8 8x8 14 x 14 20 x 20 28 x 28 13 x 13 17 x 17 23 x 23 Nominal Area (mm2) 36 36 64 64 196 400 784 169 289 529 Pitch (mm) 0.4 0.5 0.4 0.5 0.5 0.5 0.5 1.0 1.0 1.0 Height (mm) 0.90 0.99 0.90 0.75 1.00 1.40 3.40 1.45 1.60 2.23 II v1.3 ProASIC3 Flash Family FPGAs ProASIC3 Ordering Information . A3P1000 _ 1 FG G 144 I Application (Temperature Range) Blank = Commercial (0C to +70C Ambient Temperature) I = Industrial (-40C to +85C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant (Green) Packaging (some packages also halogen-free) Package Type QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) TQ = Thin Quad Flat Pack (0.5 mm pitch) PQ = Plastic Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) CS = Chip Scale Package (0.5 mm pitch) Speed Grade Blank = Standard 1 = 15% Faster than Standard 2 = 25% Faster than Standard Part Number ProASIC3 Devices A3P015 = A3P030 = A3P060 = A3P125 = A3P250 = A3P400 = A3P600 = A3P1000 = 15,000 System Gates 30,000 System Gates 60,000 System Gates 125,000 System Gates 250,000 System Gates 400,000 System Gates 600,000 System Gates 1,000,000 System Gates ProASIC3 Devices with Cortex-M1 M1A3P250 = M1A3P400 = M1A3P600 = M1A3P1000 = 250,000 System Gates 400,000 System Gates 600,000 System Gates 1,000,000 System Gates v1.3 III Temperature Grade Offerings Package A3P015 A3P030 A3P060 A3P125 Cortex-M1 Devices A3P250 A3P400 A3P600 A3P1000 M1A3P250 M1A3P400 M1A3P600 M1A3P1000 QN48 - C, I - - - - - - QN68 C, I C, I - - - - - - QN132 - C, I C, I C, I C, I - - - CS121 - - C, I - - - - - VQ100 - C, I C, I C, I C, I - - - TQ144 - - C, I C, I - - - - PQ208 - - - C, I C, I C, I C, I C, I FG144 - - C, I C, I C, I C, I C, I C, I FG256 - - - - C, I C, I C, I C, I FG484 - - - - - C, I C, I C, I Notes: 1. C = Commercial temperature range: 0C to 70C ambient temperature 2. I = Industrial temperature range: -40C to 85C ambient temperature Speed Grade and Temperature Grade Matrix Temperature Grade Std. -1 -2 C1 2 I Notes: 1. C = Commercial temperature range: 0C to 70C ambient temperature 2. I = Industrial temperature range: -40C to 85C ambient temperature References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. A3P015 and A3P030 The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features. IV v1.3 1 - ProASIC3 Device Family Overview General Description ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS(R) family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up (LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os. ProASIC3 devices support the ARM Cortex-M1 processor. The ARM-enabled devices have Actel ordering numbers that begin with M1A3P (Cortex-M1) and do not support AES decryption. Flash Advantages Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, flash-based ProASIC3 devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3 family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/ communications, computing, and avionics markets. Security The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. ProASIC3 devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed ProASIC3 device cannot be read back, although secure design verification is possible. ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the ARM core must be protected at all times, AES encryption is always on for the core logic, so bitstreams are always encrypted. There is no user access to encryption for the FlashROM programming data. v1.3 1-1 ProASIC3 Device Family Overview Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The ProASIC3 family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. A ProASIC3 device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up The Actel flash-based ProASIC3 devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based ProASIC3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3 devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. Firm Errors Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 flashbased FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Low Power Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. ProASIC3 devices also have low dynamic power consumption to further maximize power savings. 1 -2 v1.3 ProASIC3 Device Family Overview Advanced Flash Technology The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 and Figure 1-2 on page 1-4): * FPGA VersaTiles * Dedicated FlashROM * Dedicated SRAM/FIFO memory * Extensive CCCs and PLLs * Advanced I/O structure Bank 0 Bank 0 Bank 1 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* I/Os ISP AES Decryption* Bank 0 Bank 1 VersaTile User Nonvolatile FlashROM Charge Pumps Bank 1 * Not supported by A3P015 and A3P030 devices Figure 1-1 * ProASIC3 Device Architecture Overview with Two I/O Banks (A3P015, A3P030, A3P060, and A3P125) The A3P015 and A3P030 do not support PLL or SRAM. v1.3 1-3 ProASIC3 Device Family Overview Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile Bank 3 Bank 1 ISP AES Decryption User Nonvolatile FlashROM Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (A3P600 and A3P1000) Bank 2 Figure 1-2 * ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000) The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the ProASIC3 core tile as either a three-input lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of ProASIC3 devices via an IEEE 1532 JTAG interface. VersaTiles The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The ProASIC3 VersaTile supports the following: 1 -4 * All 3-input logic functions--LUT-3 equivalent * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set v1.3 ProASIC3 Device Family Overview Refer to Figure 1-3 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 D-Flip-Flop with Clear or Set Y Data CLK CLR Y Enable D-Flip-Flop with Clear or Set Data CLK D-FF Y D-FF Enable CLR Figure 1-3 * VersaTile Configurations User Nonvolatile FlashROM Actel ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * Internet protocol addressing (wireless or fixed) * System calibration settings * Device serialization and/or inventory control * Subscription-based business models (for example, set-top boxes) * Secure key storage for secure communications algorithms * Asset management/tracking * Date stamping * Version management The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the A3P015 and A3P030 devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-bybyte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel ProASIC3 development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in A3P015 and A3P030 devices). v1.3 1-5 ProASIC3 Device Family Overview In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and A3P030 devices do not have a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: * Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz * Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz * Clock delay adjustment via programmable and fixed delays from -7.56 ns to +11.12 ns * 2 programmable delay types for clock skew minimization * Clock frequency synthesis (for PLL only) Additional CCC specifications: * Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration (for PLL only). * Output duty cycle = 50% 1.5% or better (for PLL only) * Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used (for PLL only) * Maximum acquisition time = 300 s (for PLL only) * Low power consumption of 5 mW * Exceptional tolerance to input period jitter-- allowable input jitter is up to 1.5 ns (for PLL only) * Four precise phases; maximum misalignment between adjacent phases of 40 ps x (350 MHz / fOUT_CCC) (for PLL only) Global Clocking ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets. 1 -6 v1.3 ProASIC3 Device Family Overview I/Os with Advanced I/O Standards The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards--single-ended and differential. The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the I/O standards supported (Table 1-1). Table 1-1 * I/O Standards Supported I/O Standards Supported I/O Bank Type Device and Bank Location LVTTL/ LVCMOS PCI/PCI-X LVPECL, LVDS, B-LVDS, M-LVDS Advanced East and west Banks of A3P250 and larger devices Standard Plus North and south banks of A3P250 and larger devices Not supported Not supported Not supported All banks of A3P060 and A3P125 Standard All banks of A3P015 and A3P030 Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: * Single-Data-Rate applications * Double-Data-Rate applications--DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support Actel ProASIC3 devices support JEDEC-defined wide range I/O operation. ProASIC3 supports the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. v1.3 1-7 ProASIC3 Device Family Overview Part Number and Revision Date Part Number 51700097-001-4 Revised October 2009 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version v1.2 (August 2009) v1.1 (February 2009) v1.0 (February 2008) Changes in Current Version (v1.3) Page The CS121 package was added to Table 1 * ProASIC3 Product Family, the "I/Os Per Package 1" table, Table 2 * ProASIC3 FPGAs Package Sizes Dimensions, "ProASIC3 Ordering Information", and the "Temperature Grade Offerings" table. I - IV "ProASIC3 Ordering Information" was revised to include the face that some RoHS compliant packages are halogen-free. III All references to M7 devices (CoreMP7) and speed grade -F were removed from this document. N/A Table 1-1 * I/O Standards Supported is new. 1-7 The "I/Os with Advanced I/O Standards" section was revised to add definitions of hot-swap and cold-sparing. 1-7 The "Advanced I/O" section was revised to add a bullet regarding wide range power supply voltage support. I The Table 1 * ProASIC3 Product Family was updated to include a value for typical equivalent macrocells for A3P250. I The QN48 package was added to the following tables: N/A "ProASIC3 Product Family" "I/Os Per Package 1" "ProASIC3 FPGAs Package Sizes Dimensions" "Temperature Grade Offerings" The number of singled-ended I/Os for QN68 was added to the "I/Os Per Package 1" table. The "Wide Range I/O Support" section is new. 1-7 51700097-001-1 This document was divided into two sections and given a version number, starting at v1.0. The first section of the document includes features, benefits, ordering information, and temperature and speed grade offerings. The second section is a device family overview. N/A 51700097-001-0 (January 2008) This document was updated to include A3P015 device information. QN68 is a new package that was added because it is offered in the A3P015. The following sections were updated: N/A "Features and Benefits" "ProASIC3 Ordering Information" "Temperature Grade Offerings" "ProASIC3 Product Family" "A3P015 and A3P030" note "Introduction and Overview" The "ProASIC3 FPGAs Package Sizes Dimensions" table is new. 1 -8 v1.3 II ProASIC3 Device Family Overview Previous Version Changes in Current Version (v1.3) Page 51700097-001-0 (continued) In the "ProASIC3 Ordering Information", the QN package measurements were updated to include both 0.4 mm and 0.5 mm. III In the "General Description" section, the number of I/Os was updated from 288 to 300. 1-1 v2.2 (July 2007) This document was previously in datasheet v2.2. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is 51700097-001-0. N/A v2.1 (May 2007) The M7 and M1 device part numbers have been updated in Table 1 * ProASIC3 Product Family, "I/Os Per Package", "Automotive ProASIC3 Ordering Information", "Temperature Grade Offerings", and "Speed Grade and Temperature Grade Matrix". i, ii, iii, iii, iv The words "ambient temperature" were added to the temperature range in the "Automotive ProASIC3 Ordering Information", "Temperature Grade Offerings", and "Speed Grade and Temperature Grade Matrix" sections. iii, iv In the "Clock Conditioning Circuit (CCC) and PLL" section, the Wide Input Frequency Range (1.5 MHz to 200 MHz) was changed to (1.5 MHz to 350 MHz). i The "Clock Conditioning Circuit (CCC) and PLL" section was updated. i In the "I/Os Per Package" section, the A3P030, A3P060, A3P125, ACP250, and A3P600 device I/Os were updated. ii Advance v0.7 (January 2007) In the "Packaging Tables", Ambient was deleted. ii Ambient was deleted from the "Speed Grade and Temperature Grade Matrix". iv Advance v0.6 (April 2006) In the "I/Os Per Package" table, the I/O numbers were added for A3P060, A3P125, and A3P250. The A3P030-VQ100 I/O was changed from 79 to 77. ii Advance v0.5 (January 2006) B-LVDS and M-LDVS are new I/O standards added to the datasheet. N/A The term flow-through was changed to pass-through. N/A v2.0 (April 2007) Advance v0.4 (November 2005) Table 1 was updated to include the QN132. ii The "I/Os Per Package" table was updated with the QN132. The footnotes were also updated. The A3P400-FG144 I/O count was updated. ii "Automotive ProASIC3 Ordering Information" was updated with the QN132. iii "Temperature Grade Offerings" was updated with the QN132. iii The "I/Os Per Package" table was updated for the following devices and packages: ii Device A3P250/M7ACP250 A3P250/M7ACP250 A3P1000 Advance v0.3 Advance v0.2 Package VQ100 FG144 FG256 M7 device information is new. N/A The I/O counts in the "I/Os Per Package" table were updated. ii The "I/Os Per Package" table was updated. ii v1.3 1-9 ProASIC3 Device Family Overview Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. 1 -1 0 v1.3 2 - ProASIC3 DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 * Symbol Absolute Maximum Ratings Parameter Limits Units VCC DC core supply voltage -0.3 to 1.65 V VJTAG JTAG DC voltage -0.3 to 3.75 V VPUMP Programming voltage -0.3 to 3.75 V VCCPLL Analog power supply (PLL) -0.3 to 1.65 V VCCI DC I/O output buffer supply voltage -0.3 to 3.75 V VMV DC I/O input buffer supply voltage -0.3 to 3.75 V VI I/O input voltage -0.3 V to 3.6 V V (when I/O hot insertion mode is enabled) -0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) TSTG 2 Storage temperature -65 to +150 C TJ 2 Junction temperature +125 C Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2. v1.4 2-1 ProASIC3 DC and Switching Characteristics Table 2-2 * Recommended Operating Conditions 1,2 Symbol Parameter Commercial Industrial Units C TA Ambient temperature 0 to +70 -40 to +85 TJ Junction temperature 0 to 85 -40 to 100 VCC3 1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V VPUMP Programming voltage 3.0 to 3.6 3.0 to 3.6 V 0 to 3.6 0 to 3.6 V 1.4 to 1.6 1.4 to 1.6 V Programming Mode Operation 4 VCCPLL Analog power supply (PLL) VCCI and VMV 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V 2.7 to 3.6 2.7 to 3.6 V 3.0 to 3.6 3.0 to 3.6 V 2.375 to 2.625 2.375 to 2.625 V 3.0 to 3.6 3.0 to 3.6 V 3.3 V DC supply voltage 3.3 V wide range DC supply voltage 5 LVDS/B-LVDS/M-LVDS differential I/O LVPECL differential I/O Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel's timing and power simulation tools. 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-18 on page 2-18. VMV and VCCI should be at the same voltage within a given I/O bank. 4. VPUMP can be left floating during operation (not programming mode). 5. 3.3 V wide range is compliant to the JDEC8b specification and supports 3.0 V VCCI operation. Table 2-3 * Flash Programming Limits - Retention, Storage and Operating Temperature1 Product Grade Programming Program Retention Cycles (biased/unbiased) Maximum Storage Temperature TSTG (C) 2 Maximum Operating Junction Temperature TJ (C) 2 Commercial 500 20 years 110 100 Industrial 500 20 years 110 100 Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. 2 -2 v1.4 ProASIC3 DC and Switching Characteristics Table 2-4 * Overshoot and Undershoot Limits 1 VCCI and VMV Average VCCI-GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 10% 1.4 V 5% 1.49 V 2.7 V or less 3V 3.3 V 3.6 V 10% 1.1 V 5% 1.19 V 10% 0.79 V 5% 0.88 V 10% 0.45 V 5% 0.54 V Notes: 1. Based on reliability requirements at 85C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. This table does not provide PCI overshoot/undershoot limits. I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every ProASIC(R)3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4. There are five regions to consider during power-up. ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4). 2. VCCI > VCC - 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: * During programming, I/Os become tristated and weakly pulled up to VCCI. * JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the v1.4 2-3 ProASIC3 DC and Switching Characteristics Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V Figure 2-1 * I/O State as a Function of VCCI and VCC Voltage Levels 2 -4 Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. v1.4 VCCI ProASIC3 DC and Switching Characteristics Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 2-1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 2-1 where: TA = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 100C. EQ 2-2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. * 100C - 70C Max. junction temp. (C) - Max. ambient temp. (C) Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 1.463 W 20.5C/W ja (C/W) EQ 2-2 Table 2-5 * Package Thermal Resistivities ja Package Type Device Pin Count jc Quad Flat No Lead A3P030 132 0.4 21.4 16.8 15.3 C/W A3P060 132 0.3 21.2 16.6 15.0 C/W A3P125 132 0.2 21.1 16.5 14.9 C/W A3P250 132 0.1 21.0 16.4 14.8 C/W Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W Thin Quad Flat Pack (TQFP) All devices 144 11.0 33.5 28.0 25.7 C/W Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 C/W PQFP with embedded heatspreader All devices 208 3.8 16.2 13.3 11.9 C/W Fine Pitch Ball Grid Array (FBGA) See note* 144 3.8 26.9 22.9 21.5 C/W See note* 256 3.8 26.6 22.8 21.5 C/W See note* 484 3.2 20.5 17.0 15.9 C/W A3P1000 144 6.3 31.6 26.2 24.2 C/W A3P1000 256 6.6 28.1 24.4 22.7 C/W A3P1000 484 8.0 23.3 19.0 16.7 C/W Still Air 200 ft./min. 500 ft./min. Units * This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal information will be available in future revisions of the datasheet. v1.4 2-5 ProASIC3 DC and Switching Characteristics Temperature and Voltage Derating Factors Table 2-6 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70C, VCC = 1.425 V) Junction Temperature (C) -40C 0C 25C 70C 85C 100C 1.425 Array Voltage VCC (V) 0.88 0.93 0.95 1.00 1.02 1.04 1.500 0.83 0.88 0.90 0.95 0.96 0.98 1.575 0.80 0.84 0.87 0.91 0.93 0.94 Calculating Power Dissipation Quiescent Supply Current Table 2-7 * Quiescent Supply Current Characteristics A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 Typical (25C) 2 mA 2 mA 2 mA 2 mA 3 mA 3 mA 5 mA 8 mA Max. (Commercial) 10 mA 10 mA 10 mA 10 mA 20 mA 20 mA 30 mA 50 mA Max. (Industrial) 15 mA 15 mA 15 mA 15 mA 30 mA 30 mA 45 mA 75 mA Note: IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 2-11 and Table 2-12 on page 2-8. Power per I/O Pin Table 2-8 * Summary of I/O Input Buffer Power (Per Pin) - Default I/O Software Settings Applicable to Advanced I/O Banks VMV (V) Static Power PDC2 (mW) 1 Dynamic Power PAC9 (W/MHz) 2 3.3 - 16.22 3.3 - 16.22 2.5 V LVCMOS 2.5 - 5.12 1.8 V LVCMOS 1.8 - 2.13 1.5 V LVCMOS (JESD8-11) 1.5 - 1.45 3.3 V PCI 3.3 - 18.11 3.3 V PCI-X 3.3 - 18.11 LVDS 2.5 2.26 1.20 LVPECL 3.3 5.72 1.87 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 3 Differential Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. 2 -6 v1.4 ProASIC3 DC and Switching Characteristics Table 2-9 * Summary of I/O Input Buffer Power (Per Pin) - Default I/O Software Settings Applicable to Standard Plus I/O Banks VMV (V) Static Power PDC2 (mW) 1 Dynamic Power PAC9 (W/MHz) 2 3.3 - 16.23 3.3 - 16.23 2.5 V LVCMOS 2.5 - 5.14 1.8 V LVCMOS 1.8 - 2.13 1.5 V LVCMOS (JESD8-11) 1.5 - 1.48 3.3 V PCI 3.3 - 18.13 3.3 V PCI-X 3.3 - 18.13 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 3 Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. Table 2-10 * Summary of I/O Input Buffer Power (Per Pin) - Default I/O Software Settings Applicable to Standard I/O Banks VMV (V) Static Power PDC2 (mW) 1 Dynamic Power PAC9 (W/MHz) 2 3.3 V LVTTL / 3.3 V LVCMOS 3.3 - 17.24 Range3 3.3 - 17.24 2.5 V LVCMOS 2.5 - 5.19 1.8 V LVCMOS 1.8 - 2.18 1.5 V LVCMOS (JESD8-11) 1.5 - 1.52 Single-Ended 3.3 V LVCMOS Wide Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. v1.4 2-7 ProASIC3 DC and Switching Characteristics Table 2-11 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 Applicable to Advanced I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (W/MHz)3 35 3.3 - 468.67 3.3 V LVCMOS Wide Range 35 3.3 - 468.67 2.5 V LVCMOS 35 2.5 - 267.48 1.8 V LVCMOS 35 1.8 - 149.46 1.5 V LVCMOS (JESD8-11) 35 1.5 - 103.12 3.3 V PCI 10 3.3 - 201.02 3.3 V PCI-X 10 3.3 - 201.02 LVDS - 2.5 7.74 88.92 LVPECL - 3.3 19.54 166.52 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 4 Differential Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCC and VCCI. 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. Table 2-12 * Summary of I/O Output Buffer Power (Per Pin) - Default I/O Software Settings1 Applicable to Standard Plus I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (W/MHz)3 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 - 452.67 3.3 V LVCMOS Wide Range4 35 3.3 - 452.67 2.5 V LVCMOS 35 2.5 - 258.32 1.8 V LVCMOS 35 1.8 - 133.59 1.5 V LVCMOS (JESD8-11) 35 1.5 - 92.84 3.3 V PCI 10 3.3 - 184.92 3.3 V PCI-X 10 3.3 - 184.92 Single-Ended Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VMV. 3. PAC10 is the total dynamic power measured on VCC and VMV. 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. 2 -8 v1.4 ProASIC3 DC and Switching Characteristics Table 2-13 * Summary of I/O Output Buffer Power (Per Pin) - Default I/O Software Settings 1 Applicable to Standard I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW) 2 Dynamic Power PAC10 (W/MHz) 3 35 3.3 - 431.08 3.3 V LVCMOS Wide Range 35 3.3 - 431.08 2.5 V LVCMOS 35 2.5 - 247.36 1.8 V LVCMOS 35 1.8 - 128.46 1.5 V LVCMOS (JESD8-11) 35 1.5 - 89.46 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 4 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCC and VCCI. 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. v1.4 2-9 ProASIC3 DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-14 * Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 Definition A3P600 Parameter A3P1000 Device Specific Dynamic Contributions (W/MHz) PAC1 Clock contribution of a Global Rib 14.50 12.80 12.80 11.00 11.00 9.30 9.30 9.30 PAC2 Clock contribution of a Global Spine 2.48 0.41 0.41 PAC3 Clock contribution of a VersaTile row 0.81 PAC4 Clock contribution of a VersaTile used as a sequential module 0.12 PAC5 First contribution of a VersaTile used as a sequential module 0.07 PAC6 Second contribution of a VersaTile used as a sequential module 0.29 PAC7 Contribution of a VersaTile used as a combinatorial Module 0.29 PAC8 Average contribution of a routing net 0.70 PAC9 Contribution of an I/O input pin (standard dependent) See Table 2-8 on page 2-6 through Table 2-10 on page 2-7. PAC10 Contribution of an I/O output pin (standard dependent) See Table 2-11 on page 2-8 through Table 2-13 on page 2-9. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.60 1.85 1.35 1.58 0.81 0.81 Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet calculator or SmartPower tool in Libero(R) Integrated Design Environment (IDE) software. Table 2-15 * Different Components Contributing to the Static Power Consumption in ProASIC3 Devices PDC1 Array static power in Active mode See Table 2-7 on page 2-6. PDC2 I/O input pin static power (standard-dependent) See Table 2-8 on page 2-6 through Table 2-10 on page 2-7. PDC3 I/O output pin static power (standard-dependent) See Table 2-11 on page 2-8 through Table 2-13 on page 2-9. PDC4 Static PLL contribution PDC5 Bank quiescent power (VCCI -dependent) 2.55 mW See Table 2-7 on page 2-6. Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel 2 -1 0 v1.4 A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 Parameter A3P600 Device Specific Static Power (mW) A3P1000 Definition ProASIC3 DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: * The number of PLLs as well as the number and the frequency of each output clock generated * The number of combinatorial and sequential cells used in the design * The internal clock frequencies * The number and the standard of I/O pins used in the design * The number of RAM blocks used in the design * Toggle rates of I/O pins as well as VersaTiles--guidelines are provided in Table 2-16 on page 2-13. * Enable rates of output buffers--guidelines are provided for typical applications in Table 2-17 on page 2-13. * Read rate and write rate to the memory--guidelines are provided for typical applications in Table 2-17 on page 2-13. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption--PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption--PSTAT PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. Total Dynamic Power Consumption--PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution--PCLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design--guidelines are provided in Table 2-16 on page 2-13. NROW is the number of VersaTile rows used in the design--guidelines are provided in Table 2-16 on page 2-13. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution--PS-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-16 on page 2-13. FCLK is the global clock signal frequency. v1.4 2 - 11 ProASIC3 DC and Switching Characteristics Combinatorial Cells Contribution--PC-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-16 on page 2-13. FCLK is the global clock signal frequency. Routing Net Contribution--PNET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-16 on page 2-13. FCLK is the global clock signal frequency. I/O Input Buffer Contribution--PINPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-16 on page 2-13. FCLK is the global clock signal frequency. I/O Output Buffer Contribution--POUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-16 on page 2-13. 1 is the I/O buffer enable rate--guidelines are provided in Table 2-17 on page 2-13. FCLK is the global clock signal frequency. RAM Contribution--PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations--guidelines are provided in Table 2-17 on page 2-13. PLL Contribution--PPLL PPLL = PDC4 + PAC13 *FCLKOUT FCLKOUT is the output clock frequency.1 1. 2 -1 2 The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution. v1.4 ProASIC3 DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: * The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. * The average toggle rate of an 8-bit counter is 25%: - Bit 0 (LSB) = 100% - Bit 1 = 50% - Bit 2 = 25% - ... - Bit 7 (MSB) = 0.78125% - Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-16 * Toggle Rate Guidelines Recommended for Power Calculation Component 1 2 Definition Guideline Toggle rate of VersaTile outputs 10% I/O buffer toggle rate 10% Table 2-17 * Enable Rate Guidelines Recommended for Power Calculation Component 1 2 3 Definition Guideline I/O output buffer enable rate 100% RAM enable rate for read operations 12.5% RAM enable rate for write operations 12.5% v1.4 2 - 13 ProASIC3 DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell Y LVPECL (Applicable to Advanced I/O Banks Only)L Y tPD = 0.56 ns tPD = 0.49 ns tDP = 1.34 ns I/O Module (Non-Registered) Combinational Cell Y LVTTL Output drive strength = 12 mA High slew rate tDP = 2.64 ns (Advanced I/O Banks) tPD = 0.87 ns Combinational Cell I/O Module (Registered) I/O Module (Non-Registered) Y LVTTL Output drive strength = 8 mA High slew rate tDP = 3.66 ns (Advanced I/O Banks) tPY = 1.05 ns LVPECL (Applicable to Advanced I/O Banks only) D tPD = 0.47 ns Q Combinational Cell I/O Module (Non-Registered) Y tICLKQ = 0.24 ns tISUD = 0.26 ns LVCMOS 1.5 V Output drive strength = 4 mA High slew rate tDP = 3.97 ns (Advanced I/O Banks) tPD = 0.47 ns Input LVTTL Clock Register Cell tPY = 0.76 ns (Advanced I/O Banks) D Combinational Cell Y Q I/O Module (Non-Registered) LVDS, BLVDS, M-LVDS (Applicable for Advanced I/O Banks only) D Q D tPD = 0.47 ns tCLKQ = 0.55 ns tSUD = 0.43 ns tPY = 1.20 ns I/O Module (Registered) Register Cell tCLKQ = 0.55 ns tSUD = 0.43 ns Q LVTTL 3.3 V Output drive strength = 12 mA High slew rate tDP = 2.64 ns (Advanced I/O Banks) tOCLKQ = 0.59 ns tOSUD = 0.31 ns Input LVTTL Clock Input LVTTL Clock tPY = 0.76 ns (Advanced I/O Banks) tPY = 0.76 ns (Advanced I/O Banks) Figure 2-2 * Timing Model Operating Conditions: -2 Speed, Commercial Temperature Range (TJ = 70C), Worst Case VCC = 1.425 V 2 -1 4 v1.4 ProASIC3 DC and Switching Characteristics tPY tDIN D PAD Q DIN Y CLK tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) To Array I/O Interface VIH PAD Vtrip Vtrip VIL VCC 50% 50% Y GND tPY (F) tPY (R) VCC 50% DIN GND 50% tDOUT tDOUT (R) (F) Figure 2-3 * Input Buffer Timing Model and Delays (example) v1.4 2 - 15 ProASIC3 DC and Switching Characteristics tDOUT tDP D Q D PAD DOUT Std Load CLK From Array tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) I/O Interface tDOUT (R) D 50% tDOUT VCC (F) 50% 0V VCC DOUT 50% 50% 0V VOH Vtrip Vtrip VOL PAD tDP (R) Figure 2-4 * Output Buffer Model and Delays (example) 2 -1 6 v1.4 tDP (F) ProASIC3 DC and Switching Characteristics tEOUT D Q CLK E tZL, tZH, tHZ, tLZ, tZLS, tZHS EOUT D Q PAD DOUT CLK D tEOUT = MAX(tEOUT(r), tEOUT(f)) I/O Interface VCC D VCC 50% E 50% tEOUT (F) tEOUT (R) VCC 50% 50% EOUT tZL 50% tZH tHZ Vtrip VCCI 90% VCCI PAD 50% tLZ Vtrip VOL 10% VCCI VCC D VCC E 50% 50% tEOUT (R) tEOUT (F) VCC EOUT 50% 50% tZLS VOH PAD Vtrip 50% tZHS Vtrip VOL Figure 2-5 * Tristate Output Buffer Timing Model and Delays (example) v1.4 2 - 17 ProASIC3 DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels - Default I/O Software Settings Table 2-18 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Applicable to Advanced I/O Banks IOL1 IOH1 Min, V mA mA Drive Strength Slew Rate Min, V Max, V Min, V 3.3 V LVTTL / 3.3 V LVCMOS 12 mA 12 mA High -0.3 0.8 2 3.6 0.4 2.4 12 12 3.3 V LVCMOS Wide Range3 100 A 12 mA High -0.3 0.8 2 3.6 0.2 VCCI - 0.2 0.1 0.1 2.5 V LVCMOS 12 mA 12 mA High -0.3 0.7 1.7 2.7 0.7 1.7 12 12 1.8 V LVCMOS 12 mA 12 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 12 12 1.5 V LVCMOS 12 mA 12 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI 12 12 I/O Standard 3.3 V PCI 3.3 V PCI-X VIL VOH Equiv. Software Default Drive Strength Option2 VIH VOL Max, V Max, V Per PCI specifications Per PCI-X specifications Notes: 1. Currents are measured at 85C junction temperature. 2. Please note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. 2 -1 8 v1.4 ProASIC3 DC and Switching Characteristics Table 2-19 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Applicable to Standard Plus I/O Banks I/O Standard Equiv. VIL Software Default Drive Drive Strength Slew Strength Option2 Rate Min, V Max, V VIH Min, V VOL Max, V Max, V VOH IOL1 IOH1 Min, V mA mA 3.3 V LVTTL / 3.3 V LVCMOS 12 mA 12 mA High -0.3 0.8 2 3.6 0.4 2.4 12 12 3.3 V LVCMOS Wide Range3 100 A 12 mA High -0.3 0.8 2 3.6 0.2 VCCI-0.2 0.1 0.1 2.5 V LVCMOS 12 mA 12 mA High -0.3 0.7 1.7 2.7 0.7 1.7 12 12 1.8 V LVCMOS 8 mA 8 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 8 8 1.5 V LVCMOS 4 mA 4 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI 4 4 3.3 V PCI 3.3 V PCI-X Per PCI specifications Per PCI-X specifications Notes: 1. Currents are measured at 85C junction temperature. 2. Please note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. v1.4 2 - 19 ProASIC3 DC and Switching Characteristics Table 2-20 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Applicable to Standard I/O Banks Equiv. VIL Software Default Drive Drive Strength Slew I/O Standard Strength Option2 Rate Min, V Max, V 3.3 V LVTTL / 3.3 V LVCMOS VIH VOL VOH IOL1 IOH1 mA mA Min, V Max, V Max, V Min, V 8 mA 8 mA High -0.3 0.8 2 3.6 0.4 2.4 8 8 3.3 V LVCMOS Wide Range3 100 A 8 mA High -0.3 0.8 2 3.6 0.2 VCCI-0.2 0.1 0.1 2.5 V LVCMOS 8 mA 8 mA High -0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 V LVCMOS 4 mA 4 mA High -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI - 0.45 4 4 1.5 V LVCMOS 2 mA 2 mA High -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 Notes: 1. Currents are measured at 85C junction temperature. 2. Please note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. Table 2-21 * Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 Industrial2 IIL3 IIH4 IIL3 IIH4 DC I/O Standards A A A A 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15 3.3 V LVCMOS Wide Range 10 10 15 15 2.5 V LVCMOS 10 10 15 15 1.8 V LVCMOS 10 10 15 15 1.5 V LVCMOS 10 10 15 15 3.3 V PCI 10 10 15 15 3.3 V PCI-X 10 10 15 15 Notes: 1. Commercial range (0C < TA < 70C) 2. Industrial range (-40C < TA < 85C) 3. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3V < VIN 20 years 0C > 20 years 25C > 20 years 70C 5 years 85C 2 years 100C 6 months 110C 3 months Table 2-36 * I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS No requirement 10 ns * 20 years (110C) LVDS/B-LVDS/ M-LVDS/LVPECL No requirement 10 ns * 10 years (100C) * The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. 2 -3 0 v1.4 ProASIC3 DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor-Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-37 * Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength VIH VIL VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 A4 A4 2 mA -0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 mA -0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 mA -0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 mA -0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 mA -0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 mA -0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10 24 mA -0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH