1M 10M 100M
Frequency (Hz)
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-40
HD (dBc)
-55
-50
-45 HD2, RL = 1 k:
HD3, RL = 1 k:
HD2, RL = 100 :
HD3, RL = 100 :
1M 10M 100M 1G
Frequency (Hz)
-7
-6
-5
-4
-3
-2
-1
0
1
Gain (dB)
-430
-380
-330
-280
-230
-180
-130
-80
-30
Phase (°)
AV = -1
AV = -10
AV = -4
AV = -2
PHASE
GAIN
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Software
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6702
SNOSA03H –NOVEMBER 2002–REVISED MAY 2016
LMH6702 1.7-GHz Ultra-Low Distortion Wideband Op Amp
1
1 Features
1VS= ±5 V, TA= 25°C, AV= 2V/V, RL= 100 Ω,
VOUT =2VPP, Typical Unless Noted:
• 2nd and 3rd Harmonics (5 MHz, SOT-23) −100/−96
dBc
•−3-dB Bandwidth (VOUT = 0.5 VPP) 1.7 GHz
• Low Noise 1.83 nV/√Hz
• Fast Settling to 0.1% 13.4 ns
• Fast Slew Rate 3100 V/μs
• Supply Current 12.5 mA
• Output Current 80 mA
• Low Intermodulation Distortion (75 MHz) −67 dBc
• Improved Replacement for CLC409 and CLC449
2 Applications
• Flash A-D Driver
• D-A Transimpedance Buffer
• Wide Dynamic Range IF Amp
• Radar and Communication Receivers
• Line Driver
• High Resolution Video
3 Description
The LMH6702 is a very wideband, DC-coupled
monolithic operational amplifier designed specifically
for wide dynamic range systems requiring exceptional
signal fidelity. Benefitting from current feedback
architecture, the LMH6702 offers unity gain stability at
exceptional speed without need for external
compensation.
With its 720-MHz bandwidth (AV= 2 V/V, VO=2VPP),
10-bit distortion levels through 60-MHz (RL= 100 Ω),
1.83-nV/√Hz input referred noise and 12.5-mA supply
current, the LMH6702 is the ideal driver or buffer for
high-speed flash A-D and D-A converters.
Wide dynamic range systems such as radar and
communication receivers that require a wideband
amplifier offering exceptional signal purity will find the
low input referred noise and low harmonic and
intermodulation distortion of the LMH6702 an
attractive high speed solution.
The LMH6702 is constructed using VIP10™
complimentary bipolar process and proven current
feedback architecture. The LMH6702 is available in
SOIC and SOT-23 packages.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LMH6702 SOIC (8) 4.90 mm × 3.91 mm
SOT-23 (5) 2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Inverting Frequency Response Harmonic Distortion vs Load and Frequency
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
7 Detailed Description............................................ 11
7.1 Overview................................................................. 11
7.2 Feature Description................................................. 11
7.3 Device Functional Modes........................................ 12
8 Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 16
11 Device and Documentation Support................. 17
11.1 Documentation Support ....................................... 17
11.2 Community Resources.......................................... 17
11.3 Trademarks........................................................... 17
11.4 Electrostatic Discharge Caution............................ 17
11.5 Glossary................................................................ 17
12 Mechanical, Packaging, and Orderable
Information........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (October 2014) to Revision H Page
• Updated Thermal Information................................................................................................................................................. 4
• Changed non-inverting input bias (with no test conditions) current maximum value from ±15 µA to –15 µA........................ 6
• Changed non-inverting input bias (-40 ≤TJ≤85) current maximum value from ±21 µA to –21 µA...................................... 6
• Added Community Resources section ................................................................................................................................. 17
Changes from Revision F (March 2013) to Revision G Page
• Added, updated, or renamed the following sections: Device Information;Specifications; Application and
Implementation;Power Supply Recommendations;Layout;Device and Documentation Support;Mechanical,
Packaging, and Ordering Information .................................................................................................................................... 1
• Changed ±5 V to ±4 V in Recommended Operating Conditions............................................................................................ 4
Changes from Revision E (March 2013) to Revision F Page
• Changed layout of National Data Sheet to TI format ............................................................................................................. 1
V+
1
2
3
4 5
6
7
8
N/C
-IN
+IN
V-
N/C
OUT
N/C
-
+
OUT
V-
+IN
V+
-IN
+-
1
2
3
5
4
3
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View D Package
8-Pin SOIC
Top View
NC: No internal connection
Pin Functions
PIN
I/O DESCRIPTION
NAME NUMBER
D DBV
-IN 2 4 I Inverting input voltage
+IN 3 3 I Non-inverting input voltage
N/C 1, 5, 8 – – No connection
OUT 6 1 O Output
V- 4 2 I Negative supply
V+ 7 5 I Positive supply
4
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The maximum output current (IOUT) is determined by device power dissipation limitations.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
VS±6.75 V
IOUT See(3)
Common mode input voltage V−to V+V
Maximum junction temperature 150 °C
Storage temperature −65 150 °C
Soldering information Infrared or convection (20 s) 235 °C
Wave soldering (10 s) 260 °C
(1) Human body model: 1.5 kΩin series with 100 pF. JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a
standard ESD control process. Manufacturing with less than 2000-V HBM is possible with the necessary precautions. Pins listed as
±2000 V may actually have higher performance.
(2) Machine model: 0 Ωin series with 200 pF. JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard
ESD control process. Manufacturing with less than 200-V MM is possible with the necessary precautions. Pins listed as ±200 V may
actually have higher performance.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Machine Model (MM), per JEDEC specification JESD22-C101, all pins(2) ±200
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Operating temperature −40 85 °C
Nominal supply voltage ±4 ±6 V
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.4 Thermal Information
THERMAL METRIC(1) LMH6702
UNITDBV (SOT-23) D (SOIC)
5 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 182 133 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 139 79 °C/W
RθJB Junction-to-board thermal resistance 40 73 °C/W
ψJT Junction-to-top characterization parameter 28 28 °C/W
ψJB Junction-to-board characterization parameter 40 73 °C/W
5
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(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ> TA. Min/Max ratings are based on production testing unless otherwise specified.
(2) All limits are ensured by testing or statistical analysis.
(3) Typical numbers are the most likely parametric norm.
(4) Slew Rate is the average of the rising and falling edges.
(5) Harmonic distortion is strongly influenced by package type (SOT-23 or SOIC). See Application Note section under Harmonic Distortion
for more information.
6.5 Electrical Characteristics
at AV= 2, VS= ±5 V, RL= 100 Ω, RF= 237 Ω(unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBWSM
-3-dB Bandwidth
VOUT = 0.5 VPP 1700
MHz
SSBWLG VOUT = 2 VPP 720
LSBWLG VOUT = 4 VPP 480
SSBWHG VOUT = 2 VPP, AV= +10 140
GF0.1dB 0.1-dB gain flatness VOUT = 2 VPP 120 MHz
LPD Linear phase deviation DC to 100 MHz 0.09 deg
DG Differential gain RL=150 Ω, 3.58 MHz 0.024%
RL=150 Ω, 4.43 MHz 0.021%
DP Differential phase RL= 150 Ω, 3.58 MHz 0.004 deg
RL= 150 Ω, 4.43 MHz 0.007
TIME DOMAIN RESPONSE
tRRise time 2-V Step, TRS 0.87 ns
2-V Step, TRL 0.77
tFFall time 6-V Step, TRS 1.70 ns
6-V Step, TRL 1.70
OS Overshoot 2-V Step 0%
SR Slew rate 6 VPP, 40% to 60%(4) 3100 V/µs
TsSettling time to 0.1% 2-V Step 13.4 ns
DISTORTION AND NOISE RESPONSE
HD2L
2nd Harmonic distortion
2 VPP, 5 MHz(5) (SOT-23) −100 dBc
2 VPP, 5 MHz(5) (SOIC) −87
HD2 2VPP, 20 MHz(5) (SOT-23) −79 dBc
2VPP, 20 MHz(5) (SOIC) −72
HD2H 2VPP, 60 MHz(5) (SOT-23) −63 dBc
2VPP, 60 MHz(5) (SOIC) −64
HD3L
3rd Harmonic distortion
2VPP, 5 MHz(5) (SOT-23) −96 dBc
2VPP, 5 MHz(5) (SOIC) −98
HD3 2VPP, 20 MHz(5) (SOT-23) −88 dBc
2VPP, 20 MHz(5) (SOIC) −82
HD3H 2VPP, 60 MHz(5) (SOT-23) −70 dBc
2VPP, 60 MHz(5) (SOIC) −65
OIM3 IMD 75 MHz, PO= 10dBm/ tone −67 dBc
VNInput referred voltage noise >1 MHz 1.83 nV/√Hz
INInput referred inverting
noise current >1 MHz 18.5 pA/√Hz
INN Input referred non-inverting
noise current >1 MHz 3.0 pA/√Hz
SNF Total input noise floor >1 MHz −158 dBm1Hz
INV Total integrated input noise 1 MHz to 150 MHz 35 µV
6
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Electrical Characteristics (continued)
at AV= 2, VS= ±5 V, RL= 100 Ω, RF= 237 Ω(unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
(6) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(7) Negative input current implies current flowing out of the device.
STATIC, DC PERFORMANCE
VIO Input offset voltage ±1.0 ±4.5 mV
-40 ≤TJ≤85 ±6.0
DVIO Input offset voltage average
drift See(6) −13 µV/°C
IBN Input bias current Non-Inverting(7) −6 –15 µA
-40 ≤TJ≤85 –21
DIBN Input bias current average
drift Non-Inverting(6) +40 nA/°C
IBI Input bias current Inverting(7) −8 ±30 µA
-40 ≤TJ≤85 ±34
DIBI Input bias current average
drift Inverting(6) −10 nA/°C
PSRR Power supply rejection ratio DC 47 52 dB
-40 ≤TJ≤85 45
CMRR Common mode rejection
ration DC 45 48 dB
-40 ≤TJ≤85 44
ICC Supply current RL=∞11.0 12.5 16.1 mA
-40 ≤TJ≤85 10.0 17.5
MISCELLANEOUS PERFORMANCE
RIN Input resistance Non-Inverting 1.4 MΩ
CIN Input capacitance Non-Inverting 1.6 pF
ROUT Output resistance Closed Loop 30 mΩ
VOL Output voltage range RL= 100 Ω±3.3 ±3.5 V
-40 ≤TJ≤85 ±3.2
CMIR Input voltage range Common Mode ±1.9 ±2.2 V
IOOutput current 50 80 mA
0 100M 200M 300M 400M 500M
-7
-6
-5
-4
-3
-2
-1
0
1
Gain (dB)
Frequency (Hz)
GAIN
PHASE
50 :
1 k:
100 :-250
-200
-150
-100
-50
0
50
100
150
Phase (°)
50 :
02 4 6 8 10 14
Time (ns)
-1.5
-1
-0.5
0
0.5
1
1.5
VOUT (V)
12
AV = -2
AV = +2
0 200M 400M 600M 800M 1G
-7
-6
-5
-4
-3
-2
-1
0
1
Gain (dB)
Frequency (Hz)
GAIN
PHASE
1 k:
100 :
100 :
-250
-200
-150
-100
-50
0
50
100
150
Phase (°)
50 :
1 k:
50 :
10M 100M 1G 10G
Frequency (Hz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
Gain (dB)
-270
-216
-162
-108
-54
0
Phase (°)
GAIN
PHASE
1M 10M 100M 1G
Frequency (Hz)
-7
-6
-5
-4
-3
-2
-1
0
1
Gain (dB)
AV = +1
AV = +2
AV = +10
AV = +4
GAIN
PHASE
AV = +2
AV = +4
AV = +1
-250
-200
-150
-100
-50
0
50
100
150
Phase (°)
1M 10M 100M 1G
Frequency (Hz)
-7
-6
-5
-4
-3
-2
-1
0
1
Gain (dB)
-430
-380
-330
-280
-230
-180
-130
-80
-30
Phase (°)
AV = -1
AV = -10
AV = -4
AV = -2
PHASE
GAIN
7
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6.6 Typical Characteristics
TA= 25°C, VS= ±5 V, RL= 100 Ω, Rf= 237 Ω(unless otherwise noted)
V0= 2 Vpp RL= 100 ΩRF= 237 Ω
Figure 1. Non-Inverting Frequency Response
VOUT = 2 VPP RF= 237 ΩRL= 100 Ω
Figure 2. Inverting Frequency Response
VOUT = 0.5 VPP AV= 2 RF= 232 Ω
Figure 3. Small Signal Bandwidth
AV= 2 VO= 2 VPP RF= 237 Ω
Figure 4. Frequency Response for Various RLs, AV= 2
AV= 4 VO= 2 VPP RF= 237 Ω
Figure 5. Frequency Response for Various RLs, AV= 4
VO= 2 VPP RL= 100 Ω
Figure 6. Step Response, 2 VPP
110 100 1k 10k
CL (pF)
0
10
20
30
40
50
60
70
80
90
100
RS (:)
0
5
10
15
20
25
Settling Time (ns)
RS
0.05% SETTLING
0.1% SETTLING
-10 -5 0 5 10 15 20
POUT (dBm)
-110
-100
-90
-80
-70
-60
-50
HD (dBc)
60MHz
5MHz
10MHz
20MHz
-5 -3 -1 1 3 5
-110
-100
-90
-70
-50
-40
PS (dBc)
Test Tone Power at 50 : Load (dBm)
25 MHz
50 MHz
75 MHz
-60
-80
1M 10M 100M
Frequency (Hz)
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-40
HD (dBc)
-55
-50
-45 HD2, RL = 1 k:
HD3, RL = 1 k:
HD2, RL = 100 :
HD3, RL = 100 :
0 10 20 30 40 50 60
-4
-3
-2
-1
0
1
3
4
VOUT (V)
Time (ns)
2
110 100 1k
Time (ns)
0.001
0.01
0.1
1
Settling Error (%)
8
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Typical Characteristics (continued)
TA= 25°C, VS= ±5 V, RL= 100 Ω, Rf= 237 Ω(unless otherwise noted)
AV= 2 VOUT = 6 VPP RL= 100 Ω
Figure 7. Step Response, 6 VPP
RL= 100 Ω
Figure 8. Percent Settling vs Time
2 VPP AV= 2 RF= 237 Ω
Figure 9. Harmonic Distortion vs Load and Frequency
(SOIC Package)
AV= 2 RL= 100 ΩRF= 237 Ω
Figure 10. 2 Tone 3rd Order Spurious Level
(SOIC Package)
AV= -1 RL= 1 kΩ
Figure 11. RSand Settling Time vs CL
AV= 2 RF= 237 ΩRL= 100 Ω
Figure 12. HD2 vs Output Power (Across 100 Ω)
(SOIC Package)
0
10
20
30
40
70
CMRR/PSRR (dB)
50
60
-55
-45
-35
-25
-15
15
-5
5
20 Log (RO)
1k 10k 100k 1M 10M
Frequency (Hz) 100M
+ PSRR
- PSRR
RO
CMRR
1
10
1000
100 1k 10k 100k 1M
FREQUENCY (Hz)
100
10M
INVERTING CURRENT
VOLTAGE
NON-INVERTING
CURRENT
NOISE VOLTAGE (nV/ Hz)
NOISE CURRENT (pA/ Hz)
-40 -15 10 35 60 85 110 135
-10
-8
-4
-2
0
2
-6
8
10
IBI (µA)
TEMPERATURE (°C)
UNIT 1
UNIT 3
UNIT 2
4
6
-40 -15 10 35 60 85 110 135
-12
-11
-10
-9
-8
-7
-6
-5
-4
IBN (µA)
TEMPERATURE (°C)
UNIT 1
UNIT 3
UNIT 2
-40 -15 10 35 60 85 110 135
-4
-3.5
-2.5
-2
-1.5
-1
-3
0.5
VOS (mV)
TEMPERATURE (°C)
UNIT 1
UNIT 3
UNIT 2
-0.5
0
-10 -5 0 5 10 15 20
POUT (dBm)
-120
-110
-90
-80
-70
-60
-50
HD (dBc)
60 MHz
5 MHz
10 MHz
20 MHz
-100
9
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Typical Characteristics (continued)
TA= 25°C, VS= ±5 V, RL= 100 Ω, Rf= 237 Ω(unless otherwise noted)
AV= 2 RF= 237 ΩRL= 100 Ω
Figure 13. HD3 vs Output Power (Across 100 Ω)
(SOIC Package) Figure 14. Input Offset for 3 Representative Units
Figure 15. Inverting Input Bias
for 3 Representative Units Figure 16. Non-Inverting Input Bias for 3 Representative
Units
Figure 17. Noise
VS= ±5 V RL= 100 Ω
Figure 18. CMRR, PSRR, ROUT
-1.5 1.5
VOUT (V)
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
DP (°)
DG
DP
00.6 1.2 -0.009
-0.006
-0.003
0
0.003
0.006
0.009
DG (%)
-1.2 -0.6
-0.9 -0.3 0.3 0.9
-1.5 1.5
VOUT (V)
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
DG (%)
DG
DP
00.6 1.2
-0.6
-1.2
DP (°)
-0.006
-0.004
-0.002
0
0.002
0.004
0.006
0.3 0.9-0.3
-0.9
10k 1M 10M 100M 1G
Frequency (Hz)
20
30
50
70
90
100
Gain (dB)
100k
MAG
PHASE
40
80
60
110
120
20
40
80
120
160
180
60
140
100
200
220
Phase (°)
10
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Typical Characteristics (continued)
TA= 25°C, VS= ±5 V, RL= 100 Ω, Rf= 237 Ω(unless otherwise noted)
VS= ±5 V RL= 100 Ω
Figure 19. Transimpedance
RF= 237 ΩRL= 150 Ω
Figure 20. DG/DP (NTSC)
RF= 237 ΩRL= 150 Ω
Figure 21. DG/DP (PAL)
110 100
Frequency (MHz)
-90
-80
-70
-60
-50
-40
-30
HD2 (dBc)
CPOS & CNEG
REMOVED
CPOS & CNEG
INCLUDED
11
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7 Detailed Description
7.1 Overview
The LMH6702 has been optimized for exceptionally low harmonic distortion while driving very demanding
resistive or capacitive loads. Generally, when used as the input amplifier to very high speed flash ADCs, the
distortions introduced by the converter will dominate over the low LMH6702 distortions shown in Typical
Characteristics.
7.2 Feature Description
7.2.1 Harmonic Distortion
The capacitor CSS, shown across the supplies in Figure 24 and Figure 25, is critical to achieving the lowest 2nd
harmonic distortion. For absolute minimum distortion levels, it is also advisable to keep the supply decoupling
currents (ground connections to CPOS, and CNEG in Figure 24 and Figure 25) separate from the ground
connections to sensitive input circuitry (such as RG, RT, and RIN ground connections). Splitting the ground plane
in this fashion and separately routing the high frequency current spikes on the decoupling caps back to the
power supply (similar to Star Connection layout technique) ensures minimum coupling back to the input circuitry
and results in best harmonic distortion response (especially 2nd order distortion).
If this layout technique has not been observed on a particular application board, designer may actually find that
supply decoupling caps could adversely affect HD2 performance by increasing the coupling phenomenon already
mentioned. Figure 22 shows actual HD2 data on a board where the ground plane is shared between the supply
decoupling capacitors and the rest of the circuit. Once these capacitors are removed, the HD2 distortion levels
reduce significantly, especially between 10 MHz to 20 MHz, as shown in Figure 22:
Figure 22. Decoupling Current Adverse Effect on a Board with Shared Ground Plane
At these extremely low distortion levels, the high frequency behavior of decoupling capacitors themselves could
be significant. In general, lower value decoupling caps tend to have higher resonance frequencies making them
more effective for higher frequency regions. A particular application board which has been laid out correctly with
ground returns split to minimize coupling, would benefit the most by having low value and higher value capacitors
paralleled to take advantage of the effective bandwidth of each and extend low distortion frequency range.
Another important variable in getting the highest fidelity signal from the LMH6702 is the package itself. As
already noted, coupling between high frequency current transients on supply lines and the device input can lead
to excess harmonic distortion. An important source of this coupling is in fact through the device bonding wires. A
smaller package, in general, will have shorter bonding wires and therefore lower coupling. This is true in the case
of the SOT-23 compared to the SOIC package where a marked improvement in HD can be measured in the
SOT-23 package. Figure 23 shows the HD comparing SOT-23 to SOIC package:
110 100
Frequency (MHz)
-110
-105
-100
-95
-90
-80
-60
HD2 (dBc)
HD3, SOT23
HD2, SOIC
HD2, SOT23
HD3, SOIC
-65
-70
-85
-75
12
LMH6702
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Feature Description (continued)
Figure 23. SOIC and SOT-23 Packages Distortion Terms Compared
The LMH6702 data sheet shows both SOT-23 and SOIC data in Electrical Characteristics to aid in selecting the
right package. Typical Characteristics shows SOIC package plots only.
7.3 Device Functional Modes
7.3.1 2-Tone 3rd Order Intermodulation
Figure 10 shows a relatively constant difference between the test power level and the spurious level with the
difference depending on frequency. The LMH6702 does not show an intercept type performance, (where the
relative spurious levels change at a 2X rate versus the test tone powers), due to an internal full power bandwidth
enhancement circuit that boosts the performance as the output swing increases while dissipating negligible
quiescent power under low output power conditions. This feature enhances the distortion performance and full
power bandwidth to match that of much higher quiescent supply current parts.
7.3.2 DC Accuracy and Noise
The example in Equation 1 shows the output offset computation equation for the non-inverting configuration
using the typical bias current and offset specifications for AV= 2:
Output Offset:
VO= (±IBN · RIN ± VIO) (1 + RF/RG) ± IBI · RF
where
• RIN is the equivalent input impedance on the non-inverting input. (1)
Example computation for AV= +2, RF= 237Ω, RIN = 25Ω:
VO= (±6 μA × 25 Ω± 1mV) (1 + 237/237) ± 8 μA × 237 = ±4.20 mV (2)
A good design, however, should include a worst case calculation using min/max numbers in the data sheet
tables, in order to ensure worst case operation.
Further improvement in the output offset voltage and drift is possible using the composite amplifiers described in
Application Note OA--07, Current Feedback Op Amp Applications Circuit Guide (SNOA365). The two input bias
currents are physically unrelated in both magnitude and polarity for the current feedback topology. It is not
possible, therefore, to cancel their effects by matching the source impedance for the two inputs (as is commonly
done for matched input bias current devices).
The total output noise is computed in a similar fashion to the output offset voltage. Using the input noise voltage
and the two input noise currents, the output noise is developed through the same gain equations for each term
but combined as the square root of the sum of squared contributing elements. See Application Note OA-12,
Noise Analysis for Comlinear Amplifiers (SNOA375) for a full discussion of noise calculations for current
feedback amplifiers.
4
3
2
7
6
LMH6702
VOUT
+
-
VIN
+5V
-5V
CPOS
6.8µF
RGRF
.01µF
6.8µF
CNEG
.01µF
RT
25:0.1µF
CSS
SELECT RT TO
YIELD DESIRED
RIN = RT||RG
AV = VOUT
VIN
RF
RG=
4
3
2
7
6
LMH6702
VOUT
+
-
VIN
+5V
-5V
CPOS
6.8µF
RG
RF
.01µF
6.8µF
CNEG
.01µF
RIN 0.1µF
CSS
AV = 1 +RF/RG = VOUT/VIN
13
LMH6702
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMH6702 achieves its excellent pulse and distortion performance by using the current feedback topology.
The loop gain for a current feedback op amp, and hence the frequency response, is predominantly set by the
feedback resistor value. The LMH6702 is optimized for use with a 237-Ωfeedback resistor. Using lower values
can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth.
8.2 Typical Application
8.2.1 Feedback Resistor
The LMH6702 achieves its excellent pulse and distortion performance by using the current feedback topology.
The loop gain for a current feedback op amp, and hence the frequency response, is predominantly set by the
feedback resistor value. The LMH6702 is optimized for use with a 237-Ωfeedback resistor. Using lower values
can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth.
Figure 24. Recommended Non-Inverting Gain Circuit
Figure 25. Recommended Inverting Gain Circuit
LMH6702
+
-CIN
ADC
RS
14
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Typical Application (continued)
8.2.2 Design Requirements
The exceptional performance and uniquely targeted superior technical specifications of the LMH6702 make it a
natural choice for high speed data acquisition applications as a front end amplifier driving the input of a high
performance ADC. Of these specifications, the following can be discussed in more detail:
1. A bandwidth of 1.7 GHz and relative insensitivity of bandwidth to closed loop gain (characteristic of Current
Feedback architecture when compared to the traditional voltage feedback architecture) as shown in Figure 1.
2. Ultra-low distortion approaching -87 dBc at the lower frequencies and exceptional noise performance (see
Figure 9 and Figure 17).
3. Fast settling in less than 20 ns (see Figure 27).
As the input of an ADC could be capacitive in nature and could also alternate in capacitance value during a
typical acquisition cycle, the driver amplifier (LMH6702 in this case) should be designed so that it avoids
instability, peaking, or other undesirable artifacts.
For Capacitive Load Drive, see Figure 26, which shows a typical application using the LMH6702 to drive an
ADC.
Figure 26. Input Amplifier to ADC
8.2.3 Detailed Design Procedure
The series resistor, RS, between the amplifier output and the ADC input is critical to achieving best system
performance. This load capacitance, if applied directly to the output pin, can quickly lead to unacceptable levels
of ringing in the pulse response. Figure 27 in Application Curve (RSand Settling Time vs CL) is an excellent
starting point for selecting RS. The value derived in that plot minimizes the step settling time into a fixed discrete
capacitive load with the output driving a very light resistive load (1 kΩ). Sensitivity to capacitive loading is greatly
reduced once the output is loaded more heavily. Therefore, for cases where the output is heavily loaded, RS
value may be reduced. The exact value may best be determined experimentally for these cases.
In applications where the LMH6702 is replacing the CLC409, care must be taken when the device is lightly
loaded and some capacitance is present at the output. Due to the much higher frequency response of the
LMH6702 compared to the CLC409, there could be increased susceptibility to low value output capacitance
(parasitic or inherent to the board layout or otherwise being part of the output load). As already mentioned, this
susceptibility is most noticeable when the LMH6702's resistive load is light. Parasitic capacitance can be
minimized by careful lay out. Addition of an output snubber R-C network will also help by increasing the high
frequency resistive loading.
Referring back to Figure 26, it must be noted that several additional constraints should be considered in driving
the capacitive input of an ADC. There is an option to increase RS, band-limiting at the ADC input for either noise
or Nyquist band-limiting purposes. However, increasing RStoo much can induce an unacceptably large input
glitch due to switching transients coupling through from the convert signal. Also, CIN is oftentimes a voltage
dependent capacitance. This input impedance non-linearity will induce distortion terms that will increase as RSis
increased. Only slight adjustments up or down from the recommended RSvalue should therefore be attempted in
optimizing system performance.
110 100 1k 10k
CL (pF)
0
10
20
30
40
50
60
70
80
90
100
RS (:)
0
5
10
15
20
25
Settling Time (ns)
RS
0.05% SETTLING
0.1% SETTLING
15
LMH6702
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Typical Application (continued)
8.2.4 Application Curve
AV= -1 RL=1kΩ
Figure 27. RSand Settling Time vs CL
9 Power Supply Recommendations
The LMH6702 can operate off a single supply or with dual supplies as long as the input CM voltage range
(CMIR) has the required headroom to either supply rail. Supplies should be decoupled with low inductance, often
ceramic, capacitors to ground less than 0.5 inches from the device pins. The use of ground plane is
recommended, and as in most high speed devices, it is advisable to remove ground plane close to device
sensitive pins such as the inputs.
10 Layout
10.1 Layout Guidelines
Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations. See Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers,
Application Note OA-15 (SNOA367). Texas Instruments suggests the following evaluation boards as a guide for
high frequency layout and as an aid in device testing and characterization. See Table 1 for details.
The LMH6702 evaluation board(s) is a good example of high frequency layout techniques as a reference.
General high-speed, signal-path layout suggestions include:
• Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs.
However, open up both ground and power planes around the capacitive sensitive input and output device
pins as shown in Figure 28. After the signal is sent into a resistor, parasitic capacitance becomes more of a
bandlimiting issue and less of a stability issue.
• Use good, high-frequency decoupling capacitors (0.1 μF) on the ground plane at the device power pins as
shown in Figure 28. Higher value capacitors (2.2 μF) are required, but may be placed further from the device
power pins and shared among devices. For best high-frequency decoupling, consider X2Y supply-decoupling
capacitors that offer a much higher self-resonance frequency over standard capacitors.
• When using differential signal routing over any appreciable distance, use microstrip layout techniques with
matched impedance traces.
• The input summing junction is very sensitive to parasitic capacitance. Connect any Rf, and Rg elements into
the summing junction with minimal trace length to the device pin side of the resistor, as shown in Figure 29.
The other side of these elements can have more trace length if needed to the source or to ground.
16
LMH6702
SNOSA03H –NOVEMBER 2002–REVISED MAY 2016
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10.2 Layout Example
Figure 28. LMH6702 Evaluation Board Layer 1
Figure 29. LMH6702 Evaluation Board Layer 2
Table 1. Evaluation Board Comparison
DEVICE PACKAGE EVALUATION BOARD PART NUMBER
LMH6702MF SOT-23 LMH730216
LMH6702MA SOIC LMH730227
17
LMH6702
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•Absolute Maximum Ratings for Soldering (SNOA549)
•Current Feedback Op Amp Applications Circuit Guide, Application Note OA--07 (SNOA365)
•Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, Application Note OA-15 (SNOA367)
•Noise Analysis for Comlinear Amplifiers, Application Note OA-12 (SNOA375)
•Semiconductor and IC Package Thermal Metrics (SPRA953)
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
VIP10, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6702MA NRND SOIC D 8 95 Non-RoHS
& Green Call TI Call TI -40 to 85 LMH67
02MA
LMH6702MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH67
02MA
LMH6702MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH67
02MA
LMH6702MF/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A83A
LMH6702MFX/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A83A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6702MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6702MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6702MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6702MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6702MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMH6702MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/E 09/2019
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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