8/5/05
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PD - 97034
HEXFET® Power MOSFET
Features of this design are a 150°C junction oper-
ating temperature, fast switching speed and im-
proved repetitive avalanche rating . These features
combine to make this design an extremely efficient
and reliable device for use in a wide variety of other
applications.
Description
OAdvanced Process Technology
OUltra Low On-Resistance
O150°C Operating Temperature
OFast Switching
ORepetitive Avalanche Allowed up to Tjmax
OSome Parameters Are Differrent from
IRF4905S
OLead-Free
Features
IRF4905SPbF
IRF4905LPbF
VDSS = -55V
RDS(on) = 20mΩ
ID = -42A
D2Pak
IRF4905SPbF
TO-262
IRF4905LPbF
S
D
G
D
S
D
G
D
GDS
Gate Drain Source
S
D
G
Absolute Maximum Ratings
Parameter Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)
IDM Pulsed Drain Current
c
PD @TC = 25°C Power Dissipation W
Linear Derating Factor W/°C
VGS Gate-to-Source Voltage V
EAS (Thermally limited) Single Pulse Avalanche Energy
d
mJ
EAS (Tested ) Single Pulse Avalanche Energy Tested Value
h
IAR Avalanche Current
c
A
EAR Repetitive Avalanche Energy
g
mJ
TJ Operating Junction and
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
i
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case
j
––– 0.75
RθJA Junction-to-Ambient (PCB Mount, steady state)
ij
––– 40
-55 to + 150
300 (1.6mm from case )
10 lbf
y
in (1.1N
y
m)
170
1.3
± 20
Max.
-70
-44
-280
-42
790
140
See Fig.12a, 12b, 15, 16
IRF4905S/L
2www.irf.com
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
V(BR)DSS Drain-to-Source Breakdown Voltage -55 ––– ––– V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– -0.054 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 20 mΩ
VGS(th) Gate Threshold Voltage -2.0 ––– -4.0 V
gfs Forward Transconductance 19 ––– ––– S
IDSS Drain-to-Source Leakage Current ––– ––– -25 µA
––– ––– -200
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
QgTotal Gate Charge ––– 120 180
Qgs Gate-to-Source Charge ––– 32 ––– nC
Qgd Gate-to-Drain ("Miller") Charge ––– 53 –––
td(on) Turn-On Delay Time ––– 20 –––
trRise Time ––– 99 –––
td(off) Turn-Off Delay Time ––– 51 ––– ns
tfFall Time ––– 64 –––
LSInternal Source Inductance ––– 7.5 ––– nH Between lead,
and center of die contact
Ciss Input Capacitance ––– 3500 –––
Coss Output Capacitance ––– 1250 –––
Crss Reverse Transfer Capacitance ––– 450 ––– pF
Coss Output Capacitance ––– 4620 –––
Coss Output Capacitance ––– 940 –––
Coss eff. Effective Output Capacitance ––– 1530 –––
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units
ISContinuous Source Current ––– ––– -42
(Body Diode) A
ISM Pulsed Source Current ––– ––– -280
(Body Diode)
c
VSD Diode Forward Voltage ––– ––– -1.3 V
tr
r
Reverse Recovery Time ––– 61 92 ns
Qr
r
Reverse Recovery Charge ––– 150 220 nC
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
VDS = -25V, ID = -42A
ID = -42A
VDS = -44V
Conditions
VGS = -10V
e
VGS = 0V
VDS = -25V
ƒ = 1.0MHz
VGS = -20V
VGS = 20V
MOSFET symbol
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = -42A, VGS = 0V
e
TJ = 25°C, IF = -42A, VDD = -28V
di/dt = -100A/µs
e
Conditions
VGS = 0V, ID = -250µA
Reference to 25°C, ID = -1mA
VGS = -10V, ID = -42A
e
VDS = VGS, ID = -250µA
VDS = -55V, VGS = 0V
VDS = -44V, VGS = 0V, TJ = 125°C
VGS = 0V, VDS = -1.0V, ƒ = 1.0MH
z
VGS = 0V, VDS = -44V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to -44V
f
VGS = -10V
e
VDD = -28V
ID = -42A
RG = 2.6 Ω
IRF4905S/L
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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance
Vs. Drain Current
0.1 110 100 1000
-VDS, Drain-to-Source Voltage (V)
1
10
100
1000
-ID, Drain-to-Source Current (A)
≤ 60µs PULSE WIDTH
Tj = 25°C
-4.5V
VGS
TOP -15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM -4.5V
0.1 110 100 1000
-VDS, Drain-to-Source Voltage (V)
1
10
100
1000
-ID, Drain-to-Source Current (A)
≤ 60µs PULSE WIDTH
Tj = 150°C
-4.5V
VGS
TOP -15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM -4.5V
345678910 11 12 13 14
-VGS, Gate-to-Source Voltage (V)
0.1
1.0
10.0
100.0
1000.0
-ID, Drain-to-Source Current
(Α)
VDS = -25V
≤ 60µs PULSE WIDTH
TJ = 25°C
TJ = 150°C
0 20406080
-ID, Drain-to-Source Current (A)
0
10
20
30
40
Gfs, Forward Transconductance (S)
TJ = 25°C
TJ = 150°C
VDS = -10V
380µs PULSE WIDTH
IRF4905S/L
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
-VDS, Drain-to-Source Voltage (V)
0
1000
2000
3000
4000
5000
6000
7000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 40 80 120 160 200
QG Total Gate Charge (nC)
0
4
8
12
16
20
-VGS, Gate-to-Source Voltage (V)
VDS= -44V
VDS= -28V
VDS= -11V
ID= -42A
0.0 0.4 0.8 1.2 1.6 2.0
-VSD, Source-to-Drain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
-ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 150°C
VGS = 0V
0 1 10 100
-VDS , Drain-toSource Voltage (V)
1
10
100
1000
-ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 150°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
DC
LIMITED BY PACKAGE
IRF4905S/L
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1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
Thermal Response ( Z
thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Normalized On-Resistance
Vs. Temperature
Ri (°C/W) τi (sec)
0.1165 0.000068
0.3734 0.002347
0.2608 0.014811
τJ
τJ
τ1
τ1
τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
τ
τC
Ci τi/Ri
Ci= τi/Ri
25 50 75 100 125 150
TC , Case Temperature (°C)
0
20
40
60
80
-ID , Drain Current (A)
LIMITED BY PACKAGE
-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = -42A
VGS = -10V
IRF4905S/L
6www.irf.com
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
Fig 14. Threshold Voltage Vs. Temperature
25 50 75 100 125 150
Starting TJ, Junction Temperature (°C)
0
100
200
300
400
500
600
EAS, Single Pulse Avalanche Energy (mJ)
I D
TOP -17A
-30A
BOTTOM -42A
-75 -50 -25 025 50 75 100 125 150
TJ , Temperature ( °C )
2.0
2.4
2.8
3.2
3.6
-VGS(th) Gate threshold Voltage (V)
ID = -250µA
D.U.T. V
DS
I
D
I
G
-3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Q
G
Q
GS
Q
GD
V
G
Charge
10V
tp
V
(
BR
)
DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
V
DS
V
DD
DRIVER
A
15V
-20V
IRF4905S/L
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Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25 50 75 100 125 150
Starting TJ , Junction Temperature (°C)
0
40
80
120
160
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = -42A
IRF4905S/L
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Fig 17. Peak Diode Recovery dv/dt Test Circuit for P-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T**
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
VDS
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
VDD
RG
D.U.T.
+
-
** Reverse Polarity of D.U.T for P-Channel
IRF4905S/L
www.irf.com 9
D2Pak Part Marking Information
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
RECTIFIER
INTERNATIONAL
LOGO
LOT CODE
ASSEMBLY
YEAR 0 = 2000
DAT E CODE
PART NUMBER
F530S
A = ASSEMBLY SITE CODE
WEEK 02
P = DE S I GNAT E S L E AD- F R E E
PRODUCT (OPTIONAL)
INT E RNAT IONAL
LOT CODE
ASSEMBLY
pos ition indicates "L ead-F ree"
AS SE MBL ED ON WW 02, 2000
Note: "P" in as sembly line
IN THE ASSEMBLY LINE "L"
LOT CODE 8024
T HIS IS AN IRF 530S WITH
RECT IF IER
LOGO
LINE L
WEEK 02
YEAR 0 = 2000
DAT E CODE
PART NUMBER
F530S
OR
IRF4905S/L
10 www.irf.com
TO-262 Package Outline (Dimensions are shown in millimeters (inches))
TO-262 Part Marking Information
AS S E MB L Y
LOT CODE
RECTIFIER
INTERNATIONAL
AS S E MBL ED ON WW 19, 1997
Note: "P" in assembly line
pos iti on i ndi cates "L ead-F ree"
IN THE ASSEMBLY LINE "C" LOGO
T HIS IS AN IRL 3103L
LOT CODE 1789
EXAMPLE:
LINE C
DAT E CODE
WE E K 19
YEAR 7 = 1997
PART NUMBER
PART NUMBER
LOGO
LOT CODE
AS S E MB L Y
INT ERNATIONAL
RECTIFIER
PRODUCT (OPT IONAL)
P = DE S IGN AT E S L E AD-F R E E
A = AS S E MB L Y S I T E CODE
WEEK 19
YEAR 7 = 1997
DAT E CODE
OR
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
IRF4905S/L
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Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/05
D2Pak Tape & Reel Information
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421)
16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.16mH
RG = 25Ω, IAS = -42A, VGS =-10V. Part not
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the
same charging time as Coss while VDS is rising
from 0 to 80% VDSS .
Notes:
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
This is applied to D2Pak, when mounted on 1" square PCB (FR-
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
