MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low Supply Voltage Range 2.5 V – 5.5 V
D
Ultra Low-Power Consumption
D
Low Operation Current, 330 µA at 1 MHz,3 V
D
Two Power Saving Modes:
– Standby Mode: 1.5 µA
– RAM Retention Off Mode: 0.1 µA
D
Wake-up From Standby Mode in 6 µs
Maximum
D
16-Bit RISC Architecture, 200 ns Instruction
Cycle Time
D
Basic Clock Module Configurations:
– Various Internal Resistors
– Single External Resistor
– 32 kHz Crystal
– High Frequency Crystal
– Resonator
– External Clock Source
D
Single Slope A/D Converter With External
Components
D
16-Bit Timer With 3 Capture/Compare
Registers
D
Serial Onboard Programming
D
Program Code Protection by Security Fuse
D
Family Members Include:
MSP430C111: 2k Byte ROM,128 Byte RAM
MSP430C112: 4k Byte ROM, 256 Byte RAM
MSP430P112: 4k Byte OTP, 256 Byte RAM
D
EPROM Version Available for Prototyping:
– PMS430E112: 4k Byte EPROM, 256 Byte
RAM
D
Available in a 20-Pin Plastic Small-Outline
Wide Body (SOWB) Package, 20-Pin
Ceramic Dual-In-Line (CDIP) Package
(EPROM Only)
description
The Texas Instruments MSP430 series is an ultra
low-power microcontroller family consisting of
several devices featuring different sets of
modules targeted to various applications. The
microcontroller is designed to be battery operated
for an extended application lifetime. With 16-bit
RISC architecture, 16 bit integrated registers on
the CPU, and the constant generator, the MSP430
achieves maximum code efficiency. The digitally-
controlled oscillator provides fast wake-up from all
low-power modes to active mode in less than 6
m
s.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data and display them or transmit them to a host system. Stand alone RF sensor front-end is another
area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors. The
MSP430x11x series is an ultra low-power mixed signal microcontroller with a built in 16-bit timer and fourteen
I/O pins.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TEST/VPP
VCC
P2.5/ROSC
VSS
Xout/TCLK
Xin
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/TA0
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2
P2.3/TA1
DW PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
TASOWB
20-Pin
(DW)
CDIP
20-Pin
(JL)
40
°
Cto85
°
C
MSP430C111IDW
MSP430C112IDW
–
40°C
to
85°C
MSP430C112IDW
MSP430P112IDW
25
°
C
PMS430E112JL
25°C
—
PMS430E112JL
functional block diagram
Oscillator
System Clock
ACLK
SMCLK
2/4 kB ROM
4 kB OTP
’C’: ROM
128/256B
RAM Power-on-
Reset I/O Port
8 I/O’ s, All With
Interrupt
CPU
Incl. 16 Reg. Test
JTAG
Bus
Conv.
MAB, 16 Bit
MDB, 16 Bit
MAB, 4 Bit
MDB, 8 Bit
MCB
XIN XOut VCC VSS RST/NMI P1.0–7
DCOR
ACLK
P2.0–5
Rosc
TEST/VPP
’P’: OTP
Outx
Timer_A
3 CC Register
CCR0/1/2
Watchdog
Timer
15/16 Bit
MCLK
’E’: EPROM
x = 0, 1, 2
ACLK
SMCLK
Outx
CCIxA
CCIxB
TACLK or
INCLK INCLK
Out0
CCI0B
CCI1B
JTAG
CCIxA
TACLK
SMCLK
I/O Port 2
6 I/O’ s All With
8
6
Capabililty
Interrupt
Capabililty
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
P1.0/TACLK 13 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0 14 I/O General-purpose digital I/O pin/T imer_A, Capture: CCI0A input, Compare: Out0 output
P1.2/TA1 15 I/O General-purpose digital I/O pin/T imer_A, Capture: CCI1A input, Compare: Out1 output
P1.3/TA2 16 I/O General-purpose digital I/O pin/T imer_A, Capture: CCI2A input, Compare: Out2 output
P1.4/SMCLK/TCK 17 I/O General-purpose digital I/O pin/SMCLK signal output/Test clock, input terminal for device programming
and test
P1.5/TA0/TMS 18 I/O General-purpose digital I/O pin/Timer_A, Compare: Out0 output/test mode select, input terminal for
device programming and test.
P1.6/TA1/TDI 19 I/O General-purpose digital I/O pin/T imer_A, Compare: Out1 output/test data input terminal.
P1.7/TA2/TDO/TDI 20 I/O General-purpose digital I/O pin/Timer_A, Compare: Out2 output/test data output terminal or data input
during programming.
P2.0/ACLK 8 I/O General-purpose digital I/O pin/ACLK output
P2.1/INCLK 9 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/TA0 10 I/O General-purpose digital I/O pin/T imer_A, Capture: CCI0B input, Compare: Out0 output
P2.3/TA1 11 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI1B input, Compare: Out1 output
P2.4/TA2 12 I/O General-purpose digital I/O pin/T imer_A, Compare: Out2 output
P2.5/ROSC 3 I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency
RST/NMI 7 I Reset or nonmaskable interrupt input
TEST/VPP 1 I Select of test mode for JTAG pins on Port1/programming voltage input during EPROM programming
VCC 2Supply voltage
VSS 4Ground reference
Xin 6 I Input terminal of crystal oscillator
Xout/TCLK 5 I/O Output terminal of crystal oscillator or test clock input
detailed description
processing unit
The processing unit is based on a consistent, and orthogonally designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development and
distinguished by ease of programming. All operations other than program-flow instructions are consequently
performed as register operations in conjunction with seven addressing modes for source and four modes for
destination operations.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
CPU
All sixteen registers are located inside the CPU,
providing reduced instruction execution time. This
reduces a register-register operation execution
time to one cycle of the processor.
Four registers are reserved for special use as a
program counter, a stack pointer, a status register,
and a constant generator. The remaining twelve
registers are available as general-purpose
registers.
Peripherals are connected to the CPU using a
data address and control buses and can be
handled easily with all instructions for memory
manipulation.
instruction set
The instructions set for this register-register architecture provides a powerful and easy-to-use assembly
language. The instruction set consists of 51 instructions with three formats and seven addressing modes.
Table 1 provides a summation and example of the three types of instruction formats; the addressing modes are
listed in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g. ADD R4, R5 R4 + R5 → R5
Single operands, destination only e.g. CALL R8 PC → (TOS), R8 → PC
Relative jump, un-/conditional e.g. JNE Jump-on equal bit = 0
Most instructions can operate on both word and byte data. Byte operations are identified by the suffix B.
Examples: Instructions for word operation Instructions for byte operation
MOV EDE,TONI MOV.B EDE,TONI
ADD #235h,&MEM ADD.B #35h,&MEM
PUSH R5 PUSH.B R5
SWPB R5 —
Table 2. Address Mode Descriptions
ADDRESS MODE s d SYNTAX EXAMPLE OPERATION
Register √ √ MOV Rs, Rd MOV R10, R11 R10 → R11
Indexed √ √ MOV X(Rn), Y(Rm) MOV 2(R5), 6(R6) M(2 + R5) → M(6 + R6)
Symbolic (PC relative) √ √ MOV EDE, TONI M(EDE) → M(TONI)
Absolute √ √ MOV &MEM, &TCDAT M(MEM) → M(TCDAT)
Indirect √MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) → M(Tab + R6)
Indirect autoincrement √MOV @Rn+, RM MOV @R10+, R11 M(R10) →R11, R10 + 2 → R10
Immediate √MOV #X, TONI MOV #45, T ONI #45 → M(TONI)
NOTE: s = source d = destination Rs/Rd = source register/destination register Rn = register number
Program Counter
General-Purpose Register
PC/R0
Stack Pointer SP/R1
Status Register SR/CG1/R2
Constant Generator CG2/R3
R4
General-Purpose Register R5
General-Purpose Register R14
General-Purpose Register R15
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
instruction set (continued)
Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other
instructions. These addressing modes provide
indirect
addressing, ideally suited for computed branches and
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.
operation modes and interrupts
The MSP430 operating modes support various advanced requirements for ultra low-power and ultra low-energy
consumption. This is achieved by the intelligent management of the operations during the different module
operation modes and CPU states. The advanced requirements are fully supported during interrupt event
handling. An interrupt event awakens the system from each of the various operating modes and returns with
the
RETI
instruction to the mode that was selected before the interrupt event. The different requirements of the
CPU and modules, which are driven by system cost and current consumption objectives, necessitate the use
of different clock signals (see Figure 1):
D
Auxiliary clock ACLK (from LFXTCLK/crystal’s frequency), used by the peripheral modules
D
Main system clock MCLK, used by the CPU and system
D
Subsystem clock SMCLK, used by the peripheral modules.
DIVA
XIN
High Frequency
XT Oscillator , XTS=1
ACLK
OSCOff XTS
Low Power
LF Oscillator, XTS = 0
/1, /2, /4, /8
2
DIVM
/1, /2, /4, /8, Off
22
SELM CPUOff
Auxiliary Clock
MCLK
Main System Clock
DIVS
/1, /2, /4, /8, Off
2
SELS SCG1
SMCLK
Sub-System Clock
XOUT
SMCLKGEN
LFXTCLK
MCLKGEN
ACLKGEN
DCOMOD
DCOCLK
Digital Controlled Oscillator (DCO)
+
Modulator (MOD)
DC
Generator
53
DCO MODRsel SCG0
DCOR
The DCO-Generator is connected to pin P2.5/ROSC if DCOR control bit is set.
The port pin P2.5/ROSC is selected if DCOR control bit is reset (initial state).
P2.5
VCC
VCC
0
1
P2.5/ROSC
3
2
0
1
Figure 1. Clock Signals
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operation modes and interrupts (continued)
Two clock sources, LFXTCLK and DCOCLK, can be used to drive the MSP430 system. The LFXTCLK is defined
by connecting a low power , low frequency crystal to the oscillator , by connecting a high frequency crystal to the
oscillator , or by applying an external clock source. The high frequency crystal oscillator is used if the control bit
XTS is set. The crystal oscillator may be switched off when the LFXTCLK oscillator is not needed for the present
operation mode. The DCOCLK is active and the frequency is selected or adjusted by the software. The
DCOCLK is inactive or stopped when it is not used by the CPU or peripheral modules. The dc-generator can
be stopped when SCG0 is reset and DCOCLK is not needed. The dc-generator defines the basic DCO
frequency and can be defined by one external resistor or it is adjusted in eight steps with the integrated resistors.
NOTE:
The system clock generator always starts with the DCOCLK selected for MCLK (CPU clock) to
ensure proper start of program execution. The software then defines the final system clock, via
control bit manipulation.
low-power consumption capabilities
The various operating modes are controlled by the software through controlling the operation of the internal
clock system. This clock system provides many combinations of hardware and software capabilities to run the
application with the lowest power consumption and with optimized system costs:
D
Use the internal clock (DCO) generator without any external components.
D
Select an external crystal or ceramic resonator for lowest frequency or cost.
D
Select and activate the proper clock signals (LFXTCLK and/or DCOCLK) and clock pre-divider function.
D
Apply an external clock source.
Four of the control bits that influence the operation of the clock system and support fast turnon from low power
operating modes are located in the status register SR. The four bits that control the CPU and the system clock
generator are SCG1, SCG0, OscOff, and CPUOff:
status register R2
Reserved For Future
Enhancements
15 9 8 7 0
V SCG1 SCG0 OscOff CPUOff GIE N Z C
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
6543 21
The bits CPUOff, SCG1, SCG0, and OscOff are the most important low-power control bits when the basic
function of the system clock generator is established. They are pushed onto the stack whenever an interrupt
is accepted and thereby saved so that the previous mode of operation can be retrieved after the interrupt
request. During execution of an interrupt handler routine, the bits can be manipulated via indirect access of the
data on the stack. That allows the program to resume execution in another power operating mode after the
return from interrupt (RETI).
SCG1: The clock signal SMCLK, used for peripherals, is enabled when the bit is reset or disabled if the
bit is set.
SCG0: The dc-generator is active when it is reset. The DCO can be deactivated only if the SCG0 bit is
set and the DCOCLK signal is not used for MCLK or SMCLK. The current consumed by the
dc-generator defines the basic frequency of the DCOCLK. It is a dc current.
NOTE:
When the current is switched off (SCG0=1) the start of the DCOCLK is delayed slightly. The delay
is in the µs-range. See device parameters for the specified values.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
status register R2 (continued)
OscOff: The LFXT crystal oscillator is active when the OscOff bit is reset. The LFXT oscillator can only be
deactivated if the OscOff bit is set and it is not used for MCLK or SMCLK. The setup time to start
a crystal oscillation needs consideration when the oscillator off option is used. Mask
programmable (ROM) devices can disable this feature so that the oscillator can never be switched
off by software.
CPUOf f: The clock signal MCLK, used for the CPU, is active when the bit is reset or stopped if it is set.
DCOCLK: The clock signal DCOCLK is deactivated if it is not used for MCLK or SMCLK or if the SCG0 bit
is set. There are two situations when the SCG0 bit cannot switch off the DCOCLK signal:
1. DCOCLK frequency is used for MCLK (CPUOff=0 and SELM.1=0).
2. DCOCLK frequency is used for SMCLK (SCG1=0 and SELS=0).
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the ROM with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up, external reset, watchdog WDTIFG (see Note1) Reset 0FFFEh 15, highest
NMI, oscillator fault NMIIFG, OFIFG (see Note 1) (non)-maskable,
(non)-maskable 0FFFCh 14
0FFFAh 13
0FFF8h 12
0FFF6h 11
W atchdog Timer WDTIFG maskable 0FFF4h 10
Timer_A CCIFG0 (see Note 2) maskable 0FFF2h 9
Timer_A CCIFG1, CCIFG2, TAIFG
(see Notes 1 and 2) maskable 0FFF0h 8
0FFEEh 7
0FFECh 6
0FFEAh 5
0FFE8h 4
I/O Port P2 (eight flags – see Note 3) P2IFG.0 to P2IFG.7
(see Notes 1 and 2) maskable 0FFE6h 3
I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7
(see Notes 1 and 2) maskable 0FFE4h 2
0FFE2h 1
0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module
3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0–5) are implemented on the 11x devices.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1
7654 0
OFIE WDTIE
321
rw-0 rw-0 rw-0
Address
0h NMIIE
WDTIE: Watchdog Timer enable signal
OFIE: Oscillator fault enable signal
NMIIE: Non-maskable interrupt enable signal
interrupt flag register 1
7654 0
OFIFG WDTIFG
321
rw-0 rw-1 rw-0
Address
02h NMIIFG
WDTIFG: Set on overflow or security key violation
OR
Reset on VCC power-on or reset condition at RST/NMI-pin
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI-pin
Legend rw:
rw-0: Bit can be read and written.
Bit can be read and written. It is reset by PUC
SFR bit is not present in device.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
memory organization
Int. Vector
2 kB ROM
128B RAM
16b Per .
8b Per.
SFR
FFFFh
FFE0h
FFDFh
F800h
027Fh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
MSP430C111
Int. Vector
4 kB
EPROM
256B RAM
16b Per .
8b Per.
SFR
FFFFh
FFE0h
FFDFh
02FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
MSP430P112
PMS430E112
Int. Vector
4 kB ROM
256B RAM
16b Per .
8b Per.
SFR
FFFFh
FFE0h
FFDFh
F000h
02FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
MSP430C112
F000h
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled easily with
instructions for memory manipulation.
digital I/O
There are two eight-bit I/O ports, Port P1 and Port P2 – implemented (1 1x parts only have six Port P2 I/O signals
available on external pins). Both ports, P1 and P2, have seven control registers to give maximum flexibility of
digital input/output to the application:
•All individual I/O bits are programmable independently.
•Any combination of input, output, and interrupt conditions is possible.
•Interrupt processing of external events is fully implemented for all eight bits of port P1 and for six bits of
Port P2.
•Provides read/write access to all registers with all instructions.
The seven registers are:
•Input register 8 bits at Port P1/P2 contains information at the pins
•Output register 8 bits at Port P1/P2 contains output information
•Direction register 8 bits at Port P1/P2 controls direction
•Interrupt edge select 8 bits at Port P1/P2 input signal change necessary for interrupt
•Interrupt flags 8 bits at Port P1/P2 indicates if interrupt(s) are pending
•Interrupt enable 8 bits at Port P1/P2 contains interrupt enable bits
•Selection (Port or Mod.) 8 bits at Port P1/P2 determines if pin(s) have port or module function
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
digital I/O (continued)
All these registers contain eight bits. Two interrupt vectors are implemented: one commonly used for any
interrupt event on Port P1.0 to Port P1.7, and one commonly used for any interrupt event on Port P2.0 to P2.7.
NOTE:
Six bits of Port P2, P2.0 to P2.5, are available on external pins – but all control and data bits for Port
P2 are implemented.
Watchdog Timer
The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a
software problem has occurred. If the selected time interval expires, a system reset is generated. If this
watchdog function is not needed in an application, the module can work as an interval timer, which generates
an interrupt after the selected time interval.
The Watchdog Timer counter (WDTCNT) is a 16-bit up-counter which is not directly accessible by S/W. The
WDTCNT is controlled through the Watchdog Timer control register (WDTCTL), which is a 16-bit read/write
register . Writing to WDTCTL is, in both operating modes (watchdog or timer), only possible by using the correct
password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte must be the
password 05Ah. If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC
is generated. When the password is read, its value is 069h. This minimizes accidental write operations to the
WDTCTL register. In addition to the Watchdog Timer control bits, there are two bits included in the WDTCTL
register that configure the NMI pin.
Timer_A (3 capture/compare registers)
The Timer_A module on 11x devices offers one sixteen bit counter and three capture/compare registers. The
timer clock source can be selected to come from two external sources TACLK (SSEL=0) or INCLK (SSEL=3),
or from two internal sources, the ACLK (SSEL=1) or SMCLK (SSEL=2). The clock source can be divided by
one, two, four, or eight. The timer can be fully controlled (in word mode) since it can be halted, read, and written.
It can be stopped, run continuously , counted up or up/down, using one compare block to determine the period.
The three capture/compare blocks are configured by the application to run in capture or compare mode.
The capture mode is primarily used to measure external or internal events using any combination of positive,
negative, or both edges of the signal. Capture mode can be started and stopped by software. Three different
external events TA0, TA1, and TA2 can be selected. At capture/compare register CCR2 the ACLK is the capture
signal if CCI2B is selected. Software capture is chosen if CCISx=2 or CCISx=3 (see Figure 2).
The compare mode is primarily used to generate timings for the software or application hardware, or to generate
pulse-width modulated output signals for various purposes like D/A conversion functions or motor control. An
individual output module is assigned to each of the three capture/compare registers. The output modules can
run independently of the compare function, or can be triggered in several ways.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Timer_A (3 capture/compare registers) (continued)
P1.1
P1.5
P2.2
P1.2
P1.6
P2.3
P1.3
P1.7
P2.4
Input
Divider CLK
16-Bit Timer
SSEL0SSEL1
TACLK
ACLK
SMCLK
0
1
2
3RC
INCLK
ID1 ID0
15 0
Data
32 kHz to 8 MHz
T imer Clock
POR/CLR
Mode
Control
MC1 MC0
Equ0
Carry/Zero Set_TAIFG
16-Bit T imer
Capture
Mode
CCIS00CCIS01
CCI0A
CCI0B
GND
0
1
2
3
VCC
CCI0 CCM00
CCM01
Capture/Compare
Register CCR0
15 0
Comparator 0
15 0Output Unit 0
OM02 OM00OM01
TA0
Capture
EQU0
Capture/Compare Register CCR0T imer Bus
Capture
Mode
CCIS10CCIS11
CCI1A
CCI1B
GND
0
1
2
3
VCC
CCI1 CCM10
CCM11
Capture/Compare
Register CCR1
15 0
Comparator 1
15 0Output Unit 1
OM12 OM10OM11
Capture
EQU1
Capture/Compare Register CCR1
Capture
Mode
CCIS20CCIS21
CCI2A
CCI2B
GND
0
1
2
3
VCC
CCI2 CCM20
CCM21
15 0
Comparator 2
15 0Output Unit 2
OM22 OM20OM21
Capture
EQU2
Capture/Compare Register CCR2
P1.0
P2.1
P1.1
P2.2
P1.2
P2.3
P1.3
ACLK
Out 0
Out 1
Out 2
Capture/Compare
Register CCR2
Figure 2. Timer_A, MSP430x11x Configuration
Two interrupt vectors are used by the T imer_A module. One individual vector is assigned to capture/compare
block CCR0, and one common interrupt vector is implemented for the timer and the other two capture/compare
blocks. The three interrupt events using the same vector are identified by an individual interrupt vector word.
The interrupt vector word is used to add an offset to the program counter to continue the interrupt handler
software at the corresponding program location. This simplifies the interrupt handler and gives each interrupt
event the same overhead of 5 cycles in the interrupt handler.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog Watchdog/Timer Control WDTCTL 0120h
Timer_A Timer_A Interrupt Vector
T imer_A Control
Cap/Com Control
Cap/Com Control
Cap/Com Control
Reserved
Reserved
Reserved
Reserved
T imer_A Register
Cap/Com Register
Cap/Com Register
Cap/Com Register
Reserved
Reserved
Reserved
Reserved
TAIV
TACTL
CCTL0
CCTL1
CCTL2
TAR
CCR0
CCR1
CCR2
012Eh
0160h
0162h
0164h
0166h
0168h
016Ah
016Ch
016Eh
0170h
0172h
0174h
0176h
0178h
017Ah
017Ch
017Eh
PERIPHERALS WITH BYTE ACCESS
System Clock Basic Clock Sys. Control2
Basic Clock Sys. Control1
DCO Clock Freq. Control
BCSCTL2
BCSCTL1
DCOCTL
058h
057h
056h
EPROM EPROM Control EPCTL 054h
Port P2 Port P2 Selection
Port P2 Interrupt Enable
Port P2 Interrupt Edge Select
Port P2 Interrupt Flag
Port P2 Direction
Port P2 Output
Port P2 Input
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1 Port P1 Selection
Port P1 Interrupt Enable
Port P1 Interrupt Edge Select
Port P1 Interrupt Flag
Port P1 Direction
Port P1 Output
Port P1 Input
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
026h
025h
024h
023h
022h
021h
020h
Special Function SFR Interrupt Flag1
SFR Interrupt Enable1 IFG1
IE1 002h
000h
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings†
Voltage applied at VCC to VSS –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any pin (referenced to VSS) –0.3 V to VCC+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode current at any device terminal ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg (unprogrammed device) –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg (programmed device) –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE: All voltages referenced to VSS.
recommended operating conditions
MIN NOM MAX UNITS
MSP430C11x 2.5 5.5
V
Supply voltage, VCC MSP430P112 2.7 5.5
V
PMS430E112 2.7 5.5 V
Su
pp
ly voltage during
p
rogramming VCC
MSP430P112 4.5 5 5.5 V
S
u
ppl
y v
oltage
d
u
ring
programming
,
V
CC MSP430E112 4.5 5 5.5 V
MSP430C11x
40
85
Operating free-air temperature range, TAMSP430P112 –
40
85
°C
PMS430E112 25
XTAL frequency , f(XTAL),(ACLK signal) 32768 Hz
Processor frequency f(t)
(PMS430P/E112) (MCLK signal)
VCC = 3 V dc 2
MHz
Processor
freq
u
enc
y
f
(system)
(PMS430P/E112)
(MCLK
signal)
VCC = 5 V dc 5.35
MH
z
Processor frequency f(t)
(MCLK signal) (MSP430C11x)
VCC = 3 V dc 2.73
MHz
Processor
freq
u
enc
y
f
(system)
(MCLK
signal)
(MSP430C11
x
)
VCC = 5 V dc 5.35
MH
z
Low-level input voltage (TCK, TMS, TDI, RST/NMI), VIL (excluding Xin, Xout)
VCC = 3 V/5 V
VSS VSS+0.8 V
High-level input voltage (TCK, TMS, TDI, RST/NMI), VIH (excluding Xin, Xout)
V
CC =
3
V/5
V
0.7VCC VCC V
In
p
ut levels at Xin Xout
VIL(Xin, Xout)
VCC = 3 V/5 V
VSS 0.2×VCC
V
Inp
u
t
le
v
els
at
Xin
,
Xo
u
t
VIH(Xin, Xout)
V
CC =
3
V/5
V
0.8×VCC VCC
V
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
3
2
1
001 23
4
4567
2.2 MHz
at 2.5 V
Minimum
VCC – Supply Voltage – V
5.35 MHz
at 5 V
f(system) – Maximum Processor Frequency – MHz
Figure 3. C Version Frequency vs Supply Voltage
NOTE: Minimum processor frequency is defined by system clock.
5
3
2
1.1
001 23
4
4567
1.1 MHz
at 2.7 V
Minimum
VCC – Supply Voltage – V
5.35 MHz
at 5 V
f(system) – Maximum Processor Frequency – MHz
Figure 4. P/E Version Frequency vs Supply Voltage
NOTE: Minimum processor frequency is defined by system clock.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current (into VCC) excluding external current (f(system) = 1 MHz)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
TA = –40°C +85°C, f
(
MCLK
)
= f
(
SMCLK
)
= 1 MHz, VCC = 3 V 330 400
µA
C11x
A(MCLK) (SMCLK)
f(ACLK) = 32,768 Hz VCC = 5 V 630 700 µ
A
C11
xTA = –40°C +85°C, VCC = 3 V 3.4 4
µA
A
f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz VCC = 5 V 7.8 10 µ
A
I(AM) Active mode TA = –40°C +85°C,
fMCLK =f
(SMCLK) = 1 MHz
VCC = 3 V 400 500
µA
P112
fMCLK
=
f(SMCLK)
=
1
MHz
,
f(ACLK) = 32,768 Hz VCC = 5 V 730 900 µ
A
P112
TA = –40°C +85°C, VCC = 3 V 3.4 4
µA
A
f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz VCC = 5 V 7.8 10 µ
A
C11x
TA = –40°C +85°C, fMCLK = 0 MHz, VCC = 3 V 51 60
I(CPUOff)
Low power mode,
C11
x
AMCLK
f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz VCC = 5 V 120 150
µA
I
(CPUOff) (LPM0)
P112
TA = –40°C +85°C, f
(
MCLK
)
= 0 MHz, VCC = 3 V 70 85 µ
A
P112
A(MCLK)
f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz VCC = 5 V 125 170
I(LPM2)
Low
p
ower mode (LPM2)
TA = –40°C +85°C,
f(MCLK) =f
(SMCLK) = 0 MHz
VCC = 3 V 8 22
µA
I
(LPM2)
Lo
w
po
w
er
mode
,
(LPM2)
f(MCLK)
=
f(SMCLK)
=
0
MHz
,
f(ACLK) = 32,768 Hz, SCG0 = 0, Rsel = 3 VCC = 5 V 16 35 µ
A
TA = –40°Cf
(MCLK)
= f
(SMCLK)
= 0 MHz
,
2 2.6
TA = 25°C
f(MCLK)
f(SMCLK)
0
MHz,
f(ACLK) = 32,768 Hz,
SCG
VCC = 3 V 1.5 2.2
I(LPM3)
Low
p
ower mode (LPM3)
TA = 85°C
()
SCG0 = 1 1.85 2.2
µA
I
(LPM3)
Lo
w
po
w
er
mode
,
(LPM3)
TA = –40°C
f f 0 MHz
6.3 8 µ
A
TA = 25°C
f
(MCLK) =
f
(SMCLK) =
0
MH
z,
f(ACLK)
=
32,768 Hz, SCG0
=
1
VCC = 5 V 5.1 7
TA = 85°C
f(ACLK)
=
32
,
768
Hz
,
SCG0
=
1
5.1 7
TA = –40°Cf
(MCLK)
= f
(SMCLK)
= 0 MHz
,
V3V/
0.1 0.8
I(LPM4) Low power mode, (LPM4) TA = 25°C
f(MCLK)
f(SMCLK)
0
MHz,
f(ACLK) = 0 Hz,
SCG
V
CC =
3
V/
5V
0.1 0.8 µA
()
TA = 85°C
()
SCG0 = 1
5
V
0.4 1
NOTE: All inputs are tied to VSS or VCC. Outputs do not source or sink any current.
current consumption of active mode versus system frequency
IAM = IAM[1 MHz] × fsystem [MHz]
current consumption of active mode versus supply voltage
IAM = IAM[3 V] + 175 µA/V × (VCC–3 V)
standard inputs RST/NMI
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VIL Low-level input voltage
VCC = 3 V/5 V
VSS VSS+0.8
V
VIH High-level input voltage
V
CC =
3
V/5
V
0.7VCC VCC
V
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs Port 1 to Port P2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VIT
Positive going in
p
ut threshold voltage
VCC = 3 V 1.2 2.1
V
V
IT+
Positi
v
e
-
going
inp
u
t
threshold
v
oltage
VCC = 5 V 2.3 3.4
V
VIT
Negative going in
p
ut threshold voltage
VCC = 3 V 0.7 1.5
V
V
IT–
Negati
v
e
-
going
inp
u
t
threshold
v
oltage
VCC = 5 V 1.4 2.3
V
Vh
In
p
ut voltage hysteresis (VIT VIT )
VCC = 3 V 0.3 1
V
V
hys
Inp
u
t
v
oltage
h
y
steresis
,
(V
IT+ –
V
IT–
)
VCC = 5 V 0.6 1.4
V
outputs Port 1 to P2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VOH
High level out
p
ut voltage
I(OH) = – 1.5 mA, VCC = 3 V/5 V, See Note 4 VCC–0.4 VCC
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
I(OH) = – 4.5 mA, VCC = 3 V/5 V, See Note 5 VCC-0.6 VCC
V
VOL
Low level out
p
ut voltage
I(OL) = 1.5 mA, VCC = 3 V/5 V, See Note 4 VSS VSS+0.4
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
I(OL) = 4.5 mA, VCC = 3 V/5 V, See Note 5 VSS VSS+0.6
V
NOTES: 4. The maximum total current, IOH and IOL, or all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop
specified.
5. The maximum total current, IOH and IOL, or all outputs combined, should not exceed ±36 mA to hold the maximum voltage drop
specified.
leakage current (see Note 6)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Ilk (P )
High im
p
endance leakage current
Port P1: P1.x, 0 ≤ ×≤ 7
(see Note 7) VCC = 3 V/5 V, ±50
nA
I
lkg(Px.x)
High
-
impendance
leakage
c
u
rrent
Port P2: P2.x, 0 ≤ ×≤ 5
(see Note 7) VCC = 3 V/5 V, ±50
nA
NOTES: 6. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
7. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional
pullup or pulldown resistor.
optional resistors, individually programmable with ROM code (see Note 8)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
R(opt1) VCC = 3 V/5 V 2.1 4.1 6.2 kΩ
R(opt2) VCC = 3 V/5 V 3.1 6.2 9.3 kΩ
R(opt3) VCC = 3 V/5 V 6 12 18 kΩ
R(opt4) VCC = 3 V/5 V 10 19 29 kΩ
R(opt5) Resistors, individually programmable with ROM code, all port pins, VCC = 3 V/5 V 19 37 56 kΩ
R(opt6)
yg
values applicable for pulldown and pullup VCC = 3 V/5 V 38 75 113 kΩ
R(opt7) VCC = 3 V/5 V 56 112 168 kΩ
R(opt8) VCC = 3 V/5 V 94 187 281 kΩ
R(opt9) VCC = 3 V/5 V 131 261 392 kΩ
R(opt10) VCC = 3 V/5 V 167 337 506 kΩ
NOTE 8: Optional resistors Roptx for pulldown or pullup are not programmed in standard OTP or EPROM devices MSP430P112 or PMS430E112.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
inputs Px.x, TAx
PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT
P t P1 P2 P1 t P2
3 V/ 5 V 1.5 cycle
t(int) External Interrupt timing Port P1, P2: P1.x to P2.x,
External trigger signal for the interru
p
t flag (see Note 9)
3 V 540
ns
()
External
trigger
signal
for
the
interru t
flag
,
(see
Note
9)
5 V 270
ns
3 V/ 5 V 1.5 cycle
t(cap) T imer_A, capture timing TA0, TA1, TA2. (see Note 10) 3 V 540
ns
()
5 V 270
ns
NOTES: 9. The external signal sets the interrupt flag every time the minimum tint cycle and time parameters are met. It may be set even with
trigger signals shorter than tint. Both the cycle and timing specifications must be met to ensure the flag is set.
10. The external capture signal triggers the capture event every time when the minimum tcap cycles and time parameters are met. A
capture may be triggered with capture signals even shorter than tcap. Both the cycle and timing specifications must be met to ensure
a correct capture of the 16-bit timer value and to ensure the flag is set.
internal signals TAx, SMCLK at Timer_A
PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT
f(IN)
In
p
ut frequency
Internal TA0 TA1 TA2 tH=t
L
3 V dc 10
MHz
f
(IN)
Inp
u
t
freq
u
enc
y
Internal
TA0
,
TA1
,
TA2
,
t
H =
t
L5 V dc 15
MH
z
f(TAint) Timer_A clock frequency Internally, SMCLK signal applied 3 V/5 V dc fSystem
outputs P2x, TAx
PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT
f(P20)
Out
p
ut frequency
P2.0/ACLK, CL = 20 pF 3 V/5 V 1.1
MHz
f(TAx)
O
u
tp
u
t
freq
u
enc
yTA0, TA1, TA2, CL = 20 pF 3 V/5 V dc fSystem
MH
z
fP20 = 1.1 MHz 40% 60%
t(Xdc) P2.0/ACLK, CL = 20 pF fP20 = fXTCLK 3 V/ 5 V 35% 65%
()
Duty cycle of O/P frequency fP20 = fXTCLK/n 50%
t(TAdc) TA0, TA1, TA2, CL = 20 pF,
Duty cycle = 50% 3 V/ 5 V 0±50 ns
PUC/POR
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t(POR_delay) 150 250 µs
TA = –40°C 1.5 2.4 V
V(POR) POR TA = 25°C
VCC = 3 V/5 V
1.2 2.1 V
()
TA = 85°C
VCC
=
3
V/5
V
0.9 1.8 V
V(min) 0 0.4 V
t(reset) PUC/POR Reset is accepted internally 2µs
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
VCC
POR
V
t
V
(POR)
V
(min) POR
No POR
Figure 5. Power-On Reset (POR) vs Supply Voltage
1.8
2.1
2.4
0.9
1.2
1.5
0
0.5
1
1.5
2
2.5
3
–40 –20 0 20 40 60 80
Temperature [°C]
25°C
V POR [V]
Figure 6. V(POR) vs Temperature
crystal oscillator, Xin, Xout
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
C(Xin) Capacitance at input VCC = 3 V/5 V 12 pF
C(Xout) Capacitance at output VCC = 3 V/5 V 12 pF
RAM
PARAMETER MIN NOM MAX UNIT
V(RAMh) CPU halted (see Note 11) 1.8 V
NOTE 1 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program
execution should happen during this supply voltage condition.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO (MSP430P112)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
f(DCO03)
Rl=0 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 0.12
MHz
f
(DCO03)
R
sel =
0
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 0.13
MH
z
f(DCO13)
Rl=1 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 0.19
MHz
f
(DCO13)
R
sel =
1
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 0.21
MH
z
f(DCO23)
Rl=2 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 0.31
MHz
f
(DCO23)
R
sel =
2
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 0.34
MH
z
f(DCO33)
Rl=3 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 0.5
MHz
f
(DCO33)
R
sel =
3
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 0.55
MH
z
f(DCO43)
Rl=4 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 0.5 0.8 1.1
MHz
f
(DCO43)
R
sel =
4
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 0.6 0.9 1.2
MH
z
f(DCO53)
Rl=5 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 0.9 1.2 1.55
MHz
f
(DCO53)
R
sel =
5
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 1.1 1.4 1.7
MH
z
f(DCO63)
Rl=6 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 1.7 2 2.3
MHz
f
(DCO63)
R
sel =
6
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 2.1 2.4 2.7
MH
z
f(DCO73)
Rl=7 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 2.8 3.1 3.5
MHz
f
(DCO73)
R
sel =
7
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 3.8 4.2 4.5
MH
z
f(DCO47)
Rl=4 DCO=7 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V/5 V
FDCO40 FDCO40 FDCO40
MHz
f
(DCO47)
R
sel =
4
,
DCO
=
7
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
V
CC =
3
V/5
V
DCO40
x1.8
DCO40
x2.2
DCO40
x2.6
MH
z
S(Rsel) SR = fRsel+1/fRsel VCC = 3 V/5 V 1.4 1.65 1.9
ratio
S(DCO) SDCO = fDCO+1/fDCO VCC = 3 V/5 V 1.07 1.12 1.16
ratio
Dt
Temperature drift, Rsel = 4, DCO = 3, VCC = 3 V –0.31 –0.36 –0.40
%/
°
C
D
t
sel
MOD = 0 (see Note 12) VCC = 5 V –0.33 –0.38 –0.43
%/°C
DVDrift with VCC variation, Rsel = 4, DCO = 3,
MOD = 0 (see Note 12) VCC = 3 V to 5 V 0 5 10 %/V
NOTE 12: These parameters are not production tested.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO (MSP430C111, C112)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
f(DCO03)
Rl=0 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 0.04 0.07 0.10
MHz
f
(DCO03)
R
sel =
0
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 0.04 0.07 0.10
MH
z
f(DCO13)
Rl=1 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 0.08 0.13 0.18
MHz
f
(DCO13)
R
sel =
1
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 0.08 0.13 0.18
MH
z
f(DCO23)
Rl=2 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 0.15 0.22 0.30
MHz
f
(DCO23)
R
sel =
2
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 0.15 0.22 0.30
MH
z
f(DCO33)
Rl=3 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 0.26 0.36 0.47
MHz
f
(DCO33)
R
sel =
3
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 0.26 0.36 0.47
MH
z
f(DCO43)
Rl=4 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 0.4 0.6 0.8
MHz
f
(DCO43)
R
sel =
4
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 0.4 0.6 0.8
MH
z
f(DCO53)
Rl=5 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 0.8 1.1 1.4
MHz
f
(DCO53)
R
sel =
5
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 0.8 1.1 1.4
MH
z
f(DCO63)
Rl=6 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 1.3 1.7 2.1
MHz
f
(DCO63)
R
sel =
6
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 1.5 1.9 2.3
MH
z
f(DCO73)
Rl=7 DCO=3 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V 2.4 2.9 3.4
MHz
f
(DCO73)
R
sel =
7
,
DCO
=
3
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
VCC = 5 V 3.1 3.8 4.5
MH
z
f(DCO47)
Rl=4 DCO=7 MOD=0 DCOR=0 T
A=25
°
C
VCC = 3 V/5 V
FDCO40 FDCO40 FDCO40
MHz
f
(DCO47)
R
sel =
4
,
DCO
=
7
,
MOD
=
0
,
DCOR
=
0
,
T
A =
25°C
V
CC =
3
V/5
V
DCO40
x1.8
DCO40
x2.2
DCO40
x2.6
MH
z
S(Rsel) SR = fRsel+1/fRsel VCC = 3 V/5 V 1.4 1.65 1.9
ratio
S(DCO) SDCO = fDCO+1/fDCO VCC = 3 V/5 V 1.07 1.12 1.16
ratio
Dt
Temperature drift, Rsel = 4, DCO = 3, VCC = 3 V –0.31 –0.36 –0.40
%/
°
C
D
t
sel
MOD = 0 (see Note 12) VCC = 5 V –0.33 –0.38 –0.43
%/°C
DVDrift with VCC variation, Rsel = 4, DCO = 3,
MOD = 0 (see Note 12) VCC = 3 V to 5 V 0 5 10 %/V
NOTE 12. These parameters are not production tested.
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
35
VCC
Max
Min
Max
Min
f(DCOx7)
f(DCOx0)
Frequency Variance
01234567
DCO Steps
1
fDCOCLK
Figure 7. DCO Characteristics
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
principle characteristics of the DCO
D
Individual devices have a minimum and maximum operation frequency. The specified parameters for
fDCOx0 to fDCOx7 are valid for all devices.
D
The DCO control bits DCO0, DCO1 and DCO2 have a step size as defined in parameter SDCO.
D
The modulation control bits MOD0 to MOD4 select how often fDCO+1 is used within the period of 32 DCOCLK
cycles. fDCO is used for the remaining cycles. The frequency is an average = fDCO × (2MOD/32).
wake-up from lower power modes (LPMx)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t(LPM0)/
t(LPM2)
Delay time
VCC = 3 V/5 V 100 ns
t(LPM3)
D
e
l
ay
ti
me RSel = 4, DCO = 3, MOD = 0 VCC = 3 V/5 V 2.6 6µs
t(LPM4) RSel = 4, DCO = 3, MOD = 0 VCC = 3 V/5 V 2.8 6µs
JTAG/programming
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
f(TCK)
JTAG/test
TCK frequency
VCC = 3 V dc 5
MHz
f
(TCK)
JTAG/test
TCK
freq
u
enc
yVCC = 5 V dc 10
MH
z
V(FB)
Fuse blow voltage, C versions (see Note 14) VCC = 3 V/ 5 V 5.5 6
V
V
(FB)
JTAG/fuse (see Note 13)
Fuse blow voltage, E/P versions (see Note 14) VCC = 3 V/ 5 V 11 13
V
I(FB)
JTAG/f
u
se
(see
Note
13)
Supply current on Test/VPP during fuse is blown 100 mA
t(FB) T ime to blow the fuse 1 ms
V(PP) Programming voltage, applied to Test/VPP 12 12.5 13 V
I(PP) Current from programming voltage source 70 mA
t(pps) Programming time, single pulse 5 ms
t(ppf)
EPROM P and E versions
Programming time, fast algorithm 100 µs
P(n)
EPROM
P
-
and
E
-v
ersions
onl
y
(
see Note 15
)
Number of pulses for successful programming 4 100 Pulse
t
only
(see
Note
15)
Erase time wave length 2537 Å at 15 Ws/cm2 (UV lamp of
12 mW/ cm2)30 min
t
(erase) Write/erase cycles 1000
Data retention Tj < 55°C 10 Year
NOTES: 13. Once the JT AG fuse is blown no further access to the MSP430 JT AG/test feature is possible. The JTAG block is switched to by-pass
mode.
14. The power source to blow the fuse is applied to Test/VPP pin during blowing the fuse.
15. Refer to the Recommended Operating Conditions for the correct VCC during programing.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
EN
D
(See Note 16)
(See Note 17)
(See Note 17)
(See Note 16)
GND
VCC
P1.0 – P1.3
0
1
0
1
Interrupt
Edge
Select
EN
Set
Q
P1IE.x
P1IFG.x
P1IRQ.x
Interrupt
Flag P1IES.x
P1SEL.x
Module X IN
P1IN.x
P1OUT.x
Module X OUT
Direction Control
From Module
P1DIR.x
P1SEL.x
Pad Logic
NOTE: x = Bit Identifier, 0 to 3 For Port P1
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x Module X
IN PnIE.x PnIFG.x PnIES.x
P1Sel.0 P1DIR.0 P1DIR.0 P1OUT.0 VSS P1IN.0 TACLK†P1IE.0 P1IFG.0 P1IES.0
P1Sel.1 P1DIR.1 P1DIR.1 P1OUT.1 Out0 signal†P1IN.1 CCI0A†P1IE.1 P1IFG.1 P1IES.1
P1Sel.2 P1DIR.2 P1DIR.2 P1OUT.2 Out1 signal†P1IN.2 CCI1A†P1IE.2 P1IFG.2 P1IES.2
P1Sel.3 P1DIR.3 P1DIR.3 P1OUT.3 Out2 signal†P1IN.3 CCI2A†P1IE.3 P1IFG.3 P1IES.3
†Signal from or to T imer_A
NOTES: 16. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
17. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
CMOS INPUT (RST/NMI)
VCC
(see Note 16)
(see Note 16)
GND
(see Note 17)
(see Note 17)
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
EN
D
See Note 16
See Note 17
See Note 17
See Note 16
GND
VCC
P1.4–P1.7
0
1
0
1
Interrupt
Edge
Select
EN
Set
Q
P1IE.x
P1IFG.x
P1IRQ.x
Interrupt
Flag P1IES.x
P1SEL.x
Module X IN
P1IN.x
P1OUT.x
Module X OUT
Direction Control
From Module
P1DIR.x
P1SEL.x
Pad Logic
Bus Keeper
TST
Fuse 60 kΩ
Fuse
Blow
Control
VPP_Internal
Control By JTAG
0
1
TDO
Controlled By JTAG
P1.x
TDI P1.x
TST
TST
TMS TST
TCK TST
Controlled by JTAG
TS
T
P1.x
P1.x
P1.7/TDI/TDO
P1.6/TDI
P1.5/TMS
P1.4/TCK
Typical
Test/VPP
GND
NOTES:The test pin should be protected from potential EMI and
ESD voltage spikes. This may require a smaller
external pulldown resistor in some applications.
x = Bit identifier, 4 to 7 for port P1
During programming activity and during blowing
the fuse, the pin TDO/TDI is used to apply the test
input for JTAG circuitry.
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x Module X
IN PnIE.x PnIFG.x PnIES.x
P1Sel.4 P1DIR.4 P1DIR.4 P1OUT.4 SMCLK P1IN.4 unused P1IE.4 P1IFG.4 P1IES.4
P1Sel.5 P1DIR.5 P1DIR.5 P1OUT.5 Out0 signal†P1IN.5 unused P1IE.5 P1IFG.5 P1IES.5
P1Sel.6 P1DIR.6 P1DIR.6 P1OUT.6 Out1 signal†P1IN.6 unused P1IE.6 P1IFG.6 P1IES.6
P1Sel.7 P1DIR.7 P1DIR.7 P1OUT.7 Out2 signal†P1IN.7 unused P1IE.7 P1IFG.7 P1IES.7
†Signal from or to T imer_A
NOTES: 16. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
17. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Port P2, P2.0 to P2.4, input/output with Schmitt-trigger
EN
D
See Note 16
See Note 17
See Note 17
See Note 16
GND
VCC
P2.0 – P2.4
0
1
0
1
Interrupt
Edge
Select
EN
Set
Q
P2IE.x
P2IFG.x
P2IRQ.x
Interrupt
Flag P2IES.x
P2SEL.x
Module X IN
P2IN.x
P2OUT.x
Module X OUT
Direction Control
From Module
P2DIR.x
P2SEL.x
Pad Logic
NOTE: x = Bit Identifier, 0 to 4 For Port P2
0: Input
1: Output
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x Module X
IN PnIE.x PnIFG.x PnIES.x
P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 ACLK P2IN.0 unused P2IE.0 P2IFG.0 P1IES.0
P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 VSS P2IN.1 INCLK†P2IE.1 P2IFG.1 P1IES.1
P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 Out0 signal†P2IN.2 CCI0B†P2IE.2 P2IFG.2 P1IES.2
P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out1 signal†P2IN.3 CCI1B†P2IE.3 P2IFG.3 P1IES.3
P2Sel.4 P2DIR.4 P2DIR.4 P2OUT.4 Out2 signal†P2IN.4 unused P2IE.4 P2IFG.4 P1IES.4
†Signal from or to T imer_A
NOTES: 16. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
17. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module
EN
D
See Note 16
See Note 17
See Note 17
See Note 16
GND
VCC
P2.5
0
1
0
1
Interrupt
Edge
Select
EN
Set
Q
P2IE.5
P2IFG.5
P2IRQ.5
Interrupt
Flag P2IES.5
P2SEL.5
Module X IN
P2IN.5
P2OUT.5
Module X OUT
Direction Control
From Module
P2DIR.5
P2SEL.5 Pad Logic
NOTE: DCOR: Control bit from basic clock module if it is set, P2.5 is disconnected from P2.5 pad
Bus Keeper
0
1
01
VCC
Internal to
Basic Clock
Module
DCOR DC
Generator
0: Input
1: Output
PnSel.x PnDIR.x Director
Control from
module PnOUT.x Module X
OUT PnIN.x Module X
IN PnIE.x PnIFG.x PnIES.x
P2Sel.5 P2DIR.5 P2DIR.5 P2OUT.5 VSS P2IN.5 unused P2IE.5 P2IFG.5 P2IES.5
NOTES: 16. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
17. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Port P2, un-bonded bits P2.6 and P2.7
EN
D
0
1
0
1
Interrupt
Edge
Select
EN
Set
Q
P2IE.x
P2IFG.x
P2IRQ.x
Interrupt
Flag P2IES.x
P2SEL.x
Module X IN
P2IN.x
P2OUT.x
Module X OUT
Direction Control
From Module
P2DIR.x
P2SEL.x
Bus Keeper
0
1
0: Input
1: Output
Node Is Reset With PUC
PUC
NOTE: x = Bit identifier, 6 to 7 for Port P2 without external pins
P2Sel.x P2DIR.x Dir. Control
from module P2OUT.x Module X
OUT P2IN.x Module X
IN P2IE.x P2IFG.x P2IES.x
P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 VSS P2IN.6 unused P2IE.6 P2IFG.6 P2IES.6
P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 VSS P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7
NOTE: A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags. The interrupt flags can not be influenced from any signal
other than from software. They work then as soft interrupt.
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally
activating the fuse check mode and increasing overall system power consumption.
When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense
currents are terminated.
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
4040000/D 02/98
Seating Plane
0.400 (10,15)
0.419 (10,65)
0.104 (2,65) MAX
1
0.012 (0,30)
0.004 (0,10)
A
8
16
0.020 (0,51)
0.014 (0,35)
0.293 (7,45)
0.299 (7,59)
9
0.010 (0,25)
0.050 (1,27)
0.016 (0,40)
(15,24)
(15,49)
PINS **
0.010 (0,25) NOM
A MAX
DIM
A MIN
Gage Plane
20
0.500
(12,70)
(12,95)
0.510
(10,16)
(10,41)
0.400
0.410
16
0.600
24
0.610
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430C111IDW, MSP430C112IDW, MSP430P112IDW, pin out
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TEST/VPP
VCC
P2.5/ROSC
VSS
Xout/TCLK
Xin
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/TA0
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2
P2.3/TA1
DW PACKAGE
(TOP VIEW)
PMS430E112 pin out
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TEST/VPP
VCC
P2.5/ROSC
VSS
Xout/TCLK
Xin
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/TA0
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/PMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2
P2.3/TA1
JL PACKAGE
(TOP VIEW)
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196B– DECEMBER 1998 – REVISED APRIL 2000
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
JL (R-GDIP-T20) CERAMIC DUAL-IN-LINE PACKAGE
0.200 (5,08) MAX
0.310 (7,87)
0.290 (7,37)
0.130 (3,30) MIN
0.008 (0,20)
0.014 (0,36)
Seating Plane
4040109/C 08/96
11
0.020 (0,51) MIN
Window
10
0.015 (0,38)
0.050 (1,27)
0.050 (1,27)
0.015 (0,38)
0.975 (24,76)
0.930 (23,62)
20
1
0.023 (0,58)
0.015 (0,38)
0.245 (6,22)
0.300 (7,62)
0.100 (2,54) 0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only
E. Falls within MIL-STD-1835 GDIP1-T20
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
