LTC1063
1
1063fa
VIN**
–5V
*19.1k
5V
0.1µF
VOUT
1063 TA01
SELF-CLOCKING SCHEME
IF THE INPUT VOLTAGE CAN EXCEED V+,
CONNECT A SIGNAL DIODE BETWEEN PIN 1 AND V+.
*
**
0.1µF200pF*
1
2
3
4
8
7
6
5
LTC1063
The LTC
®
1063 is the first monolithic filter providing both
clock-tunability, low DC output offset and over 12-bit DC
accuracy. The frequency response of the LTC1063 closely
approximates a 5th order Butterworth polynomial. With
appropriate PCB layout techniques the output DC offset is
typically 1mV and is constant over a wide range of clock
frequencies. With ±5V supplies and ±4V input voltage
range, the CMR of the device is 80dB.
The filter cutoff frequency is controlled either by an inter-
nal or external clock. The clock-to-cutoff frequency ratio is
100:1. The on-board clock is power supply independent,
and it is programmed via an external RC. The 50µV
RMS
clock feedthrough is considerably reduced over existing
monolithic filters.
The LTC1063 wideband noise is 95µV
RMS
, and it can
process large AC input signals with low distortion. With
±7.5V supplies, for instance, the filter handles up to
4V
RMS
(92dB S/N ratio) while the standard 1kHz THD is
below 0.02%; 80dB dynamic ranges (S/N +THD) is ob-
tained with input levels between 1V
RMS
and 2.3V
RMS
.
The LTC1063 is available in 8-pin miniDIP and 16-pin SO
wide packages. For a linear phase response, see LTC1065
data sheet.
■
Audio
■
Strain Gauge Amplifiers
■
Anti-Aliasing Filters
■
Low Level Filtering
■
Digital Voltmeters
■
60Hz Lowpass Filters
■
Smoothing Filters
■
Reconstruction Filters
■
Clock-Tunable Cutoff Frequency
■
1mV DC Offset (Typical)
■
80dB CMRR (Typical)
■
Internal or External Clock
■
50µV
RMS
Clock Feedthrough
■
100:1 Clock-to-Cutoff Frequency Ratio
■
95µV
RMS
Total Wideband Noise
■
0.01% THD at 2V
RMS
Output Level
■
50kHz Maximum Cutoff Frequency
■
Cascadable for Faster Roll-Off
■
Operates from ±2.375 to ±8V Power Supplies
■
Self-Clocking with 1 RC
■
Available in 8-Pin DIP and 16-Pin SO Wide Packages
APPLICATIO S
U
TYPICAL APPLICATIO
U
DESCRIPTIO
U
FEATURES
DC Accurate, Clock-Tunable
5th Order Butterworth
Lowpass Filter
2.5kHz 5th Order Lowpass Filter
Frequency Response
FREQUENCY (kHz)
1
GAIN (dB)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 10 100
1063 TA02
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
LTC1063
2
1063fa
OBSOLETE PACKAGE
Consider the N8 Package for Alternate Source
PARAMETER CONDITIONS MIN TYP MAX UNITS
Clock-to-Cutoff Frequency Ratio (f
CLK
/f
C
)±2.375V ≤ V
S
≤ ±7.5V 100±0.5
Maximum Clock Frequency (Note 2) V
S
= ±7.5V 5 MHz
V
S
= ±5V 4 MHz
V
S
= ±2.5V 3 MHz
Minimum Clock Frequency (Note 3) ±2.5V ≤ V
S
≤ ±7.5V, T
A
< 85°C30Hz
Input Frequency Range 0 0.9f
CLK
Filter Gain V
S
= ±5V, f
CLK
= 25kHz, f
C
= 250Hz
f
IN
= 250Hz – 3.5 – 3.0 –2.5 dB
●– 3.6 – 3.0 – 2.4 dB
V
S
= ±5V, f
CLK
= 500kHz, f
C
= 5kHz
f
IN
= 100Hz 0 dB
f
IN
= 1kHz = 0.2f
C
– 0.06 – 0.01 0.04 dB
● – 0.075 – 0.01 0.055 dB
f
IN
= 2.5kHz = 0.5f
C
– 0.09 0.16 0.41 dB
● – 0.14 0.16 0.46 dB
f
IN
= 4kHz = 0.8f
C
– 0.5 – 0.2 0.1 dB
● – 0.6 – 0.2 0.2 dB
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C, unless otherwise specified.
ELECTRICAL CHARACTERISTICS
TOP VIEW
SW PACKAGE
16-LEAD PLASTIC SO WIDE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
VIN
GND
NC
V–
NC
NC
CLK OUT
VOS ADJ
NC
VOUT
NC
V+
NC
NC
CLK IN
1
2
3
4
8
7
6
5
TOP VIEW
VIN
GND
V–
CLK OUT
VOS ADJ
VOUT
V+
CLK IN
N8 PACKAGE
8-LEAD PLASTIC DIP
ABSOLUTE MAXIMUM RATINGS
W
WW
U
(Note 1)
Total Supply Voltage (V
+
to V
–
) .......................... 16.5V
Power Dissipation............................................. 400mW
Voltage at Any Input .... (V
–
– 0.3V) ≤ V
IN
≤ (V
+
+ 0.3V)
Burn-In Voltage ...................................................... 16V
Operating Temperature Range ............... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
WU
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
LTC1063CN8 LTC1063CSW
J8 PACKAGE
8-LEAD CERAMIC DIP
TJMAX = 150°C, θJA = 100°C/W (J) TJMAX = 100°C, θJA = 85°C/W
TJMAX = 100°C, θJA = 110°C/W (N)
LTC1063CJ8
LTC1063MJ8
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LTC1063
3
1063fa
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C, unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
f
IN
= 5kHz = f
C
– 3.5 – 3.0 –2.5 dB
● – 3.6 – 3.0 –2.4 dB
f
IN
= 20kHz = 4f
C
– 57.5 – 60.0 – 62.0 dB
●– 57.0 – 60.0 – 62.5 dB
Filter Gain V
S
= ±2.375V, f
CLK
= 500kHz, f
C
= 5kHz
f
IN
= 1kHz – 0.066 0.004 0.074 dB
●– 0.081 0.004 0.089 dB
f
IN
= 2.5kHz – 0.24 0.16 0.56 dB
●– 0.29 0.16 0.61 dB
f
IN
= 4kHz – 0.6 – 0.2 0.2 dB
●– 0.7 – 0.2 0.3 dB
f
IN
= 5kHz –3.5 – 3.0 – 2.5 dB
●–3.6 – 3.0 – 2.4 dB
Clock Feedthrough ±2.375 ≤ V
S
≤ ±7.5V 50 µV
RMS
Wideband Noise (Note 4) ±2.375 ≤ V
S
≤ ±7.5V, 1Hz < f < f
CLK
100 µV
RMS
THD + Wideband Noise (Note 5) V
S
= ±7.5V, f
C
= 20kHz, f
IN
= 1kHz, –80 dB
1V
RMS
≤ V
IN
≤ 2.3V
RMS
Filter Output ± DC Swing V
S
= ±2.375V 1.6/– 2.0 1.7/– 2.2 V
●1.4/– 1.8 V
V
S
= ±5V 4.0/– 4.5 4.3/– 4.8 V
●3.8/– 4.3 V
V
S
= ±7.5V 6.5/– 7.0 6.8/– 7.3 V
●6.3/– 6.8 V
Input Bias Current 10 nA
Dynamic Input Impedance 800 MΩ
Output DC Offset (Note 6) V
S
= ±2.375V 2 mV
V
S
= ±5V 0 ±5mV
V
S
= ±7.5V – 4 mV
Output DC Offset Drift V
S
= ±2.375V 10 µV/°C
V
S
= ±5V 20 µV/°C
V
S
= ±7.5V 25 µV/°C
Self-Clocking Frequency (f
OSC
) R (Pin 4 to 5) = 20k, C (Pin 5 to GND) = 470pF
V
S
= ±2.375V 99 105 112 kHz
●95 103 114 kHz
V
S
= ±5V 102 108 114 kHz
●98 106 114 kHz
V
S
= ±7.5V 104 110 116 kHz
●101 109 116 kHz
External CLK Pin Logic Thresholds V
S
= ±2.375V Min Logical “1” 1.43 V
Max Logical “0” 0.47 V
V
S
= ±5V Min Logical “1” 3 V
Max Logical “0” 1 V
V
S
= ±7.5V Min Logical “1” 4.5 V
Max Logical “0” 1.5 V
ELECTRICAL CHARACTERISTICS
LTC1063
4
1063fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
EXTERNAL CLOCK FREQUENCY (kHz)
OUTPUT OFFSET (mV)
5
4
3
2
1
0
–1
–2
–3
–4
–5
1063 G03
500 1000
0
V
S
= ±7.5V
V
S
= ±5V
V
S
= ±2.5V
EXTERNAL CLOCK FREQUENCY (Hz)
OUTPUT OFFSET (mV)
50
45
40
35
30
25
20
15
10
5
0
1063 G02
10 110 210
A
B
A: T
A
= 25°C
B: T
A
= 85°C
V
S
= ±5V
FREQUENCY (kHz)
R PINS 4 TO 5 (kΩ)
110
100
90
80
70
60
50
40
30
20
10
1063 G01
100 300 500
LTC1063
RC
45
C = 200pF
f
OSC
≅ 1/RC
PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply Current V
S
= ±2.375V, f
CLK
= 500kHz 2.7 4.0 mA
●5.5 mA
V
S
= ±5V, f
CLK
= 500kHz 5.5 8 mA
●11 mA
V
S
= ±7.5V, f
CLK
= 500kHz 7.0 11 mA
●14.5 mA
Output Offset vs Clock,
Medium Clock RatesSelf-Clocking Frequency vs R
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The maximum clock frequency criterion is arbitrarily defined as:
The frequency at which the filter AC response exhibits ≥ 1dB of gain
peaking.
Note 3: At limited temperature ranges (i.e., T
A
≤ 50°C) the minimum clock
frequency can be as low as 10Hz. The minimum clock frequency is
arbitrarily defined as: the clock frequency at which the output DC offset
changes by more than 1mV.
Note 4: The wideband noise specification does not include the clock
feedthrough.
Note 5: To properly evaluate the filter’s harmonic distortion an inverting
output buffer is recommended as shown in the Test Circuit. An output
buffer is not necessarily needed when measuring output DC offset or
wideband noise.
Note 6: The output DC offset is optimized for ±5V supply. The output DC
offset shifts when the power supplies change; however this phenomenon
is repeatable and predictable.
Output Offset vs Clock,
Low Clock Rates
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C, unless otherwise specified.
ELECTRICAL CHARACTERISTICS
LTC1063
5
1063fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
FREQUENCY (kHz)
1
0.001
THD (%)
0.01
0.1
1
10
1063 G12
5
V
IN
= 2.5V
RMS
f
C
= 10kHz, f
CLK
= 1MHz
S/N = 88dB, T
A
= 25°C
5 REPRESENTATIVE UNITS
INPUT (V
RMS
)
0.1
0.001
THD + NOISE (%)
15
1063 G11
0.01
0.1
1
A
B
f
IN
= 1kHz, T
A
= 25°C
5 REPRESENTATIVE UNITS
A. f
C
= 10kHz, f
CLK
= 1MHz
B. f
C
= 20kHz, f
CLK
= 2MHz
FREQUENCY (kHz)
1
0.001
THD (%)
0.01
0.1
1
10
1063 G10
5
VIN = 1.5VRMS
fC = 10kHz, fCLK = 1MHz
S/N = 83.5dB, TA = 25°C
5 REPRESENTATIVE UNITS
INPUT (V
RMS
)
0.1
0.001
THD + NOISE (%)
15
1063 G09
0.01
0.1
1
A
B
f
IN
= 1kHz, T
A
= 25°C
5 REPRESENTATIVE UNITS
A. f
C
= 10kHz, f
CLK
= 1MHz
B. f
C
= 20kHz, f
CLK
= 2MHz
FREQUENCY (kHz)
1
0.001
THD (%)
0.01
0.1
1
2
1063 G08
3 4 5
V
IN
= 0.75V
RMS
f
C
= 5kHz, f
CLK
= 500kHz
S/N = 78dB, T
A
= 25°C
5 REPRESENTATIVE UNITS
INPUT (V
RMS
)
0.1
0.001
THD + NOISE (%)
15
1063 G07
0.01
0.1
1
A
B
f
IN
= 1kHz, T
A
= 25°C
5 REPRESENTATIVE UNITS
A. f
C
= 5kHz, f
CLK
= 0.5MHz
B. f
C
= 10kHz, f
CLK
= 1MHz
INPUT FREQUENCY (kHz)
1
GAIN (dB)
10 100
1063 G06
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
200
ABC E
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
E. fCLK = 5MHz
VIN = 2.5VRMS
TA = 25°C
D
INPUT FREQUENCY (kHz)
1
GAIN (dB)
10 100
1063 G05
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
200
AB C D
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
V
IN
= 1.5V
RMS
T
A
= 25°C
INPUT FREQUENCY (kHz)
1
GAIN (dB)
10 100
1063 G04
B C
V
IN
= 750mV
RMS
T
A
= 25°C
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
200
A
A. fCLK = 0.5MHz
B. fCLK = 1MHz
C. fCLK = 2MHz
Gain vs Frequency; VS = ±2.5V Gain vs Frequency; VS = ±5V Gain vs Frequency; VS = ±7.5V
THD vs Frequency; VS = ±5V
THD + Noise vs Input Voltage;
VS = Single 5V
THD vs Frequency;
VS = Single 5V
THD + Noise vs Input Voltage;
VS = ±5V
THD vs Frequency;
VS = ±7.5V
THD + Noise vs Input Voltage;
VS = ±7.5V
LTC1063
6
1063fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TOTAL POWER SUPPLY VOLTAGE (V)
0
POWER SUPPLY CURRENT (mA)
10
9
8
7
6
5
4
3
2
1
016
1063 G15
4812 20
610 14 18
2
–40°C
85°C
25°C
INPUT FREQUENCY (kHz)
0
PHASE MISMATCH (±DEG)
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0481216
1063 G14
20 2426
10 14 18 22
VS = ± 7.5V
VIN = 1VRMS
fCLK = 2MHz
fC = 20kHz
INPUT FREQUENCY (Hz)
100
PASSBAND GAIN (dB)
1
0
–1
–2
–3
–4
–5
–6
1k 10k 100k
1063 G13
0
–20
–60
–100
–140
–180
–220
–260
PHASE (DEG)
±2.5V ≤ V
S
≤ ±7.5V, T
A
= 25°C
B
AAB
PHASE PHASE
f
CLK
=100kHz
f
C
=1kHz
f
CLK
=1MHz
f
C
=10kHz
Transient Response
HORIZONTAL: 0.1ms/DIV, VERTICAL: 2V/DIV
V
S
= ±5V, f
C
= 10kHz, V
IN
= 1kHz ±3V
P
SQUARE WAVE
1063 G16
Passband Gain and Phase
vs Input Frequency Phase Matching
Power Supply Current vs
Power Supply Voltage
LTC1063
7
1063fa
PI FU CTIO S
U
UU
Power Supply Pins (Pins 6, 3, N Package)
The positive and negative supply pin should be bypassed
with a high quality 0.1µF ceramic capacitor. In applications
where the clock pin (5) is externally swept to provide
several cutoff frequencies, the output DC offset variation
is minimized by connecting an additional 1µF solid tanta-
lum capacitor in parallel with the 0.1µF disc ceramic. This
technique was used to generate the graphs of the output
DC offset variation versus clock; they are illustrated in the
Typical Performance Characteristics section.
When the power supply voltage exceeds ±7V, and when V
–
is applied before V
+
, if V
+
is allowed to go below ground,
connect a signal diode between the positive supply pin and
ground to prevent latch-up (see Typical Applications).
Ground Pin (Pin 2, N Package)
The ground pin merges the internal analog and digital
ground paths. The potential of the ground pin is the
reference for the internal switched-capacitor resistors,
and the reference for the external clock. The positive input
of the internal op amp is also tied to the ground pin.
For dual supply operation, the ground pin should be
connected to a high quality AC and DC ground. A ground
plane, if possible, should be used. A poor ground will
degrade DC offset and it will increase clock feedthrough,
noise and distortion.
A small amount of AC current flows out of the ground pin
whether or not the internal oscillator is used. The fre-
quency of the ground current equals the frequency of the
internal or external clock. The average value of this current
is approximately 55µA, 110µA, 170µA for ±2.5V, ±5V and
±7.5V supplies respectively.
For single supply operation, the ground pin should be
preferably biased at half supply (see Typical Applications).
V
OS
Adjust Pin (Pin 8, N Package)
The V
OS
adjust pin can be used to trim any small amount
of output DC offset voltage or to introduce a desired output
DC level. The DC gain from the V
OS
adjust pin to the filter
output pin equals two.
Any DC voltage applied to this pin will reflect at the output
pin of the filter multiplied by two.
If the V
OS
adjust pin is not used, it should be shorted to the
ground pin. The DC bias current flowing into the V
OS
adjust
pin is typically 10pA.
Pin 8 should always be connected to an AC ground; AC
signals applied to this pin will degrade the filter response.
Input Pin (Pin 1, N Package)
Pin 1 is the filter input and it is connected to an internal
switched-capacitor resistor. If the input pin is left floating,
the filter output will saturate. The DC input impedance of
pin 1 is very high; with ±5V supplies and 1MHz clock, the
DC input impedance is typically 1GΩ. A resistor, R
IN
, in
series, with the input pin will not alter the value of the
filter’s DC output offset (Figure 1). R
IN
should, however,
be limited to a maximum value (Table 1), otherwise the
filter’s passband flatness will be affected. Refer to the
Applications Information section for more details.
V
IN
V
OUT
1063 F01
V
–
V
+
R
IN
1
2
3
4
8
7
6
5
LTC1063
f
CLK
Table 1. RIN(MAX) vs Clock and Power Supply
R
IN(MAX)
V
S
= ±7.5V V
S
= ±5V V
S
= ±2.5V
f
CLK
= 4MHz 2.2k – –
f
CLK
= 3MHz 3.4k 2.9k –
f
CLK
= 2MHz 5.5k 5k 2.7k
f
CLK
= 1MHz 11k 11k 9.2k
f
CLK
= 500kHz 24k 23k 21k
f
CLK
= 100kHz 120k 120k 110k
Figure 1.
LTC1063
8
1063fa
V
–
50k
V
+
0.1µF
V
OUT
1063 TC01
0.1µF
CLOCK IN
–
+
LT1022
20pF
V
IN
50k
8
7
6
5
1
2
3
4
LTC1063
CLOCK FREQUENCY (MHz)
1
MAXIMUM LOAD CAPACITANCE (pF )
200
180
160
140
120
100
80
60
40
20
0310
1063 F02
245
678
9
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±7.5V
T
A
= 25°C
Output Pin (Pin 7, N Package)
Pin 7 is the filter output. This pin can typically source over
20mA and sink 2mA. Pin 7 should not drive long coax
cables, otherwise the filter’s total harmonic distortion will
degrade.
Clock Input Pin (Pin 5, N Package)
An external clock when applied to pin 5 tunes the filter
cutoff frequency. The clock-to-cutoff frequency ratio is
100:1. The high (V
HIGH
) and low (V
LOW
) clock logic
threshold levels are illustrated in Table 2. Square wave
clocks with duty cycles between 30% and 50% are strongly
recommended. Sinewave clocks are not recommended.
Clock Output Pin (Pin 4, N Package)
Any external clock applied to the clock input pin appears
at the clock output pin. The duty cycle of the clock output
equals the duty cycle of the external clock applied to the
clock input pin. The clock output pin swings to the power
supply rails. When the LTC1063 is used in a self-clocking
mode, the clock of the internal oscillator appears at the
clock output pin with a 30% duty cycle. The clock output
pin can be used to drive other LTC1063s or other ICs. The
maximum capacitance, C
L(MAX)
, the clock output pin can
drive is illustrated in Figure 2.
Table 2. Clock Pin Threshold Levels
POWER SUPPLY V
HIGH
V
LOW
V
S
= ±2.5V 1.5V 0.5V
V
S
= ±5V 3V 1V
V
S
= ±7.5V 4.5V 1.5V
V
S
= ±8V 4.8V 1.6V
V
S
= 5V, 0V 4V 3V
V
S
= 12, 0V 9.6V 7.2V
V
S
=15V, 0V 12V 9V
Figure 3. Test Circuit for THD
Figure 2. Maximum Load Capacitance at the Clock Output Pin
TEST CIRCUIT
PI FU CTIO S
UUU
LTC1063
9
1063fa
CLOCK FREQUENCY (MHz)
0.5
K
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40 2.5
1063 F06
1.0 1.5 2.0 3.0
f
CLK
= K/RC
C = 10pF
T
A
= 25°C
V
S
= ±7.5V
V
S
= ±2.5V
V
S
= ±5V
CLOCK FREQUENCY (kHz)
0
f
CLK
CHANGE NORMALIZED
TO ITS 25°C VALUE (%)
4
3
2
1
0
–1
–2
–3
–4 400
1063 F05
100 200 300 500
C = 200pF T
A
= –40°C
T
A
= 85°C
V
S
= ±2.5V V
S
= ±5V
V
S
= ±7.5V
V
S
= ±7.5V
V
S
= ±5V
V
S
= ±2.5V
INTERNAL CLOCK FREQUENCY (kHz)
K
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
1063 F04b
100 300 500
V
S
= ±7.5V
V
S
= ±2.5V
F
CLK
= K/RC
C = 200pF
T
A
= 25°C
V
S
= ±5V
200 400
VIN
R
VOUT
1063 F04a
C
V–V+
1
2
3
4
8
7
6
5
LTC1063
Self-Clocking Operation
The LTC1063 features an internal oscillator which can be
tuned via an external RC. The LTC1063’s internal oscillator
is primarily intended for generation of clock frequencies
below 500kHz. The first curve of the Typical Performance
Characteristics section shows how to quickly choose the
value of the RC for a given frequency. More precisely, the
frequency of the internal oscillator is equal to:
f
CLK
= K/RC
For clock frequencies (f
CLK
) below 100kHz, K equals 1.07.
Figure 4b shows the variation of the parameter K versus
clock frequency and power supply. First choose the de-
sired clock frequency, (f
CLK
< 500kHz), then through
Figure 4b pick the right value of K, set C = 200pF and solve
for R.
Example 1: f
CUTOFF
= 2kHz, f
CLK
= 200kHz, V
S
= ±5V,
T
A
= 25°C, K = 1.0, C = 200pF
then, R = (1.0)/(200kHz × 204pF) = 24.5k.
Figure 4b. fCLK vs K
Note a 4pF parasitic capacitance is assumed in parallel
with the external 200pF timing capacitor. Figure 5 shows
the clock frequency variation from – 40°C to 85°C. The
200kHz clock of Example 1 will change by –1.75% at 85°C.
Figure 5. fCLK vs Temperature
For a very limited temperature range, the internal oscillator
of the LTC1063 can be used to generate clock frequencies
above 500kHz (Figures 6 and 7). The data of Figure 6 is
derived from several devices. For a given external (RC)
value, the observed device-to-device clock frequency varia-
tion was ±1% (V
S
= ±5V), and ±1.25% for V
S
= ±2.5V.
Example 2: f
CUTOFF
= 20kHz, f
CLK
= 2MHz, V
S
= ±7.5V,
T
A
= 25°C, C = 10pF
from Figure 6, K = 0.575,
and, R = (0.575)/(2MHz × 14pF) = 20.5k.
Figure 6. fCLK vs K
Figure 4a.
APPLICATIO S I FOR ATIO
WUUU
LTC1063
10
1063fa
CLOCK FREQUENCY (MHz)
0.5
K
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40 2.5
1063 F07
1.0 1.5 2.0 3.0
f
CLK
= K/RC
C = 10pF
T
A
= 70°C
V
S
= ±7.5V
V
S
= ±2.5V
V
S
= ±5V
Figure 7. fCLK vs K
A 4pF parasitic capacitance is assumed in parallel with the
external 10pF capacitor. A ±1% clock frequency variation
from device to device can be expected. The 2MHz clock
frequency designed above will typically drift to 1.74MHz at
70°C (Figure 7).
The internal clock of the LTC1063 can be overridden by an
external clock provided that the external clock source can
drive the timing capacitor, C, which is connected from the
clock input pin to ground.
Output Offset
The DC output offset of the LTC1063 is trimmed to
typically less than ±1mV . The trimming is done at V
S
=
±5V. To obtain optimum DC offset performance, appropri-
ate PC layout techniques should be used and the filter IC
should be soldered to the PC board. A socket will degrade
the output DC offset by typically 1mV. The output DC offset
is sensitive to the coupling of the clock output pin 4 (N
package) to the negative power supply pin 3 (N package).
The negative supply pin should be well decoupled. When
the surface mount package is used, all the unused pins
should be grounded.
When the power supplies are fixed, the output DC offset
should not change by more than ±100µV over 10Hz to
1MHz clock frequency variation. When the filter clock
frequency is fixed, the output DC offset will typically
change by –4mV (2mV) when the power supply varies
from ±5V to ±7.5V (±2.5V). See Typical Performance
Characteristics.
Common Mode Rejection Ratio
The common mode rejection ratio is defined as the change
of the output DC offset with respect to the DC change of the
input voltage applied to the filter.
CMRR = 20log (∆V
OS OUT
/∆V
IN
)(dB)
Table 3 illustrates the common mode rejection for three
power supplies and three temperatures. The common
mode rejection improves if the output offset is adjusted to
approximately 0V. The output offset can be adjusted via
pin 8 (N package) (see Typical Applications).
The above data is valid for clock frequencies up to 800kHz, 900kHz, 1MHz, for
V
S
= ±2.5V, ±5V, ±7.5V respectively.
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics which are present at the
filter’s output pin. The clock feedthrough is tested with the
filter input grounded and it depends on the quality of the
PC board layout and power supply decoupling. Any para-
sitic switching transients, during the rise and fall of the
incoming clock, are not part of the clock feedthrough
specifications; their amplitude strongly depends on scope
probing techniques as well as ground quality and power
supply bypassing. For a power supply V
S
= ±5V, the clock
feedthrough of the LTC1063 is 50µV
RMS
; for V
S
= ±7.5V,
the clock feedthrough approaches 75µV
RMS
. Figure 8
shows a typical scope photo of the LTC1063 output pin
when the input pin is grounded. The filter cutoff frequency
was 1kHz, while scope bandwidth was chosen to be 1MHz
such as switching transients above the 100kHz clock
frequency will show.
Wideband Noise
The wideband noise of the filter is the RMS value of the
device’s output noise spectral density. The wideband
noise data is used to determine the operating signal-to-
Table 3. CMRR Data, fCLK = 100kHz
25°C
POWER SUPPLY ∆V
IN
–40°C25°C85°C(V
OS
Nulled)
±2.5V ±1.8V 76dB 78dB 76dB 85dB
±5V ±4V 74dB 79dB 75dB 82dB
±7.5V ±6V 70dB 72dB 74dB 76dB
APPLICATIO S I FOR ATIO
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LTC1063
11
1063fa
VIN
VOUT
1063 F10
C
V–V+
R
0.1µF
1
2
3
4
8
7
6
5
LTC1063
0.1µF
fCLK
20 102πRC
≤≤
1 fCLK
fCLK
Aliasing
Aliasing is an inherent phenomenon of sampled data filters
and it primarily occurs when the frequency of an input
signal approaches the sampling frequency. For the
LTC1063, an input signal whose frequency is in the range
of f
CLK
±6% will generate an alias signal into the filter’s
passband and stopband. Table 4 shows details.
Example: LTC1063, f
CLK
= 20kHz, f
C
= 200kHz,
f
IN
= (19.6kHz, 100mV
RMS
)
f
ALIAS
= (400Hz, 3.16mV
RMS
)
An input RC can be used to attenuate incoming signals
close to the filter clock frequency (Figure 10). A Butterworth
passband response will be maintained if the value of the
input resistor follows Table 1.
Table 4. Aliasing Data
INPUT FREQUENCY OUTPUT FREQUENCY
0.9995f
CLK
0.0005 f
CLK
0dB
0.995 f
CLK
0.005 f
CLK
0dB
0.99 f
CLK
0.01 f
CLK
–3 dB
0.9875f
CLK
0.0125 f
CLK
–10.2 dB
0.985 f
CLK
0.015 f
CLK
– 17.7 dB
0.9825f
CLK
0.0175 f
CLK
– 24.3 dB
0.98 f
CLK
0.02 f
CLK
–30 dB
0.975 f
CLK
0.025 f
CLK
–40 dB
0.97 f
CLK
0.03 f
CLK
–48 dB
0.965 f
CLK
0.035 f
CLK
– 54.5 dB
0.96 f
CLK
0.04 f
CLK
– 60.4 dB
0.955 f
CLK
0.045 f
CLK
– 65.5 dB
0.95 f
CLK
0.05 f
CLK
– 70.16 dB
0.94 f
CLK
0.06 f
CLK
– 78.25 dB
0.93 f
CLK
0.07 f
CLK
– 85.3 dB
0.9 f
CLK
0.1 f
CLK
–100.3 dB
Figure 10. Adding an Input Anti-Aliasing RC
noise ratio at a given distortion level. The wideband noise
(µV
RMS
) is nearly independent of the value of the clock
frequency and excludes the clock feedthrough. The
LTC1063’s typical wideband noise is 95µV
RMS
. Figure 9
shows the same scope photo as Figure 8 but with a more
sensitive vertical scale: The clock feedthrough is imbed-
ded in the filter’s wideband noise. The peak-to-peak
wideband noise of the filter can be clearly seen; it is
approximately 500µV
P-P
. Note that 500µV
P-P
equals the
95µV
RMS
wideband noise of the part, multiplied by a crest
factor or 5.25.
OUTPUT AMPLITUDE
REFERENCED TO
INPUT SIGNAL
2µs/DIV
1063 F08
f
CLK
= 100kHz, f
C
= 1kHz, V
S
= ±5V, 1MHz SCOPE BW
5mV/DIV
0.5mV/DIV
2µs/DIV
1063 F09
f
CLK
= 100kHz, f
C
= 1kHz, V
S
= ±5V, 1MHz SCOPE BW
Figure 8. LTC1063 Output Clock Feedthrough + Noise
Figure 9. LTC1063 Output Clock Feedthrough + Noise
APPLICATIO S I FOR ATIO
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LTC1063
12
1063fa
VIN*
–5V
R
5V
0.1µF
VOUT
1063 TA06
* IF THE INPUT VOLTAGE CAN EXCEED V+,
CONNECT A SIGNAL DIODE BETWEEN PIN 1 AND V+.
1
2
3
4
8
7
6
5
LTC1063
C
1
2
3
4
8
7
6
5
LTC1063
–5V
5V
0.1µF
0.1µF
0.1µF
VIN*
VOUT
V
IN
V
–
–7.5V
V
+
7.5V
0.1µF
1
2
3
4
8
7
6
5
LTC1063
f
CLK
0.1µF
7.5V
1µF
TANT
+
1063 TA05
V
OUT
10k
≅2.5mV
LT1009
10k
*
* OPTIONAL, 1N4148
VIN*
–5V
R
5V
0.1µF
VOUT
1063 TA04
* IF THE INPUT VOLTAGE CAN EXCEED V+,
CONNECT A SIGNAL DIODE BETWEEN PIN 1 AND V+.
1
2
3
4
8
7
6
5
LTC1063
C
1
2
3
4
8
7
6
5
LTC1063
–5V
5V
0.1µF
0.1µF
0.1µF
fC ≅ (1/RC)(1/100)
WIDEBAND NOISE = 140µVRMS
ATTENUATION AT f = 2fC = 60dB
INPUT FREQUENCY (kHz)
0
(ms)
100
90
80
70
60
50
40
30
20 8
1063 F11
24610
(A) LTC1063
BUTTERWORTH
13579
(B) GROUP
DELAY
CORRECTED
VIN
5V
13k
5V
0.1µF
VOUT
1063 TA03
0.1µF
200pF
1
2
3
4
8
7
6
5
LTC1063
4.53k
+
4.99k
1µF
TANT
Group Delay
The group delay of the LTC1063 closely approximates the
delay of an ideal 5-pole Butterworth lowpass filter (Figure
11, Curve A). To linearize the group delay of the LTC1063
(Figure 11, Curve B), use an input resistor about six times
higher than the maximum value of R
IN
, shown in Table 1.
The passband response of the group delay corrected filter
approximates a 5-pole Bessel response while its transi-
tion band rolls off like a Butterworth.
Figure 11. Group Delay
Single 5V Supply Operation (fC = 3.4kHz) Adjusting VOS(OUT) for
±7.5 Supply Operation
Sharing Clock for Multichannel Applications
Cascading Two LTC1063s for Steeper Roll-Off
APPLICATIO S I FOR ATIO
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TYPICAL APPLICATIO S
U
LTC1063
13
1063fa
OBSOLETE PACKAGE
PACKAGE DESCRIPTIO
U
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
J8 0801
.014 – .026
(0.360 – 0.660)
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.125
3.175
MIN
.100
(2.54)
BSC
.300 BSC
(7.62 BSC)
.008 – .018
(0.203 – 0.457) 0° – 15°
.005
(0.127)
MIN
.405
(10.287)
MAX
.220 – .310
(5.588 – 7.874)
1234
87
65
.025
(0.635)
RAD TYP
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
CORNER LEADS OPTION
(4 PLCS)
.045 – .065
(1.143 – 1.651)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
LTC1063
14
1063fa
PACKAGE DESCRIPTIO
U
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
N8 1002
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.020
(0.508)
MIN
.018 ± .003
(0.457 ± 0.076)
.120
(3.048)
MIN
12 34
87 65
.255 ± .015*
(6.477 ± 0.381)
.400*
(10.160)
MAX
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
LTC1063
15
1063fa
PACKAGE DESCRIPTIO
U
SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
S16 (WIDE) 0502
NOTE 3
.398 – .413
(10.109 – 10.490)
NOTE 4
16 15 14 13 12 11 10 9
1
N
2345678
N/2
.394 – .419
(10.007 – 10.643)
.037 – .045
(0.940 – 1.143)
.004 – .012
(0.102 – 0.305)
.093 – .104
(2.362 – 2.642)
.050
(1.270)
BSC .014 – .019
(0.356 – 0.482)
TYP
0° – 8° TYP
NOTE 3
.009 – .013
(0.229 – 0.330)
.005
(0.127)
RAD MIN
.016 – .050
(0.406 – 1.270)
.291 – .299
(7.391 – 7.595)
NOTE 4
× 45°
.010 – .029
(0.254 – 0.737)
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.420
MIN
.325 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
N
1 2 3 N/2
.050 BSC
.030 ±.005
TYP
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1063
16
1063fa
(LTC1063)VOS
2
fNOTCH
f(–20dB)BW =10.4
1
• fNOTCH =
• NOTCH DEPTH > 50dB
• OUPUT DC OFFSET = ≅ 500µV
• OUTPUT NOISE = 50µVRMS
•
fCLK
119.04
R2
9.53k ±0.1%
VIN
–5V
R1
10k ± 0.1%
V+
5V
0.1µF
1
2
3
4
8
7
6
5
LTC1063
fCLK
0.1µF
–
LT1007
1µF
TANT
+
1063 TA07
INPUT FREQUENCY (Hz)
340
GAIN (dB)
0
–10
–20
–30
–40
–50
–60
–70
215 465 590 715 840 965 1090 1215 1340 1465
81Hz
fCLK = 100kHz
fn = 840Hz
+
Low Noise DC Accurate Clock-Tunable Notch
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1993
LT/LT 0905 REV A • PRINTED IN USA
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TYPICAL APPLICATIO S
U
